* [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: peter.maydell, zev, andrew, irischenlj, openbmc, qemu-devel,
qemu-arm, clg, pdel, joel
v2:
- Rebased on Cedric's irq proposal. [1]
- Added "Introduce common UART init function" patch
- Added "Add uarts_num SoC attribute" patch
- Rewrote last commit's message for clarity
I tried testing this by running acceptance tests, particularly the
boot_linux_console.py file, but I had to disable the raspi2_initrd case.
It's not related to my changes (A/B tested and it fails on upstream/master
too), but thought I would mention that.
I also manually tested several machines:
AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
[1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
Peter Delevoryas (5):
hw: aspeed: Add missing UART's
hw: aspeed: Add uarts_num SoC attribute
hw: aspeed: Ensure AST1030 respects uart-default
hw: aspeed: Introduce common UART init function
hw: aspeed: Init all UART's with serial devices
hw/arm/aspeed_ast10x0.c | 32 +++++++++++++++++++++++++++-----
hw/arm/aspeed_ast2600.c | 27 ++++++++++++++++++++++-----
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++++----
include/hw/arm/aspeed_soc.h | 10 ++++++++++
4 files changed, 88 insertions(+), 14 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: pdel, irischenlj, qemu-arm, qemu-devel, clg, zev, openbmc,
andrew, peter.maydell, joel
v2:
- Rebased on Cedric's irq proposal. [1]
- Added "Introduce common UART init function" patch
- Added "Add uarts_num SoC attribute" patch
- Rewrote last commit's message for clarity
I tried testing this by running acceptance tests, particularly the
boot_linux_console.py file, but I had to disable the raspi2_initrd case.
It's not related to my changes (A/B tested and it fails on upstream/master
too), but thought I would mention that.
I also manually tested several machines:
AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
[1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
Peter Delevoryas (5):
hw: aspeed: Add missing UART's
hw: aspeed: Add uarts_num SoC attribute
hw: aspeed: Ensure AST1030 respects uart-default
hw: aspeed: Introduce common UART init function
hw: aspeed: Init all UART's with serial devices
hw/arm/aspeed_ast10x0.c | 32 +++++++++++++++++++++++++++-----
hw/arm/aspeed_ast2600.c | 27 ++++++++++++++++++++++-----
hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++++----
include/hw/arm/aspeed_soc.h | 10 ++++++++++
4 files changed, 88 insertions(+), 14 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 1/5] hw: aspeed: Add missing UART's
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 6:23 ` Peter Delevoryas
-1 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: peter.maydell, zev, andrew, irischenlj, openbmc, qemu-devel,
qemu-arm, clg, pdel, joel
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030
from UART6 to UART13. The addresses and interrupt numbers for these two
later chips are identical.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++
hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++
hw/arm/aspeed_soc.c | 6 ++++++
include/hw/arm/aspeed_soc.h | 8 ++++++++
4 files changed, 57 insertions(+)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 9ae9efaac1..fa2cc4406c 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -33,14 +33,38 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SBC] = 0x7E6F2000,
[ASPEED_DEV_GPIO] = 0x7E780000,
[ASPEED_DEV_TIMER1] = 0x7E782000,
+ [ASPEED_DEV_UART1] = 0x7E783000,
+ [ASPEED_DEV_UART2] = 0x7E78D000,
+ [ASPEED_DEV_UART3] = 0x7E78E000,
+ [ASPEED_DEV_UART4] = 0x7E78F000,
[ASPEED_DEV_UART5] = 0x7E784000,
+ [ASPEED_DEV_UART6] = 0x7E790000,
+ [ASPEED_DEV_UART7] = 0x7E790100,
+ [ASPEED_DEV_UART8] = 0x7E790200,
+ [ASPEED_DEV_UART9] = 0x7E790300,
+ [ASPEED_DEV_UART10] = 0x7E790400,
+ [ASPEED_DEV_UART11] = 0x7E790500,
+ [ASPEED_DEV_UART12] = 0x7E790600,
+ [ASPEED_DEV_UART13] = 0x7E790700,
[ASPEED_DEV_WDT] = 0x7E785000,
[ASPEED_DEV_LPC] = 0x7E789000,
[ASPEED_DEV_I2C] = 0x7E7B0000,
};
static const int aspeed_soc_ast1030_irqmap[] = {
+ [ASPEED_DEV_UART1] = 47,
+ [ASPEED_DEV_UART2] = 48,
+ [ASPEED_DEV_UART3] = 49,
+ [ASPEED_DEV_UART4] = 50,
[ASPEED_DEV_UART5] = 8,
+ [ASPEED_DEV_UART6] = 57,
+ [ASPEED_DEV_UART7] = 58,
+ [ASPEED_DEV_UART8] = 59,
+ [ASPEED_DEV_UART9] = 60,
+ [ASPEED_DEV_UART10] = 61,
+ [ASPEED_DEV_UART11] = 62,
+ [ASPEED_DEV_UART12] = 63,
+ [ASPEED_DEV_UART13] = 64,
[ASPEED_DEV_GPIO] = 11,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_TIMER2] = 17,
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 4161a0cc4b..f3ecc0f3b7 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -61,7 +61,18 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_IBT] = 0x1E789140,
[ASPEED_DEV_I2C] = 0x1E78A000,
[ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
[ASPEED_DEV_UART5] = 0x1E784000,
+ [ASPEED_DEV_UART6] = 0x1E790000,
+ [ASPEED_DEV_UART7] = 0x1E790100,
+ [ASPEED_DEV_UART8] = 0x1E790200,
+ [ASPEED_DEV_UART9] = 0x1E790300,
+ [ASPEED_DEV_UART10] = 0x1E790400,
+ [ASPEED_DEV_UART11] = 0x1E790500,
+ [ASPEED_DEV_UART12] = 0x1E790600,
+ [ASPEED_DEV_UART13] = 0x1E790700,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_I3C] = 0x1E7A0000,
[ASPEED_DEV_SDRAM] = 0x80000000,
@@ -78,6 +89,14 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_DEV_UART3] = 49,
[ASPEED_DEV_UART4] = 50,
[ASPEED_DEV_UART5] = 8,
+ [ASPEED_DEV_UART6] = 57,
+ [ASPEED_DEV_UART7] = 58,
+ [ASPEED_DEV_UART8] = 59,
+ [ASPEED_DEV_UART9] = 60,
+ [ASPEED_DEV_UART10] = 61,
+ [ASPEED_DEV_UART11] = 62,
+ [ASPEED_DEV_UART12] = 63,
+ [ASPEED_DEV_UART13] = 64,
[ASPEED_DEV_VUART] = 8,
[ASPEED_DEV_FMC] = 39,
[ASPEED_DEV_SDMC] = 0,
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c339b5c74d..96bc060680 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -48,6 +48,9 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x40000000,
@@ -80,6 +83,9 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x80000000,
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3789f38603..709a78285b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -105,6 +105,14 @@ enum {
ASPEED_DEV_UART3,
ASPEED_DEV_UART4,
ASPEED_DEV_UART5,
+ ASPEED_DEV_UART6,
+ ASPEED_DEV_UART7,
+ ASPEED_DEV_UART8,
+ ASPEED_DEV_UART9,
+ ASPEED_DEV_UART10,
+ ASPEED_DEV_UART11,
+ ASPEED_DEV_UART12,
+ ASPEED_DEV_UART13,
ASPEED_DEV_VUART,
ASPEED_DEV_FMC,
ASPEED_DEV_SPI1,
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 1/5] hw: aspeed: Add missing UART's
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: pdel, irischenlj, qemu-arm, qemu-devel, clg, zev, openbmc,
andrew, peter.maydell, joel
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030
from UART6 to UART13. The addresses and interrupt numbers for these two
later chips are identical.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++
hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++
hw/arm/aspeed_soc.c | 6 ++++++
include/hw/arm/aspeed_soc.h | 8 ++++++++
4 files changed, 57 insertions(+)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 9ae9efaac1..fa2cc4406c 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -33,14 +33,38 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SBC] = 0x7E6F2000,
[ASPEED_DEV_GPIO] = 0x7E780000,
[ASPEED_DEV_TIMER1] = 0x7E782000,
+ [ASPEED_DEV_UART1] = 0x7E783000,
+ [ASPEED_DEV_UART2] = 0x7E78D000,
+ [ASPEED_DEV_UART3] = 0x7E78E000,
+ [ASPEED_DEV_UART4] = 0x7E78F000,
[ASPEED_DEV_UART5] = 0x7E784000,
+ [ASPEED_DEV_UART6] = 0x7E790000,
+ [ASPEED_DEV_UART7] = 0x7E790100,
+ [ASPEED_DEV_UART8] = 0x7E790200,
+ [ASPEED_DEV_UART9] = 0x7E790300,
+ [ASPEED_DEV_UART10] = 0x7E790400,
+ [ASPEED_DEV_UART11] = 0x7E790500,
+ [ASPEED_DEV_UART12] = 0x7E790600,
+ [ASPEED_DEV_UART13] = 0x7E790700,
[ASPEED_DEV_WDT] = 0x7E785000,
[ASPEED_DEV_LPC] = 0x7E789000,
[ASPEED_DEV_I2C] = 0x7E7B0000,
};
static const int aspeed_soc_ast1030_irqmap[] = {
+ [ASPEED_DEV_UART1] = 47,
+ [ASPEED_DEV_UART2] = 48,
+ [ASPEED_DEV_UART3] = 49,
+ [ASPEED_DEV_UART4] = 50,
[ASPEED_DEV_UART5] = 8,
+ [ASPEED_DEV_UART6] = 57,
+ [ASPEED_DEV_UART7] = 58,
+ [ASPEED_DEV_UART8] = 59,
+ [ASPEED_DEV_UART9] = 60,
+ [ASPEED_DEV_UART10] = 61,
+ [ASPEED_DEV_UART11] = 62,
+ [ASPEED_DEV_UART12] = 63,
+ [ASPEED_DEV_UART13] = 64,
[ASPEED_DEV_GPIO] = 11,
[ASPEED_DEV_TIMER1] = 16,
[ASPEED_DEV_TIMER2] = 17,
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index 4161a0cc4b..f3ecc0f3b7 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -61,7 +61,18 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
[ASPEED_DEV_IBT] = 0x1E789140,
[ASPEED_DEV_I2C] = 0x1E78A000,
[ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
[ASPEED_DEV_UART5] = 0x1E784000,
+ [ASPEED_DEV_UART6] = 0x1E790000,
+ [ASPEED_DEV_UART7] = 0x1E790100,
+ [ASPEED_DEV_UART8] = 0x1E790200,
+ [ASPEED_DEV_UART9] = 0x1E790300,
+ [ASPEED_DEV_UART10] = 0x1E790400,
+ [ASPEED_DEV_UART11] = 0x1E790500,
+ [ASPEED_DEV_UART12] = 0x1E790600,
+ [ASPEED_DEV_UART13] = 0x1E790700,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_I3C] = 0x1E7A0000,
[ASPEED_DEV_SDRAM] = 0x80000000,
@@ -78,6 +89,14 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_DEV_UART3] = 49,
[ASPEED_DEV_UART4] = 50,
[ASPEED_DEV_UART5] = 8,
+ [ASPEED_DEV_UART6] = 57,
+ [ASPEED_DEV_UART7] = 58,
+ [ASPEED_DEV_UART8] = 59,
+ [ASPEED_DEV_UART9] = 60,
+ [ASPEED_DEV_UART10] = 61,
+ [ASPEED_DEV_UART11] = 62,
+ [ASPEED_DEV_UART12] = 63,
+ [ASPEED_DEV_UART13] = 64,
[ASPEED_DEV_VUART] = 8,
[ASPEED_DEV_FMC] = 39,
[ASPEED_DEV_SDMC] = 0,
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c339b5c74d..96bc060680 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -48,6 +48,9 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x40000000,
@@ -80,6 +83,9 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
[ASPEED_DEV_ETH1] = 0x1E660000,
[ASPEED_DEV_ETH2] = 0x1E680000,
[ASPEED_DEV_UART1] = 0x1E783000,
+ [ASPEED_DEV_UART2] = 0x1E78D000,
+ [ASPEED_DEV_UART3] = 0x1E78E000,
+ [ASPEED_DEV_UART4] = 0x1E78F000,
[ASPEED_DEV_UART5] = 0x1E784000,
[ASPEED_DEV_VUART] = 0x1E787000,
[ASPEED_DEV_SDRAM] = 0x80000000,
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 3789f38603..709a78285b 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -105,6 +105,14 @@ enum {
ASPEED_DEV_UART3,
ASPEED_DEV_UART4,
ASPEED_DEV_UART5,
+ ASPEED_DEV_UART6,
+ ASPEED_DEV_UART7,
+ ASPEED_DEV_UART8,
+ ASPEED_DEV_UART9,
+ ASPEED_DEV_UART10,
+ ASPEED_DEV_UART11,
+ ASPEED_DEV_UART12,
+ ASPEED_DEV_UART13,
ASPEED_DEV_VUART,
ASPEED_DEV_FMC,
ASPEED_DEV_SPI1,
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/5] hw: aspeed: Add uarts_num SoC attribute
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 6:23 ` Peter Delevoryas
-1 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: peter.maydell, zev, andrew, irischenlj, openbmc, qemu-devel,
qemu-arm, clg, pdel, joel
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 1 +
hw/arm/aspeed_ast2600.c | 1 +
hw/arm/aspeed_soc.c | 2 ++
include/hw/arm/aspeed_soc.h | 1 +
4 files changed, 5 insertions(+)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index fa2cc4406c..bb8177e86c 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -301,6 +301,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
sc->ehcis_num = 0;
sc->wdts_num = 4;
sc->macs_num = 1;
+ sc->uarts_num = 13;
sc->irqmap = aspeed_soc_ast1030_irqmap;
sc->memmap = aspeed_soc_ast1030_memmap;
sc->num_cpus = 1;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index f3ecc0f3b7..a9523074a0 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -588,6 +588,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
sc->ehcis_num = 2;
sc->wdts_num = 4;
sc->macs_num = 4;
+ sc->uarts_num = 13;
sc->irqmap = aspeed_soc_ast2600_irqmap;
sc->memmap = aspeed_soc_ast2600_memmap;
sc->num_cpus = 2;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 96bc060680..7008cd1af7 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -490,6 +490,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
sc->ehcis_num = 1;
sc->wdts_num = 2;
sc->macs_num = 2;
+ sc->uarts_num = 5;
sc->irqmap = aspeed_soc_ast2400_irqmap;
sc->memmap = aspeed_soc_ast2400_memmap;
sc->num_cpus = 1;
@@ -516,6 +517,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
sc->ehcis_num = 2;
sc->wdts_num = 3;
sc->macs_num = 2;
+ sc->uarts_num = 5;
sc->irqmap = aspeed_soc_ast2500_irqmap;
sc->memmap = aspeed_soc_ast2500_memmap;
sc->num_cpus = 1;
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 709a78285b..669bc49855 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -91,6 +91,7 @@ struct AspeedSoCClass {
int ehcis_num;
int wdts_num;
int macs_num;
+ int uarts_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/5] hw: aspeed: Add uarts_num SoC attribute
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: pdel, irischenlj, qemu-arm, qemu-devel, clg, zev, openbmc,
andrew, peter.maydell, joel
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 1 +
hw/arm/aspeed_ast2600.c | 1 +
hw/arm/aspeed_soc.c | 2 ++
include/hw/arm/aspeed_soc.h | 1 +
4 files changed, 5 insertions(+)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index fa2cc4406c..bb8177e86c 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -301,6 +301,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
sc->ehcis_num = 0;
sc->wdts_num = 4;
sc->macs_num = 1;
+ sc->uarts_num = 13;
sc->irqmap = aspeed_soc_ast1030_irqmap;
sc->memmap = aspeed_soc_ast1030_memmap;
sc->num_cpus = 1;
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index f3ecc0f3b7..a9523074a0 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -588,6 +588,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
sc->ehcis_num = 2;
sc->wdts_num = 4;
sc->macs_num = 4;
+ sc->uarts_num = 13;
sc->irqmap = aspeed_soc_ast2600_irqmap;
sc->memmap = aspeed_soc_ast2600_memmap;
sc->num_cpus = 2;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 96bc060680..7008cd1af7 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -490,6 +490,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
sc->ehcis_num = 1;
sc->wdts_num = 2;
sc->macs_num = 2;
+ sc->uarts_num = 5;
sc->irqmap = aspeed_soc_ast2400_irqmap;
sc->memmap = aspeed_soc_ast2400_memmap;
sc->num_cpus = 1;
@@ -516,6 +517,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
sc->ehcis_num = 2;
sc->wdts_num = 3;
sc->macs_num = 2;
+ sc->uarts_num = 5;
sc->irqmap = aspeed_soc_ast2500_irqmap;
sc->memmap = aspeed_soc_ast2500_memmap;
sc->num_cpus = 1;
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 709a78285b..669bc49855 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -91,6 +91,7 @@ struct AspeedSoCClass {
int ehcis_num;
int wdts_num;
int macs_num;
+ int uarts_num;
const int *irqmap;
const hwaddr *memmap;
uint32_t num_cpus;
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/5] hw: aspeed: Ensure AST1030 respects uart-default
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 6:23 ` Peter Delevoryas
-1 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: peter.maydell, zev, andrew, irischenlj, openbmc, qemu-devel,
qemu-arm, clg, pdel, joel
The AST1030 machine initialization was not respecting the Aspeed SoC
property "uart-default", which specifies which UART should be connected to
the first serial device, it was just always connecting UART5. This doesn't
change any behavior, because the default value for "uart-default" is UART5,
but it makes it possible to override this in new machine definitions using
the AST1030.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index bb8177e86c..faafb800f3 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -215,9 +215,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&s->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
- /* UART5 - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
- aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
+ /* UART - attach an 8250 to the IO space as our UART */
+ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
+ aspeed_soc_get_irq(s, s->uart_default),
38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* Timer */
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/5] hw: aspeed: Ensure AST1030 respects uart-default
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: pdel, irischenlj, qemu-arm, qemu-devel, clg, zev, openbmc,
andrew, peter.maydell, joel
The AST1030 machine initialization was not respecting the Aspeed SoC
property "uart-default", which specifies which UART should be connected to
the first serial device, it was just always connecting UART5. This doesn't
change any behavior, because the default value for "uart-default" is UART5,
but it makes it possible to override this in new machine definitions using
the AST1030.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index bb8177e86c..faafb800f3 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -215,9 +215,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&s->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
- /* UART5 - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
- aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
+ /* UART - attach an 8250 to the IO space as our UART */
+ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
+ aspeed_soc_get_irq(s, s->uart_default),
38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
/* Timer */
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 4/5] hw: aspeed: Introduce common UART init function
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 6:23 ` Peter Delevoryas
-1 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: peter.maydell, zev, andrew, irischenlj, openbmc, qemu-devel,
qemu-arm, clg, pdel, joel
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 7 ++-----
hw/arm/aspeed_ast2600.c | 7 ++-----
hw/arm/aspeed_soc.c | 16 ++++++++++++----
include/hw/arm/aspeed_soc.h | 1 +
4 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index faafb800f3..938615d55f 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -15,7 +15,6 @@
#include "sysemu/sysemu.h"
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
-#include "hw/char/serial.h"
#include "hw/arm/aspeed_soc.h"
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
@@ -215,10 +214,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&s->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
- /* UART - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
- aspeed_soc_get_irq(s, s->uart_default),
- 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ /* UART */
+ aspeed_soc_uart_init(s);
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a9523074a0..b0a4199b69 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -11,7 +11,6 @@
#include "qapi/error.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
-#include "hw/char/serial.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
@@ -372,10 +371,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
- /* UART - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
- aspeed_soc_get_irq(s, s->uart_default), 38400,
- serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ /* UART */
+ aspeed_soc_uart_init(s);
/* I2C */
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 7008cd1af7..912798a9c9 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -303,10 +303,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
- /* UART - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
- aspeed_soc_get_irq(s, s->uart_default), 38400,
- serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ /* UART */
+ aspeed_soc_uart_init(s);
/* I2C */
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
@@ -544,3 +542,13 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
{
return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
}
+
+void aspeed_soc_uart_init(AspeedSoCState *s)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ /* Attach an 8250 to the IO space as our UART */
+ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
+ aspeed_soc_get_irq(s, s->uart_default), 38400,
+ serial_hd(0), DEVICE_LITTLE_ENDIAN);
+}
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 669bc49855..02a5a9ffcb 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -164,5 +164,6 @@ enum {
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
+void aspeed_soc_uart_init(AspeedSoCState *s);
#endif /* ASPEED_SOC_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 4/5] hw: aspeed: Introduce common UART init function
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: pdel, irischenlj, qemu-arm, qemu-devel, clg, zev, openbmc,
andrew, peter.maydell, joel
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_ast10x0.c | 7 ++-----
hw/arm/aspeed_ast2600.c | 7 ++-----
hw/arm/aspeed_soc.c | 16 ++++++++++++----
include/hw/arm/aspeed_soc.h | 1 +
4 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index faafb800f3..938615d55f 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -15,7 +15,6 @@
#include "sysemu/sysemu.h"
#include "hw/qdev-clock.h"
#include "hw/misc/unimp.h"
-#include "hw/char/serial.h"
#include "hw/arm/aspeed_soc.h"
#define ASPEED_SOC_IOMEM_SIZE 0x00200000
@@ -215,10 +214,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
qdev_get_gpio_in(DEVICE(&s->armv7m),
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
- /* UART - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
- aspeed_soc_get_irq(s, s->uart_default),
- 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ /* UART */
+ aspeed_soc_uart_init(s);
/* Timer */
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a9523074a0..b0a4199b69 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -11,7 +11,6 @@
#include "qapi/error.h"
#include "hw/misc/unimp.h"
#include "hw/arm/aspeed_soc.h"
-#include "hw/char/serial.h"
#include "qemu/module.h"
#include "qemu/error-report.h"
#include "hw/i2c/aspeed_i2c.h"
@@ -372,10 +371,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
- /* UART - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
- aspeed_soc_get_irq(s, s->uart_default), 38400,
- serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ /* UART */
+ aspeed_soc_uart_init(s);
/* I2C */
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 7008cd1af7..912798a9c9 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -303,10 +303,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
- /* UART - attach an 8250 to the IO space as our UART */
- serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
- aspeed_soc_get_irq(s, s->uart_default), 38400,
- serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ /* UART */
+ aspeed_soc_uart_init(s);
/* I2C */
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
@@ -544,3 +542,13 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
{
return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
}
+
+void aspeed_soc_uart_init(AspeedSoCState *s)
+{
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ /* Attach an 8250 to the IO space as our UART */
+ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
+ aspeed_soc_get_irq(s, s->uart_default), 38400,
+ serial_hd(0), DEVICE_LITTLE_ENDIAN);
+}
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 669bc49855..02a5a9ffcb 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -164,5 +164,6 @@ enum {
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
+void aspeed_soc_uart_init(AspeedSoCState *s);
#endif /* ASPEED_SOC_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 5/5] hw: aspeed: Init all UART's with serial devices
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 6:23 ` Peter Delevoryas
-1 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: peter.maydell, zev, andrew, irischenlj, openbmc, qemu-devel,
qemu-arm, clg, pdel, joel
Background:
AspeedMachineClass.uart_default specifies the serial console UART, which
usually corresponds to the "stdout-path" in the device tree.
The default value is UART5, since most boards use UART5 for this:
amc->uart_default = ASPEED_DEV_UART5;
Users can override AspeedMachineClass.uart_default in their board's machine
class init to specify something besides UART5. For example, for fuji-bmc:
amc->uart_default = ASPEED_DEV_UART1;
We only connect this one UART, of the 5 UART's on the AST2400 and AST2500
and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU
users can use. None of the other UART's are initialized, and the only way
to override this attribute is by creating a specialized board definition,
requiring QEMU source code changes and rebuilding.
The result of this is that if you want to get serial console output on a
board that uses UART3, you need to add a board definition. This was
encountered by Zev in OpenBMC. [1]
Changes:
This commit initializes all of the UART's present on each Aspeed chip with
serial devices and allows the QEMU user to connect as many or few as they
like to serial devices. For example, you can still run QEMU and just connect
stdout to the machine's default UART, without specifying any additional
serial devices:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
However, if you don't want to add a special machine definition, you can now
manually configure UART1 to connect to stdout and get serial console output,
even if the machine's default is UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
In the example above, the first "-serial null" argument is connected to
UART5, and "-serial mon:stdio" is connected to UART1.
Another example: you can get serial console output from Wedge100, which uses
UART3, by reusing the palmetto AST2400 machine and rewiring the serial
device arguments:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
There is a slight change in behavior introduced with this change: now, each
UART's memory-mapped IO region will have a serial device model connected to
it. Previously, all reads and writes to those regions would be ineffective
and return zero values, but now some values will be nonzero, even when the
user doesn't connect a serial device backend (like a socket, file, etc). For
example, the line status register might indicate that the transmit buffer is
empty now, whereas previously it might have always indicated it was full.
[1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/
[2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
[3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_soc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 912798a9c9..30574d4276 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -546,9 +546,18 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
void aspeed_soc_uart_init(AspeedSoCState *s)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i, uart;
/* Attach an 8250 to the IO space as our UART */
serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
aspeed_soc_get_irq(s, s->uart_default), 38400,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+ if (uart == s->uart_default) {
+ uart++;
+ }
+ serial_mm_init(get_system_memory(), sc->memmap[uart], 2,
+ aspeed_soc_get_irq(s, uart), 38400,
+ serial_hd(i), DEVICE_LITTLE_ENDIAN);
+ }
}
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 5/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 6:23 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 6:23 UTC (permalink / raw)
Cc: pdel, irischenlj, qemu-arm, qemu-devel, clg, zev, openbmc,
andrew, peter.maydell, joel
Background:
AspeedMachineClass.uart_default specifies the serial console UART, which
usually corresponds to the "stdout-path" in the device tree.
The default value is UART5, since most boards use UART5 for this:
amc->uart_default = ASPEED_DEV_UART5;
Users can override AspeedMachineClass.uart_default in their board's machine
class init to specify something besides UART5. For example, for fuji-bmc:
amc->uart_default = ASPEED_DEV_UART1;
We only connect this one UART, of the 5 UART's on the AST2400 and AST2500
and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU
users can use. None of the other UART's are initialized, and the only way
to override this attribute is by creating a specialized board definition,
requiring QEMU source code changes and rebuilding.
The result of this is that if you want to get serial console output on a
board that uses UART3, you need to add a board definition. This was
encountered by Zev in OpenBMC. [1]
Changes:
This commit initializes all of the UART's present on each Aspeed chip with
serial devices and allows the QEMU user to connect as many or few as they
like to serial devices. For example, you can still run QEMU and just connect
stdout to the machine's default UART, without specifying any additional
serial devices:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
However, if you don't want to add a special machine definition, you can now
manually configure UART1 to connect to stdout and get serial console output,
even if the machine's default is UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
In the example above, the first "-serial null" argument is connected to
UART5, and "-serial mon:stdio" is connected to UART1.
Another example: you can get serial console output from Wedge100, which uses
UART3, by reusing the palmetto AST2400 machine and rewiring the serial
device arguments:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
There is a slight change in behavior introduced with this change: now, each
UART's memory-mapped IO region will have a serial device model connected to
it. Previously, all reads and writes to those regions would be ineffective
and return zero values, but now some values will be nonzero, even when the
user doesn't connect a serial device backend (like a socket, file, etc). For
example, the line status register might indicate that the transmit buffer is
empty now, whereas previously it might have always indicated it was full.
[1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/
[2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
[3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
hw/arm/aspeed_soc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 912798a9c9..30574d4276 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -546,9 +546,18 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
void aspeed_soc_uart_init(AspeedSoCState *s)
{
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ int i, uart;
/* Attach an 8250 to the IO space as our UART */
serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
aspeed_soc_get_irq(s, s->uart_default), 38400,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
+ if (uart == s->uart_default) {
+ uart++;
+ }
+ serial_mm_init(get_system_memory(), sc->memmap[uart], 2,
+ aspeed_soc_get_irq(s, uart), 38400,
+ serial_hd(i), DEVICE_LITTLE_ENDIAN);
+ }
}
--
2.30.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 7:18 ` Cédric Le Goater
-1 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:18 UTC (permalink / raw)
To: Peter Delevoryas
Cc: irischenlj, qemu-arm, qemu-devel, zev, openbmc, andrew,
peter.maydell, joel, Jamin Lin
On 5/16/22 08:23, Peter Delevoryas wrote:
> v2:
> - Rebased on Cedric's irq proposal. [1]
> - Added "Introduce common UART init function" patch
> - Added "Add uarts_num SoC attribute" patch
> - Rewrote last commit's message for clarity
Looks good to me.
> I tried testing this by running acceptance tests, particularly the
> boot_linux_console.py file, but I had to disable the raspi2_initrd case.
> It's not related to my changes (A/B tested and it fails on upstream/master
> too), but thought I would mention that.>
> I also manually tested several machines:
>
> AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
> AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
> AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
> AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
>
> [1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
I have quite a few images which I run manually. OpenBMC is providing
images, Aspeed also. Joel did a small tool for the IBM rainier :
https://github.com/shenki/qemu-boot-test
Having an automated framework for Aspeed machines pulling images
from different places would be nice but we cannot put all under
QEMU.
I like the buildroot CI using the QEMU boards. See a pipeline example:
https://gitlab.com/legoater/buildroot/-/pipelines/539559209
but that's buildroot only and integrating a custom uboot might be
difficult.
For my ppc needs, I did a quick-and-dirty non-regression test suite :
https://github.com/legoater/qemu-ppc-boot
Anyway, I haven't found a solution nor spent much time on it but
I am interested !
C.
>
> Peter Delevoryas (5):
> hw: aspeed: Add missing UART's
> hw: aspeed: Add uarts_num SoC attribute
> hw: aspeed: Ensure AST1030 respects uart-default
> hw: aspeed: Introduce common UART init function
> hw: aspeed: Init all UART's with serial devices
>
> hw/arm/aspeed_ast10x0.c | 32 +++++++++++++++++++++++++++-----
> hw/arm/aspeed_ast2600.c | 27 ++++++++++++++++++++++-----
> hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++++----
> include/hw/arm/aspeed_soc.h | 10 ++++++++++
> 4 files changed, 88 insertions(+), 14 deletions(-)
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 7:18 ` Cédric Le Goater
0 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:18 UTC (permalink / raw)
To: Peter Delevoryas
Cc: peter.maydell, Jamin Lin, zev, andrew, irischenlj, openbmc,
qemu-devel, qemu-arm, joel
On 5/16/22 08:23, Peter Delevoryas wrote:
> v2:
> - Rebased on Cedric's irq proposal. [1]
> - Added "Introduce common UART init function" patch
> - Added "Add uarts_num SoC attribute" patch
> - Rewrote last commit's message for clarity
Looks good to me.
> I tried testing this by running acceptance tests, particularly the
> boot_linux_console.py file, but I had to disable the raspi2_initrd case.
> It's not related to my changes (A/B tested and it fails on upstream/master
> too), but thought I would mention that.>
> I also manually tested several machines:
>
> AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
> AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
> AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
> AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
>
> [1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
I have quite a few images which I run manually. OpenBMC is providing
images, Aspeed also. Joel did a small tool for the IBM rainier :
https://github.com/shenki/qemu-boot-test
Having an automated framework for Aspeed machines pulling images
from different places would be nice but we cannot put all under
QEMU.
I like the buildroot CI using the QEMU boards. See a pipeline example:
https://gitlab.com/legoater/buildroot/-/pipelines/539559209
but that's buildroot only and integrating a custom uboot might be
difficult.
For my ppc needs, I did a quick-and-dirty non-regression test suite :
https://github.com/legoater/qemu-ppc-boot
Anyway, I haven't found a solution nor spent much time on it but
I am interested !
C.
>
> Peter Delevoryas (5):
> hw: aspeed: Add missing UART's
> hw: aspeed: Add uarts_num SoC attribute
> hw: aspeed: Ensure AST1030 respects uart-default
> hw: aspeed: Introduce common UART init function
> hw: aspeed: Init all UART's with serial devices
>
> hw/arm/aspeed_ast10x0.c | 32 +++++++++++++++++++++++++++-----
> hw/arm/aspeed_ast2600.c | 27 ++++++++++++++++++++++-----
> hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++++----
> include/hw/arm/aspeed_soc.h | 10 ++++++++++
> 4 files changed, 88 insertions(+), 14 deletions(-)
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 1/5] hw: aspeed: Add missing UART's
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 7:19 ` Cédric Le Goater
-1 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:19 UTC (permalink / raw)
To: Peter Delevoryas
Cc: peter.maydell, Jamin Lin, zev, andrew, irischenlj, openbmc,
qemu-devel, qemu-arm, joel
On 5/16/22 08:23, Peter Delevoryas wrote:
> This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
> AST2600, and AST1030.
>
> This also includes the new UART interfaces added in the AST2600 and AST1030
> from UART6 to UART13. The addresses and interrupt numbers for these two
> later chips are identical.
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++
> hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++
> hw/arm/aspeed_soc.c | 6 ++++++
> include/hw/arm/aspeed_soc.h | 8 ++++++++
> 4 files changed, 57 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 9ae9efaac1..fa2cc4406c 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -33,14 +33,38 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
> [ASPEED_DEV_SBC] = 0x7E6F2000,
> [ASPEED_DEV_GPIO] = 0x7E780000,
> [ASPEED_DEV_TIMER1] = 0x7E782000,
> + [ASPEED_DEV_UART1] = 0x7E783000,
> + [ASPEED_DEV_UART2] = 0x7E78D000,
> + [ASPEED_DEV_UART3] = 0x7E78E000,
> + [ASPEED_DEV_UART4] = 0x7E78F000,
> [ASPEED_DEV_UART5] = 0x7E784000,
> + [ASPEED_DEV_UART6] = 0x7E790000,
> + [ASPEED_DEV_UART7] = 0x7E790100,
> + [ASPEED_DEV_UART8] = 0x7E790200,
> + [ASPEED_DEV_UART9] = 0x7E790300,
> + [ASPEED_DEV_UART10] = 0x7E790400,
> + [ASPEED_DEV_UART11] = 0x7E790500,
> + [ASPEED_DEV_UART12] = 0x7E790600,
> + [ASPEED_DEV_UART13] = 0x7E790700,
> [ASPEED_DEV_WDT] = 0x7E785000,
> [ASPEED_DEV_LPC] = 0x7E789000,
> [ASPEED_DEV_I2C] = 0x7E7B0000,
> };
>
> static const int aspeed_soc_ast1030_irqmap[] = {
> + [ASPEED_DEV_UART1] = 47,
> + [ASPEED_DEV_UART2] = 48,
> + [ASPEED_DEV_UART3] = 49,
> + [ASPEED_DEV_UART4] = 50,
> [ASPEED_DEV_UART5] = 8,
> + [ASPEED_DEV_UART6] = 57,
> + [ASPEED_DEV_UART7] = 58,
> + [ASPEED_DEV_UART8] = 59,
> + [ASPEED_DEV_UART9] = 60,
> + [ASPEED_DEV_UART10] = 61,
> + [ASPEED_DEV_UART11] = 62,
> + [ASPEED_DEV_UART12] = 63,
> + [ASPEED_DEV_UART13] = 64,
> [ASPEED_DEV_GPIO] = 11,
> [ASPEED_DEV_TIMER1] = 16,
> [ASPEED_DEV_TIMER2] = 17,
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index 4161a0cc4b..f3ecc0f3b7 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -61,7 +61,18 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
> [ASPEED_DEV_IBT] = 0x1E789140,
> [ASPEED_DEV_I2C] = 0x1E78A000,
> [ASPEED_DEV_UART1] = 0x1E783000,
> + [ASPEED_DEV_UART2] = 0x1E78D000,
> + [ASPEED_DEV_UART3] = 0x1E78E000,
> + [ASPEED_DEV_UART4] = 0x1E78F000,
> [ASPEED_DEV_UART5] = 0x1E784000,
> + [ASPEED_DEV_UART6] = 0x1E790000,
> + [ASPEED_DEV_UART7] = 0x1E790100,
> + [ASPEED_DEV_UART8] = 0x1E790200,
> + [ASPEED_DEV_UART9] = 0x1E790300,
> + [ASPEED_DEV_UART10] = 0x1E790400,
> + [ASPEED_DEV_UART11] = 0x1E790500,
> + [ASPEED_DEV_UART12] = 0x1E790600,
> + [ASPEED_DEV_UART13] = 0x1E790700,
> [ASPEED_DEV_VUART] = 0x1E787000,
> [ASPEED_DEV_I3C] = 0x1E7A0000,
> [ASPEED_DEV_SDRAM] = 0x80000000,
> @@ -78,6 +89,14 @@ static const int aspeed_soc_ast2600_irqmap[] = {
> [ASPEED_DEV_UART3] = 49,
> [ASPEED_DEV_UART4] = 50,
> [ASPEED_DEV_UART5] = 8,
> + [ASPEED_DEV_UART6] = 57,
> + [ASPEED_DEV_UART7] = 58,
> + [ASPEED_DEV_UART8] = 59,
> + [ASPEED_DEV_UART9] = 60,
> + [ASPEED_DEV_UART10] = 61,
> + [ASPEED_DEV_UART11] = 62,
> + [ASPEED_DEV_UART12] = 63,
> + [ASPEED_DEV_UART13] = 64,
> [ASPEED_DEV_VUART] = 8,
> [ASPEED_DEV_FMC] = 39,
> [ASPEED_DEV_SDMC] = 0,
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index c339b5c74d..96bc060680 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -48,6 +48,9 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
> [ASPEED_DEV_ETH1] = 0x1E660000,
> [ASPEED_DEV_ETH2] = 0x1E680000,
> [ASPEED_DEV_UART1] = 0x1E783000,
> + [ASPEED_DEV_UART2] = 0x1E78D000,
> + [ASPEED_DEV_UART3] = 0x1E78E000,
> + [ASPEED_DEV_UART4] = 0x1E78F000,
> [ASPEED_DEV_UART5] = 0x1E784000,
> [ASPEED_DEV_VUART] = 0x1E787000,
> [ASPEED_DEV_SDRAM] = 0x40000000,
> @@ -80,6 +83,9 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
> [ASPEED_DEV_ETH1] = 0x1E660000,
> [ASPEED_DEV_ETH2] = 0x1E680000,
> [ASPEED_DEV_UART1] = 0x1E783000,
> + [ASPEED_DEV_UART2] = 0x1E78D000,
> + [ASPEED_DEV_UART3] = 0x1E78E000,
> + [ASPEED_DEV_UART4] = 0x1E78F000,
> [ASPEED_DEV_UART5] = 0x1E784000,
> [ASPEED_DEV_VUART] = 0x1E787000,
> [ASPEED_DEV_SDRAM] = 0x80000000,
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 3789f38603..709a78285b 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -105,6 +105,14 @@ enum {
> ASPEED_DEV_UART3,
> ASPEED_DEV_UART4,
> ASPEED_DEV_UART5,
> + ASPEED_DEV_UART6,
> + ASPEED_DEV_UART7,
> + ASPEED_DEV_UART8,
> + ASPEED_DEV_UART9,
> + ASPEED_DEV_UART10,
> + ASPEED_DEV_UART11,
> + ASPEED_DEV_UART12,
> + ASPEED_DEV_UART13,
> ASPEED_DEV_VUART,
> ASPEED_DEV_FMC,
> ASPEED_DEV_SPI1,
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 1/5] hw: aspeed: Add missing UART's
@ 2022-05-16 7:19 ` Cédric Le Goater
0 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:19 UTC (permalink / raw)
To: Peter Delevoryas
Cc: irischenlj, qemu-arm, qemu-devel, zev, openbmc, andrew,
peter.maydell, joel, Jamin Lin
On 5/16/22 08:23, Peter Delevoryas wrote:
> This adds the missing UART memory and IRQ mappings for the AST2400, AST2500,
> AST2600, and AST1030.
>
> This also includes the new UART interfaces added in the AST2600 and AST1030
> from UART6 to UART13. The addresses and interrupt numbers for these two
> later chips are identical.
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++
> hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++
> hw/arm/aspeed_soc.c | 6 ++++++
> include/hw/arm/aspeed_soc.h | 8 ++++++++
> 4 files changed, 57 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index 9ae9efaac1..fa2cc4406c 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -33,14 +33,38 @@ static const hwaddr aspeed_soc_ast1030_memmap[] = {
> [ASPEED_DEV_SBC] = 0x7E6F2000,
> [ASPEED_DEV_GPIO] = 0x7E780000,
> [ASPEED_DEV_TIMER1] = 0x7E782000,
> + [ASPEED_DEV_UART1] = 0x7E783000,
> + [ASPEED_DEV_UART2] = 0x7E78D000,
> + [ASPEED_DEV_UART3] = 0x7E78E000,
> + [ASPEED_DEV_UART4] = 0x7E78F000,
> [ASPEED_DEV_UART5] = 0x7E784000,
> + [ASPEED_DEV_UART6] = 0x7E790000,
> + [ASPEED_DEV_UART7] = 0x7E790100,
> + [ASPEED_DEV_UART8] = 0x7E790200,
> + [ASPEED_DEV_UART9] = 0x7E790300,
> + [ASPEED_DEV_UART10] = 0x7E790400,
> + [ASPEED_DEV_UART11] = 0x7E790500,
> + [ASPEED_DEV_UART12] = 0x7E790600,
> + [ASPEED_DEV_UART13] = 0x7E790700,
> [ASPEED_DEV_WDT] = 0x7E785000,
> [ASPEED_DEV_LPC] = 0x7E789000,
> [ASPEED_DEV_I2C] = 0x7E7B0000,
> };
>
> static const int aspeed_soc_ast1030_irqmap[] = {
> + [ASPEED_DEV_UART1] = 47,
> + [ASPEED_DEV_UART2] = 48,
> + [ASPEED_DEV_UART3] = 49,
> + [ASPEED_DEV_UART4] = 50,
> [ASPEED_DEV_UART5] = 8,
> + [ASPEED_DEV_UART6] = 57,
> + [ASPEED_DEV_UART7] = 58,
> + [ASPEED_DEV_UART8] = 59,
> + [ASPEED_DEV_UART9] = 60,
> + [ASPEED_DEV_UART10] = 61,
> + [ASPEED_DEV_UART11] = 62,
> + [ASPEED_DEV_UART12] = 63,
> + [ASPEED_DEV_UART13] = 64,
> [ASPEED_DEV_GPIO] = 11,
> [ASPEED_DEV_TIMER1] = 16,
> [ASPEED_DEV_TIMER2] = 17,
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index 4161a0cc4b..f3ecc0f3b7 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -61,7 +61,18 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
> [ASPEED_DEV_IBT] = 0x1E789140,
> [ASPEED_DEV_I2C] = 0x1E78A000,
> [ASPEED_DEV_UART1] = 0x1E783000,
> + [ASPEED_DEV_UART2] = 0x1E78D000,
> + [ASPEED_DEV_UART3] = 0x1E78E000,
> + [ASPEED_DEV_UART4] = 0x1E78F000,
> [ASPEED_DEV_UART5] = 0x1E784000,
> + [ASPEED_DEV_UART6] = 0x1E790000,
> + [ASPEED_DEV_UART7] = 0x1E790100,
> + [ASPEED_DEV_UART8] = 0x1E790200,
> + [ASPEED_DEV_UART9] = 0x1E790300,
> + [ASPEED_DEV_UART10] = 0x1E790400,
> + [ASPEED_DEV_UART11] = 0x1E790500,
> + [ASPEED_DEV_UART12] = 0x1E790600,
> + [ASPEED_DEV_UART13] = 0x1E790700,
> [ASPEED_DEV_VUART] = 0x1E787000,
> [ASPEED_DEV_I3C] = 0x1E7A0000,
> [ASPEED_DEV_SDRAM] = 0x80000000,
> @@ -78,6 +89,14 @@ static const int aspeed_soc_ast2600_irqmap[] = {
> [ASPEED_DEV_UART3] = 49,
> [ASPEED_DEV_UART4] = 50,
> [ASPEED_DEV_UART5] = 8,
> + [ASPEED_DEV_UART6] = 57,
> + [ASPEED_DEV_UART7] = 58,
> + [ASPEED_DEV_UART8] = 59,
> + [ASPEED_DEV_UART9] = 60,
> + [ASPEED_DEV_UART10] = 61,
> + [ASPEED_DEV_UART11] = 62,
> + [ASPEED_DEV_UART12] = 63,
> + [ASPEED_DEV_UART13] = 64,
> [ASPEED_DEV_VUART] = 8,
> [ASPEED_DEV_FMC] = 39,
> [ASPEED_DEV_SDMC] = 0,
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index c339b5c74d..96bc060680 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -48,6 +48,9 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = {
> [ASPEED_DEV_ETH1] = 0x1E660000,
> [ASPEED_DEV_ETH2] = 0x1E680000,
> [ASPEED_DEV_UART1] = 0x1E783000,
> + [ASPEED_DEV_UART2] = 0x1E78D000,
> + [ASPEED_DEV_UART3] = 0x1E78E000,
> + [ASPEED_DEV_UART4] = 0x1E78F000,
> [ASPEED_DEV_UART5] = 0x1E784000,
> [ASPEED_DEV_VUART] = 0x1E787000,
> [ASPEED_DEV_SDRAM] = 0x40000000,
> @@ -80,6 +83,9 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = {
> [ASPEED_DEV_ETH1] = 0x1E660000,
> [ASPEED_DEV_ETH2] = 0x1E680000,
> [ASPEED_DEV_UART1] = 0x1E783000,
> + [ASPEED_DEV_UART2] = 0x1E78D000,
> + [ASPEED_DEV_UART3] = 0x1E78E000,
> + [ASPEED_DEV_UART4] = 0x1E78F000,
> [ASPEED_DEV_UART5] = 0x1E784000,
> [ASPEED_DEV_VUART] = 0x1E787000,
> [ASPEED_DEV_SDRAM] = 0x80000000,
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 3789f38603..709a78285b 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -105,6 +105,14 @@ enum {
> ASPEED_DEV_UART3,
> ASPEED_DEV_UART4,
> ASPEED_DEV_UART5,
> + ASPEED_DEV_UART6,
> + ASPEED_DEV_UART7,
> + ASPEED_DEV_UART8,
> + ASPEED_DEV_UART9,
> + ASPEED_DEV_UART10,
> + ASPEED_DEV_UART11,
> + ASPEED_DEV_UART12,
> + ASPEED_DEV_UART13,
> ASPEED_DEV_VUART,
> ASPEED_DEV_FMC,
> ASPEED_DEV_SPI1,
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/5] hw: aspeed: Add uarts_num SoC attribute
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 7:20 ` Cédric Le Goater
-1 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:20 UTC (permalink / raw)
To: Peter Delevoryas
Cc: irischenlj, qemu-arm, qemu-devel, zev, openbmc, andrew,
peter.maydell, joel, Jamin Lin
On 5/16/22 08:23, Peter Delevoryas wrote:
> AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 1 +
> hw/arm/aspeed_ast2600.c | 1 +
> hw/arm/aspeed_soc.c | 2 ++
> include/hw/arm/aspeed_soc.h | 1 +
> 4 files changed, 5 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index fa2cc4406c..bb8177e86c 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -301,6 +301,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> sc->ehcis_num = 0;
> sc->wdts_num = 4;
> sc->macs_num = 1;
> + sc->uarts_num = 13;
> sc->irqmap = aspeed_soc_ast1030_irqmap;
> sc->memmap = aspeed_soc_ast1030_memmap;
> sc->num_cpus = 1;
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index f3ecc0f3b7..a9523074a0 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -588,6 +588,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
> sc->ehcis_num = 2;
> sc->wdts_num = 4;
> sc->macs_num = 4;
> + sc->uarts_num = 13;
> sc->irqmap = aspeed_soc_ast2600_irqmap;
> sc->memmap = aspeed_soc_ast2600_memmap;
> sc->num_cpus = 2;
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 96bc060680..7008cd1af7 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -490,6 +490,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> sc->ehcis_num = 1;
> sc->wdts_num = 2;
> sc->macs_num = 2;
> + sc->uarts_num = 5;
> sc->irqmap = aspeed_soc_ast2400_irqmap;
> sc->memmap = aspeed_soc_ast2400_memmap;
> sc->num_cpus = 1;
> @@ -516,6 +517,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> sc->ehcis_num = 2;
> sc->wdts_num = 3;
> sc->macs_num = 2;
> + sc->uarts_num = 5;
> sc->irqmap = aspeed_soc_ast2500_irqmap;
> sc->memmap = aspeed_soc_ast2500_memmap;
> sc->num_cpus = 1;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 709a78285b..669bc49855 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -91,6 +91,7 @@ struct AspeedSoCClass {
> int ehcis_num;
> int wdts_num;
> int macs_num;
> + int uarts_num;
> const int *irqmap;
> const hwaddr *memmap;
> uint32_t num_cpus;
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/5] hw: aspeed: Add uarts_num SoC attribute
@ 2022-05-16 7:20 ` Cédric Le Goater
0 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:20 UTC (permalink / raw)
To: Peter Delevoryas
Cc: peter.maydell, Jamin Lin, zev, andrew, irischenlj, openbmc,
qemu-devel, qemu-arm, joel
On 5/16/22 08:23, Peter Delevoryas wrote:
> AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 1 +
> hw/arm/aspeed_ast2600.c | 1 +
> hw/arm/aspeed_soc.c | 2 ++
> include/hw/arm/aspeed_soc.h | 1 +
> 4 files changed, 5 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index fa2cc4406c..bb8177e86c 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -301,6 +301,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
> sc->ehcis_num = 0;
> sc->wdts_num = 4;
> sc->macs_num = 1;
> + sc->uarts_num = 13;
> sc->irqmap = aspeed_soc_ast1030_irqmap;
> sc->memmap = aspeed_soc_ast1030_memmap;
> sc->num_cpus = 1;
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index f3ecc0f3b7..a9523074a0 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -588,6 +588,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
> sc->ehcis_num = 2;
> sc->wdts_num = 4;
> sc->macs_num = 4;
> + sc->uarts_num = 13;
> sc->irqmap = aspeed_soc_ast2600_irqmap;
> sc->memmap = aspeed_soc_ast2600_memmap;
> sc->num_cpus = 2;
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 96bc060680..7008cd1af7 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -490,6 +490,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
> sc->ehcis_num = 1;
> sc->wdts_num = 2;
> sc->macs_num = 2;
> + sc->uarts_num = 5;
> sc->irqmap = aspeed_soc_ast2400_irqmap;
> sc->memmap = aspeed_soc_ast2400_memmap;
> sc->num_cpus = 1;
> @@ -516,6 +517,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
> sc->ehcis_num = 2;
> sc->wdts_num = 3;
> sc->macs_num = 2;
> + sc->uarts_num = 5;
> sc->irqmap = aspeed_soc_ast2500_irqmap;
> sc->memmap = aspeed_soc_ast2500_memmap;
> sc->num_cpus = 1;
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 709a78285b..669bc49855 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -91,6 +91,7 @@ struct AspeedSoCClass {
> int ehcis_num;
> int wdts_num;
> int macs_num;
> + int uarts_num;
> const int *irqmap;
> const hwaddr *memmap;
> uint32_t num_cpus;
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 3/5] hw: aspeed: Ensure AST1030 respects uart-default
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 7:20 ` Cédric Le Goater
-1 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:20 UTC (permalink / raw)
To: Peter Delevoryas
Cc: irischenlj, qemu-arm, qemu-devel, zev, openbmc, andrew,
peter.maydell, joel, Jamin Lin
On 5/16/22 08:23, Peter Delevoryas wrote:
> The AST1030 machine initialization was not respecting the Aspeed SoC
> property "uart-default", which specifies which UART should be connected to
> the first serial device, it was just always connecting UART5. This doesn't
> change any behavior, because the default value for "uart-default" is UART5,
> but it makes it possible to override this in new machine definitions using
> the AST1030.
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index bb8177e86c..faafb800f3 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -215,9 +215,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> qdev_get_gpio_in(DEVICE(&s->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
>
> - /* UART5 - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
> - aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
> + /* UART - attach an 8250 to the IO space as our UART */
> + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> + aspeed_soc_get_irq(s, s->uart_default),
> 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
>
> /* Timer */
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 3/5] hw: aspeed: Ensure AST1030 respects uart-default
@ 2022-05-16 7:20 ` Cédric Le Goater
0 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:20 UTC (permalink / raw)
To: Peter Delevoryas
Cc: peter.maydell, Jamin Lin, zev, andrew, irischenlj, openbmc,
qemu-devel, qemu-arm, joel
On 5/16/22 08:23, Peter Delevoryas wrote:
> The AST1030 machine initialization was not respecting the Aspeed SoC
> property "uart-default", which specifies which UART should be connected to
> the first serial device, it was just always connecting UART5. This doesn't
> change any behavior, because the default value for "uart-default" is UART5,
> but it makes it possible to override this in new machine definitions using
> the AST1030.
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index bb8177e86c..faafb800f3 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -215,9 +215,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> qdev_get_gpio_in(DEVICE(&s->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
>
> - /* UART5 - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2,
> - aspeed_soc_get_irq(s, ASPEED_DEV_UART5),
> + /* UART - attach an 8250 to the IO space as our UART */
> + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> + aspeed_soc_get_irq(s, s->uart_default),
> 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
>
> /* Timer */
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] hw: aspeed: Introduce common UART init function
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 7:20 ` Cédric Le Goater
-1 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:20 UTC (permalink / raw)
To: Peter Delevoryas
Cc: peter.maydell, Jamin Lin, zev, andrew, irischenlj, openbmc,
qemu-devel, qemu-arm, joel
On 5/16/22 08:23, Peter Delevoryas wrote:
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 7 ++-----
> hw/arm/aspeed_ast2600.c | 7 ++-----
> hw/arm/aspeed_soc.c | 16 ++++++++++++----
> include/hw/arm/aspeed_soc.h | 1 +
> 4 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index faafb800f3..938615d55f 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -15,7 +15,6 @@
> #include "sysemu/sysemu.h"
> #include "hw/qdev-clock.h"
> #include "hw/misc/unimp.h"
> -#include "hw/char/serial.h"
> #include "hw/arm/aspeed_soc.h"
>
> #define ASPEED_SOC_IOMEM_SIZE 0x00200000
> @@ -215,10 +214,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> qdev_get_gpio_in(DEVICE(&s->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
>
> - /* UART - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> - aspeed_soc_get_irq(s, s->uart_default),
> - 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + /* UART */
> + aspeed_soc_uart_init(s);
>
> /* Timer */
> object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index a9523074a0..b0a4199b69 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -11,7 +11,6 @@
> #include "qapi/error.h"
> #include "hw/misc/unimp.h"
> #include "hw/arm/aspeed_soc.h"
> -#include "hw/char/serial.h"
> #include "qemu/module.h"
> #include "qemu/error-report.h"
> #include "hw/i2c/aspeed_i2c.h"
> @@ -372,10 +371,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
>
> - /* UART - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> - aspeed_soc_get_irq(s, s->uart_default), 38400,
> - serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + /* UART */
> + aspeed_soc_uart_init(s);
>
> /* I2C */
> object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 7008cd1af7..912798a9c9 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -303,10 +303,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
>
> - /* UART - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> - aspeed_soc_get_irq(s, s->uart_default), 38400,
> - serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + /* UART */
> + aspeed_soc_uart_init(s);
>
> /* I2C */
> object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
> @@ -544,3 +542,13 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> {
> return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
> }
> +
> +void aspeed_soc_uart_init(AspeedSoCState *s)
> +{
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> +
> + /* Attach an 8250 to the IO space as our UART */
> + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> + aspeed_soc_get_irq(s, s->uart_default), 38400,
> + serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +}
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 669bc49855..02a5a9ffcb 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -164,5 +164,6 @@ enum {
> };
>
> qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
> +void aspeed_soc_uart_init(AspeedSoCState *s);
>
> #endif /* ASPEED_SOC_H */
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 4/5] hw: aspeed: Introduce common UART init function
@ 2022-05-16 7:20 ` Cédric Le Goater
0 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:20 UTC (permalink / raw)
To: Peter Delevoryas
Cc: irischenlj, qemu-arm, qemu-devel, zev, openbmc, andrew,
peter.maydell, joel, Jamin Lin
On 5/16/22 08:23, Peter Delevoryas wrote:
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_ast10x0.c | 7 ++-----
> hw/arm/aspeed_ast2600.c | 7 ++-----
> hw/arm/aspeed_soc.c | 16 ++++++++++++----
> include/hw/arm/aspeed_soc.h | 1 +
> 4 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
> index faafb800f3..938615d55f 100644
> --- a/hw/arm/aspeed_ast10x0.c
> +++ b/hw/arm/aspeed_ast10x0.c
> @@ -15,7 +15,6 @@
> #include "sysemu/sysemu.h"
> #include "hw/qdev-clock.h"
> #include "hw/misc/unimp.h"
> -#include "hw/char/serial.h"
> #include "hw/arm/aspeed_soc.h"
>
> #define ASPEED_SOC_IOMEM_SIZE 0x00200000
> @@ -215,10 +214,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
> qdev_get_gpio_in(DEVICE(&s->armv7m),
> sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
>
> - /* UART - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> - aspeed_soc_get_irq(s, s->uart_default),
> - 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + /* UART */
> + aspeed_soc_uart_init(s);
>
> /* Timer */
> object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
> diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
> index a9523074a0..b0a4199b69 100644
> --- a/hw/arm/aspeed_ast2600.c
> +++ b/hw/arm/aspeed_ast2600.c
> @@ -11,7 +11,6 @@
> #include "qapi/error.h"
> #include "hw/misc/unimp.h"
> #include "hw/arm/aspeed_soc.h"
> -#include "hw/char/serial.h"
> #include "qemu/module.h"
> #include "qemu/error-report.h"
> #include "hw/i2c/aspeed_i2c.h"
> @@ -372,10 +371,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
>
> - /* UART - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> - aspeed_soc_get_irq(s, s->uart_default), 38400,
> - serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + /* UART */
> + aspeed_soc_uart_init(s);
>
> /* I2C */
> object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 7008cd1af7..912798a9c9 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -303,10 +303,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
>
> - /* UART - attach an 8250 to the IO space as our UART */
> - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> - aspeed_soc_get_irq(s, s->uart_default), 38400,
> - serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + /* UART */
> + aspeed_soc_uart_init(s);
>
> /* I2C */
> object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
> @@ -544,3 +542,13 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> {
> return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
> }
> +
> +void aspeed_soc_uart_init(AspeedSoCState *s)
> +{
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> +
> + /* Attach an 8250 to the IO space as our UART */
> + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> + aspeed_soc_get_irq(s, s->uart_default), 38400,
> + serial_hd(0), DEVICE_LITTLE_ENDIAN);
> +}
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index 669bc49855..02a5a9ffcb 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -164,5 +164,6 @@ enum {
> };
>
> qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
> +void aspeed_soc_uart_init(AspeedSoCState *s);
>
> #endif /* ASPEED_SOC_H */
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/5] hw: aspeed: Init all UART's with serial devices
2022-05-16 6:23 ` Peter Delevoryas
@ 2022-05-16 7:22 ` Cédric Le Goater
-1 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:22 UTC (permalink / raw)
To: Peter Delevoryas
Cc: peter.maydell, Jamin Lin, zev, andrew, irischenlj, openbmc,
qemu-devel, qemu-arm, joel
On 5/16/22 08:23, Peter Delevoryas wrote:
> Background:
>
> AspeedMachineClass.uart_default specifies the serial console UART, which
> usually corresponds to the "stdout-path" in the device tree.
>
> The default value is UART5, since most boards use UART5 for this:
>
> amc->uart_default = ASPEED_DEV_UART5;
>
> Users can override AspeedMachineClass.uart_default in their board's machine
> class init to specify something besides UART5. For example, for fuji-bmc:
>
> amc->uart_default = ASPEED_DEV_UART1;
>
> We only connect this one UART, of the 5 UART's on the AST2400 and AST2500
> and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU
> users can use. None of the other UART's are initialized, and the only way
> to override this attribute is by creating a specialized board definition,
> requiring QEMU source code changes and rebuilding.
>
> The result of this is that if you want to get serial console output on a
> board that uses UART3, you need to add a board definition. This was
> encountered by Zev in OpenBMC. [1]
>
> Changes:
>
> This commit initializes all of the UART's present on each Aspeed chip with
> serial devices and allows the QEMU user to connect as many or few as they
> like to serial devices. For example, you can still run QEMU and just connect
> stdout to the machine's default UART, without specifying any additional
> serial devices:
>
> qemu-system-arm -machine fuji-bmc \
> -drive file=fuji.mtd,format=raw,if=mtd \
> -nographic
>
> However, if you don't want to add a special machine definition, you can now
> manually configure UART1 to connect to stdout and get serial console output,
> even if the machine's default is UART5:
>
> qemu-system-arm -machine ast2600-evb \
> -drive file=fuji.mtd,format=raw,if=mtd \
> -serial null -serial mon:stdio -display none
>
> In the example above, the first "-serial null" argument is connected to
> UART5, and "-serial mon:stdio" is connected to UART1.
>
> Another example: you can get serial console output from Wedge100, which uses
> UART3, by reusing the palmetto AST2400 machine and rewiring the serial
> device arguments:
>
> qemu-system-arm -machine palmetto-bmc \
> -drive file=wedge100.mtd,format=raw,if=mtd \
> -serial null -serial null -serial null \
> -serial mon:stdio -display none
>
> There is a slight change in behavior introduced with this change: now, each
> UART's memory-mapped IO region will have a serial device model connected to
> it. Previously, all reads and writes to those regions would be ineffective
> and return zero values, but now some values will be nonzero, even when the
> user doesn't connect a serial device backend (like a socket, file, etc). For
> example, the line status register might indicate that the transmit buffer is
> empty now, whereas previously it might have always indicated it was full.
>
> [1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/
> [2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
> [3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_soc.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 912798a9c9..30574d4276 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -546,9 +546,18 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> void aspeed_soc_uart_init(AspeedSoCState *s)
> {
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + int i, uart;
>
> /* Attach an 8250 to the IO space as our UART */
> serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> aspeed_soc_get_irq(s, s->uart_default), 38400,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
> + if (uart == s->uart_default) {
> + uart++;
> + }
> + serial_mm_init(get_system_memory(), sc->memmap[uart], 2,
> + aspeed_soc_get_irq(s, uart), 38400,
> + serial_hd(i), DEVICE_LITTLE_ENDIAN);
> + }
> }
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 5/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 7:22 ` Cédric Le Goater
0 siblings, 0 replies; 28+ messages in thread
From: Cédric Le Goater @ 2022-05-16 7:22 UTC (permalink / raw)
To: Peter Delevoryas
Cc: irischenlj, qemu-arm, qemu-devel, zev, openbmc, andrew,
peter.maydell, joel, Jamin Lin
On 5/16/22 08:23, Peter Delevoryas wrote:
> Background:
>
> AspeedMachineClass.uart_default specifies the serial console UART, which
> usually corresponds to the "stdout-path" in the device tree.
>
> The default value is UART5, since most boards use UART5 for this:
>
> amc->uart_default = ASPEED_DEV_UART5;
>
> Users can override AspeedMachineClass.uart_default in their board's machine
> class init to specify something besides UART5. For example, for fuji-bmc:
>
> amc->uart_default = ASPEED_DEV_UART1;
>
> We only connect this one UART, of the 5 UART's on the AST2400 and AST2500
> and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU
> users can use. None of the other UART's are initialized, and the only way
> to override this attribute is by creating a specialized board definition,
> requiring QEMU source code changes and rebuilding.
>
> The result of this is that if you want to get serial console output on a
> board that uses UART3, you need to add a board definition. This was
> encountered by Zev in OpenBMC. [1]
>
> Changes:
>
> This commit initializes all of the UART's present on each Aspeed chip with
> serial devices and allows the QEMU user to connect as many or few as they
> like to serial devices. For example, you can still run QEMU and just connect
> stdout to the machine's default UART, without specifying any additional
> serial devices:
>
> qemu-system-arm -machine fuji-bmc \
> -drive file=fuji.mtd,format=raw,if=mtd \
> -nographic
>
> However, if you don't want to add a special machine definition, you can now
> manually configure UART1 to connect to stdout and get serial console output,
> even if the machine's default is UART5:
>
> qemu-system-arm -machine ast2600-evb \
> -drive file=fuji.mtd,format=raw,if=mtd \
> -serial null -serial mon:stdio -display none
>
> In the example above, the first "-serial null" argument is connected to
> UART5, and "-serial mon:stdio" is connected to UART1.
>
> Another example: you can get serial console output from Wedge100, which uses
> UART3, by reusing the palmetto AST2400 machine and rewiring the serial
> device arguments:
>
> qemu-system-arm -machine palmetto-bmc \
> -drive file=wedge100.mtd,format=raw,if=mtd \
> -serial null -serial null -serial null \
> -serial mon:stdio -display none
>
> There is a slight change in behavior introduced with this change: now, each
> UART's memory-mapped IO region will have a serial device model connected to
> it. Previously, all reads and writes to those regions would be ineffective
> and return zero values, but now some values will be nonzero, even when the
> user doesn't connect a serial device backend (like a socket, file, etc). For
> example, the line status register might indicate that the transmit buffer is
> empty now, whereas previously it might have always indicated it was full.
>
> [1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/
> [2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
> [3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
>
> Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed_soc.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 912798a9c9..30574d4276 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -546,9 +546,18 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
> void aspeed_soc_uart_init(AspeedSoCState *s)
> {
> AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + int i, uart;
>
> /* Attach an 8250 to the IO space as our UART */
> serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2,
> aspeed_soc_get_irq(s, s->uart_default), 38400,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + for (i = 1, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
> + if (uart == s->uart_default) {
> + uart++;
> + }
> + serial_mm_init(get_system_memory(), sc->memmap[uart], 2,
> + aspeed_soc_get_irq(s, uart), 38400,
> + serial_hd(i), DEVICE_LITTLE_ENDIAN);
> + }
> }
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
2022-05-16 7:18 ` Cédric Le Goater
@ 2022-05-16 12:33 ` Andrew Jeffery
-1 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2022-05-16 12:33 UTC (permalink / raw)
To: Cédric Le Goater, Peter Delevoryas
Cc: Peter Maydell, Jamin Lin, Zev Weiss, irischenlj, openbmc,
Cameron Esfahani via, Philippe Mathieu-Daudé via,
Joel Stanley
On Mon, 16 May 2022, at 16:48, Cédric Le Goater wrote:
> On 5/16/22 08:23, Peter Delevoryas wrote:
>> v2:
>> - Rebased on Cedric's irq proposal. [1]
>> - Added "Introduce common UART init function" patch
>> - Added "Add uarts_num SoC attribute" patch
>> - Rewrote last commit's message for clarity
>
> Looks good to me.
>
>> I tried testing this by running acceptance tests, particularly the
>> boot_linux_console.py file, but I had to disable the raspi2_initrd case.
>> It's not related to my changes (A/B tested and it fails on upstream/master
>> too), but thought I would mention that.>
>> I also manually tested several machines:
>>
>> AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
>> AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
>> AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
>> AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
>>
>> [1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
> I have quite a few images which I run manually. OpenBMC is providing
> images, Aspeed also. Joel did a small tool for the IBM rainier :
>
> https://github.com/shenki/qemu-boot-test
>
> Having an automated framework for Aspeed machines pulling images
> from different places would be nice but we cannot put all under
> QEMU.
For what it's worth I run this as a smoke test before pushing updates to openbmc/qemu:
https://github.com/openbmc/openbmc-build-scripts/blob/master/scripts/test-qemu
Andrew
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 12:33 ` Andrew Jeffery
0 siblings, 0 replies; 28+ messages in thread
From: Andrew Jeffery @ 2022-05-16 12:33 UTC (permalink / raw)
To: Cédric Le Goater, Peter Delevoryas
Cc: irischenlj, Philippe Mathieu-Daudé via,
Cameron Esfahani via, Zev Weiss, openbmc, Peter Maydell,
Joel Stanley, Jamin Lin
On Mon, 16 May 2022, at 16:48, Cédric Le Goater wrote:
> On 5/16/22 08:23, Peter Delevoryas wrote:
>> v2:
>> - Rebased on Cedric's irq proposal. [1]
>> - Added "Introduce common UART init function" patch
>> - Added "Add uarts_num SoC attribute" patch
>> - Rewrote last commit's message for clarity
>
> Looks good to me.
>
>> I tried testing this by running acceptance tests, particularly the
>> boot_linux_console.py file, but I had to disable the raspi2_initrd case.
>> It's not related to my changes (A/B tested and it fails on upstream/master
>> too), but thought I would mention that.>
>> I also manually tested several machines:
>>
>> AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
>> AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
>> AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
>> AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
>>
>> [1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
> I have quite a few images which I run manually. OpenBMC is providing
> images, Aspeed also. Joel did a small tool for the IBM rainier :
>
> https://github.com/shenki/qemu-boot-test
>
> Having an automated framework for Aspeed machines pulling images
> from different places would be nice but we cannot put all under
> QEMU.
For what it's worth I run this as a smoke test before pushing updates to openbmc/qemu:
https://github.com/openbmc/openbmc-build-scripts/blob/master/scripts/test-qemu
Andrew
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
2022-05-16 7:18 ` Cédric Le Goater
@ 2022-05-16 16:20 ` Peter Delevoryas
-1 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 16:20 UTC (permalink / raw)
Cc: Peter Maydell, Jamin Lin, zev, Andrew Jeffery, Iris Chen,
OpenBMC List, Cameron Esfahani via, qemu-arm, Joel Stanley,
Peter Delevoryas, Cédric Le Goater
> On May 16, 2022, at 12:18 AM, Cédric Le Goater <clg@kaod.org> wrote:
>
> On 5/16/22 08:23, Peter Delevoryas wrote:
>> v2:
>> - Rebased on Cedric's irq proposal. [1]
>> - Added "Introduce common UART init function" patch
>> - Added "Add uarts_num SoC attribute" patch
>> - Rewrote last commit's message for clarity
>
> Looks good to me.
>
>> I tried testing this by running acceptance tests, particularly the
>> boot_linux_console.py file, but I had to disable the raspi2_initrd case.
>> It's not related to my changes (A/B tested and it fails on upstream/master
>> too), but thought I would mention that.>
>> I also manually tested several machines:
>> AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
>> AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
>> AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
>> AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
>> [1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
> I have quite a few images which I run manually. OpenBMC is providing
> images, Aspeed also. Joel did a small tool for the IBM rainier :
>
> https://github.com/shenki/qemu-boot-test
>
> Having an automated framework for Aspeed machines pulling images
> from different places would be nice but we cannot put all under
> QEMU.
>
>
> I like the buildroot CI using the QEMU boards. See a pipeline example:
>
> https://gitlab.com/legoater/buildroot/-/pipelines/539559209
> but that's buildroot only and integrating a custom uboot might be
> difficult.
>
> For my ppc needs, I did a quick-and-dirty non-regression test suite :
>
> https://github.com/legoater/qemu-ppc-boot
>
>
> Anyway, I haven't found a solution nor spent much time on it but
> I am interested !
Oh thanks for the links, I’m somewhat interested in looking into this further.
>
>
> C.
>
>
>
>
>> Peter Delevoryas (5):
>> hw: aspeed: Add missing UART's
>> hw: aspeed: Add uarts_num SoC attribute
>> hw: aspeed: Ensure AST1030 respects uart-default
>> hw: aspeed: Introduce common UART init function
>> hw: aspeed: Init all UART's with serial devices
>> hw/arm/aspeed_ast10x0.c | 32 +++++++++++++++++++++++++++-----
>> hw/arm/aspeed_ast2600.c | 27 ++++++++++++++++++++++-----
>> hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++++----
>> include/hw/arm/aspeed_soc.h | 10 ++++++++++
>> 4 files changed, 88 insertions(+), 14 deletions(-)
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices
@ 2022-05-16 16:20 ` Peter Delevoryas
0 siblings, 0 replies; 28+ messages in thread
From: Peter Delevoryas @ 2022-05-16 16:20 UTC (permalink / raw)
Cc: Iris Chen, qemu-arm, Cameron Esfahani via, zev, OpenBMC List,
Andrew Jeffery, Peter Maydell, Joel Stanley, Jamin Lin,
Cédric Le Goater, Peter Delevoryas
> On May 16, 2022, at 12:18 AM, Cédric Le Goater <clg@kaod.org> wrote:
>
> On 5/16/22 08:23, Peter Delevoryas wrote:
>> v2:
>> - Rebased on Cedric's irq proposal. [1]
>> - Added "Introduce common UART init function" patch
>> - Added "Add uarts_num SoC attribute" patch
>> - Rewrote last commit's message for clarity
>
> Looks good to me.
>
>> I tried testing this by running acceptance tests, particularly the
>> boot_linux_console.py file, but I had to disable the raspi2_initrd case.
>> It's not related to my changes (A/B tested and it fails on upstream/master
>> too), but thought I would mention that.>
>> I also manually tested several machines:
>> AST2400: https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
>> AST2500: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fby3.mtd
>> AST2600: https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
>> AST1030: https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
>> [1] https://lore.kernel.org/qemu-devel/20220516055620.2380197-1-clg@kaod.org/
> I have quite a few images which I run manually. OpenBMC is providing
> images, Aspeed also. Joel did a small tool for the IBM rainier :
>
> https://github.com/shenki/qemu-boot-test
>
> Having an automated framework for Aspeed machines pulling images
> from different places would be nice but we cannot put all under
> QEMU.
>
>
> I like the buildroot CI using the QEMU boards. See a pipeline example:
>
> https://gitlab.com/legoater/buildroot/-/pipelines/539559209
> but that's buildroot only and integrating a custom uboot might be
> difficult.
>
> For my ppc needs, I did a quick-and-dirty non-regression test suite :
>
> https://github.com/legoater/qemu-ppc-boot
>
>
> Anyway, I haven't found a solution nor spent much time on it but
> I am interested !
Oh thanks for the links, I’m somewhat interested in looking into this further.
>
>
> C.
>
>
>
>
>> Peter Delevoryas (5):
>> hw: aspeed: Add missing UART's
>> hw: aspeed: Add uarts_num SoC attribute
>> hw: aspeed: Ensure AST1030 respects uart-default
>> hw: aspeed: Introduce common UART init function
>> hw: aspeed: Init all UART's with serial devices
>> hw/arm/aspeed_ast10x0.c | 32 +++++++++++++++++++++++++++-----
>> hw/arm/aspeed_ast2600.c | 27 ++++++++++++++++++++++-----
>> hw/arm/aspeed_soc.c | 33 +++++++++++++++++++++++++++++----
>> include/hw/arm/aspeed_soc.h | 10 ++++++++++
>> 4 files changed, 88 insertions(+), 14 deletions(-)
>
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2022-05-16 16:29 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-16 6:23 [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices Peter Delevoryas
2022-05-16 6:23 ` Peter Delevoryas
2022-05-16 6:23 ` [PATCH v2 1/5] hw: aspeed: Add missing UART's Peter Delevoryas
2022-05-16 6:23 ` Peter Delevoryas
2022-05-16 7:19 ` Cédric Le Goater
2022-05-16 7:19 ` Cédric Le Goater
2022-05-16 6:23 ` [PATCH v2 2/5] hw: aspeed: Add uarts_num SoC attribute Peter Delevoryas
2022-05-16 6:23 ` Peter Delevoryas
2022-05-16 7:20 ` Cédric Le Goater
2022-05-16 7:20 ` Cédric Le Goater
2022-05-16 6:23 ` [PATCH v2 3/5] hw: aspeed: Ensure AST1030 respects uart-default Peter Delevoryas
2022-05-16 6:23 ` Peter Delevoryas
2022-05-16 7:20 ` Cédric Le Goater
2022-05-16 7:20 ` Cédric Le Goater
2022-05-16 6:23 ` [PATCH v2 4/5] hw: aspeed: Introduce common UART init function Peter Delevoryas
2022-05-16 6:23 ` Peter Delevoryas
2022-05-16 7:20 ` Cédric Le Goater
2022-05-16 7:20 ` Cédric Le Goater
2022-05-16 6:23 ` [PATCH v2 5/5] hw: aspeed: Init all UART's with serial devices Peter Delevoryas
2022-05-16 6:23 ` Peter Delevoryas
2022-05-16 7:22 ` Cédric Le Goater
2022-05-16 7:22 ` Cédric Le Goater
2022-05-16 7:18 ` [PATCH v2 0/5] " Cédric Le Goater
2022-05-16 7:18 ` Cédric Le Goater
2022-05-16 12:33 ` Andrew Jeffery
2022-05-16 12:33 ` Andrew Jeffery
2022-05-16 16:20 ` Peter Delevoryas
2022-05-16 16:20 ` Peter Delevoryas
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