[PATCH 3/4] spi: synquacer: DMSTART bit must not be set while transferring

From: Masahisa Kojima <masahisa.kojima@linaro.org>
To: u-boot@lists.denx.de
Cc: Jassi Brar <jaswinder.singh@linaro.org>,
	Satoru Okamoto <okamoto.satoru@socionext.com>,
	Masahisa Kojima <masahisa.kojima@linaro.org>,
	Jagan Teki <jagan@amarulasolutions.com>
Subject: [PATCH 3/4] spi: synquacer: DMSTART bit must not be set while transferring
Date: Tue, 17 May 2022 17:41:38 +0900	[thread overview]
Message-ID: <20220517084139.6986-4-masahisa.kojima@linaro.org> (raw)
In-Reply-To: <20220517084139.6986-1-masahisa.kojima@linaro.org>

DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
---
 drivers/spi/spi-synquacer.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c
index f1422cf893..5e1b3aedc7 100644
--- a/drivers/spi/spi-synquacer.c
+++ b/drivers/spi/spi-synquacer.c
@@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen,
 	writel(~0, priv->base + RXC);
 
 	/* Trigger */
-	val = readl(priv->base + DMSTART);
-	val |= BIT(TRIGGER);
-	writel(val, priv->base + DMSTART);
+	if (flags & SPI_XFER_BEGIN) {
+		val = readl(priv->base + DMSTART);
+		val |= BIT(TRIGGER);
+		writel(val, priv->base + DMSTART);
+	}
 
 	while (busy & (BIT(RXBIT) | BIT(TXBIT))) {
 		if (priv->rx_words)
-- 
2.17.1

