From: Tom Rini <trini@konsulko.com>
To: Masahisa Kojima <masahisa.kojima@linaro.org>
Cc: u-boot@lists.denx.de, Jassi Brar <jaswinder.singh@linaro.org>,
Satoru Okamoto <okamoto.satoru@socionext.com>,
Jagan Teki <jagan@amarulasolutions.com>
Subject: Re: [PATCH 4/4] spi: synquacer: simplify tx completion checking
Date: Fri, 10 Jun 2022 17:40:38 -0400 [thread overview]
Message-ID: <20220610214038.GD2484912@bill-the-cat> (raw)
In-Reply-To: <20220517084139.6986-5-masahisa.kojima@linaro.org>
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On Tue, May 17, 2022 at 05:41:39PM +0900, Masahisa Kojima wrote:
> There is a TX-FIFO and Shift Register empty(TFES) status
> bit in spi controller. This commit checks the TFES bit
> to wait the TX transfer completes.
>
> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
> Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
> Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
Applied to u-boot/next, thanks!
--
Tom
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prev parent reply other threads:[~2022-06-10 21:41 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-17 8:41 [PATCH 0/4] spi-synquacer fixes and improvement Masahisa Kojima
2022-05-17 8:41 ` [PATCH 1/4] spi: synquacer: busy variable must be initialized before use Masahisa Kojima
2022-05-18 3:42 ` Jassi Brar
2022-06-10 21:40 ` Tom Rini
2022-05-17 8:41 ` [PATCH 2/4] spi: synquacer: wait until slave is deselected Masahisa Kojima
2022-05-18 3:42 ` Jassi Brar
2022-06-10 21:40 ` Tom Rini
2022-05-17 8:41 ` [PATCH 3/4] spi: synquacer: DMSTART bit must not be set while transferring Masahisa Kojima
2022-05-18 3:43 ` Jassi Brar
2022-06-10 21:40 ` Tom Rini
2022-05-17 8:41 ` [PATCH 4/4] spi: synquacer: simplify tx completion checking Masahisa Kojima
2022-05-18 3:43 ` Jassi Brar
2022-06-10 21:40 ` Tom Rini [this message]
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