* [PATCH] clk: renesas: r9a09g011: Add PFC clock and reset entries
@ 2022-05-18 13:52 Phil Edworthy
2022-05-19 9:52 ` Geert Uytterhoeven
0 siblings, 1 reply; 2+ messages in thread
From: Phil Edworthy @ 2022-05-18 13:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: Phil Edworthy, linux-renesas-soc, linux-clk, Lad Prabhakar
Add PFC clock/reset entries to CPG driver.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a09g011-cpg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g011-cpg.c b/drivers/clk/renesas/r9a09g011-cpg.c
index 40693bb85b80..b01d79a73dd8 100644
--- a/drivers/clk/renesas/r9a09g011-cpg.c
+++ b/drivers/clk/renesas/r9a09g011-cpg.c
@@ -126,6 +126,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
};
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
+ DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
@@ -137,6 +138,7 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
};
static const struct rzg2l_reset r9a09g011_resets[] = {
+ DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: renesas: r9a09g011: Add PFC clock and reset entries
2022-05-18 13:52 [PATCH] clk: renesas: r9a09g011: Add PFC clock and reset entries Phil Edworthy
@ 2022-05-19 9:52 ` Geert Uytterhoeven
0 siblings, 0 replies; 2+ messages in thread
From: Geert Uytterhoeven @ 2022-05-19 9:52 UTC (permalink / raw)
To: Phil Edworthy
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk, Lad Prabhakar
On Wed, May 18, 2022 at 3:52 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> Add PFC clock/reset entries to CPG driver.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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2022-05-18 13:52 [PATCH] clk: renesas: r9a09g011: Add PFC clock and reset entries Phil Edworthy
2022-05-19 9:52 ` Geert Uytterhoeven
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