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* [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel
@ 2022-05-18 17:27 Ralph Siemsen
  2022-05-18 17:27 ` [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields Ralph Siemsen
                   ` (3 more replies)
  0 siblings, 4 replies; 11+ messages in thread
From: Ralph Siemsen @ 2022-05-18 17:27 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: phil.edworthy, Ralph Siemsen, Geert Uytterhoeven, linux-clk

There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.

Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 drivers/clk/renesas/r9a06g032-clocks.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index c99942f0e4d4..0baa6a06ada8 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -287,7 +287,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.type = K_BITSEL,
 		.source = 1 + R9A06G032_DIV_UART,
 		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
-		.dual.sel = ((0xec / 4) << 5) | 24,
+		.dual.sel = ((0x34 / 4) << 5) | 30,
 		.dual.group = 0,
 	},
 	{
@@ -296,7 +296,7 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.type = K_BITSEL,
 		.source = 1 + R9A06G032_DIV_P2_PG,
 		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
-		.dual.sel = ((0x34 / 4) << 5) | 30,
+		.dual.sel = ((0xec / 4) << 5) | 24,
 		.dual.group = 1,
 	},
 	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields
  2022-05-18 17:27 [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Ralph Siemsen
@ 2022-05-18 17:27 ` Ralph Siemsen
  2022-05-18 17:44   ` Phil Edworthy
  2022-05-19  9:41   ` Geert Uytterhoeven
  2022-05-18 17:27 ` [PATCH 3/3] clk: renesas: r9a06g032: remove unused field Ralph Siemsen
                   ` (2 subsequent siblings)
  3 siblings, 2 replies; 11+ messages in thread
From: Ralph Siemsen @ 2022-05-18 17:27 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: phil.edworthy, Ralph Siemsen, Geert Uytterhoeven, linux-clk

Minor cleanup, remove unused fields from struct r9a06g032_clkdesc.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 drivers/clk/renesas/r9a06g032-clocks.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 0baa6a06ada8..9dbcf9620fa0 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -47,11 +47,9 @@ struct r9a06g032_clkdesc {
 		struct {
 			u16 div, mul;
 		};
-		unsigned int factor;
-		unsigned int frequency;
 		/* for dual gate */
 		struct {
-			uint16_t group : 1, index: 3;
+			uint16_t group : 1;
 			u16 sel, g1, r1, g2, r2;
 		} dual;
 	};
@@ -84,7 +82,7 @@ struct r9a06g032_clkdesc {
 #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
 	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
 		.source = 1 + R9A06G032_##_src, .name = _n, \
-		.dual = { .group = _g, .index = _gi, \
+		.dual = { .group = _g, \
 			.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
 
 enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 3/3] clk: renesas: r9a06g032: remove unused field
  2022-05-18 17:27 [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Ralph Siemsen
  2022-05-18 17:27 ` [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields Ralph Siemsen
@ 2022-05-18 17:27 ` Ralph Siemsen
  2022-05-18 17:45   ` Phil Edworthy
  2022-05-19  9:41   ` Geert Uytterhoeven
  2022-05-18 17:32 ` [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Phil Edworthy
  2022-05-18 18:25 ` [PATCH v2 " Ralph Siemsen
  3 siblings, 2 replies; 11+ messages in thread
From: Ralph Siemsen @ 2022-05-18 17:27 UTC (permalink / raw)
  To: linux-renesas-soc
  Cc: phil.edworthy, Ralph Siemsen, Geert Uytterhoeven, linux-clk

As the D_UGATE macro no longer uses _gi, drop it from all declarations.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 drivers/clk/renesas/r9a06g032-clocks.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index 9dbcf9620fa0..fe56560c54df 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -79,7 +79,7 @@ struct r9a06g032_clkdesc {
 		.source = 1 + R9A06G032_##_src, .name = _n, \
 		.reg = _reg, .div_min = _min, .div_max = _max, \
 		.div_table = { __VA_ARGS__ } }
-#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
+#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
 	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
 		.source = 1 + R9A06G032_##_src, .name = _n, \
 		.dual = { .group = _g, \
@@ -297,14 +297,14 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.dual.sel = ((0xec / 4) << 5) | 24,
 		.dual.group = 1,
 	},
-	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
-	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
-	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
-	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
-	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
-	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
-	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
-	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
+	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
+	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
+	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
+	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
+	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
+	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
+	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
+	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
 };
 
 struct r9a06g032_priv {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* RE: [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  2022-05-18 17:27 [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Ralph Siemsen
  2022-05-18 17:27 ` [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields Ralph Siemsen
  2022-05-18 17:27 ` [PATCH 3/3] clk: renesas: r9a06g032: remove unused field Ralph Siemsen
@ 2022-05-18 17:32 ` Phil Edworthy
  2022-05-18 18:25 ` [PATCH v2 " Ralph Siemsen
  3 siblings, 0 replies; 11+ messages in thread
From: Phil Edworthy @ 2022-05-18 17:32 UTC (permalink / raw)
  To: Ralph Siemsen, linux-renesas-soc; +Cc: Geert Uytterhoeven, linux-clk

H Ralph,

Thanks for the patch!

On 18 May 2022 18:27 Ralph Siemsen wrote:
> There are two UART clock groups, each having a mux to select its
> upstream clock source. The register/bit definitions for accessing these
> two muxes appear to have been reversed since introduction. Correct them
> so as to match the hardware manual.
> 
> Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>  drivers/clk/renesas/r9a06g032-clocks.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
> b/drivers/clk/renesas/r9a06g032-clocks.c
> index c99942f0e4d4..0baa6a06ada8 100644
> --- a/drivers/clk/renesas/r9a06g032-clocks.c
> +++ b/drivers/clk/renesas/r9a06g032-clocks.c
> @@ -287,7 +287,7 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
>  		.type = K_BITSEL,
>  		.source = 1 + R9A06G032_DIV_UART,
>  		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
> -		.dual.sel = ((0xec / 4) << 5) | 24,
> +		.dual.sel = ((0x34 / 4) << 5) | 30,
The comment above also needs swapping.


>  		.dual.group = 0,
>  	},
>  	{
> @@ -296,7 +296,7 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
>  		.type = K_BITSEL,
>  		.source = 1 + R9A06G032_DIV_P2_PG,
>  		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
> -		.dual.sel = ((0x34 / 4) << 5) | 30,
> +		.dual.sel = ((0xec / 4) << 5) | 24,
>  		.dual.group = 1,
>  	},
>  	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3,
> 0x1b4, 0x1b5),
> --
> 2.25.1

With the above change:
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>

Thanks
Phil


^ permalink raw reply	[flat|nested] 11+ messages in thread
* RE: [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields
  2022-05-18 17:27 ` [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields Ralph Siemsen
@ 2022-05-18 17:44   ` Phil Edworthy
  2022-05-19  9:41   ` Geert Uytterhoeven
  1 sibling, 0 replies; 11+ messages in thread
From: Phil Edworthy @ 2022-05-18 17:44 UTC (permalink / raw)
  To: Ralph Siemsen, linux-renesas-soc; +Cc: Geert Uytterhoeven, linux-clk

Hi Ralph,

Thanks for your patch!

On 18 May 2022 18:27 Ralph Siemsen wrote:
> Minor cleanup, remove unused fields from struct r9a06g032_clkdesc.
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>  drivers/clk/renesas/r9a06g032-clocks.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
> b/drivers/clk/renesas/r9a06g032-clocks.c
> index 0baa6a06ada8..9dbcf9620fa0 100644
> --- a/drivers/clk/renesas/r9a06g032-clocks.c
> +++ b/drivers/clk/renesas/r9a06g032-clocks.c
> @@ -47,11 +47,9 @@ struct r9a06g032_clkdesc {
>  		struct {
>  			u16 div, mul;
>  		};
> -		unsigned int factor;
> -		unsigned int frequency;
>  		/* for dual gate */
>  		struct {
> -			uint16_t group : 1, index: 3;
> +			uint16_t group : 1;
>  			u16 sel, g1, r1, g2, r2;
>  		} dual;
>  	};
> @@ -84,7 +82,7 @@ struct r9a06g032_clkdesc {
>  #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
>  	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
>  		.source = 1 + R9A06G032_##_src, .name = _n, \
> -		.dual = { .group = _g, .index = _gi, \
> +		.dual = { .group = _g, \
>  			.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
> 
>  enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
> --
> 2.25.1

Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>

Thanks
Phil

^ permalink raw reply	[flat|nested] 11+ messages in thread
* RE: [PATCH 3/3] clk: renesas: r9a06g032: remove unused field
  2022-05-18 17:27 ` [PATCH 3/3] clk: renesas: r9a06g032: remove unused field Ralph Siemsen
@ 2022-05-18 17:45   ` Phil Edworthy
  2022-05-19  9:41   ` Geert Uytterhoeven
  1 sibling, 0 replies; 11+ messages in thread
From: Phil Edworthy @ 2022-05-18 17:45 UTC (permalink / raw)
  To: Ralph Siemsen, linux-renesas-soc; +Cc: Geert Uytterhoeven, linux-clk

Hi Ralph,

Thanks for your patch!

On 18 May 2022 18:27 Ralph Siemsen wrote:
> As the D_UGATE macro no longer uses _gi, drop it from all declarations.
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>  drivers/clk/renesas/r9a06g032-clocks.c | 18 +++++++++---------
>  1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
> b/drivers/clk/renesas/r9a06g032-clocks.c
> index 9dbcf9620fa0..fe56560c54df 100644
> --- a/drivers/clk/renesas/r9a06g032-clocks.c
> +++ b/drivers/clk/renesas/r9a06g032-clocks.c
> @@ -79,7 +79,7 @@ struct r9a06g032_clkdesc {
>  		.source = 1 + R9A06G032_##_src, .name = _n, \
>  		.reg = _reg, .div_min = _min, .div_max = _max, \
>  		.div_table = { __VA_ARGS__ } }
> -#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
> +#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
>  	{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
>  		.source = 1 + R9A06G032_##_src, .name = _n, \
>  		.dual = { .group = _g, \
> @@ -297,14 +297,14 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
>  		.dual.sel = ((0xec / 4) << 5) | 24,
>  		.dual.group = 1,
>  	},
> -	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3,
> 0x1b4, 0x1b5),
> -	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7,
> 0x1b8, 0x1b9),
> -	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb,
> 0x1bc, 0x1bd),
> -	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760,
> 0x761, 0x762, 0x763),
> -	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764,
> 0x765, 0x766, 0x767),
> -	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768,
> 0x769, 0x76a, 0x76b),
> -	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c,
> 0x76d, 0x76e, 0x76f),
> -	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770,
> 0x771, 0x772, 0x773),
> +	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3,
> 0x1b4, 0x1b5),
> +	D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7,
> 0x1b8, 0x1b9),
> +	D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb,
> 0x1bc, 0x1bd),
> +	D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761,
> 0x762, 0x763),
> +	D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765,
> 0x766, 0x767),
> +	D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769,
> 0x76a, 0x76b),
> +	D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d,
> 0x76e, 0x76f),
> +	D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771,
> 0x772, 0x773),
>  };
> 
>  struct r9a06g032_priv {
> --
> 2.25.1

Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>

Thanks
Phil

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH v2 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  2022-05-18 17:27 [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Ralph Siemsen
                   ` (2 preceding siblings ...)
  2022-05-18 17:32 ` [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Phil Edworthy
@ 2022-05-18 18:25 ` Ralph Siemsen
  2022-05-18 18:32   ` Phil Edworthy
  3 siblings, 1 reply; 11+ messages in thread
From: Ralph Siemsen @ 2022-05-18 18:25 UTC (permalink / raw)
  To: ralph.siemsen; +Cc: geert+renesas, linux-clk, linux-renesas-soc, phil.edworthy

There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.

Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
v2 changes:
- reverse the comments as well

 drivers/clk/renesas/r9a06g032-clocks.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c
index c99942f0e4d4..abc0891fd96d 100644
--- a/drivers/clk/renesas/r9a06g032-clocks.c
+++ b/drivers/clk/renesas/r9a06g032-clocks.c
@@ -286,8 +286,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.name = "uart_group_012",
 		.type = K_BITSEL,
 		.source = 1 + R9A06G032_DIV_UART,
-		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
-		.dual.sel = ((0xec / 4) << 5) | 24,
+		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
+		.dual.sel = ((0x34 / 4) << 5) | 30,
 		.dual.group = 0,
 	},
 	{
@@ -295,8 +295,8 @@ static const struct r9a06g032_clkdesc r9a06g032_clocks[] = {
 		.name = "uart_group_34567",
 		.type = K_BITSEL,
 		.source = 1 + R9A06G032_DIV_P2_PG,
-		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
-		.dual.sel = ((0x34 / 4) << 5) | 30,
+		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
+		.dual.sel = ((0xec / 4) << 5) | 24,
 		.dual.group = 1,
 	},
 	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 11+ messages in thread
* RE: [PATCH v2 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  2022-05-18 18:25 ` [PATCH v2 " Ralph Siemsen
@ 2022-05-18 18:32   ` Phil Edworthy
  2022-05-19  9:31     ` Geert Uytterhoeven
  0 siblings, 1 reply; 11+ messages in thread
From: Phil Edworthy @ 2022-05-18 18:32 UTC (permalink / raw)
  To: Ralph Siemsen; +Cc: geert+renesas, linux-clk, linux-renesas-soc

Hi Ralph,

Thanks for your patch!

On 18 May 2022 19:25 Ralph Siemsen wrote:
> There are two UART clock groups, each having a mux to select its
> upstream clock source. The register/bit definitions for accessing these
> two muxes appear to have been reversed since introduction. Correct them
> so as to match the hardware manual.
> 
> Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
> v2 changes:
> - reverse the comments as well
> 
>  drivers/clk/renesas/r9a06g032-clocks.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/renesas/r9a06g032-clocks.c
> b/drivers/clk/renesas/r9a06g032-clocks.c
> index c99942f0e4d4..abc0891fd96d 100644
> --- a/drivers/clk/renesas/r9a06g032-clocks.c
> +++ b/drivers/clk/renesas/r9a06g032-clocks.c
> @@ -286,8 +286,8 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
>  		.name = "uart_group_012",
>  		.type = K_BITSEL,
>  		.source = 1 + R9A06G032_DIV_UART,
> -		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
> -		.dual.sel = ((0xec / 4) << 5) | 24,
> +		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
> +		.dual.sel = ((0x34 / 4) << 5) | 30,
>  		.dual.group = 0,
>  	},
>  	{
> @@ -295,8 +295,8 @@ static const struct r9a06g032_clkdesc
> r9a06g032_clocks[] = {
>  		.name = "uart_group_34567",
>  		.type = K_BITSEL,
>  		.source = 1 + R9A06G032_DIV_P2_PG,
> -		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
> -		.dual.sel = ((0x34 / 4) << 5) | 30,
> +		/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
> +		.dual.sel = ((0xec / 4) << 5) | 24,
>  		.dual.group = 1,
>  	},
>  	D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3,
> 0x1b4, 0x1b5),
> --
> 2.25.1

Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>

Thanks
Phil


^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  2022-05-18 18:32   ` Phil Edworthy
@ 2022-05-19  9:31     ` Geert Uytterhoeven
  0 siblings, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2022-05-19  9:31 UTC (permalink / raw)
  To: Phil Edworthy; +Cc: Ralph Siemsen, geert+renesas, linux-clk, linux-renesas-soc

On Wed, May 18, 2022 at 8:32 PM Phil Edworthy <phil.edworthy@renesas.com> wrote:
> On 18 May 2022 19:25 Ralph Siemsen wrote:
> > There are two UART clock groups, each having a mux to select its
> > upstream clock source. The register/bit definitions for accessing these
> > two muxes appear to have been reversed since introduction. Correct them
> > so as to match the hardware manual.
> >
> > Fixes: 4c3d88526eba ("clk: renesas: Renesas R9A06G032 clock driver")
> >
> > Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> > ---
> > v2 changes:
> > - reverse the comments as well
>
> Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>

Thanks, will queue in renesas-clk-for-v5.20.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields
  2022-05-18 17:27 ` [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields Ralph Siemsen
  2022-05-18 17:44   ` Phil Edworthy
@ 2022-05-19  9:41   ` Geert Uytterhoeven
  1 sibling, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2022-05-19  9:41 UTC (permalink / raw)
  To: Ralph Siemsen; +Cc: Linux-Renesas, Phil Edworthy, Geert Uytterhoeven, linux-clk

Hi Ralph,

On Wed, May 18, 2022 at 7:28 PM Ralph Siemsen <ralph.siemsen@linaro.org> wrote:
> Minor cleanup, remove unused fields from struct r9a06g032_clkdesc.
>
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.20.

> --- a/drivers/clk/renesas/r9a06g032-clocks.c
> +++ b/drivers/clk/renesas/r9a06g032-clocks.c
> @@ -84,7 +82,7 @@ struct r9a06g032_clkdesc {
>  #define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
>         { .type = K_DUALGATE, .index = R9A06G032_##_idx, \
>                 .source = 1 + R9A06G032_##_src, .name = _n, \
> -               .dual = { .group = _g, .index = _gi, \
> +               .dual = { .group = _g, \

My first reaction was: this makes _gi unused.
Then I noticed you handle that in your next patch.
I'll merge them into a single commit while applying.

>                         .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
>
>  enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] clk: renesas: r9a06g032: remove unused field
  2022-05-18 17:27 ` [PATCH 3/3] clk: renesas: r9a06g032: remove unused field Ralph Siemsen
  2022-05-18 17:45   ` Phil Edworthy
@ 2022-05-19  9:41   ` Geert Uytterhoeven
  1 sibling, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2022-05-19  9:41 UTC (permalink / raw)
  To: Ralph Siemsen; +Cc: Linux-Renesas, Phil Edworthy, Geert Uytterhoeven, linux-clk

On Wed, May 18, 2022 at 7:29 PM Ralph Siemsen <ralph.siemsen@linaro.org> wrote:
> As the D_UGATE macro no longer uses _gi, drop it from all declarations.
>
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.20, folded into [PATCH 2/3].

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-05-19  9:42 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-18 17:27 [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Ralph Siemsen
2022-05-18 17:27 ` [PATCH 2/3] clk: renesas: r9a06g032: drop some unused fields Ralph Siemsen
2022-05-18 17:44   ` Phil Edworthy
2022-05-19  9:41   ` Geert Uytterhoeven
2022-05-18 17:27 ` [PATCH 3/3] clk: renesas: r9a06g032: remove unused field Ralph Siemsen
2022-05-18 17:45   ` Phil Edworthy
2022-05-19  9:41   ` Geert Uytterhoeven
2022-05-18 17:32 ` [PATCH 1/3] clk: renesas: r9a06g032: Fix UART clkgrp bitsel Phil Edworthy
2022-05-18 18:25 ` [PATCH v2 " Ralph Siemsen
2022-05-18 18:32   ` Phil Edworthy
2022-05-19  9:31     ` Geert Uytterhoeven

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