* [CI 1/3] drm/i915: Introduce has_media_ratio_mode
@ 2022-05-19 8:57 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-05-19 8:57 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Media ratio mode (the ability for media IP to work at a different frequency
from the GT) is available for a subset of dGfx platforms supporting
GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to
identify these platforms and set it for XEHPSDV and DG2/ATS-M.
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10f273800645..3897dcb5d68d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1230,6 +1230,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
+#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
+
/*
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
* All later gens can run the final buffer from the ppgtt
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8d893bafa51..6e309595b1e7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1006,6 +1006,7 @@ static const struct intel_device_info xehpsdv_info = {
.display = { },
.has_64k_pages = 1,
.needs_compact_pt = 1,
+ .has_media_ratio_mode = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1027,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.needs_compact_pt = 1, \
+ .has_media_ratio_mode = 1, \
.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 60fc35ae81df..ebfaa6bcd508 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -152,6 +152,7 @@ enum intel_ppgtt_type {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
+ func(has_media_ratio_mode); \
func(has_mslices); \
func(has_pooled_eu); \
func(has_pxp); \
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [CI 1/3] drm/i915: Introduce has_media_ratio_mode
@ 2022-05-19 8:57 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-05-19 8:57 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Media ratio mode (the ability for media IP to work at a different frequency
from the GT) is available for a subset of dGfx platforms supporting
GuC/SLPC. Introduce 'has_media_ratio_mode' flag in intel_device_info to
identify these platforms and set it for XEHPSDV and DG2/ATS-M.
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10f273800645..3897dcb5d68d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1230,6 +1230,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define CCS_MASK(gt) \
ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
+#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
+
/*
* The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
* All later gens can run the final buffer from the ppgtt
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d8d893bafa51..6e309595b1e7 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1006,6 +1006,7 @@ static const struct intel_device_info xehpsdv_info = {
.display = { },
.has_64k_pages = 1,
.needs_compact_pt = 1,
+ .has_media_ratio_mode = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1027,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
.has_guc_deprivilege = 1, \
.has_heci_pxp = 1, \
.needs_compact_pt = 1, \
+ .has_media_ratio_mode = 1, \
.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 60fc35ae81df..ebfaa6bcd508 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -152,6 +152,7 @@ enum intel_ppgtt_type {
func(has_l3_dpf); \
func(has_llc); \
func(has_logical_ring_contexts); \
+ func(has_media_ratio_mode); \
func(has_mslices); \
func(has_pooled_eu); \
func(has_pxp); \
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [CI 2/3] drm/i915/pcode: Extend pcode functions for multiple gt's
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-19 8:57 ` Tvrtko Ursulin
-1 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-05-19 8:57 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Each gt contains an independent instance of pcode. Extend pcode functions
to interface with pcode on different gt's. To avoid creating dependency of
display functionality on intel_gt, pcode function interfaces are exposed in
terms of uncore rather than intel_gt. Callers have been converted to pass
in the appropritate (i915 or intel_gt) uncore to the pcode functions.
v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo)
v3: Retain previous function names to eliminate needless #defines (Rodrigo)
v4: Move out i915_pcode_init() to a separate patch (Tvrtko)
Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.c | 6 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++---
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_llc.c | 3 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_llc.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 +-
drivers/gpu/drm/i915/intel_dram.c | 2 +-
drivers/gpu/drm/i915/intel_pcode.c | 69 ++++++++-----------
drivers/gpu/drm/i915/intel_pcode.h | 14 ++--
drivers/gpu/drm/i915/intel_pm.c | 10 +--
17 files changed, 70 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 38014e0cc9ad..861dcd2eb890 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -28,7 +28,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
if (IS_BROADWELL(i915)) {
drm_WARN_ON(&i915->drm,
- snb_pcode_write(i915, DISPLAY_IPS_CONTROL,
+ snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
IPS_ENABLE | IPS_PCODE_CONTROL));
/*
* Quoting Art Runyan: "its not safe to expect any particular
@@ -62,7 +62,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
if (IS_BROADWELL(i915)) {
drm_WARN_ON(&i915->drm,
- snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
+ snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 37bd7b17f3d0..79269d2c476b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -78,7 +78,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
u16 dclk;
int ret;
- ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
&val, &val2);
if (ret)
@@ -104,7 +104,7 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
int ret;
int i;
- ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
if (ret)
return ret;
@@ -123,7 +123,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
int ret;
/* bspec says to keep retrying for at least 1 ms */
- ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
points_mask,
ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b2017d8161b4..6e80162632dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -800,7 +800,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
"trying to change cdclk frequency with cdclk not enabled\n"))
return;
- ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+ ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
if (ret) {
drm_err(&dev_priv->drm,
"failed to inform pcode about cdclk change\n");
@@ -828,7 +828,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
- snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+ snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_config->voltage_level);
intel_de_write(dev_priv, CDCLK_FREQ,
@@ -1086,7 +1086,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
drm_WARN_ON_ONCE(&dev_priv->drm,
IS_SKYLAKE(dev_priv) && vco == 8640000);
- ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1132,7 +1132,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_posting_read(dev_priv, CDCLK_CTL);
/* inform PCU of the change */
- snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
intel_update_cdclk(dev_priv);
@@ -1702,7 +1702,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
/* Inform power controller of upcoming frequency change. */
if (DISPLAY_VER(dev_priv) >= 11)
- ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1711,7 +1711,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* BSpec requires us to wait up to 150usec, but that leads to
* timeouts; the 2ms used here is based on experiment.
*/
- ret = snb_pcode_write_timeout(dev_priv,
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
HSW_PCODE_DE_WRITE_FREQ_REQ,
0x80000000, 150, 2);
if (ret) {
@@ -1774,7 +1774,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
if (DISPLAY_VER(dev_priv) >= 11) {
- ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
} else {
/*
@@ -1783,7 +1783,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* FIXME: Waiting for the request completion could be delayed
* until the next PCODE request based on BSpec.
*/
- ret = snb_pcode_write_timeout(dev_priv,
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_config->voltage_level,
150, 2);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5eb8d63fb89e..fb17439bd4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1196,7 +1196,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
{
if (IS_HASWELL(dev_priv)) {
- if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+ if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
drm_dbg_kms(&dev_priv->drm,
"Failed to write to D_COMP\n");
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5be18eb94042..91cfd5890f46 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -474,7 +474,7 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
int ret, tries = 0;
while (1) {
- ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
+ ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
250, 1);
if (ret != -EAGAIN || ++tries == 3)
break;
@@ -1739,7 +1739,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
* Spec states that we should timeout the request after 200us
* but the function below will timeout after 500us
*/
- ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
+ ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
if (ret == 0) {
if (block &&
(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 44ac0cee8b77..8ea66a2e1b09 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -298,7 +298,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
* Mailbox interface.
*/
if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
- ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
+ ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1);
if (ret) {
drm_err(&dev_priv->drm,
"Failed to initiate HDCP key load (%d)\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 0c6b9eb724ae..90a440865037 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -138,7 +138,7 @@ static int gen6_drpc(struct seq_file *m)
}
if (GRAPHICS_VER(i915) <= 7)
- snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+ snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
seq_printf(m, "RC1e Enabled: %s\n",
str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -545,7 +545,7 @@ static int llc_show(struct seq_file *m, void *data)
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
- snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&ia_freq, NULL);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(rps,
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 40e2e28ee6c7..14fe65812e42 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -124,7 +124,6 @@ static void calc_ia_freq(struct intel_llc *llc,
static void gen6_update_ring_freq(struct intel_llc *llc)
{
- struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
struct ia_constants consts;
unsigned int gpu_freq;
@@ -142,7 +141,7 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
unsigned int ia_freq, ring_freq;
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
- snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
+ snb_pcode_write(llc_to_gt(llc)->uncore, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
gpu_freq);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index b4770690e794..f8d0523f4c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -272,7 +272,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_HW_ENABLE;
rc6vids = 0;
- ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+ ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
if (GRAPHICS_VER(i915) == 6 && ret) {
drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
} else if (GRAPHICS_VER(i915) == 6 &&
@@ -282,7 +282,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
rc6vids &= 0xffff00;
rc6vids |= GEN6_ENCODE_RC6_VID(450);
- ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+ ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
if (ret)
drm_err(&i915->drm,
"Couldn't fix incorrect rc6 voltage\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3bd8415a0f1b..a62d323ff056 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1144,7 +1144,7 @@ static void gen6_rps_init(struct intel_rps *rps)
if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11)
mult = GEN9_FREQ_SCALER;
- if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ if (snb_pcode_read(rps_to_gt(rps)->uncore, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
&ddcc_status, NULL) == 0)
rps->efficient_freq =
clamp_t(u32,
@@ -1984,7 +1984,7 @@ void intel_rps_init(struct intel_rps *rps)
if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
u32 params = 0;
- snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
+ snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, ¶ms, NULL);
if (params & BIT(31)) { /* OC supported */
drm_dbg(&i915->drm,
"Overclocking supported, max: %dMHz, overclock: %dMHz\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
index 2cd184ab32b1..cfd736d88939 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -31,7 +31,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
val = gpu_freq;
- if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ if (snb_pcode_read(llc_to_gt(llc)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&val, NULL)) {
pr_err("Failed to read freq table[%d], range [%d, %d]\n",
gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 6a69ac0184ad..cfb4708dd62e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -521,7 +521,7 @@ static void show_pcu_config(struct intel_rps *rps)
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
int ia_freq = gpu_freq;
- snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&ia_freq, NULL);
pr_info("%5d %5d %5d\n",
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index ed6028fd442d..b47746152d97 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -629,7 +629,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
intel_opregion_setup(dev_priv);
- ret = intel_pcode_init(dev_priv);
+ ret = intel_pcode_init(&dev_priv->uncore);
if (ret)
goto err_msi;
@@ -1251,7 +1251,7 @@ static int i915_drm_resume(struct drm_device *dev)
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
- ret = intel_pcode_init(dev_priv);
+ ret = intel_pcode_init(&dev_priv->uncore);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 2b9e7833da96..437447119770 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -393,7 +393,7 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
u32 val = 0;
int ret;
- ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index ac727546868e..2be700932322 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -52,14 +52,12 @@ static int gen7_check_mailbox_status(u32 mbox)
}
}
-static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
+static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
u32 *val, u32 *val1,
int fast_timeout_us, int slow_timeout_ms,
bool is_read)
{
- struct intel_uncore *uncore = &i915->uncore;
-
- lockdep_assert_held(&i915->sb_lock);
+ lockdep_assert_held(&uncore->i915->sb_lock);
/*
* GEN6_PCODE_* are outside of the forcewake domain, we can use
@@ -88,22 +86,22 @@ static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (GRAPHICS_VER(i915) > 6)
+ if (GRAPHICS_VER(uncore->i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
}
-int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
+int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
{
int err;
- mutex_lock(&i915->sb_lock);
- err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
- mutex_unlock(&i915->sb_lock);
+ mutex_lock(&uncore->i915->sb_lock);
+ err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
+ mutex_unlock(&uncore->i915->sb_lock);
if (err) {
- drm_dbg(&i915->drm,
+ drm_dbg(&uncore->i915->drm,
"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
mbox, __builtin_return_address(0), err);
}
@@ -111,18 +109,18 @@ int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
return err;
}
-int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
int fast_timeout_us, int slow_timeout_ms)
{
int err;
- mutex_lock(&i915->sb_lock);
- err = __snb_pcode_rw(i915, mbox, &val, NULL,
+ mutex_lock(&uncore->i915->sb_lock);
+ err = __snb_pcode_rw(uncore, mbox, &val, NULL,
fast_timeout_us, slow_timeout_ms, false);
- mutex_unlock(&i915->sb_lock);
+ mutex_unlock(&uncore->i915->sb_lock);
if (err) {
- drm_dbg(&i915->drm,
+ drm_dbg(&uncore->i915->drm,
"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
val, mbox, __builtin_return_address(0), err);
}
@@ -130,18 +128,18 @@ int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
return err;
}
-static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
+static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
u32 request, u32 reply_mask, u32 reply,
u32 *status)
{
- *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
+ *status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);
return (*status == 0) && ((request & reply_mask) == reply);
}
/**
* skl_pcode_request - send PCODE request until acknowledgment
- * @i915: device private
+ * @uncore: uncore
* @mbox: PCODE mailbox ID the request is targeted for
* @request: request ID
* @reply_mask: mask used to check for request acknowledgment
@@ -158,16 +156,16 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
* other error as reported by PCODE.
*/
-int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms)
{
u32 status;
int ret;
- mutex_lock(&i915->sb_lock);
+ mutex_lock(&uncore->i915->sb_lock);
#define COND \
- skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
+ skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, &status)
/*
* Prime the PCODE by doing a request first. Normally it guarantees
@@ -193,35 +191,26 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
* requests, and for any quirks of the PCODE firmware that delays
* the request completion.
*/
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(&uncore->i915->drm,
"PCODE timeout, retrying with preemption disabled\n");
- drm_WARN_ON_ONCE(&i915->drm, timeout_base_ms > 3);
+ drm_WARN_ON_ONCE(&uncore->i915->drm, timeout_base_ms > 3);
preempt_disable();
ret = wait_for_atomic(COND, 50);
preempt_enable();
out:
- mutex_unlock(&i915->sb_lock);
+ mutex_unlock(&uncore->i915->sb_lock);
return status ? status : ret;
#undef COND
}
-int intel_pcode_init(struct drm_i915_private *i915)
+int intel_pcode_init(struct intel_uncore *uncore)
{
- int ret = 0;
-
- if (!IS_DGFX(i915))
- return ret;
-
- ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
- DG1_UNCORE_GET_INIT_STATUS,
- DG1_UNCORE_INIT_STATUS_COMPLETE,
- DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
-
- drm_dbg(&i915->drm, "PCODE init status %d\n", ret);
-
- if (ret)
- drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+ if (!IS_DGFX(uncore->i915))
+ return 0;
- return ret;
+ return skl_pcode_request(uncore, DG1_PCODE_STATUS,
+ DG1_UNCORE_GET_INIT_STATUS,
+ DG1_UNCORE_INIT_STATUS_COMPLETE,
+ DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 0962a17fac48..8f6241b114a5 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -8,17 +8,17 @@
#include <linux/types.h>
-struct drm_i915_private;
+struct intel_uncore;
-int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
-int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
int fast_timeout_us, int slow_timeout_ms);
-#define snb_pcode_write(i915, mbox, val) \
- snb_pcode_write_timeout(i915, mbox, val, 500, 0)
+#define snb_pcode_write(uncore, mbox, val) \
+ snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
-int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-int intel_pcode_init(struct drm_i915_private *i915);
+int intel_pcode_init(struct intel_uncore *uncore);
#endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee0047fdc95d..aacb21cbc62e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2874,7 +2874,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
- ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
&val, NULL);
if (ret) {
@@ -2893,7 +2893,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the second set of memory latencies[4:7] */
val = 1; /* data0 to be programmed to 1 for second set */
- ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
&val, NULL);
if (ret) {
drm_err(&dev_priv->drm,
@@ -3679,7 +3679,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
u32 val = 0;
int ret;
- ret = snb_pcode_read(dev_priv,
+ ret = snb_pcode_read(&dev_priv->uncore,
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
&val, NULL);
if (ret) {
@@ -3748,7 +3748,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
return;
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
- ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+ ret = snb_pcode_write(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_ENABLE);
/* We don't need to wait for SAGV when enabling */
@@ -3781,7 +3781,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
/* bspec says to keep retrying for at least 1 ms */
- ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+ ret = skl_pcode_request(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_DISABLE,
GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
1);
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [CI 2/3] drm/i915/pcode: Extend pcode functions for multiple gt's
@ 2022-05-19 8:57 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-05-19 8:57 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Ashutosh Dixit <ashutosh.dixit@intel.com>
Each gt contains an independent instance of pcode. Extend pcode functions
to interface with pcode on different gt's. To avoid creating dependency of
display functionality on intel_gt, pcode function interfaces are exposed in
terms of uncore rather than intel_gt. Callers have been converted to pass
in the appropritate (i915 or intel_gt) uncore to the pcode functions.
v2: Expose pcode functions in terms of uncore rather than gt (Jani/Rodrigo)
v3: Retain previous function names to eliminate needless #defines (Rodrigo)
v4: Move out i915_pcode_init() to a separate patch (Tvrtko)
Remove duplicated drm_err/drm_dbg from intel_pcode_init() (Tvrtko)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 4 +-
drivers/gpu/drm/i915/display/intel_bw.c | 6 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 16 ++---
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_llc.c | 3 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 4 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_llc.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 2 +-
drivers/gpu/drm/i915/i915_driver.c | 4 +-
drivers/gpu/drm/i915/intel_dram.c | 2 +-
drivers/gpu/drm/i915/intel_pcode.c | 69 ++++++++-----------
drivers/gpu/drm/i915/intel_pcode.h | 14 ++--
drivers/gpu/drm/i915/intel_pm.c | 10 +--
17 files changed, 70 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 38014e0cc9ad..861dcd2eb890 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -28,7 +28,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
if (IS_BROADWELL(i915)) {
drm_WARN_ON(&i915->drm,
- snb_pcode_write(i915, DISPLAY_IPS_CONTROL,
+ snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
IPS_ENABLE | IPS_PCODE_CONTROL));
/*
* Quoting Art Runyan: "its not safe to expect any particular
@@ -62,7 +62,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
if (IS_BROADWELL(i915)) {
drm_WARN_ON(&i915->drm,
- snb_pcode_write(i915, DISPLAY_IPS_CONTROL, 0));
+ snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 37bd7b17f3d0..79269d2c476b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -78,7 +78,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
u16 dclk;
int ret;
- ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
&val, &val2);
if (ret)
@@ -104,7 +104,7 @@ static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
int ret;
int i;
- ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
if (ret)
return ret;
@@ -123,7 +123,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
int ret;
/* bspec says to keep retrying for at least 1 ms */
- ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
points_mask,
ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b2017d8161b4..6e80162632dd 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -800,7 +800,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
"trying to change cdclk frequency with cdclk not enabled\n"))
return;
- ret = snb_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+ ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
if (ret) {
drm_err(&dev_priv->drm,
"failed to inform pcode about cdclk change\n");
@@ -828,7 +828,7 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
- snb_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
+ snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_config->voltage_level);
intel_de_write(dev_priv, CDCLK_FREQ,
@@ -1086,7 +1086,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
drm_WARN_ON_ONCE(&dev_priv->drm,
IS_SKYLAKE(dev_priv) && vco == 8640000);
- ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1132,7 +1132,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_posting_read(dev_priv, CDCLK_CTL);
/* inform PCU of the change */
- snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
intel_update_cdclk(dev_priv);
@@ -1702,7 +1702,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
/* Inform power controller of upcoming frequency change. */
if (DISPLAY_VER(dev_priv) >= 11)
- ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
@@ -1711,7 +1711,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* BSpec requires us to wait up to 150usec, but that leads to
* timeouts; the 2ms used here is based on experiment.
*/
- ret = snb_pcode_write_timeout(dev_priv,
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
HSW_PCODE_DE_WRITE_FREQ_REQ,
0x80000000, 150, 2);
if (ret) {
@@ -1774,7 +1774,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
if (DISPLAY_VER(dev_priv) >= 11) {
- ret = snb_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
+ ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
cdclk_config->voltage_level);
} else {
/*
@@ -1783,7 +1783,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* FIXME: Waiting for the request completion could be delayed
* until the next PCODE request based on BSpec.
*/
- ret = snb_pcode_write_timeout(dev_priv,
+ ret = snb_pcode_write_timeout(&dev_priv->uncore,
HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_config->voltage_level,
150, 2);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5eb8d63fb89e..fb17439bd4f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1196,7 +1196,7 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
{
if (IS_HASWELL(dev_priv)) {
- if (snb_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
+ if (snb_pcode_write(&dev_priv->uncore, GEN6_PCODE_WRITE_D_COMP, val))
drm_dbg_kms(&dev_priv->drm,
"Failed to write to D_COMP\n");
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5be18eb94042..91cfd5890f46 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -474,7 +474,7 @@ static void icl_tc_cold_exit(struct drm_i915_private *i915)
int ret, tries = 0;
while (1) {
- ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
+ ret = snb_pcode_write_timeout(&i915->uncore, ICL_PCODE_EXIT_TCCOLD, 0,
250, 1);
if (ret != -EAGAIN || ++tries == 3)
break;
@@ -1739,7 +1739,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
* Spec states that we should timeout the request after 200us
* but the function below will timeout after 500us
*/
- ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
+ ret = snb_pcode_read(&i915->uncore, TGL_PCODE_TCCOLD, &low_val, &high_val);
if (ret == 0) {
if (block &&
(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 44ac0cee8b77..8ea66a2e1b09 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -298,7 +298,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
* Mailbox interface.
*/
if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
- ret = snb_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1);
+ ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1);
if (ret) {
drm_err(&dev_priv->drm,
"Failed to initiate HDCP key load (%d)\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 0c6b9eb724ae..90a440865037 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -138,7 +138,7 @@ static int gen6_drpc(struct seq_file *m)
}
if (GRAPHICS_VER(i915) <= 7)
- snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+ snb_pcode_read(gt->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
seq_printf(m, "RC1e Enabled: %s\n",
str_yes_no(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -545,7 +545,7 @@ static int llc_show(struct seq_file *m, void *data)
wakeref = intel_runtime_pm_get(gt->uncore->rpm);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
- snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ snb_pcode_read(gt->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&ia_freq, NULL);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(rps,
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 40e2e28ee6c7..14fe65812e42 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -124,7 +124,6 @@ static void calc_ia_freq(struct intel_llc *llc,
static void gen6_update_ring_freq(struct intel_llc *llc)
{
- struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
struct ia_constants consts;
unsigned int gpu_freq;
@@ -142,7 +141,7 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
unsigned int ia_freq, ring_freq;
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
- snb_pcode_write(i915, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
+ snb_pcode_write(llc_to_gt(llc)->uncore, GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
gpu_freq);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index b4770690e794..f8d0523f4c18 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -272,7 +272,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_HW_ENABLE;
rc6vids = 0;
- ret = snb_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
+ ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
if (GRAPHICS_VER(i915) == 6 && ret) {
drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
} else if (GRAPHICS_VER(i915) == 6 &&
@@ -282,7 +282,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
rc6vids &= 0xffff00;
rc6vids |= GEN6_ENCODE_RC6_VID(450);
- ret = snb_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
+ ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
if (ret)
drm_err(&i915->drm,
"Couldn't fix incorrect rc6 voltage\n");
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 3bd8415a0f1b..a62d323ff056 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1144,7 +1144,7 @@ static void gen6_rps_init(struct intel_rps *rps)
if (IS_GEN9_BC(i915) || GRAPHICS_VER(i915) >= 11)
mult = GEN9_FREQ_SCALER;
- if (snb_pcode_read(i915, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
+ if (snb_pcode_read(rps_to_gt(rps)->uncore, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
&ddcc_status, NULL) == 0)
rps->efficient_freq =
clamp_t(u32,
@@ -1984,7 +1984,7 @@ void intel_rps_init(struct intel_rps *rps)
if (GRAPHICS_VER(i915) == 6 || IS_IVYBRIDGE(i915) || IS_HASWELL(i915)) {
u32 params = 0;
- snb_pcode_read(i915, GEN6_READ_OC_PARAMS, ¶ms, NULL);
+ snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_READ_OC_PARAMS, ¶ms, NULL);
if (params & BIT(31)) { /* OC supported */
drm_dbg(&i915->drm,
"Overclocking supported, max: %dMHz, overclock: %dMHz\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
index 2cd184ab32b1..cfd736d88939 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -31,7 +31,7 @@ static int gen6_verify_ring_freq(struct intel_llc *llc)
calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
val = gpu_freq;
- if (snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ if (snb_pcode_read(llc_to_gt(llc)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&val, NULL)) {
pr_err("Failed to read freq table[%d], range [%d, %d]\n",
gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 6a69ac0184ad..cfb4708dd62e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -521,7 +521,7 @@ static void show_pcu_config(struct intel_rps *rps)
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
int ia_freq = gpu_freq;
- snb_pcode_read(i915, GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ snb_pcode_read(rps_to_gt(rps)->uncore, GEN6_PCODE_READ_MIN_FREQ_TABLE,
&ia_freq, NULL);
pr_info("%5d %5d %5d\n",
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index ed6028fd442d..b47746152d97 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -629,7 +629,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
intel_opregion_setup(dev_priv);
- ret = intel_pcode_init(dev_priv);
+ ret = intel_pcode_init(&dev_priv->uncore);
if (ret)
goto err_msi;
@@ -1251,7 +1251,7 @@ static int i915_drm_resume(struct drm_device *dev)
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
- ret = intel_pcode_init(dev_priv);
+ ret = intel_pcode_init(&dev_priv->uncore);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 2b9e7833da96..437447119770 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -393,7 +393,7 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
u32 val = 0;
int ret;
- ret = snb_pcode_read(dev_priv, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index ac727546868e..2be700932322 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -52,14 +52,12 @@ static int gen7_check_mailbox_status(u32 mbox)
}
}
-static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
+static int __snb_pcode_rw(struct intel_uncore *uncore, u32 mbox,
u32 *val, u32 *val1,
int fast_timeout_us, int slow_timeout_ms,
bool is_read)
{
- struct intel_uncore *uncore = &i915->uncore;
-
- lockdep_assert_held(&i915->sb_lock);
+ lockdep_assert_held(&uncore->i915->sb_lock);
/*
* GEN6_PCODE_* are outside of the forcewake domain, we can use
@@ -88,22 +86,22 @@ static int __snb_pcode_rw(struct drm_i915_private *i915, u32 mbox,
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
- if (GRAPHICS_VER(i915) > 6)
+ if (GRAPHICS_VER(uncore->i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
}
-int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
+int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)
{
int err;
- mutex_lock(&i915->sb_lock);
- err = __snb_pcode_rw(i915, mbox, val, val1, 500, 20, true);
- mutex_unlock(&i915->sb_lock);
+ mutex_lock(&uncore->i915->sb_lock);
+ err = __snb_pcode_rw(uncore, mbox, val, val1, 500, 20, true);
+ mutex_unlock(&uncore->i915->sb_lock);
if (err) {
- drm_dbg(&i915->drm,
+ drm_dbg(&uncore->i915->drm,
"warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
mbox, __builtin_return_address(0), err);
}
@@ -111,18 +109,18 @@ int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1)
return err;
}
-int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
int fast_timeout_us, int slow_timeout_ms)
{
int err;
- mutex_lock(&i915->sb_lock);
- err = __snb_pcode_rw(i915, mbox, &val, NULL,
+ mutex_lock(&uncore->i915->sb_lock);
+ err = __snb_pcode_rw(uncore, mbox, &val, NULL,
fast_timeout_us, slow_timeout_ms, false);
- mutex_unlock(&i915->sb_lock);
+ mutex_unlock(&uncore->i915->sb_lock);
if (err) {
- drm_dbg(&i915->drm,
+ drm_dbg(&uncore->i915->drm,
"warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
val, mbox, __builtin_return_address(0), err);
}
@@ -130,18 +128,18 @@ int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
return err;
}
-static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
+static bool skl_pcode_try_request(struct intel_uncore *uncore, u32 mbox,
u32 request, u32 reply_mask, u32 reply,
u32 *status)
{
- *status = __snb_pcode_rw(i915, mbox, &request, NULL, 500, 0, true);
+ *status = __snb_pcode_rw(uncore, mbox, &request, NULL, 500, 0, true);
return (*status == 0) && ((request & reply_mask) == reply);
}
/**
* skl_pcode_request - send PCODE request until acknowledgment
- * @i915: device private
+ * @uncore: uncore
* @mbox: PCODE mailbox ID the request is targeted for
* @request: request ID
* @reply_mask: mask used to check for request acknowledgment
@@ -158,16 +156,16 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
* Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
* other error as reported by PCODE.
*/
-int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms)
{
u32 status;
int ret;
- mutex_lock(&i915->sb_lock);
+ mutex_lock(&uncore->i915->sb_lock);
#define COND \
- skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
+ skl_pcode_try_request(uncore, mbox, request, reply_mask, reply, &status)
/*
* Prime the PCODE by doing a request first. Normally it guarantees
@@ -193,35 +191,26 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
* requests, and for any quirks of the PCODE firmware that delays
* the request completion.
*/
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(&uncore->i915->drm,
"PCODE timeout, retrying with preemption disabled\n");
- drm_WARN_ON_ONCE(&i915->drm, timeout_base_ms > 3);
+ drm_WARN_ON_ONCE(&uncore->i915->drm, timeout_base_ms > 3);
preempt_disable();
ret = wait_for_atomic(COND, 50);
preempt_enable();
out:
- mutex_unlock(&i915->sb_lock);
+ mutex_unlock(&uncore->i915->sb_lock);
return status ? status : ret;
#undef COND
}
-int intel_pcode_init(struct drm_i915_private *i915)
+int intel_pcode_init(struct intel_uncore *uncore)
{
- int ret = 0;
-
- if (!IS_DGFX(i915))
- return ret;
-
- ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
- DG1_UNCORE_GET_INIT_STATUS,
- DG1_UNCORE_INIT_STATUS_COMPLETE,
- DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
-
- drm_dbg(&i915->drm, "PCODE init status %d\n", ret);
-
- if (ret)
- drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
+ if (!IS_DGFX(uncore->i915))
+ return 0;
- return ret;
+ return skl_pcode_request(uncore, DG1_PCODE_STATUS,
+ DG1_UNCORE_GET_INIT_STATUS,
+ DG1_UNCORE_INIT_STATUS_COMPLETE,
+ DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 0962a17fac48..8f6241b114a5 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -8,17 +8,17 @@
#include <linux/types.h>
-struct drm_i915_private;
+struct intel_uncore;
-int snb_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val, u32 *val1);
-int snb_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, u32 val,
+int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
+int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
int fast_timeout_us, int slow_timeout_ms);
-#define snb_pcode_write(i915, mbox, val) \
- snb_pcode_write_timeout(i915, mbox, val, 500, 0)
+#define snb_pcode_write(uncore, mbox, val) \
+ snb_pcode_write_timeout(uncore, mbox, val, 500, 0)
-int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-int intel_pcode_init(struct drm_i915_private *i915);
+int intel_pcode_init(struct intel_uncore *uncore);
#endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ee0047fdc95d..aacb21cbc62e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2874,7 +2874,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
- ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
&val, NULL);
if (ret) {
@@ -2893,7 +2893,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the second set of memory latencies[4:7] */
val = 1; /* data0 to be programmed to 1 for second set */
- ret = snb_pcode_read(dev_priv, GEN9_PCODE_READ_MEM_LATENCY,
+ ret = snb_pcode_read(&dev_priv->uncore, GEN9_PCODE_READ_MEM_LATENCY,
&val, NULL);
if (ret) {
drm_err(&dev_priv->drm,
@@ -3679,7 +3679,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
u32 val = 0;
int ret;
- ret = snb_pcode_read(dev_priv,
+ ret = snb_pcode_read(&dev_priv->uncore,
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
&val, NULL);
if (ret) {
@@ -3748,7 +3748,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
return;
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
- ret = snb_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+ ret = snb_pcode_write(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_ENABLE);
/* We don't need to wait for SAGV when enabling */
@@ -3781,7 +3781,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
/* bspec says to keep retrying for at least 1 ms */
- ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
+ ret = skl_pcode_request(&dev_priv->uncore, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_DISABLE,
GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
1);
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [CI 3/3] drm/i915/pcode: Add a couple of pcode helpers
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-19 8:57 ` Tvrtko Ursulin
-1 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-05-19 8:57 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Dale B Stimson <dale.b.stimson@intel.com>
Some dGfx pcode commands take additional sub-commands and parameters. Add a
couple of helpers to help formatting these commands to improve code
readability.
v2: Fixed commit author (Rodrigo)
v3: Function rename and convert to new uncore interface for pcode functions
Remove unnecessary #define's (Andi)
v4: Another function rename
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pcode.c | 32 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pcode.h | 6 ++++++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dff3f88d8090..d8579ab9384c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6735,6 +6735,9 @@
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
+#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
+#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
+#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
#define GEN6_PCODE_ERROR_MASK 0xFF
#define GEN6_PCODE_SUCCESS 0x0
#define GEN6_PCODE_ILLEGAL_CMD 0x1
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 2be700932322..a234d9b4ed14 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -214,3 +214,35 @@ int intel_pcode_init(struct intel_uncore *uncore)
DG1_UNCORE_INIT_STATUS_COMPLETE,
DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
}
+
+int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
+{
+ intel_wakeref_t wakeref;
+ u32 mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ err = snb_pcode_read(uncore, mbox, val, NULL);
+
+ return err;
+}
+
+int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
+{
+ intel_wakeref_t wakeref;
+ u32 mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ err = snb_pcode_write(uncore, mbox, val);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8f6241b114a5..8d2198e29422 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -21,4 +21,10 @@ int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
int intel_pcode_init(struct intel_uncore *uncore);
+/*
+ * Helpers for dGfx PCODE mailbox command formatting
+ */
+int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
+int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
+
#endif /* _INTEL_PCODE_H */
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [CI 3/3] drm/i915/pcode: Add a couple of pcode helpers
@ 2022-05-19 8:57 ` Tvrtko Ursulin
0 siblings, 0 replies; 9+ messages in thread
From: Tvrtko Ursulin @ 2022-05-19 8:57 UTC (permalink / raw)
To: Intel-gfx; +Cc: dri-devel
From: Dale B Stimson <dale.b.stimson@intel.com>
Some dGfx pcode commands take additional sub-commands and parameters. Add a
couple of helpers to help formatting these commands to improve code
readability.
v2: Fixed commit author (Rodrigo)
v3: Function rename and convert to new uncore interface for pcode functions
Remove unnecessary #define's (Andi)
v4: Another function rename
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pcode.c | 32 ++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pcode.h | 6 ++++++
3 files changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dff3f88d8090..d8579ab9384c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6735,6 +6735,9 @@
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
#define GEN6_PCODE_READY (1 << 31)
+#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
+#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
+#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
#define GEN6_PCODE_ERROR_MASK 0xFF
#define GEN6_PCODE_SUCCESS 0x0
#define GEN6_PCODE_ILLEGAL_CMD 0x1
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 2be700932322..a234d9b4ed14 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -214,3 +214,35 @@ int intel_pcode_init(struct intel_uncore *uncore)
DG1_UNCORE_INIT_STATUS_COMPLETE,
DG1_UNCORE_INIT_STATUS_COMPLETE, 180000);
}
+
+int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val)
+{
+ intel_wakeref_t wakeref;
+ u32 mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ err = snb_pcode_read(uncore, mbox, val, NULL);
+
+ return err;
+}
+
+int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val)
+{
+ intel_wakeref_t wakeref;
+ u32 mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1)
+ | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2);
+
+ with_intel_runtime_pm(uncore->rpm, wakeref)
+ err = snb_pcode_write(uncore, mbox, val);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8f6241b114a5..8d2198e29422 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -21,4 +21,10 @@ int skl_pcode_request(struct intel_uncore *uncore, u32 mbox, u32 request,
int intel_pcode_init(struct intel_uncore *uncore);
+/*
+ * Helpers for dGfx PCODE mailbox command formatting
+ */
+int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
+int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
+
#endif /* _INTEL_PCODE_H */
--
2.32.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
` (2 preceding siblings ...)
(?)
@ 2022-05-19 13:20 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-05-19 13:20 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode
URL : https://patchwork.freedesktop.org/series/104165/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
` (3 preceding siblings ...)
(?)
@ 2022-05-19 13:41 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-05-19 13:41 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5786 bytes --]
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode
URL : https://patchwork.freedesktop.org/series/104165/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11677 -> Patchwork_104165v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/index.html
Participating hosts (46 -> 46)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_104165v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [PASS][1] -> [INCOMPLETE][2] ([i915#4418])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/fi-pnv-d510/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: [PASS][5] -> [INCOMPLETE][6] ([i915#5982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#402])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_lrc:
- {bat-dg2-9}: [DMESG-WARN][9] ([i915#5763]) -> [PASS][10] +7 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/bat-dg2-9/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@flip:
- bat-adlp-4: [DMESG-WARN][13] ([i915#1982] / [i915#3576]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/bat-adlp-4/igt@kms_busy@basic@flip.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/bat-adlp-4/igt@kms_busy@basic@flip.html
* igt@kms_busy@basic@modeset:
- {bat-adlp-6}: [DMESG-WARN][15] ([i915#3576]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/bat-adlp-6/igt@kms_busy@basic@modeset.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/bat-adlp-6/igt@kms_busy@basic@modeset.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- fi-tgl-u2: [DMESG-WARN][17] ([i915#402]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
- bat-adlp-4: [DMESG-WARN][19] ([i915#3576]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5879]: https://gitlab.freedesktop.org/drm/intel/issues/5879
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
Build changes
-------------
* Linux: CI_DRM_11677 -> Patchwork_104165v1
CI-20190529: 20190529
CI_DRM_11677: e98617aab83890ce7097639943e65ce1420f8983 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6481: f2a9c2e6f6f7aa97e5d92274f20aa698087359c4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104165v1: e98617aab83890ce7097639943e65ce1420f8983 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
6cc6aa9444e4 drm/i915/pcode: Add a couple of pcode helpers
bbc1d5590a5a drm/i915/pcode: Extend pcode functions for multiple gt's
b8ea956367f1 drm/i915: Introduce has_media_ratio_mode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/index.html
[-- Attachment #2: Type: text/html, Size: 6713 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
` (4 preceding siblings ...)
(?)
@ 2022-05-19 16:18 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-05-19 16:18 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 47881 bytes --]
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode
URL : https://patchwork.freedesktop.org/series/104165/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11677_full -> Patchwork_104165v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_104165v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_104165v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (13 -> 11)
------------------------------
Missing (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104165v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@prime_self_import@export-vs-gem_close-race:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@prime_self_import@export-vs-gem_close-race.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl6/igt@prime_self_import@export-vs-gem_close-race.html
Known issues
------------
Here are the changes found in Patchwork_104165v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][3] -> [TIMEOUT][4] ([i915#3070])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb8/igt@gem_eio@unwedge-stress.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][5] ([i915#2846])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_params@no-vebox:
- shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271]) +161 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl7/igt@gem_exec_params@no-vebox.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][12] ([i915#2190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- shard-skl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl5/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#4613])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@gem_lmem_swapping@verify-ccs.html
- shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][16] ([i915#768])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-tglb: NOTRUN -> [SKIP][17] ([i915#3297])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@input-checking:
- shard-iclb: NOTRUN -> [DMESG-WARN][18] ([i915#4991])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@gem_userptr_blits@input-checking.html
* igt@gen3_mixed_blits:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@gen3_mixed_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-tglb: NOTRUN -> [SKIP][20] ([i915#2527] / [i915#2856])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@gen9_exec_parse@allowed-single.html
- shard-glk: [PASS][21] -> [DMESG-WARN][22] ([i915#5566] / [i915#716])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk4/igt@gen9_exec_parse@allowed-single.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk6/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-iclb: NOTRUN -> [SKIP][23] ([i915#2856])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: NOTRUN -> [SKIP][24] ([i915#658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rpm@pc8-residency:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#109293] / [fdo#109506])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#109303])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@i915_query@query-topology-known-pci-ids.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#5286]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#5286])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110725] / [fdo#111614])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][30] ([i915#3743]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111614])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-glk: [PASS][32] -> [FAIL][33] ([i915#1888] / [i915#5138])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk2/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk9/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#111615]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#3689]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278] / [i915#3886]) +4 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +8 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl9/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#111615] / [i915#3689])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][40] ([i915#3742])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +10 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl5/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@vga-hpd:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#109284] / [fdo#111827]) +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +4 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#1063]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-iclb: NOTRUN -> [SKIP][46] ([i915#3116])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][47] ([i915#1319])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#3319]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html
* igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109278] / [fdo#109279]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_cursor_crc@pipe-a-cursor-512x512-rapid-movement.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274] / [fdo#109278]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: NOTRUN -> [FAIL][52] ([i915#2346])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-iclb: NOTRUN -> [SKIP][54] ([i915#6029])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
* igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#5287])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled:
- shard-iclb: NOTRUN -> [SKIP][56] ([i915#5287])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#109274] / [fdo#111825]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109274]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][59] -> [FAIL][60] ([i915#79])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +4 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [PASS][63] -> [INCOMPLETE][64] ([i915#4839])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl6/igt@kms_flip@flip-vs-suspend@b-edp1.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl5/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip@plain-flip-ts-check@b-edp1:
- shard-skl: [PASS][65] -> [FAIL][66] ([i915#2122])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl5/igt@kms_flip@plain-flip-ts-check@b-edp1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl3/igt@kms_flip@plain-flip-ts-check@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-iclb: NOTRUN -> [SKIP][67] ([i915#2587])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271]) +64 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109280]) +10 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-skl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#1888])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][71] ([i915#5439])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
- shard-tglb: NOTRUN -> [SKIP][72] ([fdo#109280] / [fdo#111825]) +13 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][73] -> [FAIL][74] ([fdo#108145] / [i915#265])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][75] ([fdo#108145] / [i915#265])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109278]) +15 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-a-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][77] ([i915#3536]) +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-none.html
* igt@kms_plane_lowres@pipe-b-tiling-4:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#5288])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_plane_lowres@pipe-b-tiling-4.html
* igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-c-edp-1-downscale-with-modifier:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#5176]) +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_plane_scaling@downscale-with-modifier-factor-0-25@pipe-c-edp-1-downscale-with-modifier.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][80] -> [SKIP][81] ([i915#5235]) +2 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_basic:
- shard-tglb: NOTRUN -> [FAIL][83] ([i915#132] / [i915#3467]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@kms_psr@psr2_basic.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109441])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][85] -> [SKIP][86] ([fdo#109441]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-iclb: NOTRUN -> [SKIP][87] ([i915#5289])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_tv_load_detect@load-detect:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109309])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][89] -> [DMESG-WARN][90] ([i915#180]) +3 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_writeback@writeback-fb-id:
- shard-skl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2437])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl5/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#2437])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#2530])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-c-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][94] ([i915#2530])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@nouveau_crc@pipe-c-source-outp-inactive.html
* igt@perf@mi-rpc:
- shard-tglb: NOTRUN -> [SKIP][95] ([fdo#109289]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@perf@mi-rpc.html
* igt@perf_pmu@module-unload:
- shard-skl: [PASS][96] -> [DMESG-WARN][97] ([i915#1982])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl10/igt@perf_pmu@module-unload.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl1/igt@perf_pmu@module-unload.html
* igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
- shard-tglb: NOTRUN -> [SKIP][98] ([fdo#109291])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html
* igt@prime_nv_test@i915_import_cpu_mmap:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109291])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@prime_nv_test@i915_import_cpu_mmap.html
* igt@prime_vgem@coherency-gtt:
- shard-tglb: NOTRUN -> [SKIP][100] ([fdo#111656])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb8/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-read-hang:
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109295])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@prime_vgem@fence-read-hang.html
* igt@syncobj_timeline@transfer-timeline-point:
- shard-kbl: NOTRUN -> [DMESG-FAIL][102] ([i915#5098])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@syncobj_timeline@transfer-timeline-point.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][103] ([fdo#109271] / [i915#2994]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl5/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#2994]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@sysfs_clients@fair-3.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-1us:
- shard-glk: [TIMEOUT][105] ([i915#3063]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk9/igt@gem_eio@in-flight-contexts-1us.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk1/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_capture@pi@bcs0:
- shard-tglb: [INCOMPLETE][107] ([i915#3371]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-tglb2/igt@gem_exec_capture@pi@bcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglb7/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][109] ([i915#2842]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- {shard-tglu}: [FAIL][111] ([i915#2842]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][113] ([i915#2842]) -> [PASS][114] +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-iclb: [FAIL][115] ([i915#2842]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb8/igt@gem_exec_fair@basic-pace@bcs0.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb4/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-wb:
- shard-snb: [SKIP][117] ([fdo#109271]) -> [PASS][118] +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-snb4/igt@gem_exec_flush@basic-batch-kernel-default-wb.html
* igt@gem_exec_schedule@wide@rcs0:
- shard-apl: [FAIL][119] ([i915#5965]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-apl7/igt@gem_exec_schedule@wide@rcs0.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-apl7/igt@gem_exec_schedule@wide@rcs0.html
* igt@gem_exec_whisper@basic-queues-priority-all:
- shard-glk: [DMESG-WARN][121] ([i915#118]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk8/igt@gem_exec_whisper@basic-queues-priority-all.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk2/igt@gem_exec_whisper@basic-queues-priority-all.html
* igt@gem_softpin@evict-single-offset:
- {shard-tglu}: [FAIL][123] ([i915#4171]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-tglu-5/igt@gem_softpin@evict-single-offset.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-tglu-2/igt@gem_softpin@evict-single-offset.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][125] ([i915#4281]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][127] ([i915#2346]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][129] ([i915#2346] / [i915#533]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [INCOMPLETE][131] ([i915#1982] / [i915#4939]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl3/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][133] ([i915#180]) -> [PASS][134] +4 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [DMESG-WARN][135] ([i915#180]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][137] ([i915#2122]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-glk: [FAIL][139] ([i915#4911]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-glk4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [SKIP][141] ([i915#5235]) -> [PASS][142] +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][143] ([fdo#109441]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][145] ([i915#5639]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl5/igt@perf@polling-parameterized.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl9/igt@perf@polling-parameterized.html
* igt@prime_mmap@test_userptr@test_userptr-smem:
- shard-skl: [DMESG-WARN][147] ([i915#1982]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl10/igt@prime_mmap@test_userptr@test_userptr-smem.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl3/igt@prime_mmap@test_userptr@test_userptr-smem.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [DMESG-WARN][149] ([i915#5614]) -> [SKIP][150] ([i915#4525]) +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][151] ([i915#4525]) -> [DMESG-WARN][152] ([i915#5614])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][153] ([i915#2852]) -> [FAIL][154] ([i915#2842])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@kms_color@pipe-c-deep-color:
- shard-skl: [SKIP][155] ([fdo#109271]) -> [SKIP][156] ([fdo#109271] / [i915#1888])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl5/igt@kms_color@pipe-c-deep-color.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl9/igt@kms_color@pipe-c-deep-color.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-skl: [SKIP][157] ([fdo#109271] / [i915#1888]) -> [SKIP][158] ([fdo#109271]) +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl1/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl7/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [FAIL][159] ([i915#4767]) -> [INCOMPLETE][160] ([i915#180])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-iclb: [SKIP][161] ([i915#2920]) -> [SKIP][162] ([fdo#111068] / [i915#658])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-iclb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl1/igt@runner@aborted.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl3/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl7/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl3/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl6/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl7/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl1/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-kbl4/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl4/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl1/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl6/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl7/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl6/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-kbl6/igt@runner@aborted.html
- shard-skl: ([FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192], [FAIL][193]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197]) ([i915#3002] / [i915#4312] / [i915#5257])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl7/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl8/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl5/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl10/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11677/shard-skl5/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl1/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl10/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl2/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/shard-skl10/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5965]: https://gitlab.freedesktop.org/drm/intel/issues/5965
[i915#6029]: https://gitlab.freedesktop.org/drm/intel/issues/6029
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* Linux: CI_DRM_11677 -> Patchwork_104165v1
CI-20190529: 20190529
CI_DRM_11677: e98617aab83890ce7097639943e65ce1420f8983 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6481: f2a9c2e6f6f7aa97e5d92274f20aa698087359c4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104165v1: e98617aab83890ce7097639943e65ce1420f8983 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104165v1/index.html
[-- Attachment #2: Type: text/html, Size: 57601 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-05-19 16:18 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-19 8:57 [CI 1/3] drm/i915: Introduce has_media_ratio_mode Tvrtko Ursulin
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-19 8:57 ` [CI 2/3] drm/i915/pcode: Extend pcode functions for multiple gt's Tvrtko Ursulin
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-19 8:57 ` [CI 3/3] drm/i915/pcode: Add a couple of pcode helpers Tvrtko Ursulin
2022-05-19 8:57 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-19 13:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/3] drm/i915: Introduce has_media_ratio_mode Patchwork
2022-05-19 13:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-19 16:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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