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From: Anusha Srivatsa <anusha.srivatsa@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH] drm/i915/dg2: Enable DC5
Date: Fri, 20 May 2022 09:12:44 -0700	[thread overview]
Message-ID: <20220520161244.2571563-1-anusha.srivatsa@intel.com> (raw)

Enable DC5 on dg2.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fb17439bd4f8..f58e277fdadf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -908,7 +908,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		return 0;
 
 	if (IS_DG2(dev_priv))
-		max_dc = 0;
+		max_dc = 1;
 	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
-- 
2.25.1


             reply	other threads:[~2022-05-20 16:17 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-20 16:12 Anusha Srivatsa [this message]
2022-05-20 17:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Enable DC5 Patchwork
2022-05-20 23:11   ` Matt Roper
2022-05-21  6:49     ` Vudum, Lakshminarayana
2022-05-21 16:13     ` Srivatsa, Anusha
2022-05-22  6:34       ` Vudum, Lakshminarayana
2022-05-21  6:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-21  7:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-22  6:04 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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