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* [Intel-gfx] [PATCH] drm/i915/dg2: Enable DC5
@ 2022-05-20 16:12 Anusha Srivatsa
  2022-05-20 17:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 9+ messages in thread
From: Anusha Srivatsa @ 2022-05-20 16:12 UTC (permalink / raw)
  To: intel-gfx

Enable DC5 on dg2.

Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index fb17439bd4f8..f58e277fdadf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -908,7 +908,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		return 0;
 
 	if (IS_DG2(dev_priv))
-		max_dc = 0;
+		max_dc = 1;
 	else if (IS_DG1(dev_priv))
 		max_dc = 3;
 	else if (DISPLAY_VER(dev_priv) >= 12)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-05-22  6:34 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-20 16:12 [Intel-gfx] [PATCH] drm/i915/dg2: Enable DC5 Anusha Srivatsa
2022-05-20 17:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2022-05-20 23:11   ` Matt Roper
2022-05-21  6:49     ` Vudum, Lakshminarayana
2022-05-21 16:13     ` Srivatsa, Anusha
2022-05-22  6:34       ` Vudum, Lakshminarayana
2022-05-21  6:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-21  7:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-22  6:04 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork

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