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From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, Johan Hovold <johan@kernel.org>,
	Johan Hovold <johan+linaro@kernel.org>
Subject: [PATCH v11 6/7] arm64: dts: qcom: sm8250: provide additional MSI interrupts
Date: Fri, 20 May 2022 21:31:13 +0300	[thread overview]
Message-ID: <20220520183114.1356599-7-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220520183114.1356599-1-dmitry.baryshkov@linaro.org>

On SM8250 each group of MSI interrupts is mapped to the separate host
interrupt. Describe each of interrupts in the device tree for PCIe0
host.

Tested on Qualcomm RB5 platform with first group of MSI interrupts being
used by the PME and attached ath11k WiFi chip using second group of MSI
interrupts.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 410272a1e19b..523a035ffc5f 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1807,8 +1807,16 @@ pcie0: pci@1c00000 {
 			ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
 				 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
 
-			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "msi";
+			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi0", "msi1", "msi2", "msi3",
+					  "msi4", "msi5", "msi6", "msi7";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
-- 
2.35.1


  parent reply	other threads:[~2022-05-20 18:32 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-20 18:31 [PATCH v11 0/7] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 1/7] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 2/7] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 3/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-23  7:53   ` Johan Hovold
2022-05-23 13:39     ` Dmitry Baryshkov
2022-05-23 14:02       ` Johan Hovold
2022-05-23 15:17         ` Dmitry Baryshkov
2022-05-23 15:32           ` Johan Hovold
2022-05-23 15:36             ` Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 4/7] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-05-20 18:31 ` Dmitry Baryshkov [this message]
2022-05-20 18:31 ` [PATCH v11 7/7] dt-bindings: mfd: qcom,qca639x: add binding for QCA639x defvice Dmitry Baryshkov
2022-05-23  7:42 ` [PATCH v11 0/7] PCI: qcom: Fix higher MSI vectors handling Johan Hovold
2022-05-23 13:03   ` Dmitry Baryshkov

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