From: Nava kishore Manne <nava.manne@xilinx.com> To: <mdf@kernel.org>, <hao.wu@intel.com>, <yilun.xu@intel.com>, <trix@redhat.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <michal.simek@xilinx.com>, <nava.manne@xilinx.com>, <linux-fpga@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <git@xilinx.com> Cc: Rob Herring <robh@kernel.org> Subject: [PATCH v2 2/3] fpga: region: Add fpga-region 'power-domains' property Date: Mon, 23 May 2022 19:15:16 +0530 [thread overview] Message-ID: <20220523134517.4056873-3-nava.manne@xilinx.com> (raw) In-Reply-To: <20220523134517.4056873-1-nava.manne@xilinx.com> Add fpga-region 'power-domains' property to allow to handle the FPGA/PL power domains. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> --- Changes for v2: - Updated power-domains description. .../devicetree/bindings/fpga/fpga-region.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 7d3515264838..f299c3749505 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,20 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- power-domains : A phandle and power domain specifier pair to the power domain + which is responsible for turning on/off the power to the FPGA/PL region. +Example: + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&zynqmp_firmware PL_PD>; + }; + + The PL_PD power domain will be turned on before loading the bitstream +and turned off while removing/unloading the bitstream using overlays. In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. Two bridges are controlled during -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Nava kishore Manne <nava.manne@xilinx.com> To: <mdf@kernel.org>, <hao.wu@intel.com>, <yilun.xu@intel.com>, <trix@redhat.com>, <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>, <michal.simek@xilinx.com>, <nava.manne@xilinx.com>, <linux-fpga@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <git@xilinx.com> Cc: Rob Herring <robh@kernel.org> Subject: [PATCH v2 2/3] fpga: region: Add fpga-region 'power-domains' property Date: Mon, 23 May 2022 19:15:16 +0530 [thread overview] Message-ID: <20220523134517.4056873-3-nava.manne@xilinx.com> (raw) In-Reply-To: <20220523134517.4056873-1-nava.manne@xilinx.com> Add fpga-region 'power-domains' property to allow to handle the FPGA/PL power domains. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Acked-by: Rob Herring <robh@kernel.org> --- Changes for v2: - Updated power-domains description. .../devicetree/bindings/fpga/fpga-region.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index 7d3515264838..f299c3749505 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -196,6 +196,20 @@ Optional properties: - config-complete-timeout-us : The maximum time in microseconds time for the FPGA to go to operating mode after the region has been programmed. - child nodes : devices in the FPGA after programming. +- power-domains : A phandle and power domain specifier pair to the power domain + which is responsible for turning on/off the power to the FPGA/PL region. +Example: + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&zynqmp_pcap>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&zynqmp_firmware PL_PD>; + }; + + The PL_PD power domain will be turned on before loading the bitstream +and turned off while removing/unloading the bitstream using overlays. In the example below, when an overlay is applied targeting fpga-region0, fpga_mgr is used to program the FPGA. Two bridges are controlled during -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-05-23 13:46 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-23 13:45 [PATCH v2 0/3]Enable PM generic domain support Nava kishore Manne 2022-05-23 13:45 ` Nava kishore Manne 2022-05-23 13:45 ` [PATCH v2 1/3] dt-bindings: zynqmp: Add new PD_PL macro Nava kishore Manne 2022-05-23 13:45 ` Nava kishore Manne 2022-05-23 13:45 ` Nava kishore Manne [this message] 2022-05-23 13:45 ` [PATCH v2 2/3] fpga: region: Add fpga-region 'power-domains' property Nava kishore Manne 2022-06-24 16:28 ` Xu Yilun 2022-06-24 16:28 ` Xu Yilun 2022-07-18 6:46 ` Manne, Nava kishore 2022-07-18 6:46 ` Manne, Nava kishore 2022-07-21 6:54 ` Xu Yilun 2022-07-21 6:54 ` Xu Yilun 2022-08-16 10:22 ` Manne, Nava kishore 2022-08-16 10:22 ` Manne, Nava kishore 2022-08-18 2:58 ` Xu Yilun 2022-08-18 2:58 ` Xu Yilun 2022-07-21 7:38 ` Krzysztof Kozlowski 2022-07-21 7:38 ` Krzysztof Kozlowski 2022-05-23 13:45 ` [PATCH v2 3/3] fpga: region: Add runtime PM support Nava kishore Manne 2022-05-23 13:45 ` Nava kishore Manne 2022-06-20 5:38 ` Manne, Nava kishore 2022-06-20 5:38 ` Manne, Nava kishore 2022-06-20 7:34 ` Xu Yilun 2022-06-20 7:34 ` Xu Yilun
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