[PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3

[PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3

[Michal Simek]

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

This would prevent configuring non-secure regs in case gic security
extensions are not emulated in Qemu.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 arch/arm/lib/gic_64.S | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
index 155212a419be..86cd882fc759 100644
--- a/arch/arm/lib/gic_64.S
+++ b/arch/arm/lib/gic_64.S
@@ -40,6 +40,8 @@ ENTRY(gic_init_secure)
 	sub	w10, w10, #0x1
 	cbnz	w10, 0b
 #elif defined(CONFIG_GICV2)
+	switch_el x1, 2f, 1f, 1f
+2:
 	mov	w9, #0x3		/* EnableGrp0 | EnableGrp1 */
 	str	w9, [x0, GICD_CTLR]	/* Secure GICD_CTLR */
 	ldr	w9, [x0, GICD_TYPER]
@@ -141,6 +143,8 @@ ENTRY(gic_init_secure_percpu)
 	 * x0: Distributor Base
 	 * x1: Cpu Interface Base
 	 */
+	switch_el x2, 4f, 5f, 5f
+4:
 	mov	w9, #~0			/* Config SGIs and PPIs as Grp1 */
 	str	w9, [x0, GICD_IGROUPRn]	/* GICD_IGROUPR0 */
 	mov	w9, #0x1		/* Enable SGI 0 */
@@ -155,6 +159,7 @@ ENTRY(gic_init_secure_percpu)
 	mov	w9, #0x1 << 7		/* Non-Secure access to GICC_PMR */
 	str	w9, [x1, GICC_PMR]
 #endif
+5:
 	ret
 ENDPROC(gic_init_secure_percpu)
 
-- 
2.36.0

Re: [PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3

[Michal Simek]

Hi Tom,

st 11. 5. 2022 v 10:39 odesílatel Michal Simek <monstr@monstr.eu> napsal:
>
> From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
>
> This would prevent configuring non-secure regs in case gic security
> extensions are not emulated in Qemu.
>
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
>  arch/arm/lib/gic_64.S | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
> index 155212a419be..86cd882fc759 100644
> --- a/arch/arm/lib/gic_64.S
> +++ b/arch/arm/lib/gic_64.S
> @@ -40,6 +40,8 @@ ENTRY(gic_init_secure)
>         sub     w10, w10, #0x1
>         cbnz    w10, 0b
>  #elif defined(CONFIG_GICV2)
> +       switch_el x1, 2f, 1f, 1f
> +2:
>         mov     w9, #0x3                /* EnableGrp0 | EnableGrp1 */
>         str     w9, [x0, GICD_CTLR]     /* Secure GICD_CTLR */
>         ldr     w9, [x0, GICD_TYPER]
> @@ -141,6 +143,8 @@ ENTRY(gic_init_secure_percpu)
>          * x0: Distributor Base
>          * x1: Cpu Interface Base
>          */
> +       switch_el x2, 4f, 5f, 5f
> +4:
>         mov     w9, #~0                 /* Config SGIs and PPIs as Grp1 */
>         str     w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
>         mov     w9, #0x1                /* Enable SGI 0 */
> @@ -155,6 +159,7 @@ ENTRY(gic_init_secure_percpu)
>         mov     w9, #0x1 << 7           /* Non-Secure access to GICC_PMR */
>         str     w9, [x1, GICC_PMR]
>  #endif
> +5:
>         ret
>  ENDPROC(gic_init_secure_percpu)
>
> --
> 2.36.0
>

Can you please review this patch?

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

Re: [PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3

[Tom Rini]

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On Wed, May 18, 2022 at 01:22:24PM +0200, Michal Simek wrote:
> Hi Tom,
> 
> st 11. 5. 2022 v 10:39 odesílatel Michal Simek <monstr@monstr.eu> napsal:
> >
> > From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> >
> > This would prevent configuring non-secure regs in case gic security
> > extensions are not emulated in Qemu.
> >
> > Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> > Signed-off-by: Michal Simek <michal.simek@amd.com>
> > ---
> >
> >  arch/arm/lib/gic_64.S | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/arm/lib/gic_64.S b/arch/arm/lib/gic_64.S
> > index 155212a419be..86cd882fc759 100644
> > --- a/arch/arm/lib/gic_64.S
> > +++ b/arch/arm/lib/gic_64.S
> > @@ -40,6 +40,8 @@ ENTRY(gic_init_secure)
> >         sub     w10, w10, #0x1
> >         cbnz    w10, 0b
> >  #elif defined(CONFIG_GICV2)
> > +       switch_el x1, 2f, 1f, 1f
> > +2:
> >         mov     w9, #0x3                /* EnableGrp0 | EnableGrp1 */
> >         str     w9, [x0, GICD_CTLR]     /* Secure GICD_CTLR */
> >         ldr     w9, [x0, GICD_TYPER]
> > @@ -141,6 +143,8 @@ ENTRY(gic_init_secure_percpu)
> >          * x0: Distributor Base
> >          * x1: Cpu Interface Base
> >          */
> > +       switch_el x2, 4f, 5f, 5f
> > +4:
> >         mov     w9, #~0                 /* Config SGIs and PPIs as Grp1 */
> >         str     w9, [x0, GICD_IGROUPRn] /* GICD_IGROUPR0 */
> >         mov     w9, #0x1                /* Enable SGI 0 */
> > @@ -155,6 +159,7 @@ ENTRY(gic_init_secure_percpu)
> >         mov     w9, #0x1 << 7           /* Non-Secure access to GICC_PMR */
> >         str     w9, [x1, GICC_PMR]
> >  #endif
> > +5:
> >         ret
> >  ENDPROC(gic_init_secure_percpu)
> >
> > --
> > 2.36.0
> >
> 
> Can you please review this patch?

I've put this in my queue to make sure I don't miss it for -rc3.

-- 
Tom

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Re: [PATCH] arm: gic_v2: Skip gic_init_secure when cpu is not in el3

[Tom Rini]

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On Wed, May 11, 2022 at 10:39:07AM +0200, Michal Simek wrote:

> From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> 
> This would prevent configuring non-secure regs in case gic security
> extensions are not emulated in Qemu.
> 
> Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>

Applied to u-boot/master, thanks!

-- 
Tom

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