* [Intel-gfx] [PATCH v2] drm/i915/dg2: Support 4k@30 on HDMI
@ 2022-05-25 7:54 Ankit Nautiyal
2022-05-25 8:00 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dg2: Support 4k@30 on HDMI (rev2) Patchwork
0 siblings, 1 reply; 2+ messages in thread
From: Ankit Nautiyal @ 2022-05-25 7:54 UTC (permalink / raw)
To: intel-gfx
From: Vandita Kulkarni <vandita.kulkarni@intel.com>
This patch adds a fix to support 297MHz of dot clock by calculating
the pll values using synopsis algorithm.
This will help to support 4k@30 mode for HDMI monitors on DG2.
v2: As per the algorithm, set MPLLB VCO range control bits to 3,
in register SNPS_PHY_MPLLB_DIV for 297Mhz. (Matt)
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 0dd4775e8195..69fe32b8a662 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -517,6 +517,37 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = {
REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
};
+/* values in the below table are calculted using the algo */
+static const struct intel_mpllb_state dg2_hdmi_297 = {
+ .clock = 297000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
static const struct intel_mpllb_state dg2_hdmi_594 = {
.clock = 594000,
.ref_control =
@@ -551,6 +582,7 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
&dg2_hdmi_27_0,
&dg2_hdmi_74_25,
&dg2_hdmi_148_5,
+ &dg2_hdmi_297,
&dg2_hdmi_594,
NULL,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dg2: Support 4k@30 on HDMI (rev2)
2022-05-25 7:54 [Intel-gfx] [PATCH v2] drm/i915/dg2: Support 4k@30 on HDMI Ankit Nautiyal
@ 2022-05-25 8:00 ` Patchwork
0 siblings, 0 replies; 2+ messages in thread
From: Patchwork @ 2022-05-25 8:00 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dg2: Support 4k@30 on HDMI (rev2)
URL : https://patchwork.freedesktop.org/series/103862/
State : failure
== Summary ==
Error: make failed
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/display/intel_snps_phy.o
In file included from drivers/gpu/drm/i915/display/intel_ddi.h:9,
from drivers/gpu/drm/i915/display/intel_snps_phy.c:8:
./drivers/gpu/drm/i915/i915_reg_defs.h:71:2: error: initialized field overwritten [-Werror=override-init]
((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
^
drivers/gpu/drm/i915/display/intel_snps_phy.c:537:3: note: in expansion of macro ‘REG_FIELD_PREP’
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
^~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg_defs.h:71:2: note: (near initialization for ‘dg2_hdmi_297.mpllb_div2’)
((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
^
drivers/gpu/drm/i915/display/intel_snps_phy.c:537:3: note: in expansion of macro ‘REG_FIELD_PREP’
REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
^~~~~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target 'drivers/gpu/drm/i915/display/intel_snps_phy.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_snps_phy.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1834: recipe for target 'drivers' failed
make: *** [drivers] Error 2
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2022-05-25 8:00 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-25 7:54 [Intel-gfx] [PATCH v2] drm/i915/dg2: Support 4k@30 on HDMI Ankit Nautiyal
2022-05-25 8:00 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dg2: Support 4k@30 on HDMI (rev2) Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.