* [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
--
2.34.3
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 0/9] small BAR uapi bits
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
--
2.34.3
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
For now dump into i915_drm_local.h. Once the uapi on the kernel side is
merged, and is part of drm-next, we can sync the kernel headers and
remove this.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/i915_drm_local.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index 9a2273c4..ac35abf6 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -23,6 +23,27 @@ extern "C" {
#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
+/*
+ * Signal to the kernel that the object will need to be accessed via
+ * the CPU.
+ *
+ * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
+ * strictly required on platforms where only some of the device memory
+ * is directly visible or mappable through the CPU, like on DG2+.
+ *
+ * One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to
+ * ensure we can always spill the allocation to system memory, if we
+ * can't place the object in the mappable part of
+ * I915_MEMORY_CLASS_DEVICE.
+ *
+ * Without this hint, the kernel will assume that non-mappable
+ * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
+ * kernel can still migrate the object to the mappable part, as a last
+ * resort, if userspace ever CPU faults this object, but this might be
+ * expensive, and so ideally should be avoided.
+ */
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
+
#if defined(__cplusplus)
}
#endif
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
For now dump into i915_drm_local.h. Once the uapi on the kernel side is
merged, and is part of drm-next, we can sync the kernel headers and
remove this.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/i915_drm_local.h | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index 9a2273c4..ac35abf6 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -23,6 +23,27 @@ extern "C" {
#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
+/*
+ * Signal to the kernel that the object will need to be accessed via
+ * the CPU.
+ *
+ * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
+ * strictly required on platforms where only some of the device memory
+ * is directly visible or mappable through the CPU, like on DG2+.
+ *
+ * One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to
+ * ensure we can always spill the allocation to system memory, if we
+ * can't place the object in the mappable part of
+ * I915_MEMORY_CLASS_DEVICE.
+ *
+ * Without this hint, the kernel will assume that non-mappable
+ * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
+ * kernel can still migrate the object to the mappable part, as a last
+ * resort, if userspace ever CPU faults this object, but this might be
+ * expensive, and so ideally should be avoided.
+ */
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
+
#if defined(__cplusplus)
}
#endif
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
For now limit to direct callers.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/gem_create.c | 9 ++++++---
lib/i915/gem_create.h | 5 +++--
lib/i915/intel_memory_region.c | 2 +-
tests/i915/gem_create.c | 24 ++++++++++++------------
tests/i915/gem_pxp.c | 2 +-
5 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/lib/i915/gem_create.c b/lib/i915/gem_create.c
index 605c4513..1f9b7fcc 100644
--- a/lib/i915/gem_create.c
+++ b/lib/i915/gem_create.c
@@ -61,11 +61,12 @@ uint32_t gem_create(int fd, uint64_t size)
return handle;
}
-int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
+int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle,
struct i915_user_extension *ext)
{
struct drm_i915_gem_create_ext create = {
.size = *size,
+ .flags = flags,
.extensions = to_user_pointer(ext),
};
int err = 0;
@@ -86,6 +87,7 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
* gem_create_ext:
* @fd: open i915 drm file descriptor
* @size: desired size of the buffer
+ * @flags: optional flags
* @ext: optional extensions chain
*
* This wraps the GEM_CREATE_EXT ioctl, which allocates a new gem buffer object
@@ -93,11 +95,12 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
*
* Returns: The file-private handle of the created buffer object
*/
-uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext)
+uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags,
+ struct i915_user_extension *ext)
{
uint32_t handle;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle, ext), 0);
+ igt_assert_eq(__gem_create_ext(fd, &size, flags, &handle, ext), 0);
return handle;
}
diff --git a/lib/i915/gem_create.h b/lib/i915/gem_create.h
index c32a815d..47a9a16d 100644
--- a/lib/i915/gem_create.h
+++ b/lib/i915/gem_create.h
@@ -12,9 +12,10 @@
int __gem_create(int fd, uint64_t *size, uint32_t *handle);
uint32_t gem_create(int fd, uint64_t size);
-int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
+int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle,
struct i915_user_extension *ext);
-uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext);
+uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags,
+ struct i915_user_extension *ext);
void gem_pool_init(void);
void gem_pool_dump(void);
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index 6bf6aab1..f0589e98 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -208,7 +208,7 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
};
int ret;
- ret = __gem_create_ext(fd, size, handle, &ext_regions.base);
+ ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
/*
* Provide fallback for stable kernels if region passed in the array
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index 31fd6526..f8ae7804 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -330,38 +330,38 @@ static void create_ext_placement_sanity_check(int fd)
* behaviour.
*/
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle, 0), 0);
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle, 0), 0);
gem_close(fd, handle);
/* Try some uncreative invalid combinations */
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = regions->num_regions + 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = -1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_invalid);
setparam_region.num_regions = 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_invalid);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
uregions = calloc(regions->num_regions + 1, sizeof(uint32_t));
@@ -372,7 +372,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(uregions);
setparam_region.num_regions = regions->num_regions + 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
if (regions->num_regions > 1) {
@@ -385,7 +385,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(dups);
setparam_region.num_regions = 2;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
}
}
@@ -395,7 +395,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(uregions);
setparam_region.num_regions = regions->num_regions;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
free(uregions);
@@ -411,7 +411,7 @@ static void create_ext_placement_sanity_check(int fd)
to_user_pointer(&setparam_region_next);
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.base.next_extension = 0;
}
@@ -443,7 +443,7 @@ static void create_ext_placement_all(int fd)
setparam_region.num_regions = regions->num_regions;
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
gem_close(fd, handle);
free(uregions);
@@ -472,7 +472,7 @@ static void create_ext_placement_each(int fd)
setparam_region.num_regions = 1;
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
gem_close(fd, handle);
}
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 5f269bab..65618556 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -40,7 +40,7 @@ static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32
ext = &protected_ext.base;
*bo_out = 0;
- ret = __gem_create_ext(i915, &size64, bo_out, ext);
+ ret = __gem_create_ext(i915, &size64, 0, bo_out, ext);
return ret;
}
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
For now limit to direct callers.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/gem_create.c | 9 ++++++---
lib/i915/gem_create.h | 5 +++--
lib/i915/intel_memory_region.c | 2 +-
tests/i915/gem_create.c | 24 ++++++++++++------------
tests/i915/gem_pxp.c | 2 +-
5 files changed, 23 insertions(+), 19 deletions(-)
diff --git a/lib/i915/gem_create.c b/lib/i915/gem_create.c
index 605c4513..1f9b7fcc 100644
--- a/lib/i915/gem_create.c
+++ b/lib/i915/gem_create.c
@@ -61,11 +61,12 @@ uint32_t gem_create(int fd, uint64_t size)
return handle;
}
-int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
+int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle,
struct i915_user_extension *ext)
{
struct drm_i915_gem_create_ext create = {
.size = *size,
+ .flags = flags,
.extensions = to_user_pointer(ext),
};
int err = 0;
@@ -86,6 +87,7 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
* gem_create_ext:
* @fd: open i915 drm file descriptor
* @size: desired size of the buffer
+ * @flags: optional flags
* @ext: optional extensions chain
*
* This wraps the GEM_CREATE_EXT ioctl, which allocates a new gem buffer object
@@ -93,11 +95,12 @@ int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
*
* Returns: The file-private handle of the created buffer object
*/
-uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext)
+uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags,
+ struct i915_user_extension *ext)
{
uint32_t handle;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle, ext), 0);
+ igt_assert_eq(__gem_create_ext(fd, &size, flags, &handle, ext), 0);
return handle;
}
diff --git a/lib/i915/gem_create.h b/lib/i915/gem_create.h
index c32a815d..47a9a16d 100644
--- a/lib/i915/gem_create.h
+++ b/lib/i915/gem_create.h
@@ -12,9 +12,10 @@
int __gem_create(int fd, uint64_t *size, uint32_t *handle);
uint32_t gem_create(int fd, uint64_t size);
-int __gem_create_ext(int fd, uint64_t *size, uint32_t *handle,
+int __gem_create_ext(int fd, uint64_t *size, uint32_t flags, uint32_t *handle,
struct i915_user_extension *ext);
-uint32_t gem_create_ext(int fd, uint64_t size, struct i915_user_extension *ext);
+uint32_t gem_create_ext(int fd, uint64_t size, uint32_t flags,
+ struct i915_user_extension *ext);
void gem_pool_init(void);
void gem_pool_dump(void);
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index 6bf6aab1..f0589e98 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -208,7 +208,7 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
};
int ret;
- ret = __gem_create_ext(fd, size, handle, &ext_regions.base);
+ ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
/*
* Provide fallback for stable kernels if region passed in the array
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index 31fd6526..f8ae7804 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -330,38 +330,38 @@ static void create_ext_placement_sanity_check(int fd)
* behaviour.
*/
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle, 0), 0);
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle, 0), 0);
gem_close(fd, handle);
/* Try some uncreative invalid combinations */
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = regions->num_regions + 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = -1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_invalid);
setparam_region.num_regions = 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.regions = to_user_pointer(®ion_invalid);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
uregions = calloc(regions->num_regions + 1, sizeof(uint32_t));
@@ -372,7 +372,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(uregions);
setparam_region.num_regions = regions->num_regions + 1;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
if (regions->num_regions > 1) {
@@ -385,7 +385,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(dups);
setparam_region.num_regions = 2;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
}
}
@@ -395,7 +395,7 @@ static void create_ext_placement_sanity_check(int fd)
setparam_region.regions = to_user_pointer(uregions);
setparam_region.num_regions = regions->num_regions;
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
free(uregions);
@@ -411,7 +411,7 @@ static void create_ext_placement_sanity_check(int fd)
to_user_pointer(&setparam_region_next);
size = PAGE_SIZE;
- igt_assert_neq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_neq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
setparam_region.base.next_extension = 0;
}
@@ -443,7 +443,7 @@ static void create_ext_placement_all(int fd)
setparam_region.num_regions = regions->num_regions;
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
gem_close(fd, handle);
free(uregions);
@@ -472,7 +472,7 @@ static void create_ext_placement_each(int fd)
setparam_region.num_regions = 1;
size = PAGE_SIZE;
- igt_assert_eq(__gem_create_ext(fd, &size, &handle,
+ igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
&setparam_region.base), 0);
gem_close(fd, handle);
}
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 5f269bab..65618556 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -40,7 +40,7 @@ static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32
ext = &protected_ext.base;
*bo_out = 0;
- ret = __gem_create_ext(i915, &size64, bo_out, ext);
+ ret = __gem_create_ext(i915, &size64, 0, bo_out, ext);
return ret;
}
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Add some basic tests for this new flag.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/gem_create.c | 309 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 308 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index f8ae7804..5cfbd611 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -43,6 +43,8 @@
#include <getopt.h>
#include <pthread.h>
#include <stdatomic.h>
+#include <setjmp.h>
+#include <signal.h>
#include "drm.h"
#include "drmtest.h"
@@ -317,8 +319,8 @@ static void create_ext_placement_sanity_check(int fd)
.memory_class = -1,
.memory_instance = -1,
};
+ uint32_t handle, create_ext_supported_flags;
uint64_t size;
- uint32_t handle;
int i;
regions = gem_get_query_memory_regions(fd);
@@ -334,6 +336,11 @@ static void create_ext_placement_sanity_check(int fd)
gem_close(fd, handle);
/* Try some uncreative invalid combinations */
+ create_ext_supported_flags =
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS;
+ igt_assert_neq(__gem_create_ext(fd, &size, ~create_ext_supported_flags,
+ &handle, 0), 0);
+
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
@@ -480,6 +487,295 @@ static void create_ext_placement_each(int fd)
free(regions);
}
+static bool supports_needs_cpu_access(int fd)
+{
+ struct drm_i915_gem_memory_class_instance regions[] = {
+ { I915_MEMORY_CLASS_DEVICE, },
+ { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ .regions = to_user_pointer(®ions),
+ .num_regions = ARRAY_SIZE(regions),
+ };
+ uint64_t size = PAGE_SIZE;
+ uint32_t handle;
+ int ret;
+
+ ret = __gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base);
+ if (!ret) {
+ gem_close(fd, handle);
+ igt_assert(gem_has_lmem(fd)); /* Should be dgpu only */
+ }
+
+ return ret == 0;
+}
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static int upload(int fd, uint32_t handle)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 2,
+ };
+
+ /*
+ * To be reasonably sure that we are not being swindled, let's make
+ * sure to 'touch' the pages from the GPU first to ensure the object is
+ * for sure placed in one of requested regions.
+ */
+ exec[0].handle = handle;
+ exec[1].handle = batch_create_size(fd, PAGE_SIZE);
+
+ return __gem_execbuf(fd, &execbuf);
+}
+
+static int alloc_lmem(int fd, uint32_t *handle,
+ struct drm_i915_gem_memory_class_instance ci,
+ uint64_t size, bool cpu_access, bool do_upload)
+{
+ struct drm_i915_gem_memory_class_instance regions[] = {
+ ci, { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ .regions = to_user_pointer(®ions),
+ };
+ uint32_t flags;
+
+ igt_assert_eq(ci.memory_class, I915_MEMORY_CLASS_DEVICE);
+
+ flags = 0;
+ setparam_region.num_regions = 1;
+ if (cpu_access) {
+ flags = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ setparam_region.num_regions = 2;
+ }
+
+ *handle = gem_create_ext(fd, size, flags, &setparam_region.base);
+
+ if (do_upload)
+ return upload(fd, *handle);
+
+ return 0;
+}
+
+static void create_ext_cpu_access_sanity_check(int fd)
+{
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ };
+ struct drm_i915_query_memory_regions *regions;
+ uint64_t size = PAGE_SIZE;
+ uint32_t handle;
+ int i;
+
+ /*
+ * The ABI is that FLAG_NEEDS_CPU_ACCESS can only be applied to LMEM +
+ * SMEM objects. Make sure the kernel follows that, while also checking
+ * the basic CPU faulting behavour.
+ */
+
+ /* Implicit placement; should fail */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, NULL), -EINVAL);
+
+ regions = gem_get_query_memory_regions(fd);
+ igt_assert(regions);
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_gem_memory_class_instance ci_regions[2] = {
+ regions->regions[i].region,
+ { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ uint32_t *ptr;
+
+ setparam_region.regions = to_user_pointer(ci_regions);
+ setparam_region.num_regions = 1;
+
+ /* Single explicit placement; should fail */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base),
+ -EINVAL);
+
+ if (ci_regions[0].memory_class == I915_MEMORY_CLASS_SYSTEM)
+ continue;
+
+ /*
+ * Now combine with system memory; should pass. We should also
+ * be able to fault it.
+ */
+ setparam_region.num_regions = 2;
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base),
+ 0);
+ upload(fd, handle);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * It should also work just fine without the flag, where in the
+ * worst case we need to migrate it when faulting it.
+ */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ 0,
+ &handle, &setparam_region.base),
+ 0);
+ upload(fd, handle);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+ }
+
+ free(regions);
+}
+
+static jmp_buf jmp;
+
+__noreturn static void sigtrap(int sig)
+{
+ siglongjmp(jmp, sig);
+}
+
+static void trap_sigbus(uint32_t *ptr)
+{
+ sighandler_t old_sigbus;
+
+ old_sigbus = signal(SIGBUS, sigtrap);
+ switch (sigsetjmp(jmp, SIGBUS)) {
+ case SIGBUS:
+ break;
+ case 0:
+ *ptr = 0xdeadbeaf;
+ default:
+ igt_assert(!"reached");
+ break;
+ }
+ signal(SIGBUS, old_sigbus);
+}
+
+/**
+ * XXX: Remove this once we can safely sync the uapi header with the kernel.
+ * Should be source compatible either way though.
+ */
+#define probed_cpu_visible_size rsvd1[0]
+static void create_ext_cpu_access_big(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ int i;
+
+ /*
+ * Sanity check that we can still CPU map an overly large object, even
+ * if it happens to be larger the CPU visible portion of LMEM. Also
+ * check that an overly large allocation, which can't be spilled into
+ * system memory does indeed fail.
+ */
+
+ regions = gem_get_query_memory_regions(fd);
+ igt_assert(regions);
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info qmr = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance ci = qmr.region;
+ uint64_t size, visible_size, lmem_size;
+ uint32_t handle;
+ uint32_t *ptr;
+
+ if (ci.memory_class == I915_MEMORY_CLASS_SYSTEM)
+ continue;
+
+ lmem_size = qmr.probed_size;
+ visible_size = qmr.probed_cpu_visible_size;
+ igt_assert_neq(visible_size, 0);
+
+ if (visible_size <= (0.70 * lmem_size)) {
+ /*
+ * Too big. We should still be able to allocate it just
+ * fine, but faulting should result in tears.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ trap_sigbus(ptr);
+ gem_close(fd, handle);
+
+ /*
+ * Too big again, but this time we can spill to system
+ * memory when faulting the object.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * Let's also move the upload to after faulting the
+ * pages. The current behaviour is that the pages are
+ * only allocated in device memory when initially
+ * touched by the GPU. With this in mind we should also
+ * make sure that the pages are indeed migrated, as
+ * expected.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, false), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf; /* temp system memory */
+ igt_assert_eq(upload(fd, handle), 0);
+ trap_sigbus(ptr); /* non-mappable device memory */
+ gem_close(fd, handle);
+ }
+
+ /*
+ * Should fit. We likely need to migrate to the mappable portion
+ * on fault though, if this device has a small BAR, given how
+ * large the initial allocation is.
+ */
+ size = visible_size >> 1;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * And then with the CPU_ACCESS flag enabled; should also be no
+ * surprises here.
+ */
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+ }
+
+ free(regions);
+}
+
igt_main
{
int fd = -1;
@@ -531,4 +827,15 @@ igt_main
igt_subtest("create-ext-placement-all")
create_ext_placement_all(fd);
+ igt_describe("Verify the basic functionally and expected ABI contract around I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS");
+ igt_subtest("create-ext-cpu-access-sanity-check") {
+ igt_require(supports_needs_cpu_access(fd));
+ create_ext_cpu_access_sanity_check(fd);
+ }
+
+ igt_describe("Verify the extreme cases with very large objects and I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS");
+ igt_subtest("create-ext-cpu-access-big") {
+ igt_require(supports_needs_cpu_access(fd));
+ create_ext_cpu_access_big(fd);
+ }
}
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Add some basic tests for this new flag.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/gem_create.c | 309 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 308 insertions(+), 1 deletion(-)
diff --git a/tests/i915/gem_create.c b/tests/i915/gem_create.c
index f8ae7804..5cfbd611 100644
--- a/tests/i915/gem_create.c
+++ b/tests/i915/gem_create.c
@@ -43,6 +43,8 @@
#include <getopt.h>
#include <pthread.h>
#include <stdatomic.h>
+#include <setjmp.h>
+#include <signal.h>
#include "drm.h"
#include "drmtest.h"
@@ -317,8 +319,8 @@ static void create_ext_placement_sanity_check(int fd)
.memory_class = -1,
.memory_instance = -1,
};
+ uint32_t handle, create_ext_supported_flags;
uint64_t size;
- uint32_t handle;
int i;
regions = gem_get_query_memory_regions(fd);
@@ -334,6 +336,11 @@ static void create_ext_placement_sanity_check(int fd)
gem_close(fd, handle);
/* Try some uncreative invalid combinations */
+ create_ext_supported_flags =
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS;
+ igt_assert_neq(__gem_create_ext(fd, &size, ~create_ext_supported_flags,
+ &handle, 0), 0);
+
setparam_region.regions = to_user_pointer(®ion_smem);
setparam_region.num_regions = 0;
size = PAGE_SIZE;
@@ -480,6 +487,295 @@ static void create_ext_placement_each(int fd)
free(regions);
}
+static bool supports_needs_cpu_access(int fd)
+{
+ struct drm_i915_gem_memory_class_instance regions[] = {
+ { I915_MEMORY_CLASS_DEVICE, },
+ { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ .regions = to_user_pointer(®ions),
+ .num_regions = ARRAY_SIZE(regions),
+ };
+ uint64_t size = PAGE_SIZE;
+ uint32_t handle;
+ int ret;
+
+ ret = __gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base);
+ if (!ret) {
+ gem_close(fd, handle);
+ igt_assert(gem_has_lmem(fd)); /* Should be dgpu only */
+ }
+
+ return ret == 0;
+}
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static int upload(int fd, uint32_t handle)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 2,
+ };
+
+ /*
+ * To be reasonably sure that we are not being swindled, let's make
+ * sure to 'touch' the pages from the GPU first to ensure the object is
+ * for sure placed in one of requested regions.
+ */
+ exec[0].handle = handle;
+ exec[1].handle = batch_create_size(fd, PAGE_SIZE);
+
+ return __gem_execbuf(fd, &execbuf);
+}
+
+static int alloc_lmem(int fd, uint32_t *handle,
+ struct drm_i915_gem_memory_class_instance ci,
+ uint64_t size, bool cpu_access, bool do_upload)
+{
+ struct drm_i915_gem_memory_class_instance regions[] = {
+ ci, { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ .regions = to_user_pointer(®ions),
+ };
+ uint32_t flags;
+
+ igt_assert_eq(ci.memory_class, I915_MEMORY_CLASS_DEVICE);
+
+ flags = 0;
+ setparam_region.num_regions = 1;
+ if (cpu_access) {
+ flags = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ setparam_region.num_regions = 2;
+ }
+
+ *handle = gem_create_ext(fd, size, flags, &setparam_region.base);
+
+ if (do_upload)
+ return upload(fd, *handle);
+
+ return 0;
+}
+
+static void create_ext_cpu_access_sanity_check(int fd)
+{
+ struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+ .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+ };
+ struct drm_i915_query_memory_regions *regions;
+ uint64_t size = PAGE_SIZE;
+ uint32_t handle;
+ int i;
+
+ /*
+ * The ABI is that FLAG_NEEDS_CPU_ACCESS can only be applied to LMEM +
+ * SMEM objects. Make sure the kernel follows that, while also checking
+ * the basic CPU faulting behavour.
+ */
+
+ /* Implicit placement; should fail */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, NULL), -EINVAL);
+
+ regions = gem_get_query_memory_regions(fd);
+ igt_assert(regions);
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_gem_memory_class_instance ci_regions[2] = {
+ regions->regions[i].region,
+ { I915_MEMORY_CLASS_SYSTEM, },
+ };
+ uint32_t *ptr;
+
+ setparam_region.regions = to_user_pointer(ci_regions);
+ setparam_region.num_regions = 1;
+
+ /* Single explicit placement; should fail */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base),
+ -EINVAL);
+
+ if (ci_regions[0].memory_class == I915_MEMORY_CLASS_SYSTEM)
+ continue;
+
+ /*
+ * Now combine with system memory; should pass. We should also
+ * be able to fault it.
+ */
+ setparam_region.num_regions = 2;
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS,
+ &handle, &setparam_region.base),
+ 0);
+ upload(fd, handle);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * It should also work just fine without the flag, where in the
+ * worst case we need to migrate it when faulting it.
+ */
+ igt_assert_eq(__gem_create_ext(fd, &size,
+ 0,
+ &handle, &setparam_region.base),
+ 0);
+ upload(fd, handle);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+ }
+
+ free(regions);
+}
+
+static jmp_buf jmp;
+
+__noreturn static void sigtrap(int sig)
+{
+ siglongjmp(jmp, sig);
+}
+
+static void trap_sigbus(uint32_t *ptr)
+{
+ sighandler_t old_sigbus;
+
+ old_sigbus = signal(SIGBUS, sigtrap);
+ switch (sigsetjmp(jmp, SIGBUS)) {
+ case SIGBUS:
+ break;
+ case 0:
+ *ptr = 0xdeadbeaf;
+ default:
+ igt_assert(!"reached");
+ break;
+ }
+ signal(SIGBUS, old_sigbus);
+}
+
+/**
+ * XXX: Remove this once we can safely sync the uapi header with the kernel.
+ * Should be source compatible either way though.
+ */
+#define probed_cpu_visible_size rsvd1[0]
+static void create_ext_cpu_access_big(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ int i;
+
+ /*
+ * Sanity check that we can still CPU map an overly large object, even
+ * if it happens to be larger the CPU visible portion of LMEM. Also
+ * check that an overly large allocation, which can't be spilled into
+ * system memory does indeed fail.
+ */
+
+ regions = gem_get_query_memory_regions(fd);
+ igt_assert(regions);
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info qmr = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance ci = qmr.region;
+ uint64_t size, visible_size, lmem_size;
+ uint32_t handle;
+ uint32_t *ptr;
+
+ if (ci.memory_class == I915_MEMORY_CLASS_SYSTEM)
+ continue;
+
+ lmem_size = qmr.probed_size;
+ visible_size = qmr.probed_cpu_visible_size;
+ igt_assert_neq(visible_size, 0);
+
+ if (visible_size <= (0.70 * lmem_size)) {
+ /*
+ * Too big. We should still be able to allocate it just
+ * fine, but faulting should result in tears.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ trap_sigbus(ptr);
+ gem_close(fd, handle);
+
+ /*
+ * Too big again, but this time we can spill to system
+ * memory when faulting the object.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * Let's also move the upload to after faulting the
+ * pages. The current behaviour is that the pages are
+ * only allocated in device memory when initially
+ * touched by the GPU. With this in mind we should also
+ * make sure that the pages are indeed migrated, as
+ * expected.
+ */
+ size = visible_size;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, false), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf; /* temp system memory */
+ igt_assert_eq(upload(fd, handle), 0);
+ trap_sigbus(ptr); /* non-mappable device memory */
+ gem_close(fd, handle);
+ }
+
+ /*
+ * Should fit. We likely need to migrate to the mappable portion
+ * on fault though, if this device has a small BAR, given how
+ * large the initial allocation is.
+ */
+ size = visible_size >> 1;
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, false, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+
+ /*
+ * And then with the CPU_ACCESS flag enabled; should also be no
+ * surprises here.
+ */
+ igt_assert_eq(alloc_lmem(fd, &handle, ci, size, true, true), 0);
+ ptr = gem_mmap_offset__fixed(fd, handle, 0, size,
+ PROT_READ | PROT_WRITE);
+ ptr[0] = 0xdeadbeaf;
+ gem_close(fd, handle);
+ }
+
+ free(regions);
+}
+
igt_main
{
int fd = -1;
@@ -531,4 +827,15 @@ igt_main
igt_subtest("create-ext-placement-all")
create_ext_placement_all(fd);
+ igt_describe("Verify the basic functionally and expected ABI contract around I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS");
+ igt_subtest("create-ext-cpu-access-sanity-check") {
+ igt_require(supports_needs_cpu_access(fd));
+ create_ext_cpu_access_sanity_check(fd);
+ }
+
+ igt_describe("Verify the extreme cases with very large objects and I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS");
+ igt_subtest("create-ext-cpu-access-big") {
+ igt_require(supports_needs_cpu_access(fd));
+ create_ext_cpu_access_big(fd);
+ }
}
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Most users shouldn't care about such an interface, but where required,
this should be useful to aid in setting NEEDS_CPU_ACCESS for a given BO.
Underneath we try to smooth over needing to provide an explicit SMEM
region, or if this is SMEM-only, we don't want the kernel to throw an
error.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/intel_memory_region.c | 10 +++++---
lib/i915/intel_memory_region.h | 46 +++++++++++++++++++++++++++++++---
tests/i915/gem_eio.c | 1 +
tests/i915/gem_lmem_swapping.c | 2 +-
tests/i915/i915_pm_rpm.c | 6 ++---
5 files changed, 53 insertions(+), 12 deletions(-)
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index f0589e98..da81650d 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -197,7 +197,7 @@ bool gem_has_lmem(int fd)
/* A version of gem_create_in_memory_region_list which can be allowed to
fail so that the object creation can be retried */
-int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
+int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions)
{
@@ -208,7 +208,9 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
};
int ret;
- ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
+ ret = __gem_create_ext(fd, size, flags, handle, &ext_regions.base);
+ if (flags && ret == -EINVAL)
+ ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
/*
* Provide fallback for stable kernels if region passed in the array
@@ -231,12 +233,12 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
* @mem_regions: memory regions array (priority list)
* @num_regions: @mem_regions length
*/
-uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions)
{
uint32_t handle;
- int ret = __gem_create_in_memory_region_list(fd, &handle, &size,
+ int ret = __gem_create_in_memory_region_list(fd, &handle, &size, flags,
mem_regions, num_regions);
igt_assert_eq(ret, 0);
return handle;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index f9af9401..5aa163dd 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
#include "igt_collection.h"
+#include "i915_drm_local.h"
#ifndef INTEL_MEMORY_REGION_H
#define INTEL_MEMORY_REGION_H
@@ -64,11 +65,11 @@ bool gem_has_lmem(int fd);
struct drm_i915_gem_memory_class_instance;
-int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
+int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions);
-uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions);
@@ -84,7 +85,7 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
} \
- __gem_create_in_memory_region_list(fd, handle, size, arr_query__, ARRAY_SIZE(arr_query__)); \
+ __gem_create_in_memory_region_list(fd, handle, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \
})
#define gem_create_in_memory_regions(fd, size, regions...) ({ \
unsigned int arr__[] = { regions }; \
@@ -93,7 +94,44 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
} \
- gem_create_in_memory_region_list(fd, size, arr_query__, ARRAY_SIZE(arr_query__)); \
+ gem_create_in_memory_region_list(fd, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \
+})
+
+/*
+ * Create an object that requires CPU access. This only becomes interesting on
+ * platforms that have a small BAR for LMEM CPU access. Without this the object
+ * might need to be migrated when CPU faulting the object, or if that is not
+ * possible we hit SIGBUS. Most users should be fine with this. If enabled the
+ * kernel will never allocate this object in the non-CPU visible portion of
+ * LMEM.
+ *
+ * Underneath this just enables the I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS
+ * flag, if we also have an LMEM placement. Also since the kernel requires SMEM
+ * as a potential placement, we automatically attach that as a possible
+ * placement, if not already provided. If this happens to be an SMEM-only
+ * placement then we don't supply the flag, and instead just treat as normal
+ * allocation.
+ */
+#define gem_create_with_cpu_access_in_memory_regions(fd, size, regions...) ({ \
+ unsigned int arr__[] = { regions }; \
+ struct drm_i915_gem_memory_class_instance arr_query__[ARRAY_SIZE(arr__) + 1]; \
+ int i__, arr_query_size__ = ARRAY_SIZE(arr__); \
+ uint32_t ext_flags__ = 0; \
+ bool ext_found_smem__ = false; \
+ for (i__ = 0; i__ < arr_query_size__; ++i__) { \
+ arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
+ if (arr_query__[i__].memory_class == I915_MEMORY_CLASS_DEVICE) \
+ ext_flags__ = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS; \
+ else \
+ ext_found_smem__ = true; \
+ arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
+ } \
+ if (ext_flags__ && !ext_found_smem__) { \
+ arr_query__[i__].memory_class = I915_MEMORY_CLASS_SYSTEM; \
+ arr_query__[i__].memory_instance = 0; \
+ arr_query_size__++; \
+ } \
+ gem_create_in_memory_region_list(fd, size, ext_flags__, arr_query__, arr_query_size__); \
})
struct igt_collection *
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 913a21f9..a9641cca 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -146,6 +146,7 @@ static void test_create_ext(int fd)
igt_assert_eq(__gem_create_in_memory_region_list(fd,
&handle,
&size,
+ 0,
&r->ci, 1),
0);
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 5d93e9da..bb9e69db 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -131,7 +131,7 @@ static uint32_t create_bo(int i915,
int ret;
retry:
- ret = __gem_create_in_memory_region_list(i915, &handle, size, region, 1);
+ ret = __gem_create_in_memory_region_list(i915, &handle, size, 0, region, 1);
if (do_oom_test && ret == -ENOMEM)
goto retry;
igt_assert_eq(ret, 0);
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index bf145b6c..e95875dc 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1117,7 +1117,7 @@ static void gem_mmap_args(const struct mmap_offset *t,
/* Create, map and set data while the device is active. */
enable_one_screen_or_forcewake_get_and_wait(&ms_data);
- handle = gem_create_in_memory_region_list(drm_fd, buf_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, buf_size, 0, mem_regions, 1);
gem_buf = __gem_mmap_offset(drm_fd, handle, 0, buf_size,
PROT_READ | PROT_WRITE, t->type);
@@ -1348,7 +1348,7 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
/* Create and set data while the device is active. */
enable_one_screen_or_forcewake_get_and_wait(&ms_data);
- handle = gem_create_in_memory_region_list(drm_fd, dst_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, dst_size, 0, mem_regions, 1);
cpu_buf = malloc(dst_size);
igt_assert(cpu_buf);
@@ -1453,7 +1453,7 @@ gem_execbuf_stress_subtest(int rounds, int wait_flags,
if (wait_flags & WAIT_PC8_RES)
handle = gem_create(drm_fd, batch_size);
else
- handle = gem_create_in_memory_region_list(drm_fd, batch_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, batch_size, 0, mem_regions, 1);
gem_write(drm_fd, handle, 0, batch_buf, batch_size);
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Most users shouldn't care about such an interface, but where required,
this should be useful to aid in setting NEEDS_CPU_ACCESS for a given BO.
Underneath we try to smooth over needing to provide an explicit SMEM
region, or if this is SMEM-only, we don't want the kernel to throw an
error.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/intel_memory_region.c | 10 +++++---
lib/i915/intel_memory_region.h | 46 +++++++++++++++++++++++++++++++---
tests/i915/gem_eio.c | 1 +
tests/i915/gem_lmem_swapping.c | 2 +-
tests/i915/i915_pm_rpm.c | 6 ++---
5 files changed, 53 insertions(+), 12 deletions(-)
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index f0589e98..da81650d 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -197,7 +197,7 @@ bool gem_has_lmem(int fd)
/* A version of gem_create_in_memory_region_list which can be allowed to
fail so that the object creation can be retried */
-int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
+int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions)
{
@@ -208,7 +208,9 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
};
int ret;
- ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
+ ret = __gem_create_ext(fd, size, flags, handle, &ext_regions.base);
+ if (flags && ret == -EINVAL)
+ ret = __gem_create_ext(fd, size, 0, handle, &ext_regions.base);
/*
* Provide fallback for stable kernels if region passed in the array
@@ -231,12 +233,12 @@ int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
* @mem_regions: memory regions array (priority list)
* @num_regions: @mem_regions length
*/
-uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions)
{
uint32_t handle;
- int ret = __gem_create_in_memory_region_list(fd, &handle, &size,
+ int ret = __gem_create_in_memory_region_list(fd, &handle, &size, flags,
mem_regions, num_regions);
igt_assert_eq(ret, 0);
return handle;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index f9af9401..5aa163dd 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
#include "igt_collection.h"
+#include "i915_drm_local.h"
#ifndef INTEL_MEMORY_REGION_H
#define INTEL_MEMORY_REGION_H
@@ -64,11 +65,11 @@ bool gem_has_lmem(int fd);
struct drm_i915_gem_memory_class_instance;
-int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size,
+int __gem_create_in_memory_region_list(int fd, uint32_t *handle, uint64_t *size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions);
-uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
+uint32_t gem_create_in_memory_region_list(int fd, uint64_t size, uint32_t flags,
struct drm_i915_gem_memory_class_instance *mem_regions,
int num_regions);
@@ -84,7 +85,7 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
} \
- __gem_create_in_memory_region_list(fd, handle, size, arr_query__, ARRAY_SIZE(arr_query__)); \
+ __gem_create_in_memory_region_list(fd, handle, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \
})
#define gem_create_in_memory_regions(fd, size, regions...) ({ \
unsigned int arr__[] = { regions }; \
@@ -93,7 +94,44 @@ uint32_t gem_create_in_memory_region_list(int fd, uint64_t size,
arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
} \
- gem_create_in_memory_region_list(fd, size, arr_query__, ARRAY_SIZE(arr_query__)); \
+ gem_create_in_memory_region_list(fd, size, 0, arr_query__, ARRAY_SIZE(arr_query__)); \
+})
+
+/*
+ * Create an object that requires CPU access. This only becomes interesting on
+ * platforms that have a small BAR for LMEM CPU access. Without this the object
+ * might need to be migrated when CPU faulting the object, or if that is not
+ * possible we hit SIGBUS. Most users should be fine with this. If enabled the
+ * kernel will never allocate this object in the non-CPU visible portion of
+ * LMEM.
+ *
+ * Underneath this just enables the I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS
+ * flag, if we also have an LMEM placement. Also since the kernel requires SMEM
+ * as a potential placement, we automatically attach that as a possible
+ * placement, if not already provided. If this happens to be an SMEM-only
+ * placement then we don't supply the flag, and instead just treat as normal
+ * allocation.
+ */
+#define gem_create_with_cpu_access_in_memory_regions(fd, size, regions...) ({ \
+ unsigned int arr__[] = { regions }; \
+ struct drm_i915_gem_memory_class_instance arr_query__[ARRAY_SIZE(arr__) + 1]; \
+ int i__, arr_query_size__ = ARRAY_SIZE(arr__); \
+ uint32_t ext_flags__ = 0; \
+ bool ext_found_smem__ = false; \
+ for (i__ = 0; i__ < arr_query_size__; ++i__) { \
+ arr_query__[i__].memory_class = MEMORY_TYPE_FROM_REGION(arr__[i__]); \
+ if (arr_query__[i__].memory_class == I915_MEMORY_CLASS_DEVICE) \
+ ext_flags__ = I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS; \
+ else \
+ ext_found_smem__ = true; \
+ arr_query__[i__].memory_instance = MEMORY_INSTANCE_FROM_REGION(arr__[i__]); \
+ } \
+ if (ext_flags__ && !ext_found_smem__) { \
+ arr_query__[i__].memory_class = I915_MEMORY_CLASS_SYSTEM; \
+ arr_query__[i__].memory_instance = 0; \
+ arr_query_size__++; \
+ } \
+ gem_create_in_memory_region_list(fd, size, ext_flags__, arr_query__, arr_query_size__); \
})
struct igt_collection *
diff --git a/tests/i915/gem_eio.c b/tests/i915/gem_eio.c
index 913a21f9..a9641cca 100644
--- a/tests/i915/gem_eio.c
+++ b/tests/i915/gem_eio.c
@@ -146,6 +146,7 @@ static void test_create_ext(int fd)
igt_assert_eq(__gem_create_in_memory_region_list(fd,
&handle,
&size,
+ 0,
&r->ci, 1),
0);
diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index 5d93e9da..bb9e69db 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -131,7 +131,7 @@ static uint32_t create_bo(int i915,
int ret;
retry:
- ret = __gem_create_in_memory_region_list(i915, &handle, size, region, 1);
+ ret = __gem_create_in_memory_region_list(i915, &handle, size, 0, region, 1);
if (do_oom_test && ret == -ENOMEM)
goto retry;
igt_assert_eq(ret, 0);
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index bf145b6c..e95875dc 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1117,7 +1117,7 @@ static void gem_mmap_args(const struct mmap_offset *t,
/* Create, map and set data while the device is active. */
enable_one_screen_or_forcewake_get_and_wait(&ms_data);
- handle = gem_create_in_memory_region_list(drm_fd, buf_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, buf_size, 0, mem_regions, 1);
gem_buf = __gem_mmap_offset(drm_fd, handle, 0, buf_size,
PROT_READ | PROT_WRITE, t->type);
@@ -1348,7 +1348,7 @@ static void gem_execbuf_subtest(struct drm_i915_gem_memory_class_instance *mem_r
/* Create and set data while the device is active. */
enable_one_screen_or_forcewake_get_and_wait(&ms_data);
- handle = gem_create_in_memory_region_list(drm_fd, dst_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, dst_size, 0, mem_regions, 1);
cpu_buf = malloc(dst_size);
igt_assert(cpu_buf);
@@ -1453,7 +1453,7 @@ gem_execbuf_stress_subtest(int rounds, int wait_flags,
if (wait_flags & WAIT_PC8_RES)
handle = gem_create(drm_fd, batch_size);
else
- handle = gem_create_in_memory_region_list(drm_fd, batch_size, mem_regions, 1);
+ handle = gem_create_in_memory_region_list(drm_fd, batch_size, 0, mem_regions, 1);
gem_write(drm_fd, handle, 0, batch_buf, batch_size);
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Add some basic sanity checks for this, like checking if this falls
within the probed_size. On older kernels the value reported here should
be zero.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/i915_query.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 246a979a..6b036241 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -513,6 +513,11 @@ static bool query_regions_supported(int fd)
return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
}
+/**
+ * XXX: Remove these once we can safely sync the uapi header with the kernel.
+ * Should be source compatible either way though.
+ */
+#define probed_cpu_visible_size rsvd1[0]
static void test_query_regions_garbage_items(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -551,7 +556,10 @@ static void test_query_regions_garbage_items(int fd)
igt_assert_eq_u32(info.rsvd0, 0);
- for (j = 0; j < ARRAY_SIZE(info.rsvd1); j++)
+ /*
+ * rsvd1[0] : probed_cpu_visible_size
+ */
+ for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++)
igt_assert_eq_u32(info.rsvd1[j], 0);
}
@@ -586,13 +594,18 @@ static void test_query_regions_sanity_check(int fd)
found_system = false;
for (i = 0; i < regions->num_regions; i++) {
- struct drm_i915_gem_memory_class_instance r1 =
- regions->regions[i].region;
+ struct drm_i915_memory_region_info info = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance r1 = info.region;
int j;
if (r1.memory_class == I915_MEMORY_CLASS_SYSTEM) {
igt_assert_eq(r1.memory_instance, 0);
found_system = true;
+
+ igt_assert(info.probed_cpu_visible_size ==
+ info.probed_size);
+ } else {
+ igt_assert(info.probed_cpu_visible_size <= info.probed_size);
}
igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Add some basic sanity checks for this, like checking if this falls
within the probed_size. On older kernels the value reported here should
be zero.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/i915_query.c | 19 ++++++++++++++++---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 246a979a..6b036241 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -513,6 +513,11 @@ static bool query_regions_supported(int fd)
return __i915_query_items(fd, &item, 1) == 0 && item.length > 0;
}
+/**
+ * XXX: Remove these once we can safely sync the uapi header with the kernel.
+ * Should be source compatible either way though.
+ */
+#define probed_cpu_visible_size rsvd1[0]
static void test_query_regions_garbage_items(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -551,7 +556,10 @@ static void test_query_regions_garbage_items(int fd)
igt_assert_eq_u32(info.rsvd0, 0);
- for (j = 0; j < ARRAY_SIZE(info.rsvd1); j++)
+ /*
+ * rsvd1[0] : probed_cpu_visible_size
+ */
+ for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++)
igt_assert_eq_u32(info.rsvd1[j], 0);
}
@@ -586,13 +594,18 @@ static void test_query_regions_sanity_check(int fd)
found_system = false;
for (i = 0; i < regions->num_regions; i++) {
- struct drm_i915_gem_memory_class_instance r1 =
- regions->regions[i].region;
+ struct drm_i915_memory_region_info info = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance r1 = info.region;
int j;
if (r1.memory_class == I915_MEMORY_CLASS_SYSTEM) {
igt_assert_eq(r1.memory_instance, 0);
found_system = true;
+
+ igt_assert(info.probed_cpu_visible_size ==
+ info.probed_size);
+ } else {
+ igt_assert(info.probed_cpu_visible_size <= info.probed_size);
}
igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:36 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/i915_query.c | 273 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 272 insertions(+), 1 deletion(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 6b036241..77cbd93e 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,8 @@
*/
#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
#include <limits.h>
@@ -518,6 +520,36 @@ static bool query_regions_supported(int fd)
* Should be source compatible either way though.
*/
#define probed_cpu_visible_size rsvd1[0]
+#define unallocated_cpu_visible_size rsvd1[1]
+static bool query_regions_unallocated_supported(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_query_item item;
+ int i, ret = false;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ i915_query_items(fd, &item, 1);
+ igt_assert(item.length > 0);
+
+ regions = calloc(1, item.length);
+
+ item.data_ptr = to_user_pointer(regions);
+ i915_query_items(fd, &item, 1);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info info = regions->regions[i];
+
+ if (info.unallocated_cpu_visible_size) {
+ ret = true;
+ break;
+ }
+ }
+
+ free(regions);
+ return ret;
+}
+
static void test_query_regions_garbage_items(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -558,8 +590,9 @@ static void test_query_regions_garbage_items(int fd)
/*
* rsvd1[0] : probed_cpu_visible_size
+ * rsvd1[1] : unallocated_cpu_visible_size
*/
- for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++)
+ for (j = 2; j < ARRAY_SIZE(info.rsvd1); j++)
igt_assert_eq_u32(info.rsvd1[j], 0);
}
@@ -572,6 +605,46 @@ static void test_query_regions_garbage_items(int fd)
free(regions);
}
+struct object_handle {
+ uint32_t handle;
+ struct igt_list_head link;
+};
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static void upload(int fd, struct igt_list_head *handles, uint32_t num_handles)
+{
+ struct drm_i915_gem_exec_object2 *exec;
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct object_handle *iter;
+ uint32_t i;
+
+ exec = calloc(num_handles + 1,
+ sizeof(struct drm_i915_gem_exec_object2));
+
+ i = 0;
+ igt_list_for_each_entry(iter, handles, link)
+ exec[i++].handle = iter->handle;
+
+ exec[i].handle = batch_create_size(fd, 4096);
+
+ execbuf.buffers_ptr = to_user_pointer(exec);
+ execbuf.buffer_count = num_handles + 1;
+
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, exec[i].handle);
+ free(exec);
+}
+
static void test_query_regions_sanity_check(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -604,8 +677,19 @@ static void test_query_regions_sanity_check(int fd)
igt_assert(info.probed_cpu_visible_size ==
info.probed_size);
+ igt_assert(info.unallocated_size == info.probed_size);
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.unallocated_size);
} else {
igt_assert(info.probed_cpu_visible_size <= info.probed_size);
+ igt_assert(info.unallocated_size <= info.probed_size);
+ if (info.probed_cpu_visible_size < info.probed_size) {
+ igt_assert(info.unallocated_cpu_visible_size <
+ info.unallocated_size);
+ } else {
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.unallocated_size);
+ }
}
igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
@@ -622,6 +706,58 @@ static void test_query_regions_sanity_check(int fd)
igt_assert(!(r1.memory_class == r2.memory_class &&
r1.memory_instance == r2.memory_instance));
}
+
+ {
+ struct igt_list_head handles;
+ struct object_handle oh = {};
+
+ IGT_INIT_LIST_HEAD(&handles);
+
+ oh.handle =
+ gem_create_with_cpu_access_in_memory_regions
+ (fd, 4096,
+ INTEL_MEMORY_REGION_ID(r1.memory_class,
+ r1.memory_instance));
+ igt_list_add(&oh.link, &handles);
+ upload(fd, &handles, 1);
+
+ /*
+ * System wide metrics should be censored if we
+ * lack the correct permissions.
+ */
+ igt_fork(child, 1) {
+ igt_drop_root();
+
+ memset(regions, 0, item.length);
+ i915_query_items(fd, &item, 1);
+ info = regions->regions[i];
+
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size ==
+ info.probed_size);
+ }
+
+ igt_waitchildren();
+
+ memset(regions, 0, item.length);
+ i915_query_items(fd, &item, 1);
+ info = regions->regions[i];
+
+ if (r1.memory_class == I915_MEMORY_CLASS_DEVICE) {
+ igt_assert(info.unallocated_cpu_visible_size <
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size <
+ info.probed_size);
+ } else {
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size ==
+ info.probed_size);
+ }
+
+ gem_close(fd, oh.handle);
+ }
}
/* All devices should at least have system memory */
@@ -630,6 +766,134 @@ static void test_query_regions_sanity_check(int fd)
free(regions);
}
+#define rounddown(x, y) (x - (x % y))
+#define SZ_64K (1ULL << 16)
+
+static void fill_unallocated(int fd, struct drm_i915_query_item *item, int idx,
+ bool cpu_access)
+{
+ struct drm_i915_memory_region_info new_info, old_info;
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_gem_memory_class_instance ci;
+ struct object_handle *iter, *tmp;
+ struct igt_list_head handles;
+ uint32_t num_handles;
+ uint64_t rem, total;
+ int id;
+
+ srand(time(NULL));
+
+ IGT_INIT_LIST_HEAD(&handles);
+
+ regions = (struct drm_i915_query_memory_regions *)item->data_ptr;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+ ci = new_info.region;
+
+ id = INTEL_MEMORY_REGION_ID(ci.memory_class, ci.memory_instance);
+
+ if (cpu_access)
+ rem = new_info.unallocated_cpu_visible_size / 4;
+ else
+ rem = new_info.unallocated_size / 4;
+
+ rem = rounddown(rem, SZ_64K);
+ igt_assert_neq(rem, 0);
+ num_handles = 0;
+ total = 0;
+ do {
+ struct object_handle *oh;
+ uint64_t size;
+
+ size = rand() % rem;
+ size = rounddown(size, SZ_64K);
+ size = max_t(uint64_t, size, SZ_64K);
+
+ oh = malloc(sizeof(struct object_handle));
+ if (cpu_access)
+ oh->handle = gem_create_with_cpu_access_in_memory_regions(fd, size, id);
+ else
+ oh->handle = gem_create_in_memory_region_list(fd, size, 0, &ci, 1);
+ igt_list_add(&oh->link, &handles);
+
+ num_handles++;
+ total += size;
+ rem -= size;
+ } while (rem);
+
+ upload(fd, &handles, num_handles);
+
+ old_info = new_info;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+
+ igt_assert_lte(new_info.unallocated_size,
+ new_info.probed_size - total);
+ igt_assert_lt(new_info.unallocated_size, old_info.unallocated_size);
+ if (new_info.probed_cpu_visible_size ==
+ new_info.probed_size) { /* full BAR */
+ igt_assert_eq(new_info.unallocated_cpu_visible_size,
+ new_info.unallocated_size);
+ } else if (cpu_access) {
+ igt_assert_lt(new_info.unallocated_cpu_visible_size,
+ old_info.unallocated_cpu_visible_size);
+ igt_assert_lte(new_info.unallocated_cpu_visible_size,
+ new_info.probed_cpu_visible_size - total);
+ }
+
+ igt_debug("fill completed with idx=%d, total=%luKiB, num_handles=%u\n",
+ idx, total >> 10, num_handles);
+
+ igt_list_for_each_entry_safe(iter, tmp, &handles, link) {
+ gem_close(fd, iter->handle);
+ free(iter);
+ }
+
+ igt_drop_caches_set(fd, DROP_ALL);
+
+ old_info = new_info;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+
+ igt_assert(new_info.unallocated_size >=
+ old_info.unallocated_size + total);
+ if (cpu_access)
+ igt_assert(new_info.unallocated_cpu_visible_size >=
+ old_info.unallocated_cpu_visible_size + total);
+}
+
+static void test_query_regions_unallocated(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_query_item item;
+ int i;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ i915_query_items(fd, &item, 1);
+ igt_assert(item.length > 0);
+
+ regions = calloc(1, item.length);
+
+ item.data_ptr = to_user_pointer(regions);
+ i915_query_items(fd, &item, 1);
+
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info info = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance ci = info.region;
+
+ if (ci.memory_class == I915_MEMORY_CLASS_DEVICE) {
+ fill_unallocated(fd, &item, i, true);
+ fill_unallocated(fd, &item, i, false);
+ }
+ }
+}
+
static bool query_engine_info_supported(int fd)
{
struct drm_i915_query_item item = {
@@ -987,6 +1251,13 @@ igt_main
test_query_regions_sanity_check(fd);
}
+ igt_describe("Sanity check the region unallocated tracking");
+ igt_subtest("query-regions-unallocated") {
+ igt_require(query_regions_supported(fd));
+ igt_require(query_regions_unallocated_supported(fd));
+ test_query_regions_unallocated(fd);
+ }
+
igt_subtest_group {
igt_fixture {
igt_require(query_engine_info_supported(fd));
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking
@ 2022-05-25 18:36 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:36 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/i915_query.c | 273 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 272 insertions(+), 1 deletion(-)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 6b036241..77cbd93e 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,8 @@
*/
#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
#include <limits.h>
@@ -518,6 +520,36 @@ static bool query_regions_supported(int fd)
* Should be source compatible either way though.
*/
#define probed_cpu_visible_size rsvd1[0]
+#define unallocated_cpu_visible_size rsvd1[1]
+static bool query_regions_unallocated_supported(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_query_item item;
+ int i, ret = false;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ i915_query_items(fd, &item, 1);
+ igt_assert(item.length > 0);
+
+ regions = calloc(1, item.length);
+
+ item.data_ptr = to_user_pointer(regions);
+ i915_query_items(fd, &item, 1);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info info = regions->regions[i];
+
+ if (info.unallocated_cpu_visible_size) {
+ ret = true;
+ break;
+ }
+ }
+
+ free(regions);
+ return ret;
+}
+
static void test_query_regions_garbage_items(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -558,8 +590,9 @@ static void test_query_regions_garbage_items(int fd)
/*
* rsvd1[0] : probed_cpu_visible_size
+ * rsvd1[1] : unallocated_cpu_visible_size
*/
- for (j = 1; j < ARRAY_SIZE(info.rsvd1); j++)
+ for (j = 2; j < ARRAY_SIZE(info.rsvd1); j++)
igt_assert_eq_u32(info.rsvd1[j], 0);
}
@@ -572,6 +605,46 @@ static void test_query_regions_garbage_items(int fd)
free(regions);
}
+struct object_handle {
+ uint32_t handle;
+ struct igt_list_head link;
+};
+
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static void upload(int fd, struct igt_list_head *handles, uint32_t num_handles)
+{
+ struct drm_i915_gem_exec_object2 *exec;
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct object_handle *iter;
+ uint32_t i;
+
+ exec = calloc(num_handles + 1,
+ sizeof(struct drm_i915_gem_exec_object2));
+
+ i = 0;
+ igt_list_for_each_entry(iter, handles, link)
+ exec[i++].handle = iter->handle;
+
+ exec[i].handle = batch_create_size(fd, 4096);
+
+ execbuf.buffers_ptr = to_user_pointer(exec);
+ execbuf.buffer_count = num_handles + 1;
+
+ gem_execbuf(fd, &execbuf);
+ gem_close(fd, exec[i].handle);
+ free(exec);
+}
+
static void test_query_regions_sanity_check(int fd)
{
struct drm_i915_query_memory_regions *regions;
@@ -604,8 +677,19 @@ static void test_query_regions_sanity_check(int fd)
igt_assert(info.probed_cpu_visible_size ==
info.probed_size);
+ igt_assert(info.unallocated_size == info.probed_size);
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.unallocated_size);
} else {
igt_assert(info.probed_cpu_visible_size <= info.probed_size);
+ igt_assert(info.unallocated_size <= info.probed_size);
+ if (info.probed_cpu_visible_size < info.probed_size) {
+ igt_assert(info.unallocated_cpu_visible_size <
+ info.unallocated_size);
+ } else {
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.unallocated_size);
+ }
}
igt_assert(r1.memory_class == I915_MEMORY_CLASS_SYSTEM ||
@@ -622,6 +706,58 @@ static void test_query_regions_sanity_check(int fd)
igt_assert(!(r1.memory_class == r2.memory_class &&
r1.memory_instance == r2.memory_instance));
}
+
+ {
+ struct igt_list_head handles;
+ struct object_handle oh = {};
+
+ IGT_INIT_LIST_HEAD(&handles);
+
+ oh.handle =
+ gem_create_with_cpu_access_in_memory_regions
+ (fd, 4096,
+ INTEL_MEMORY_REGION_ID(r1.memory_class,
+ r1.memory_instance));
+ igt_list_add(&oh.link, &handles);
+ upload(fd, &handles, 1);
+
+ /*
+ * System wide metrics should be censored if we
+ * lack the correct permissions.
+ */
+ igt_fork(child, 1) {
+ igt_drop_root();
+
+ memset(regions, 0, item.length);
+ i915_query_items(fd, &item, 1);
+ info = regions->regions[i];
+
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size ==
+ info.probed_size);
+ }
+
+ igt_waitchildren();
+
+ memset(regions, 0, item.length);
+ i915_query_items(fd, &item, 1);
+ info = regions->regions[i];
+
+ if (r1.memory_class == I915_MEMORY_CLASS_DEVICE) {
+ igt_assert(info.unallocated_cpu_visible_size <
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size <
+ info.probed_size);
+ } else {
+ igt_assert(info.unallocated_cpu_visible_size ==
+ info.probed_cpu_visible_size);
+ igt_assert(info.unallocated_size ==
+ info.probed_size);
+ }
+
+ gem_close(fd, oh.handle);
+ }
}
/* All devices should at least have system memory */
@@ -630,6 +766,134 @@ static void test_query_regions_sanity_check(int fd)
free(regions);
}
+#define rounddown(x, y) (x - (x % y))
+#define SZ_64K (1ULL << 16)
+
+static void fill_unallocated(int fd, struct drm_i915_query_item *item, int idx,
+ bool cpu_access)
+{
+ struct drm_i915_memory_region_info new_info, old_info;
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_gem_memory_class_instance ci;
+ struct object_handle *iter, *tmp;
+ struct igt_list_head handles;
+ uint32_t num_handles;
+ uint64_t rem, total;
+ int id;
+
+ srand(time(NULL));
+
+ IGT_INIT_LIST_HEAD(&handles);
+
+ regions = (struct drm_i915_query_memory_regions *)item->data_ptr;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+ ci = new_info.region;
+
+ id = INTEL_MEMORY_REGION_ID(ci.memory_class, ci.memory_instance);
+
+ if (cpu_access)
+ rem = new_info.unallocated_cpu_visible_size / 4;
+ else
+ rem = new_info.unallocated_size / 4;
+
+ rem = rounddown(rem, SZ_64K);
+ igt_assert_neq(rem, 0);
+ num_handles = 0;
+ total = 0;
+ do {
+ struct object_handle *oh;
+ uint64_t size;
+
+ size = rand() % rem;
+ size = rounddown(size, SZ_64K);
+ size = max_t(uint64_t, size, SZ_64K);
+
+ oh = malloc(sizeof(struct object_handle));
+ if (cpu_access)
+ oh->handle = gem_create_with_cpu_access_in_memory_regions(fd, size, id);
+ else
+ oh->handle = gem_create_in_memory_region_list(fd, size, 0, &ci, 1);
+ igt_list_add(&oh->link, &handles);
+
+ num_handles++;
+ total += size;
+ rem -= size;
+ } while (rem);
+
+ upload(fd, &handles, num_handles);
+
+ old_info = new_info;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+
+ igt_assert_lte(new_info.unallocated_size,
+ new_info.probed_size - total);
+ igt_assert_lt(new_info.unallocated_size, old_info.unallocated_size);
+ if (new_info.probed_cpu_visible_size ==
+ new_info.probed_size) { /* full BAR */
+ igt_assert_eq(new_info.unallocated_cpu_visible_size,
+ new_info.unallocated_size);
+ } else if (cpu_access) {
+ igt_assert_lt(new_info.unallocated_cpu_visible_size,
+ old_info.unallocated_cpu_visible_size);
+ igt_assert_lte(new_info.unallocated_cpu_visible_size,
+ new_info.probed_cpu_visible_size - total);
+ }
+
+ igt_debug("fill completed with idx=%d, total=%luKiB, num_handles=%u\n",
+ idx, total >> 10, num_handles);
+
+ igt_list_for_each_entry_safe(iter, tmp, &handles, link) {
+ gem_close(fd, iter->handle);
+ free(iter);
+ }
+
+ igt_drop_caches_set(fd, DROP_ALL);
+
+ old_info = new_info;
+ memset(regions, 0, item->length);
+ i915_query_items(fd, item, 1);
+ new_info = regions->regions[idx];
+
+ igt_assert(new_info.unallocated_size >=
+ old_info.unallocated_size + total);
+ if (cpu_access)
+ igt_assert(new_info.unallocated_cpu_visible_size >=
+ old_info.unallocated_cpu_visible_size + total);
+}
+
+static void test_query_regions_unallocated(int fd)
+{
+ struct drm_i915_query_memory_regions *regions;
+ struct drm_i915_query_item item;
+ int i;
+
+ memset(&item, 0, sizeof(item));
+ item.query_id = DRM_I915_QUERY_MEMORY_REGIONS;
+ i915_query_items(fd, &item, 1);
+ igt_assert(item.length > 0);
+
+ regions = calloc(1, item.length);
+
+ item.data_ptr = to_user_pointer(regions);
+ i915_query_items(fd, &item, 1);
+
+ igt_assert(regions->num_regions);
+
+ for (i = 0; i < regions->num_regions; i++) {
+ struct drm_i915_memory_region_info info = regions->regions[i];
+ struct drm_i915_gem_memory_class_instance ci = info.region;
+
+ if (ci.memory_class == I915_MEMORY_CLASS_DEVICE) {
+ fill_unallocated(fd, &item, i, true);
+ fill_unallocated(fd, &item, i, false);
+ }
+ }
+}
+
static bool query_engine_info_supported(int fd)
{
struct drm_i915_query_item item = {
@@ -987,6 +1251,13 @@ igt_main
test_query_regions_sanity_check(fd);
}
+ igt_describe("Sanity check the region unallocated tracking");
+ igt_subtest("query-regions-unallocated") {
+ igt_require(query_regions_supported(fd));
+ igt_require(query_regions_unallocated_supported(fd));
+ test_query_regions_unallocated(fd);
+ }
+
igt_subtest_group {
igt_fixture {
igt_require(query_engine_info_supported(fd));
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:37 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Will be useful later.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/intel_memory_region.c | 2 ++
lib/i915/intel_memory_region.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index da81650d..2dd4c156 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -956,6 +956,8 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
r->ci = info->regions[i].region;
r->size = info->regions[i].probed_size;
+ /* XXX: replace with probed_cpu_visible_size */
+ r->cpu_size = info->regions[i].rsvd1[0];
if (r->size == -1ull)
r->size = intel_get_avail_ram_mb() << 20;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index 5aa163dd..8ee1ed9b 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -155,6 +155,7 @@ struct gem_memory_region {
struct drm_i915_gem_memory_class_instance ci;
uint64_t size;
+ uint64_t cpu_size;
};
struct igt_collection *
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size
@ 2022-05-25 18:37 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
Will be useful later.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/i915/intel_memory_region.c | 2 ++
lib/i915/intel_memory_region.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index da81650d..2dd4c156 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -956,6 +956,8 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
r->ci = info->regions[i].region;
r->size = info->regions[i].probed_size;
+ /* XXX: replace with probed_cpu_visible_size */
+ r->cpu_size = info->regions[i].rsvd1[0];
if (r->size == -1ull)
r->size = intel_get_avail_ram_mb() << 20;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index 5aa163dd..8ee1ed9b 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -155,6 +155,7 @@ struct gem_memory_region {
struct drm_i915_gem_memory_class_instance ci;
uint64_t size;
+ uint64_t cpu_size;
};
struct igt_collection *
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:37 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
We should mark the objects that need to be captured with
NEEDS_CPU_ACCESS to ensure we can capture them if they are allocated in
lmem. We also need to consider that capture only properly works on
non-recoverable context, for discrete platforms. We can now also expect
CPU invisible objects to be skipped, for now at least.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/gem_exec_capture.c | 143 ++++++++++++++++++++++++++++++++--
1 file changed, 135 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index 60f8df04..6ee6a155 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -268,13 +268,13 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
saved_engine = configure_hangs(fd, e, ctx->id);
memset(obj, 0, sizeof(obj));
- obj[SCRATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
+ obj[SCRATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region);
obj[SCRATCH].flags = EXEC_OBJECT_WRITE;
obj[CAPTURE].handle = target;
obj[CAPTURE].flags = EXEC_OBJECT_CAPTURE;
obj[NOCAPTURE].handle = gem_create(fd, 4096);
- obj[BATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
+ obj[BATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region);
obj[BATCH].relocs_ptr = (uintptr_t)reloc;
obj[BATCH].relocation_count = !ahnd ? ARRAY_SIZE(reloc) : 0;
@@ -387,9 +387,9 @@ static void capture(int fd, int dir, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e, uint32_t region)
{
uint32_t handle;
- uint64_t ahnd, obj_size = 4096;
+ uint64_t ahnd, obj_size = 16 * 4096;
- igt_assert_eq(__gem_create_in_memory_regions(fd, &handle, &obj_size, region), 0);
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, obj_size, region);
ahnd = get_reloc_ahnd(fd, ctx->id);
__capture1(fd, dir, ahnd, ctx, e, handle, obj_size, region);
@@ -415,7 +415,8 @@ static struct offset *
__captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
unsigned int size, int count,
- unsigned int flags, int *_fence_out)
+ unsigned int flags, int *_fence_out, uint32_t region,
+ bool force_cpu_access)
#define INCREMENTAL 0x1
#define ASYNC 0x2
{
@@ -441,7 +442,10 @@ __captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
obj[0].flags = EXEC_OBJECT_WRITE | (ahnd ? EXEC_OBJECT_PINNED : 0);
for (i = 0; i < count; i++) {
- obj[i + 1].handle = gem_create(fd, size);
+ if (force_cpu_access)
+ obj[i + 1].handle = gem_create_with_cpu_access_in_memory_regions(fd, size, region);
+ else
+ obj[i + 1].handle = gem_create_in_memory_regions(fd, size, region);
obj[i + 1].offset = get_offset(ahnd, obj[i + 1].handle, size, 0);
obj[i + 1].flags =
EXEC_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
@@ -595,6 +599,15 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
struct gem_engine_properties saved_engine;
find_first_available_engine(fd, ctx, e, saved_engine);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
gtt = gem_aperture_size(fd) / size;
ram = (intel_get_avail_ram_mb() << 20) / size;
@@ -607,7 +620,8 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
intel_require_memory(count, size, CHECK_RAM);
ahnd = get_reloc_ahnd(fd, ctx->id);
- offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL);
+ offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL,
+ REGION_SMEM, true);
blobs = check_error_state(dir, offsets, count, size, !!(flags & INCREMENTAL));
igt_info("Captured %lu %"PRId64"-blobs out of a total of %lu\n",
@@ -677,7 +691,8 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx,
/* Reopen the allocator in the new process. */
ahnd = get_reloc_ahnd(fd, ctx2->id);
- free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC, &fence_out));
+ free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC,
+ &fence_out, REGION_SMEM, true));
put_ahnd(ahnd);
write(link[1], &fd, sizeof(fd)); /* wake the parent up */
@@ -720,6 +735,15 @@ static void userptr(int fd, int dir)
struct gem_engine_properties saved_engine;
find_first_available_engine(fd, ctx, e, saved_engine);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
igt_assert(posix_memalign(&ptr, obj_size, obj_size) == 0);
memset(ptr, 0, obj_size);
@@ -735,6 +759,84 @@ static void userptr(int fd, int dir)
gem_engine_properties_restore(fd, &saved_engine);
}
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static void capture_recoverable_discrete(int fd)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 2,
+ };
+
+ /*
+ * I915_CONTEXT_PARAM_RECOVERABLE should be enabled by default. On
+ * discrete the kernel will only capture objects associated with the
+ * batch, if the context we is configured as non-recoverable.
+ */
+
+ exec[0].handle = gem_create(fd, 4096);
+ exec[0].flags = EXEC_OBJECT_CAPTURE;
+ exec[1].handle = batch_create_size(fd, 4096);
+
+ igt_assert_neq(__gem_execbuf(fd, &execbuf), 0);
+}
+
+static void capture_invisible(int fd, int dir, const intel_ctx_t *ctx,
+ struct gem_memory_region *mr)
+{
+ struct gem_engine_properties saved_engine;
+ const struct intel_execution_engine2 *e;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+ struct offset *offsets;
+ uint64_t ahnd;
+ char *error;
+
+ find_first_available_engine(fd, ctx, e, saved_engine);
+ gem_context_set_param(fd, ¶m);
+
+ ahnd = get_reloc_ahnd(fd, ctx->id);
+
+ igt_assert_eq(mr->ci.memory_class, I915_MEMORY_CLASS_DEVICE);
+
+ offsets = __captureN(fd, dir, ahnd, ctx, e, 1u << 16, 100, 0, NULL,
+ INTEL_MEMORY_REGION_ID(mr->ci.memory_class,
+ mr->ci.memory_instance),
+ false);
+
+ /*
+ * Make sure the error capture code doesn't crash-and-burn if it
+ * encounters an lmem object that can't be copied using the CPU. In such
+ * cases such objects will be skipped, otherwise we should see crashes
+ * here. Allocating a number of small objects should be enough to
+ * ensure that at least one or more end being allocated in the CPU
+ * invisible portion.
+ */
+
+ error = igt_sysfs_get(dir, "error");
+ igt_sysfs_set(dir, "error", "Begone!");
+ igt_assert(error);
+ igt_assert(errno != ENOMEM);
+
+ gem_engine_properties_restore(fd, &saved_engine);
+
+ free(offsets);
+ put_ahnd(ahnd);
+}
+
static bool has_capture(int fd)
{
drm_i915_getparam_t gp;
@@ -781,6 +883,15 @@ igt_main
gem_require_mmap_device_coherent(fd);
igt_require(has_capture(fd));
ctx = intel_ctx_create_all_physical(fd);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
igt_allow_hang(fd, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET);
dir = igt_sysfs_open(fd);
@@ -803,6 +914,22 @@ igt_main
}
}
+ igt_describe("Check that the kernel doesn't crash if the pages can't be copied from the CPU during error capture.");
+ igt_subtest_f("capture-invisible") {
+ igt_require(gem_has_lmem(fd));
+ for_each_memory_region(r, fd) {
+ igt_require(r->cpu_size && r->cpu_size < r->size);
+ igt_dynamic_f("%s", r->name)
+ capture_invisible(fd, dir, ctx, r);
+ }
+ }
+
+ igt_describe("Verify that the kernel rejects EXEC_OBJECT_CAPTURE with recoverable contexts.");
+ igt_subtest_f("capture-recoverable-discrete") {
+ igt_require(gem_has_lmem(fd));
+ capture_recoverable_discrete(fd);
+ }
+
igt_subtest_f("many-4K-zero") {
igt_require(gem_can_store_dword(fd, 0));
many(fd, dir, 1<<12, 0);
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes
@ 2022-05-25 18:37 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
We should mark the objects that need to be captured with
NEEDS_CPU_ACCESS to ensure we can capture them if they are allocated in
lmem. We also need to consider that capture only properly works on
non-recoverable context, for discrete platforms. We can now also expect
CPU invisible objects to be skipped, for now at least.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
tests/i915/gem_exec_capture.c | 143 ++++++++++++++++++++++++++++++++--
1 file changed, 135 insertions(+), 8 deletions(-)
diff --git a/tests/i915/gem_exec_capture.c b/tests/i915/gem_exec_capture.c
index 60f8df04..6ee6a155 100644
--- a/tests/i915/gem_exec_capture.c
+++ b/tests/i915/gem_exec_capture.c
@@ -268,13 +268,13 @@ static void __capture1(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
saved_engine = configure_hangs(fd, e, ctx->id);
memset(obj, 0, sizeof(obj));
- obj[SCRATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
+ obj[SCRATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region);
obj[SCRATCH].flags = EXEC_OBJECT_WRITE;
obj[CAPTURE].handle = target;
obj[CAPTURE].flags = EXEC_OBJECT_CAPTURE;
obj[NOCAPTURE].handle = gem_create(fd, 4096);
- obj[BATCH].handle = gem_create_in_memory_regions(fd, 4096, region);
+ obj[BATCH].handle = gem_create_with_cpu_access_in_memory_regions(fd, 4096, region);
obj[BATCH].relocs_ptr = (uintptr_t)reloc;
obj[BATCH].relocation_count = !ahnd ? ARRAY_SIZE(reloc) : 0;
@@ -387,9 +387,9 @@ static void capture(int fd, int dir, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e, uint32_t region)
{
uint32_t handle;
- uint64_t ahnd, obj_size = 4096;
+ uint64_t ahnd, obj_size = 16 * 4096;
- igt_assert_eq(__gem_create_in_memory_regions(fd, &handle, &obj_size, region), 0);
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, obj_size, region);
ahnd = get_reloc_ahnd(fd, ctx->id);
__capture1(fd, dir, ahnd, ctx, e, handle, obj_size, region);
@@ -415,7 +415,8 @@ static struct offset *
__captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
const struct intel_execution_engine2 *e,
unsigned int size, int count,
- unsigned int flags, int *_fence_out)
+ unsigned int flags, int *_fence_out, uint32_t region,
+ bool force_cpu_access)
#define INCREMENTAL 0x1
#define ASYNC 0x2
{
@@ -441,7 +442,10 @@ __captureN(int fd, int dir, uint64_t ahnd, const intel_ctx_t *ctx,
obj[0].flags = EXEC_OBJECT_WRITE | (ahnd ? EXEC_OBJECT_PINNED : 0);
for (i = 0; i < count; i++) {
- obj[i + 1].handle = gem_create(fd, size);
+ if (force_cpu_access)
+ obj[i + 1].handle = gem_create_with_cpu_access_in_memory_regions(fd, size, region);
+ else
+ obj[i + 1].handle = gem_create_in_memory_regions(fd, size, region);
obj[i + 1].offset = get_offset(ahnd, obj[i + 1].handle, size, 0);
obj[i + 1].flags =
EXEC_OBJECT_CAPTURE | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
@@ -595,6 +599,15 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
struct gem_engine_properties saved_engine;
find_first_available_engine(fd, ctx, e, saved_engine);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
gtt = gem_aperture_size(fd) / size;
ram = (intel_get_avail_ram_mb() << 20) / size;
@@ -607,7 +620,8 @@ static void many(int fd, int dir, uint64_t size, unsigned int flags)
intel_require_memory(count, size, CHECK_RAM);
ahnd = get_reloc_ahnd(fd, ctx->id);
- offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL);
+ offsets = __captureN(fd, dir, ahnd, ctx, e, size, count, flags, NULL,
+ REGION_SMEM, true);
blobs = check_error_state(dir, offsets, count, size, !!(flags & INCREMENTAL));
igt_info("Captured %lu %"PRId64"-blobs out of a total of %lu\n",
@@ -677,7 +691,8 @@ static void prioinv(int fd, int dir, const intel_ctx_t *ctx,
/* Reopen the allocator in the new process. */
ahnd = get_reloc_ahnd(fd, ctx2->id);
- free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC, &fence_out));
+ free(__captureN(fd, dir, ahnd, ctx2, e, size, count, ASYNC,
+ &fence_out, REGION_SMEM, true));
put_ahnd(ahnd);
write(link[1], &fd, sizeof(fd)); /* wake the parent up */
@@ -720,6 +735,15 @@ static void userptr(int fd, int dir)
struct gem_engine_properties saved_engine;
find_first_available_engine(fd, ctx, e, saved_engine);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
igt_assert(posix_memalign(&ptr, obj_size, obj_size) == 0);
memset(ptr, 0, obj_size);
@@ -735,6 +759,84 @@ static void userptr(int fd, int dir)
gem_engine_properties_restore(fd, &saved_engine);
}
+static uint32_t batch_create_size(int fd, uint64_t size)
+{
+ const uint32_t bbe = MI_BATCH_BUFFER_END;
+ uint32_t handle;
+
+ handle = gem_create(fd, size);
+ gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+ return handle;
+}
+
+static void capture_recoverable_discrete(int fd)
+{
+ struct drm_i915_gem_exec_object2 exec[2] = {};
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = to_user_pointer(&exec),
+ .buffer_count = 2,
+ };
+
+ /*
+ * I915_CONTEXT_PARAM_RECOVERABLE should be enabled by default. On
+ * discrete the kernel will only capture objects associated with the
+ * batch, if the context we is configured as non-recoverable.
+ */
+
+ exec[0].handle = gem_create(fd, 4096);
+ exec[0].flags = EXEC_OBJECT_CAPTURE;
+ exec[1].handle = batch_create_size(fd, 4096);
+
+ igt_assert_neq(__gem_execbuf(fd, &execbuf), 0);
+}
+
+static void capture_invisible(int fd, int dir, const intel_ctx_t *ctx,
+ struct gem_memory_region *mr)
+{
+ struct gem_engine_properties saved_engine;
+ const struct intel_execution_engine2 *e;
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+ struct offset *offsets;
+ uint64_t ahnd;
+ char *error;
+
+ find_first_available_engine(fd, ctx, e, saved_engine);
+ gem_context_set_param(fd, ¶m);
+
+ ahnd = get_reloc_ahnd(fd, ctx->id);
+
+ igt_assert_eq(mr->ci.memory_class, I915_MEMORY_CLASS_DEVICE);
+
+ offsets = __captureN(fd, dir, ahnd, ctx, e, 1u << 16, 100, 0, NULL,
+ INTEL_MEMORY_REGION_ID(mr->ci.memory_class,
+ mr->ci.memory_instance),
+ false);
+
+ /*
+ * Make sure the error capture code doesn't crash-and-burn if it
+ * encounters an lmem object that can't be copied using the CPU. In such
+ * cases such objects will be skipped, otherwise we should see crashes
+ * here. Allocating a number of small objects should be enough to
+ * ensure that at least one or more end being allocated in the CPU
+ * invisible portion.
+ */
+
+ error = igt_sysfs_get(dir, "error");
+ igt_sysfs_set(dir, "error", "Begone!");
+ igt_assert(error);
+ igt_assert(errno != ENOMEM);
+
+ gem_engine_properties_restore(fd, &saved_engine);
+
+ free(offsets);
+ put_ahnd(ahnd);
+}
+
static bool has_capture(int fd)
{
drm_i915_getparam_t gp;
@@ -781,6 +883,15 @@ igt_main
gem_require_mmap_device_coherent(fd);
igt_require(has_capture(fd));
ctx = intel_ctx_create_all_physical(fd);
+ if (gem_has_lmem(fd)) {
+ struct drm_i915_gem_context_param param = {
+ .ctx_id = ctx->id,
+ .param = I915_CONTEXT_PARAM_RECOVERABLE,
+ .value = 0,
+ };
+
+ gem_context_set_param(fd, ¶m);
+ }
igt_allow_hang(fd, ctx->id, HANG_ALLOW_CAPTURE | HANG_WANT_ENGINE_RESET);
dir = igt_sysfs_open(fd);
@@ -803,6 +914,22 @@ igt_main
}
}
+ igt_describe("Check that the kernel doesn't crash if the pages can't be copied from the CPU during error capture.");
+ igt_subtest_f("capture-invisible") {
+ igt_require(gem_has_lmem(fd));
+ for_each_memory_region(r, fd) {
+ igt_require(r->cpu_size && r->cpu_size < r->size);
+ igt_dynamic_f("%s", r->name)
+ capture_invisible(fd, dir, ctx, r);
+ }
+ }
+
+ igt_describe("Verify that the kernel rejects EXEC_OBJECT_CAPTURE with recoverable contexts.");
+ igt_subtest_f("capture-recoverable-discrete") {
+ igt_require(gem_has_lmem(fd));
+ capture_recoverable_discrete(fd);
+ }
+
igt_subtest_f("many-4K-zero") {
igt_require(gem_can_store_dword(fd, 0));
many(fd, dir, 1<<12, 0);
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
@ 2022-05-25 18:37 ` Matthew Auld
-1 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
from non-mappable device memory, to the mappable part, due to being
temporarily pinned for scanout, when hitting the CPU fault handler,
which just gives us SIGBUS. If the device has a small BAR let's attempt
to use the mappable portion, if possible.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/ioctl_wrappers.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 09eb3ce7..7713e78b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
uint32_t handle;
if (gem_has_lmem(fd))
- handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
+ REGION_LMEM(0));
else
handle = gem_create(fd, size);
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
@ 2022-05-25 18:37 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-05-25 18:37 UTC (permalink / raw)
To: igt-dev; +Cc: Thomas Hellström, intel-gfx
kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
from non-mappable device memory, to the mappable part, due to being
temporarily pinned for scanout, when hitting the CPU fault handler,
which just gives us SIGBUS. If the device has a small BAR let's attempt
to use the mappable portion, if possible.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
lib/ioctl_wrappers.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 09eb3ce7..7713e78b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
uint32_t handle;
if (gem_has_lmem(fd))
- handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
+ REGION_LMEM(0));
else
handle = gem_create(fd, size);
--
2.34.3
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for small BAR uapi bits
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
` (9 preceding siblings ...)
(?)
@ 2022-05-25 18:46 ` Patchwork
-1 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-05-25 18:46 UTC (permalink / raw)
To: Matthew Auld; +Cc: igt-dev
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104368/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/595891 for the overview.
build:tests-debian-meson-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/23136846):
^
In file included from ../lib/drmtest.h:39,
from ../lib/igt.h:27,
from ../tests/i915/i915_query.c:24:
../tests/i915/i915_query.c:846:12: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 5 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
igt_debug("fill completed with idx=%d, total=%luKiB, num_handles=%u\n",
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
idx, total >> 10, num_handles);
~~~~~~~~~~~
../lib/igt_core.h:1209:64: note: in definition of macro ‘igt_debug’
#define igt_debug(f...) igt_log(IGT_LOG_DOMAIN, IGT_LOG_DEBUG, f)
^
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
section_end:1653504240:step_script
section_start:1653504240:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1653504241:cleanup_file_variables
ERROR: Job failed: exit code 1
build:tests-debian-meson-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/23136848):
^
In file included from ../lib/drmtest.h:39,
from ../lib/igt.h:27,
from ../tests/i915/i915_query.c:24:
../tests/i915/i915_query.c:846:12: warning: format ‘%lu’ expects argument of type ‘long unsigned int’, but argument 5 has type ‘uint64_t’ {aka ‘long long unsigned int’} [-Wformat=]
igt_debug("fill completed with idx=%d, total=%luKiB, num_handles=%u\n",
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
idx, total >> 10, num_handles);
~~~~~~~~~~~
../lib/igt_core.h:1209:64: note: in definition of macro ‘igt_debug’
#define igt_debug(f...) igt_log(IGT_LOG_DOMAIN, IGT_LOG_DEBUG, f)
^
cc1: some warnings being treated as errors
ninja: build stopped: subcommand failed.
section_end:1653504228:step_script
section_start:1653504228:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1653504229:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/595891
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for small BAR uapi bits
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
` (10 preceding siblings ...)
(?)
@ 2022-05-25 20:09 ` Patchwork
-1 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-05-25 20:09 UTC (permalink / raw)
To: Matthew Auld; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 7998 bytes --]
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104368/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11700 -> IGTPW_7174
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
Participating hosts (46 -> 45)
------------------------------
Missing (1): bat-dg2-8
Known issues
------------
Here are the changes found in IGTPW_7174 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][1] -> [INCOMPLETE][2] ([i915#4785])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic@modeset:
- bat-adlp-4: [PASS][3] -> [DMESG-WARN][4] ([i915#3576])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-4/igt@kms_busy@basic@modeset.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-adlp-4/igt@kms_busy@basic@modeset.html
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#402])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/fi-tgl-u2/igt@kms_flip@basic-flip-vs-dpms@a-edp1.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-dg2-9}: [SKIP][7] ([i915#2582]) -> [PASS][8] +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@fbdev@read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-dg2-9/igt@fbdev@read.html
* igt@i915_getparams_basic@basic-eu-total:
- {bat-dg2-9}: [SKIP][9] ([i915#2575]) -> [PASS][10] +34 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@i915_getparams_basic@basic-eu-total.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-dg2-9/igt@i915_getparams_basic@basic-eu-total.html
* igt@i915_pm_rpm@basic-rte:
- {bat-dg2-9}: [SKIP][11] ([i915#5174]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@i915_pm_rpm@basic-rte.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-dg2-9/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_timelines:
- {bat-dg2-9}: [FAIL][13] ([i915#5703]) -> [PASS][14] +9 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-dg2-9/igt@i915_selftest@live@gt_timelines.html
* igt@i915_selftest@live@hugepages:
- {bat-adln-1}: [DMESG-WARN][15] -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adln-1/igt@i915_selftest@live@hugepages.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-adln-1/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@requests:
- bat-adlp-4: [DMESG-FAIL][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-4/igt@i915_selftest@live@requests.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-adlp-4/igt@i915_selftest@live@requests.html
* igt@kms_addfb_basic@addfb25-yf-tiled-legacy:
- {bat-dg2-9}: [SKIP][19] ([i915#5171] / [i915#5190]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-dg2-9/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html
* igt@kms_addfb_basic@bo-too-small:
- {bat-dg2-9}: [SKIP][21] ([i915#5171]) -> [PASS][22] +46 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@kms_addfb_basic@bo-too-small.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-dg2-9/igt@kms_addfb_basic@bo-too-small.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][23] ([i915#3576]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-6/igt@kms_busy@basic@flip.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/bat-adlp-6/igt@kms_busy@basic@flip.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2: [DMESG-WARN][25] ([i915#402]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5181]: https://gitlab.freedesktop.org/drm/intel/issues/5181
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5606]: https://gitlab.freedesktop.org/drm/intel/issues/5606
[i915#5703]: https://gitlab.freedesktop.org/drm/intel/issues/5703
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6492 -> IGTPW_7174
CI-20190529: 20190529
CI_DRM_11700: f5895776c32b7fc5c196fafef3f5dab7e5ad19c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7174: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
IGT_6492: ef18e59c374472e961a3a145724e7381eb4800aa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@gem_create@create-ext-cpu-access-big
+igt@gem_create@create-ext-cpu-access-sanity-check
+igt@gem_exec_capture@capture-invisible
+igt@gem_exec_capture@capture-recoverable-discrete
+igt@i915_query@query-regions-unallocated
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
[-- Attachment #2: Type: text/html, Size: 7654 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for small BAR uapi bits
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
` (11 preceding siblings ...)
(?)
@ 2022-05-26 10:43 ` Patchwork
-1 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2022-05-26 10:43 UTC (permalink / raw)
To: Matthew Auld; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 64118 bytes --]
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104368/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11700_full -> IGTPW_7174_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_7174_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_7174_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
Participating hosts (10 -> 10)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7174_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_create@create-ext-cpu-access-sanity-check} (NEW):
- {shard-dg1}: NOTRUN -> [SKIP][1] +6 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-dg1-16/igt@gem_create@create-ext-cpu-access-sanity-check.html
* {igt@gem_exec_capture@capture-invisible} (NEW):
- shard-tglb: NOTRUN -> [SKIP][2] +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb7/igt@gem_exec_capture@capture-invisible.html
- {shard-rkl}: NOTRUN -> [SKIP][3] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-rkl-6/igt@gem_exec_capture@capture-invisible.html
* {igt@gem_exec_capture@capture-recoverable-discrete} (NEW):
- shard-iclb: NOTRUN -> [SKIP][4] +4 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@gem_exec_capture@capture-recoverable-discrete.html
* igt@i915_query@query-regions-sanity-check:
- shard-snb: [PASS][5] -> [FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-snb6/igt@i915_query@query-regions-sanity-check.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-snb7/igt@i915_query@query-regions-sanity-check.html
- shard-glk: [PASS][7] -> [FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk3/igt@i915_query@query-regions-sanity-check.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk3/igt@i915_query@query-regions-sanity-check.html
- shard-apl: [PASS][9] -> [FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl8/igt@i915_query@query-regions-sanity-check.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@i915_query@query-regions-sanity-check.html
- shard-tglb: [PASS][11] -> [FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb2/igt@i915_query@query-regions-sanity-check.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb1/igt@i915_query@query-regions-sanity-check.html
- shard-iclb: [PASS][13] -> [FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@i915_query@query-regions-sanity-check.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb8/igt@i915_query@query-regions-sanity-check.html
* {igt@i915_query@query-regions-unallocated} (NEW):
- {shard-tglu}: NOTRUN -> [SKIP][15] +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglu-8/igt@i915_query@query-regions-unallocated.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding:
- {shard-dg1}: NOTRUN -> [DMESG-WARN][16]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-dg1-17/igt@kms_cursor_crc@pipe-b-cursor-128x42-sliding.html
* {igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1}:
- {shard-tglu}: NOTRUN -> [SKIP][17] +11 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglu-8/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1.html
* {igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1}:
- shard-tglb: NOTRUN -> [SKIP][18] +7 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb8/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1.html
* {igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20}:
- {shard-rkl}: NOTRUN -> [SKIP][19] +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-with-pixel-format-20x20.html
New tests
---------
New tests have been introduced between CI_DRM_11700_full and IGTPW_7174_full:
### New IGT tests (13) ###
* igt@gem_create@create-ext-cpu-access-big:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_create@create-ext-cpu-access-sanity-check:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture-invisible:
- Statuses : 9 skip(s)
- Exec time: [0.0] s
* igt@gem_exec_capture@capture-recoverable-discrete:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
* igt@i915_query@query-regions-unallocated:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.04] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-c-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.41] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.41] s
Known issues
------------
Here are the changes found in IGTPW_7174_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#111827])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@feature_discovery@chamelium.html
* igt@gem_ccs@block-copy-inplace:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#3555] / [i915#5325])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@gem_ccs@block-copy-inplace.html
* {igt@gem_create@create-ext-cpu-access-big} (NEW):
- shard-snb: NOTRUN -> [SKIP][22] ([fdo#109271]) +80 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-snb2/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_create@create-massive:
- shard-iclb: NOTRUN -> [DMESG-WARN][23] ([i915#4991])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@gem_create@create-massive.html
- shard-kbl: NOTRUN -> [DMESG-WARN][24] ([i915#4991])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@gem_create@create-massive.html
- shard-tglb: NOTRUN -> [DMESG-WARN][25] ([i915#4991])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@gem_create@create-massive.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109314])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@gem_ctx_param@set-priority-not-supported.html
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#109314])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb1/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#280])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@gem_ctx_sseu@engines.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#2846])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk6/igt@gem_exec_fair@basic-deadline.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][31] -> [FAIL][32] ([i915#2842]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-tglb: NOTRUN -> [FAIL][33] ([i915#2842])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][34] -> [FAIL][35] ([i915#2842])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][36] ([i915#2842]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-snb: [PASS][37] -> [SKIP][38] ([fdo#109271])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-snb2/igt@gem_exec_flush@basic-wb-rw-before-default.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-snb6/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#112283])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@gem_exec_params@secure-non-root.html
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#112283])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb2/igt@gem_exec_params@secure-non-root.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-tglb: NOTRUN -> [SKIP][41] ([i915#4613]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb8/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#4613])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk2/igt@gem_lmem_swapping@parallel-random.html
- shard-iclb: NOTRUN -> [SKIP][43] ([i915#4613]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@gem_lmem_swapping@parallel-random.html
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#4613]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@random:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#4613]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl1/igt@gem_lmem_swapping@random.html
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#111656])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@gem_mmap_gtt@coherency.html
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-iclb: NOTRUN -> [SKIP][47] ([i915#4270]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#4270]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][49] ([i915#768]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb1/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_userptr_blits@unsync-overlap:
- shard-iclb: NOTRUN -> [SKIP][50] ([i915#3297]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@gem_userptr_blits@unsync-overlap.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3297]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen7_exec_parse@basic-offset:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109289]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb8/igt@gen7_exec_parse@basic-offset.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][53] -> [DMESG-WARN][54] ([i915#5566] / [i915#716])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl2/igt@gen9_exec_parse@allowed-single.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl7/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@secure-batches:
- shard-iclb: NOTRUN -> [SKIP][55] ([i915#2856]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb3/igt@gen9_exec_parse@secure-batches.html
* igt@gen9_exec_parse@shadow-peek:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#2527] / [i915#2856]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][57] ([i915#2681])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@i915_pm_rc6_residency@rc6-fence.html
- shard-iclb: NOTRUN -> [WARN][58] ([i915#2684])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: NOTRUN -> [SKIP][59] ([fdo#111644] / [i915#1397] / [i915#2411])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#110892])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][61] -> [DMESG-WARN][62] ([i915#180]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl8/igt@i915_suspend@sysfs-reader.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#1769])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#5286]) +4 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#5286]) +4 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#110725] / [fdo#111614]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#111614]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#111615]) +6 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#110723]) +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@invalid-modeset:
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#2705])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@kms_big_joiner@invalid-modeset.html
- shard-tglb: NOTRUN -> [SKIP][71] ([i915#2705])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb8/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +11 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886]) +4 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][74] ([i915#3689] / [i915#3886]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk1/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#6095]) +2 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb8/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html
- shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109278] / [i915#6095]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#111615] / [i915#3689]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109278] / [i915#3886]) +8 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#3689]) +11 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#3742])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@kms_cdclk@mode-transition.html
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3742])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@common-hpd-after-suspend:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827]) +5 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl2/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109284] / [fdo#111827]) +7 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb3/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@hdmi-hpd-fast:
- shard-snb: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-snb6/igt@kms_chamelium@hdmi-hpd-fast.html
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk1/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271] / [fdo#111827]) +18 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl3/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_color@pipe-d-gamma:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109278] / [i915#1149]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@kms_color@pipe-d-gamma.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][89] ([fdo#109284] / [fdo#111827]) +11 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb7/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#3116] / [i915#3299])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#3319]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109278] / [fdo#109279]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#3359]) +4 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109279] / [i915#3359]) +5 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278]) +35 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb8/igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][96] ([fdo#109271]) +252 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109274] / [fdo#109278]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-iclb: [PASS][98] -> [FAIL][99] ([i915#2346])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-tglb: NOTRUN -> [SKIP][100] ([i915#6076])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#5287]) +5 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#5287]) +4 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109274]) +4 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][104] -> [FAIL][105] ([i915#2122])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk3/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109274] / [fdo#111825]) +9 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][107] ([i915#180])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][108] ([fdo#109280]) +30 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][109] ([i915#5439])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#109280] / [fdo#111825]) +35 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#533])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl4/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][112] ([fdo#108145] / [i915#265])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-glk: NOTRUN -> [FAIL][113] ([fdo#108145] / [i915#265])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][114] ([fdo#108145] / [i915#265]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][115] ([i915#265])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb:
- shard-glk: NOTRUN -> [SKIP][116] ([fdo#109271]) +44 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk1/igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][117] ([i915#3536]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb3/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][118] ([i915#3536])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@kms_plane_lowres@pipe-d-tiling-x.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#658])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl4/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-kbl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#658]) +3 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
- shard-tglb: NOTRUN -> [SKIP][121] ([i915#2920]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-p010:
- shard-tglb: NOTRUN -> [SKIP][122] ([i915#1911])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb7/igt@kms_psr2_su@page_flip-p010.html
- shard-iclb: NOTRUN -> [SKIP][123] ([fdo#109642] / [fdo#111068] / [i915#658])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][124] ([i915#132] / [i915#3467]) +2 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][125] ([fdo#109441]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-iclb: NOTRUN -> [SKIP][126] ([i915#3555])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
- shard-tglb: NOTRUN -> [SKIP][127] ([i915#3555])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][128] -> [DMESG-WARN][129] ([i915#180]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][130] ([fdo#109271]) +81 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl2/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglb: NOTRUN -> [SKIP][131] ([i915#2437]) +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#2437]) +1 similar issue
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][133] ([i915#2530]) +2 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@nouveau_crc@pipe-a-source-rg.html
- shard-tglb: NOTRUN -> [SKIP][134] ([i915#2530]) +4 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb3/igt@nouveau_crc@pipe-a-source-rg.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-iclb: NOTRUN -> [SKIP][135] ([fdo#109278] / [i915#2530])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb1/igt@nouveau_crc@pipe-d-source-rg.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-tglb: NOTRUN -> [SKIP][136] ([fdo#109291]) +6 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@prime_nv_test@nv_i915_sharing:
- shard-iclb: NOTRUN -> [SKIP][137] ([fdo#109291]) +4 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@prime_nv_test@nv_i915_sharing.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][138] ([fdo#109295])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@prime_vgem@fence-flip-hang.html
- shard-tglb: NOTRUN -> [SKIP][139] ([fdo#109295])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@prime_vgem@fence-flip-hang.html
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- shard-iclb: NOTRUN -> [DMESG-WARN][140] ([i915#5098])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb3/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
- shard-kbl: NOTRUN -> [DMESG-WARN][141] ([i915#5098])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
- shard-tglb: NOTRUN -> [DMESG-WARN][142] ([i915#5098])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb8/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
* igt@sysfs_clients@pidname:
- shard-kbl: NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#2994])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl6/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@sema-25:
- shard-iclb: NOTRUN -> [SKIP][144] ([i915#2994])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb8/igt@sysfs_clients@sema-25.html
- shard-tglb: NOTRUN -> [SKIP][145] ([i915#2994])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb1/igt@sysfs_clients@sema-25.html
- shard-glk: NOTRUN -> [SKIP][146] ([fdo#109271] / [i915#2994])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk3/igt@sysfs_clients@sema-25.html
- shard-apl: NOTRUN -> [SKIP][147] ([fdo#109271] / [i915#2994])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@sysfs_clients@sema-25.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][148] ([i915#4525]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb3/igt@gem_exec_balancer@parallel-balancer.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][150] ([i915#2842]) -> [PASS][151] +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][152] ([i915#2842]) -> [PASS][153] +2 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][154] ([fdo#109271]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][156] ([i915#2842]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-snb: [SKIP][158] ([fdo#109271]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-snb6/igt@gem_exec_flush@basic-uc-rw-default.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-snb4/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [DMESG-WARN][160] ([i915#180]) -> [PASS][161] +1 similar issue
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@i915_suspend@debugfs-reader.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl4/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][162] ([i915#2346] / [i915#533]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][164] ([i915#4767]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-tglb: [FAIL][166] ([i915#79]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb8/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: [FAIL][168] ([i915#1888] / [i915#2546]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
* igt@kms_hdmi_inject@inject-audio:
- shard-tglb: [SKIP][170] ([i915#433]) -> [PASS][171]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb2/igt@kms_hdmi_inject@inject-audio.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb2/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [DMESG-WARN][172] ([i915#180]) -> [PASS][173] +3 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* {igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-edp-1}:
- shard-iclb: [SKIP][174] -> [PASS][175] +1 similar issue
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-edp-1.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-edp-1.html
* {igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1}:
- shard-iclb: [SKIP][176] ([i915#5235]) -> [PASS][177] +2 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [SKIP][178] ([fdo#109441]) -> [PASS][179] +1 similar issue
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb4/igt@kms_psr@psr2_dpms.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb2/igt@kms_psr@psr2_dpms.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [SKIP][180] ([i915#5519]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-tglb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][182] ([i915#5614]) -> [SKIP][183] ([i915#4525])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb3/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [DMESG-WARN][184] ([i915#5614]) -> [SKIP][185] ([i915#4525]) +1 similar issue
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb7/igt@gem_exec_balancer@parallel-out-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][186] ([i915#2684]) -> [FAIL][187] ([i915#2680] / [i915#2684])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][188] ([i915#180]) -> [FAIL][189] ([i915#4767])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][190] ([i915#2920]) -> [SKIP][191] ([i915#658])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][192] ([i915#658]) -> [SKIP][193] ([i915#2920])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][194] ([i915#2920]) -> [SKIP][195] ([fdo#111068] / [i915#658]) +1 similar issue
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92]) -> ([FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219]) ([i915#3002] / [i915#4312] / [i915#5257])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl4/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl3/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl3/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl4/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl4/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl6/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl3/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl7/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl1/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][227], [FAIL][228], [FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232], [FAIL][233]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl2/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl7/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl3/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl1/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl6/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl8/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl7/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl4/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl6/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl4/igt@runner@aborted.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl3/igt@runner@aborted.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl4/igt@runner@aborted.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl2/igt@runner@aborted.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/shard-apl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5303]: https://gitlab.freedesktop.org/drm/intel/issues/5303
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6076]: https://gitlab.freedesktop.org/drm/intel/issues/6076
[i915#6079]: https://gitlab.freedesktop.org/drm/intel/issues/6079
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6492 -> IGTPW_7174
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_11700: f5895776c32b7fc5c196fafef3f5dab7e5ad19c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7174: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
IGT_6492: ef18e59c374472e961a3a145724e7381eb4800aa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
[-- Attachment #2: Type: text/html, Size: 70857 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
2022-05-25 18:37 ` [igt-dev] " Matthew Auld
@ 2022-06-08 13:25 ` Das, Nirmoy
-1 siblings, 0 replies; 26+ messages in thread
From: Das, Nirmoy @ 2022-06-08 13:25 UTC (permalink / raw)
To: Matthew Auld, igt-dev; +Cc: Thomas Hellström, intel-gfx
Patch 6 is missing commit message, with that and the GitLab.Pipeline
warning fix the series LGTM
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
On 5/25/2022 8:37 PM, Matthew Auld wrote:
> kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
> from non-mappable device memory, to the mappable part, due to being
> temporarily pinned for scanout, when hitting the CPU fault handler,
> which just gives us SIGBUS. If the device has a small BAR let's attempt
> to use the mappable portion, if possible.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> lib/ioctl_wrappers.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 09eb3ce7..7713e78b 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
> uint32_t handle;
>
> if (gem_has_lmem(fd))
> - handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
> + handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
> + REGION_LMEM(0));
> else
> handle = gem_create(fd, size);
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
@ 2022-06-08 13:25 ` Das, Nirmoy
0 siblings, 0 replies; 26+ messages in thread
From: Das, Nirmoy @ 2022-06-08 13:25 UTC (permalink / raw)
To: Matthew Auld, igt-dev; +Cc: Thomas Hellström, intel-gfx
Patch 6 is missing commit message, with that and the GitLab.Pipeline
warning fix the series LGTM
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
On 5/25/2022 8:37 PM, Matthew Auld wrote:
> kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
> from non-mappable device memory, to the mappable part, due to being
> temporarily pinned for scanout, when hitting the CPU fault handler,
> which just gives us SIGBUS. If the device has a small BAR let's attempt
> to use the mappable portion, if possible.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> lib/ioctl_wrappers.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index 09eb3ce7..7713e78b 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
> uint32_t handle;
>
> if (gem_has_lmem(fd))
> - handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
> + handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
> + REGION_LMEM(0));
> else
> handle = gem_create(fd, size);
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects
2022-06-29 19:06 [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS Matthew Auld
@ 2022-06-29 19:06 ` Matthew Auld
0 siblings, 0 replies; 26+ messages in thread
From: Matthew Auld @ 2022-06-29 19:06 UTC (permalink / raw)
To: igt-dev; +Cc: intel-gfx
kms_frontbuffer_tracking@basic falls over if the fb needs to be migrated
from non-mappable device memory, to the mappable part, due to being
temporarily pinned for scanout, when hitting the CPU fault handler,
which just gives us SIGBUS. If the device has a small BAR let's attempt
to use the mappable portion, if possible.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
lib/ioctl_wrappers.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 09eb3ce7..7713e78b 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -635,7 +635,8 @@ uint32_t gem_buffer_create_fb_obj(int fd, uint64_t size)
uint32_t handle;
if (gem_has_lmem(fd))
- handle = gem_create_in_memory_regions(fd, size, REGION_LMEM(0));
+ handle = gem_create_with_cpu_access_in_memory_regions(fd, size,
+ REGION_LMEM(0));
else
handle = gem_create(fd, size);
--
2.36.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
end of thread, other threads:[~2022-06-29 19:11 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-25 18:36 [Intel-gfx] [PATCH i-g-t 0/9] small BAR uapi bits Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 2/9] lib/i915: wire up optional flags for gem_create_ext Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 3/9] tests/i915/gem_create: exercise NEEDS_CPU_ACCESS Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 4/9] lib/i915: add gem_create_with_cpu_access_in_memory_regions Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 5/9] tests/i915/query: sanity check the probed_cpu_visible_size Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:36 ` [Intel-gfx] [PATCH i-g-t 6/9] tests/i915/query: sanity check the unallocated tracking Matthew Auld
2022-05-25 18:36 ` [igt-dev] " Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 7/9] lib/i915/intel_memory_region: plumb through the cpu_size Matthew Auld
2022-05-25 18:37 ` [igt-dev] " Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 8/9] tests/i915/capture: handle uapi changes Matthew Auld
2022-05-25 18:37 ` [igt-dev] " Matthew Auld
2022-05-25 18:37 ` [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects Matthew Auld
2022-05-25 18:37 ` [igt-dev] " Matthew Auld
2022-06-08 13:25 ` [Intel-gfx] " Das, Nirmoy
2022-06-08 13:25 ` [igt-dev] " Das, Nirmoy
2022-05-25 18:46 ` [igt-dev] ✗ GitLab.Pipeline: warning for small BAR uapi bits Patchwork
2022-05-25 20:09 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2022-05-26 10:43 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2022-06-29 19:06 [Intel-gfx] [PATCH i-g-t 1/9] lib/i915_drm_local: Add I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS Matthew Auld
2022-06-29 19:06 ` [Intel-gfx] [PATCH i-g-t 9/9] lib/i915: request CPU_ACCESS for fb objects Matthew Auld
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