[PATCH 0/1] hw: m25p80: add W# pin and SRWD bit for write protection

* [PATCH 0/1] hw: m25p80: add W# pin and SRWD bit for write protection
@ 2022-05-26  2:11 Iris Chen
  0 siblings, 0 replies; only message in thread
From: Iris Chen @ 2022-05-26  2:11 UTC (permalink / raw)
  Cc: irischenlj, pdel, qemu-devel, qemu-arm, clg, patrick, alistair,
	kwolf, hreitz, peter.maydell, andrew, joel, thuth, lvivier,
	pbonzini, qemu-block, Iris Chen

From: Iris Chen <irischenlj@gmail.com>

Hey everyone, 

My patch adds the W# pin and SRWD bit which work together to control the
status register write ability. 

Accordingly, when W# is low and SRWD bit is high, hardware protection
mode (HPM) is initiated. All other cases result in software protection. 

Acceptance tests have been added to verify all four scenarios: it tests
the ability to write to SRWD depending on whether write protection is
set. 

Thanks, 
Iris

Iris Chen (1):
  hw: m25p80: add W# pin and SRWD bit for write protection

 hw/block/m25p80.c             | 72 +++++++++++++++++++++++++++++++++++
 tests/qtest/aspeed_smc-test.c | 62 ++++++++++++++++++++++++++++++
 2 files changed, 134 insertions(+)

-- 
2.30.2

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