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* [PATCH 0/2] Correct "div4" clocks in Exynos7885
@ 2022-05-26  5:58 ` David Virag
  0 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-05-26  5:58 UTC (permalink / raw)
  Cc: David Virag, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

The div4 clocks in Exynos7885 were mistakenly set to have the wrong
parents making them and their children display 2x the actual clockrate.
This in turn lead to the DTSI getting the wrong clocks for UART, since
that's the configuration it worked properly with. This was noticed by
Sam Protsenko [1] but since it worked this way and not the other way
around, I didn't think much of it.

[1] https://lore.kernel.org/linux-samsung-soc/CAPLW+4k3Vmg0W0jVsTChHTG8+eeg=5QF+actz1Tk0vNV9w-y-A@mail.gmail.com/

David Virag (2):
  clk: samsung: exynos7885: Correct "div4" clock parents
  arm64: dts: exynos: Correct UART clocks on Exynos7885

 arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------
 drivers/clk/samsung/clk-exynos7885.c       |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

-- 
2.35.1


^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH 0/2] Correct "div4" clocks in Exynos7885
@ 2022-05-26  5:58 ` David Virag
  0 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-05-26  5:58 UTC (permalink / raw)
  Cc: David Virag, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

The div4 clocks in Exynos7885 were mistakenly set to have the wrong
parents making them and their children display 2x the actual clockrate.
This in turn lead to the DTSI getting the wrong clocks for UART, since
that's the configuration it worked properly with. This was noticed by
Sam Protsenko [1] but since it worked this way and not the other way
around, I didn't think much of it.

[1] https://lore.kernel.org/linux-samsung-soc/CAPLW+4k3Vmg0W0jVsTChHTG8+eeg=5QF+actz1Tk0vNV9w-y-A@mail.gmail.com/

David Virag (2):
  clk: samsung: exynos7885: Correct "div4" clock parents
  arm64: dts: exynos: Correct UART clocks on Exynos7885

 arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------
 drivers/clk/samsung/clk-exynos7885.c       |  4 ++--
 2 files changed, 8 insertions(+), 8 deletions(-)

-- 
2.35.1


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
  2022-05-26  5:58 ` David Virag
@ 2022-05-26  5:58   ` David Virag
  -1 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-05-26  5:58 UTC (permalink / raw)
  Cc: David Virag, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.

Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: David Virag <virag.david003@gmail.com>
---
 drivers/clk/samsung/clk-exynos7885.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
index a7b106302706..368c50badd15 100644
--- a/drivers/clk/samsung/clk-exynos7885.c
+++ b/drivers/clk/samsung/clk-exynos7885.c
@@ -182,7 +182,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
 	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
 	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
-	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
+	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
 	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
 	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
 	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
@@ -190,7 +190,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
 	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
 	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
-	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
+	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
 	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
 
 	/* CORE */
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
@ 2022-05-26  5:58   ` David Virag
  0 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-05-26  5:58 UTC (permalink / raw)
  Cc: David Virag, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

"div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
2 to achieve a by 4 division, thus their parents are the respective
"div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
This leads to the kernel thinking "div4"s and everything under them run
at 2x the clock speed. Fix this.

Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
Signed-off-by: David Virag <virag.david003@gmail.com>
---
 drivers/clk/samsung/clk-exynos7885.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
index a7b106302706..368c50badd15 100644
--- a/drivers/clk/samsung/clk-exynos7885.c
+++ b/drivers/clk/samsung/clk-exynos7885.c
@@ -182,7 +182,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	    CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
 	DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
 	    CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
-	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
+	DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
 	    CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
 	DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
 	    CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
@@ -190,7 +190,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
 	    CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
 	DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
 	    CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
-	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
+	DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
 	    CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
 
 	/* CORE */
-- 
2.35.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH 2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885
  2022-05-26  5:58 ` David Virag
@ 2022-05-26  5:58   ` David Virag
  -1 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-05-26  5:58 UTC (permalink / raw)
  Cc: David Virag, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

The clocks in the serial UART nodes were swapped by mistake on
Exynos7885. This only worked correctly because of a mistake in the clock
driver which has been fixed. With the fixed clock driver in place, the
baudrate of the UARTs get miscalculated. Fix this by correcting the
clocks in the dtsi.

Fixes: 06874015327b ("arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC")
Signed-off-by: David Virag <virag.david003@gmail.com>
---
 arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
index 3170661f5b67..9c233c56558c 100644
--- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
@@ -280,8 +280,8 @@ serial_0: serial@13800000 {
 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART0_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <64>;
 			status = "disabled";
@@ -293,8 +293,8 @@ serial_1: serial@13810000 {
 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart1_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART1_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
@@ -306,8 +306,8 @@ serial_2: serial@13820000 {
 			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart2_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART2_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH 2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885
@ 2022-05-26  5:58   ` David Virag
  0 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-05-26  5:58 UTC (permalink / raw)
  Cc: David Virag, Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

The clocks in the serial UART nodes were swapped by mistake on
Exynos7885. This only worked correctly because of a mistake in the clock
driver which has been fixed. With the fixed clock driver in place, the
baudrate of the UARTs get miscalculated. Fix this by correcting the
clocks in the dtsi.

Fixes: 06874015327b ("arm64: dts: exynos: Add initial device tree support for Exynos7885 SoC")
Signed-off-by: David Virag <virag.david003@gmail.com>
---
 arch/arm64/boot/dts/exynos/exynos7885.dtsi | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos7885.dtsi b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
index 3170661f5b67..9c233c56558c 100644
--- a/arch/arm64/boot/dts/exynos/exynos7885.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7885.dtsi
@@ -280,8 +280,8 @@ serial_0: serial@13800000 {
 			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart0_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART0_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <64>;
 			status = "disabled";
@@ -293,8 +293,8 @@ serial_1: serial@13810000 {
 			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart1_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART1_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
@@ -306,8 +306,8 @@ serial_2: serial@13820000 {
 			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&uart2_bus>;
-			clocks = <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>,
-				 <&cmu_peri CLK_GOUT_UART2_PCLK>;
+			clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
+				 <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
 			clock-names = "uart", "clk_uart_baud0";
 			samsung,uart-fifosize = <256>;
 			status = "disabled";
-- 
2.35.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
  2022-05-26  5:58   ` David Virag
@ 2022-05-26  7:21     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-26  7:21 UTC (permalink / raw)
  To: David Virag
  Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

On 26/05/2022 07:58, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
> 
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---
>  drivers/clk/samsung/clk-exynos7885.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
@ 2022-05-26  7:21     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-26  7:21 UTC (permalink / raw)
  To: David Virag
  Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar,
	Sylwester Nawrocki, Tomasz Figa, Chanwoo Choi, Michael Turquette,
	Stephen Boyd, Sam Protsenko, devicetree, linux-arm-kernel,
	linux-samsung-soc, linux-kernel, linux-clk

On 26/05/2022 07:58, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
> 
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---
>  drivers/clk/samsung/clk-exynos7885.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: (subset) [PATCH 2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885
  2022-05-26  5:58   ` David Virag
@ 2022-06-06  9:22     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-06  9:22 UTC (permalink / raw)
  To: David Virag
  Cc: Krzysztof Kozlowski, linux-clk, Sylwester Nawrocki,
	linux-arm-kernel, Michael Turquette, Stephen Boyd,
	Krzysztof Kozlowski, devicetree, linux-samsung-soc, Alim Akhtar,
	Sam Protsenko, linux-kernel, Chanwoo Choi, Tomasz Figa,
	Rob Herring

On Thu, 26 May 2022 07:58:40 +0200, David Virag wrote:
> The clocks in the serial UART nodes were swapped by mistake on
> Exynos7885. This only worked correctly because of a mistake in the clock
> driver which has been fixed. With the fixed clock driver in place, the
> baudrate of the UARTs get miscalculated. Fix this by correcting the
> clocks in the dtsi.
> 
> 
> [...]

Applied, thanks!

[2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885
      https://git.kernel.org/krzk/linux/c/f84d83d8165570380f55f4ce578bfb131a9266c5

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: (subset) [PATCH 2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885
@ 2022-06-06  9:22     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-06  9:22 UTC (permalink / raw)
  To: David Virag
  Cc: Krzysztof Kozlowski, linux-clk, Sylwester Nawrocki,
	linux-arm-kernel, Michael Turquette, Stephen Boyd,
	Krzysztof Kozlowski, devicetree, linux-samsung-soc, Alim Akhtar,
	Sam Protsenko, linux-kernel, Chanwoo Choi, Tomasz Figa,
	Rob Herring

On Thu, 26 May 2022 07:58:40 +0200, David Virag wrote:
> The clocks in the serial UART nodes were swapped by mistake on
> Exynos7885. This only worked correctly because of a mistake in the clock
> driver which has been fixed. With the fixed clock driver in place, the
> baudrate of the UARTs get miscalculated. Fix this by correcting the
> clocks in the dtsi.
> 
> 
> [...]

Applied, thanks!

[2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885
      https://git.kernel.org/krzk/linux/c/f84d83d8165570380f55f4ce578bfb131a9266c5

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
  2022-05-26  7:21     ` Krzysztof Kozlowski
@ 2022-06-24  7:59       ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24  7:59 UTC (permalink / raw)
  To: David Virag, Sylwester Nawrocki
  Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, Tomasz Figa,
	Chanwoo Choi, Michael Turquette, Stephen Boyd, Sam Protsenko,
	devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
	linux-clk

On 26/05/2022 09:21, Krzysztof Kozlowski wrote:
> On 26/05/2022 07:58, David Virag wrote:
>> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
>> 2 to achieve a by 4 division, thus their parents are the respective
>> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
>> This leads to the kernel thinking "div4"s and everything under them run
>> at 2x the clock speed. Fix this.
>>
>> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
>> Signed-off-by: David Virag <virag.david003@gmail.com>
>> ---
>>  drivers/clk/samsung/clk-exynos7885.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)

Sylwester,

This goes to v5.20?

Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
@ 2022-06-24  7:59       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-24  7:59 UTC (permalink / raw)
  To: David Virag, Sylwester Nawrocki
  Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, Tomasz Figa,
	Chanwoo Choi, Michael Turquette, Stephen Boyd, Sam Protsenko,
	devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
	linux-clk

On 26/05/2022 09:21, Krzysztof Kozlowski wrote:
> On 26/05/2022 07:58, David Virag wrote:
>> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
>> 2 to achieve a by 4 division, thus their parents are the respective
>> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
>> This leads to the kernel thinking "div4"s and everything under them run
>> at 2x the clock speed. Fix this.
>>
>> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
>> Signed-off-by: David Virag <virag.david003@gmail.com>
>> ---
>>  drivers/clk/samsung/clk-exynos7885.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)

Sylwester,

This goes to v5.20?

Best regards,
Krzysztof

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
  2022-06-24  7:59       ` Krzysztof Kozlowski
@ 2022-07-10 17:30         ` David Virag
  -1 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-07-10 17:30 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki
  Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, Tomasz Figa,
	Chanwoo Choi, Michael Turquette, Stephen Boyd, Sam Protsenko,
	devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
	linux-clk

On Fri, 2022-06-24 at 09:59 +0200, Krzysztof Kozlowski wrote:
> On 26/05/2022 09:21, Krzysztof Kozlowski wrote:
> > On 26/05/2022 07:58, David Virag wrote:
> > > "div4" DIVs which divide PLLs by 4 are actually dividing "div2"
> > > DIVs by
> > > 2 to achieve a by 4 division, thus their parents are the
> > > respective
> > > "div2" DIVs. These DIVs were mistakenly set to have the PLLs as
> > > parents.
> > > This leads to the kernel thinking "div4"s and everything under
> > > them run
> > > at 2x the clock speed. Fix this.
> > > 
> > > Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock
> > > driver")
> > > Signed-off-by: David Virag <virag.david003@gmail.com>
> > > ---
> > >  drivers/clk/samsung/clk-exynos7885.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> Sylwester,
> 
> This goes to v5.20?
> 
> Best regards,
> Krzysztof

Hi Krzysztof and Sylwester,

What is going on with this patch? What will happen to it? From what
I've seen, Sylwester doesn't seem to be too active lately. I just don't
want it to get lost. With only one of the patches applied, UART is
partially broken on 7885. Don't want to make unnecessary noise, but
this patch should probably be applied sooner than later.

Best regards,
David

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents
@ 2022-07-10 17:30         ` David Virag
  0 siblings, 0 replies; 14+ messages in thread
From: David Virag @ 2022-07-10 17:30 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Sylwester Nawrocki
  Cc: Rob Herring, Krzysztof Kozlowski, Alim Akhtar, Tomasz Figa,
	Chanwoo Choi, Michael Turquette, Stephen Boyd, Sam Protsenko,
	devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
	linux-clk

On Fri, 2022-06-24 at 09:59 +0200, Krzysztof Kozlowski wrote:
> On 26/05/2022 09:21, Krzysztof Kozlowski wrote:
> > On 26/05/2022 07:58, David Virag wrote:
> > > "div4" DIVs which divide PLLs by 4 are actually dividing "div2"
> > > DIVs by
> > > 2 to achieve a by 4 division, thus their parents are the
> > > respective
> > > "div2" DIVs. These DIVs were mistakenly set to have the PLLs as
> > > parents.
> > > This leads to the kernel thinking "div4"s and everything under
> > > them run
> > > at 2x the clock speed. Fix this.
> > > 
> > > Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock
> > > driver")
> > > Signed-off-by: David Virag <virag.david003@gmail.com>
> > > ---
> > >  drivers/clk/samsung/clk-exynos7885.c | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> Sylwester,
> 
> This goes to v5.20?
> 
> Best regards,
> Krzysztof

Hi Krzysztof and Sylwester,

What is going on with this patch? What will happen to it? From what
I've seen, Sylwester doesn't seem to be too active lately. I just don't
want it to get lost. With only one of the patches applied, UART is
partially broken on 7885. Don't want to make unnecessary noise, but
this patch should probably be applied sooner than later.

Best regards,
David

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-07-10 17:32 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-26  5:58 [PATCH 0/2] Correct "div4" clocks in Exynos7885 David Virag
2022-05-26  5:58 ` David Virag
2022-05-26  5:58 ` [PATCH 1/2] clk: samsung: exynos7885: Correct "div4" clock parents David Virag
2022-05-26  5:58   ` David Virag
2022-05-26  7:21   ` Krzysztof Kozlowski
2022-05-26  7:21     ` Krzysztof Kozlowski
2022-06-24  7:59     ` Krzysztof Kozlowski
2022-06-24  7:59       ` Krzysztof Kozlowski
2022-07-10 17:30       ` David Virag
2022-07-10 17:30         ` David Virag
2022-05-26  5:58 ` [PATCH 2/2] arm64: dts: exynos: Correct UART clocks on Exynos7885 David Virag
2022-05-26  5:58   ` David Virag
2022-06-06  9:22   ` (subset) " Krzysztof Kozlowski
2022-06-06  9:22     ` Krzysztof Kozlowski

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