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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 06/28] target/arm: Move get_phys_addr_pmsav7_default to ptw.c
Date: Fri,  3 Jun 2022 21:05:45 -0700	[thread overview]
Message-ID: <20220604040607.269301-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220604040607.269301-1-richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/ptw.h    |  3 +++
 target/arm/helper.c | 41 -----------------------------------------
 target/arm/ptw.c    | 41 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 44 insertions(+), 41 deletions(-)

diff --git a/target/arm/ptw.h b/target/arm/ptw.h
index 324a9dde14..d6e3fee152 100644
--- a/target/arm/ptw.h
+++ b/target/arm/ptw.h
@@ -33,6 +33,9 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
 }
 
+void get_phys_addr_pmsav7_default(CPUARMState *env,
+                                  ARMMMUIdx mmu_idx,
+                                  int32_t address, int *prot);
 bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
                           MMUAccessType access_type, ARMMMUIdx mmu_idx,
                           hwaddr *phys_ptr, int *prot,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 31abcf6fc9..7dd54c1863 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11642,47 +11642,6 @@ do_fault:
     return true;
 }
 
-static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
-                                                ARMMMUIdx mmu_idx,
-                                                int32_t address, int *prot)
-{
-    if (!arm_feature(env, ARM_FEATURE_M)) {
-        *prot = PAGE_READ | PAGE_WRITE;
-        switch (address) {
-        case 0xF0000000 ... 0xFFFFFFFF:
-            if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
-                /* hivecs execing is ok */
-                *prot |= PAGE_EXEC;
-            }
-            break;
-        case 0x00000000 ... 0x7FFFFFFF:
-            *prot |= PAGE_EXEC;
-            break;
-        }
-    } else {
-        /* Default system address map for M profile cores.
-         * The architecture specifies which regions are execute-never;
-         * at the MPU level no other checks are defined.
-         */
-        switch (address) {
-        case 0x00000000 ... 0x1fffffff: /* ROM */
-        case 0x20000000 ... 0x3fffffff: /* SRAM */
-        case 0x60000000 ... 0x7fffffff: /* RAM */
-        case 0x80000000 ... 0x9fffffff: /* RAM */
-            *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
-            break;
-        case 0x40000000 ... 0x5fffffff: /* Peripheral */
-        case 0xa0000000 ... 0xbfffffff: /* Device */
-        case 0xc0000000 ... 0xdfffffff: /* Device */
-        case 0xe0000000 ... 0xffffffff: /* System */
-            *prot = PAGE_READ | PAGE_WRITE;
-            break;
-        default:
-            g_assert_not_reached();
-        }
-    }
-}
-
 static bool pmsav7_use_background_region(ARMCPU *cpu,
                                          ARMMMUIdx mmu_idx, bool is_user)
 {
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 5c32648a16..74650c6c52 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -374,6 +374,47 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
     return false;
 }
 
+void get_phys_addr_pmsav7_default(CPUARMState *env,
+                                  ARMMMUIdx mmu_idx,
+                                  int32_t address, int *prot)
+{
+    if (!arm_feature(env, ARM_FEATURE_M)) {
+        *prot = PAGE_READ | PAGE_WRITE;
+        switch (address) {
+        case 0xF0000000 ... 0xFFFFFFFF:
+            if (regime_sctlr(env, mmu_idx) & SCTLR_V) {
+                /* hivecs execing is ok */
+                *prot |= PAGE_EXEC;
+            }
+            break;
+        case 0x00000000 ... 0x7FFFFFFF:
+            *prot |= PAGE_EXEC;
+            break;
+        }
+    } else {
+        /* Default system address map for M profile cores.
+         * The architecture specifies which regions are execute-never;
+         * at the MPU level no other checks are defined.
+         */
+        switch (address) {
+        case 0x00000000 ... 0x1fffffff: /* ROM */
+        case 0x20000000 ... 0x3fffffff: /* SRAM */
+        case 0x60000000 ... 0x7fffffff: /* RAM */
+        case 0x80000000 ... 0x9fffffff: /* RAM */
+            *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+            break;
+        case 0x40000000 ... 0x5fffffff: /* Peripheral */
+        case 0xa0000000 ... 0xbfffffff: /* Device */
+        case 0xc0000000 ... 0xdfffffff: /* Device */
+        case 0xe0000000 ... 0xffffffff: /* System */
+            *prot = PAGE_READ | PAGE_WRITE;
+            break;
+        default:
+            g_assert_not_reached();
+        }
+    }
+}
+
 /**
  * get_phys_addr - get the physical address for this virtual address
  *
-- 
2.34.1



  parent reply	other threads:[~2022-06-04  4:17 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-04  4:05 [PATCH 00/28] target/arm: Split out ptw.c from helper.c Richard Henderson
2022-06-04  4:05 ` [PATCH 01/28] target/arm: Move stage_1_mmu_idx decl to internals.h Richard Henderson
2022-06-04 10:40   ` Philippe Mathieu-Daudé via
2022-06-04 17:43     ` Richard Henderson
2022-06-04  4:05 ` [PATCH 02/28] target/arm: Move get_phys_addr to ptw.c Richard Henderson
2022-06-04  4:05 ` [PATCH 03/28] target/arm: Move get_phys_addr_v5 " Richard Henderson
2022-06-04  4:05 ` [PATCH 04/28] target/arm: Move get_phys_addr_v6 " Richard Henderson
2022-06-04  4:05 ` [PATCH 05/28] target/arm: Move get_phys_addr_pmsav5 " Richard Henderson
2022-06-04  4:05 ` Richard Henderson [this message]
2022-06-04  4:05 ` [PATCH 07/28] target/arm: Move get_phys_addr_pmsav7 " Richard Henderson
2022-06-04  4:05 ` [PATCH 08/28] target/arm: Move get_phys_addr_pmsav8 " Richard Henderson
2022-06-04  4:05 ` [PATCH 09/28] target/arm: Move pmsav8_mpu_lookup " Richard Henderson
2022-06-04  4:05 ` [PATCH 10/28] target/arm: Move pmsav7_use_background_region " Richard Henderson
2022-06-04  4:05 ` [PATCH 11/28] target/arm: Move v8m_security_lookup " Richard Henderson
2022-06-04  4:05 ` [PATCH 12/28] target/arm: Move m_is_{ppb,system}_region " Richard Henderson
2022-06-04  4:05 ` [PATCH 13/28] target/arm: Move get_level1_table_address " Richard Henderson
2022-06-04  4:05 ` [PATCH 14/28] target/arm: Move combine_cacheattrs and subroutines " Richard Henderson
2022-06-04  4:05 ` [PATCH 15/28] target/arm: Move get_phys_addr_lpae " Richard Henderson
2022-06-04  4:05 ` [PATCH 16/28] target/arm: Move arm_{ldl,ldq}_ptw " Richard Henderson
2022-06-04  4:05 ` [PATCH 17/28] target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_helper.c Richard Henderson
2022-06-04  4:05 ` [PATCH 18/28] target/arm: Move arm_pamax, pamax_map into ptw.c Richard Henderson
2022-06-04  4:05 ` [PATCH 19/28] target/arm: Move get_S1prot, get_S2prot to ptw.c Richard Henderson
2022-06-04  4:05 ` [PATCH 20/28] target/arm: Move check_s2_mmu_setup " Richard Henderson
2022-06-04  4:06 ` [PATCH 21/28] target/arm: Move aa32_va_parameters " Richard Henderson
2022-06-04  4:06 ` [PATCH 22/28] target/arm: Move ap_to_tw_prot etc " Richard Henderson
2022-06-04  4:06 ` [PATCH 23/28] target/arm: Move regime_is_user " Richard Henderson
2022-06-04  4:06 ` [PATCH 24/28] target/arm: Move regime_ttbr " Richard Henderson
2022-06-04  4:06 ` [PATCH 25/28] target/arm: Move regime_translation_disabled " Richard Henderson
2022-06-04  4:06 ` [PATCH 26/28] target/arm: Move arm_cpu_get_phys_page_attrs_debug " Richard Henderson
2022-06-04  4:06 ` [PATCH 27/28] target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx " Richard Henderson
2022-06-04  4:06 ` [PATCH 28/28] target/arm: Pass CPUARMState to arm_ld[lq]_ptw Richard Henderson
2022-06-07 15:48 ` [PATCH 00/28] target/arm: Split out ptw.c from helper.c Peter Maydell

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