[PATCH v3 0/3] J7200: CPSW5G: Add support for QSGMII mode to am65-cpsw driver

[PATCH v3 0/3] J7200: CPSW5G: Add support for QSGMII mode to am65-cpsw driver

[Siddharth Vadapalli]

Add support for QSGMII mode to am65-cpsw driver.

Change log:

v2 -> v3:
1. In ti,k3-am654-cpsw-nuss.yaml, restrict if/then statement to port
   nodes.

v1 -> v2:
1. Add new compatible for CPSW5G in ti,k3-am654-cpsw-nuss.yaml and extend
   properties for new compatible.
2. Add extra_modes member to struct am65_cpsw_pdata to be used for QSGMII
   mode by new compatible.
3. Add check for phylink supported modes to ensure that only one phy mode
   is advertised as supported.
4. Check if extra_modes supports QSGMII mode in am65_cpsw_nuss_mac_config()
   for register write.
5. Add check for assigning port->sgmii_base only when extra_modes is valid.

v2: https://lore.kernel.org/r/20220602114558.6204-1-s-vadapalli@ti.com/
v1: https://lore.kernel.org/r/20220531113058.23708-1-s-vadapalli@ti.com

Siddharth Vadapalli (3):
  dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J7200
    CPSW5G
  net: ethernet: ti: am65-cpsw: Add support for J7200 CPSW5G
  net: ethernet: ti: am65-cpsw: Move phy_set_mode_ext() to correct
    location

 .../bindings/net/ti,k3-am654-cpsw-nuss.yaml   | 135 ++++++++++++------
 drivers/net/ethernet/ti/am65-cpsw-nuss.c      |  41 +++++-
 drivers/net/ethernet/ti/am65-cpsw-nuss.h      |   2 +
 3 files changed, 129 insertions(+), 49 deletions(-)

-- 
2.36.1

[PATCH v3 1/3] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J7200 CPSW5G

[Siddharth Vadapalli]

Update bindings for TI K3 J7200 SoC which contains 5 ports (4 external
ports) CPSW5G module and add compatible for it.

Changes made:
    - Add new compatible ti,j7200-cpswxg-nuss for CPSW5G.
    - Extend pattern properties for new compatible.
    - Change maximum number of CPSW ports to 4 for new compatible.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 .../bindings/net/ti,k3-am654-cpsw-nuss.yaml   | 135 ++++++++++++------
 1 file changed, 93 insertions(+), 42 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
index b8281d8be940..49f63aaf5a08 100644
--- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
+++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -57,6 +57,7 @@ properties:
       - ti,am654-cpsw-nuss
       - ti,j721e-cpsw-nuss
       - ti,am642-cpsw-nuss
+      - ti,j7200-cpswxg-nuss
 
   reg:
     maxItems: 1
@@ -108,48 +109,98 @@ properties:
         const: 1
       '#size-cells':
         const: 0
-
-    patternProperties:
-      port@[1-2]:
-        type: object
-        description: CPSWxG NUSS external ports
-
-        $ref: ethernet-controller.yaml#
-
-        properties:
-          reg:
-            minimum: 1
-            maximum: 2
-            description: CPSW port number
-
-          phys:
-            maxItems: 1
-            description: phandle on phy-gmii-sel PHY
-
-          label:
-            description: label associated with this port
-
-          ti,mac-only:
-            $ref: /schemas/types.yaml#/definitions/flag
-            description:
-              Specifies the port works in mac-only mode.
-
-          ti,syscon-efuse:
-            $ref: /schemas/types.yaml#/definitions/phandle-array
-            items:
-              - items:
-                  - description: Phandle to the system control device node which
-                      provides access to efuse
-                  - description: offset to efuse registers???
-            description:
-              Phandle to the system control device node which provides access
-              to efuse IO range with MAC addresses
-
-        required:
-          - reg
-          - phys
-
-    additionalProperties: false
+    allOf:
+      - if:
+          properties:
+            compatible:
+              contains:
+                enum:
+                  - ti,am654-cpsw-nuss
+                  - ti,j721e-cpsw-nuss
+                  - ti,am642-cpsw-nuss
+        then:
+          patternProperties:
+            port@[1-2]:
+              type: object
+              description: CPSWxG NUSS external ports
+
+              $ref: ethernet-controller.yaml#
+
+              properties:
+                reg:
+                  minimum: 1
+                  maximum: 2
+                  description: CPSW port number
+
+              required:
+                - reg
+      - if:
+          properties:
+            compatible:
+              contains:
+                enum:
+                  - ti,j7200-cpswxg-nuss
+        then:
+          patternProperties:
+            port@[1-4]:
+              type: object
+              description: CPSWxG NUSS external ports
+
+              $ref: ethernet-controller.yaml#
+
+              properties:
+                reg:
+                  minimum: 1
+                  maximum: 4
+                  description: CPSW port number
+
+              required:
+                - reg
+      - if:
+          properties:
+            compatible:
+              contains:
+                enum:
+                  - ti,am654-cpsw-nuss
+                  - ti,j721e-cpsw-nuss
+                  - ti,am642-cpsw-nuss
+                  - ti,j7200-cpswxg-nuss
+        then:
+          patternProperties:
+            port@[*]:
+              type: object
+              description: CPSWxG NUSS external ports
+
+              $ref: ethernet-controller.yaml#
+
+              properties:
+                phys:
+                  maxItems: 1
+                  description: phandle on phy-gmii-sel PHY
+
+                label:
+                  description: label associated with this port
+
+                ti,mac-only:
+                  $ref: /schemas/types.yaml#/definitions/flag
+                  description:
+                    Specifies the port works in mac-only mode.
+
+                ti,syscon-efuse:
+                  $ref: /schemas/types.yaml#/definitions/phandle-array
+                  items:
+                    - items:
+                        - description: Phandle to the system control device node which
+                            provides access to efuse
+                        - description: offset to efuse registers???
+                  description:
+                    Phandle to the system control device node which provides access
+                    to efuse IO range with MAC addresses
+
+              required:
+                - phys
+
+  additionalProperties: false
 
 patternProperties:
   "^mdio@[0-9a-f]+$":
-- 
2.36.1

[PATCH v3 2/3] net: ethernet: ti: am65-cpsw: Add support for J7200 CPSW5G

[Siddharth Vadapalli]

CPSW5G in J7200 supports additional modes like QSGMII and SGMII.
Add new compatible for J7200 and enable QSGMII mode in am65-cpsw driver.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/net/ethernet/ti/am65-cpsw-nuss.c | 32 ++++++++++++++++++++++--
 drivers/net/ethernet/ti/am65-cpsw-nuss.h |  2 ++
 2 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index fb92d4c1547d..db94e8cdef56 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -74,6 +74,9 @@
 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG	0x318
 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2       0x31C
 
+#define AM65_CPSW_SGMII_CONTROL_REG		0x010
+#define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE	BIT(0)
+
 #define AM65_CPSW_CTL_VLAN_AWARE		BIT(1)
 #define AM65_CPSW_CTL_P0_ENABLE			BIT(2)
 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE		BIT(13)
@@ -1409,7 +1412,14 @@ static const struct net_device_ops am65_cpsw_nuss_netdev_ops = {
 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode,
 				      const struct phylink_link_state *state)
 {
-	/* Currently not used */
+	struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data,
+							  phylink_config);
+	struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave);
+	struct am65_cpsw_common *common = port->common;
+
+	if (common->pdata.extra_modes & BIT(state->interface))
+		writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE,
+		       port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG);
 }
 
 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode,
@@ -1847,6 +1857,8 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
 		port->common = common;
 		port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE +
 				  AM65_CPSW_NU_PORTS_OFFSET * (port_id);
+		if (common->pdata.extra_modes)
+			port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id);
 		port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
 				  (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
 		port->name = of_get_property(port_np, "label", NULL);
@@ -1981,7 +1993,15 @@ am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx)
 	port->slave.phylink_config.type = PHYLINK_NETDEV;
 	port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD;
 
-	phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
+	if (phy_interface_mode_is_rgmii(port->slave.phy_if)) {
+		phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces);
+	} else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) {
+		__set_bit(PHY_INTERFACE_MODE_QSGMII,
+			  port->slave.phylink_config.supported_interfaces);
+	} else {
+		dev_err(dev, "selected phy-mode is not supported\n");
+		return -EOPNOTSUPP;
+	}
 
 	phylink = phylink_create(&port->slave.phylink_config,
 				 of_node_to_fwnode(port->slave.phy_node),
@@ -2608,10 +2628,18 @@ static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
 	.fdqring_mode = K3_RINGACC_RING_MODE_RING,
 };
 
+static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
+	.quirks = 0,
+	.ale_dev_id = "am64-cpswxg",
+	.fdqring_mode = K3_RINGACC_RING_MODE_RING,
+	.extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII),
+};
+
 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
 	{ .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
 	{ .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
 	{ .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata},
+	{ .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata},
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable);
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h
index ac945631bf2f..2c9850fdfcb6 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h
@@ -46,6 +46,7 @@ struct am65_cpsw_port {
 	const char			*name;
 	u32				port_id;
 	void __iomem			*port_base;
+	void __iomem			*sgmii_base;
 	void __iomem			*stat_base;
 	void __iomem			*fetch_ram_base;
 	bool				disabled;
@@ -88,6 +89,7 @@ struct am65_cpsw_rx_chn {
 
 struct am65_cpsw_pdata {
 	u32	quirks;
+	u64	extra_modes;
 	enum k3_ring_mode fdqring_mode;
 	const char	*ale_dev_id;
 };
-- 
2.36.1

[PATCH v3 3/3] net: ethernet: ti: am65-cpsw: Move phy_set_mode_ext() to correct location

[Siddharth Vadapalli]

In TI's J7200 SoC CPSW5G ports, each of the 4 ports can be configured
as a QSGMII main or QSGMII-SUB port. This configuration is performed
by phy-gmii-sel driver on invoking the phy_set_mode_ext() function.

It is necessary for the QSGMII main port to be configured before any of
the QSGMII-SUB interfaces are brought up. Currently, the QSGMII-SUB
interfaces come up before the QSGMII main port is configured.

Fix this by moving the call to phy_set_mode_ext() from
am65_cpsw_nuss_ndo_slave_open() to am65_cpsw_nuss_init_slave_ports(),
thereby ensuring that the QSGMII main port is configured before any of
the QSGMII-SUB ports are brought up.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 drivers/net/ethernet/ti/am65-cpsw-nuss.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index db94e8cdef56..0eda6104605c 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -593,11 +593,6 @@ static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev)
 	/* mac_sl should be configured via phy-link interface */
 	am65_cpsw_sl_ctl_reset(port);
 
-	ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET,
-			       port->slave.phy_if);
-	if (ret)
-		goto error_cleanup;
-
 	ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0);
 	if (ret)
 		goto error_cleanup;
@@ -1898,6 +1893,10 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
 			goto of_node_put;
 		}
 
+		ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if);
+		if (ret)
+			goto of_node_put;
+
 		ret = of_get_mac_address(port_np, port->slave.mac_addr);
 		if (ret) {
 			am65_cpsw_am654_get_efuse_macid(port_np,
-- 
2.36.1

Re: [PATCH v3 1/3] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J7200 CPSW5G

[Rob Herring]

On Mon, Jun 06, 2022 at 04:34:41PM +0530, Siddharth Vadapalli wrote:
> Update bindings for TI K3 J7200 SoC which contains 5 ports (4 external
> ports) CPSW5G module and add compatible for it.
> 
> Changes made:
>     - Add new compatible ti,j7200-cpswxg-nuss for CPSW5G.
>     - Extend pattern properties for new compatible.
>     - Change maximum number of CPSW ports to 4 for new compatible.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>  .../bindings/net/ti,k3-am654-cpsw-nuss.yaml   | 135 ++++++++++++------
>  1 file changed, 93 insertions(+), 42 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
> index b8281d8be940..49f63aaf5a08 100644
> --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
> +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
> @@ -57,6 +57,7 @@ properties:
>        - ti,am654-cpsw-nuss
>        - ti,j721e-cpsw-nuss
>        - ti,am642-cpsw-nuss
> +      - ti,j7200-cpswxg-nuss
>  
>    reg:
>      maxItems: 1
> @@ -108,48 +109,98 @@ properties:
>          const: 1
>        '#size-cells':
>          const: 0
> -
> -    patternProperties:
> -      port@[1-2]:

Just change this to 'port@[1-4]'.

> -        type: object
> -        description: CPSWxG NUSS external ports
> -
> -        $ref: ethernet-controller.yaml#
> -
> -        properties:
> -          reg:
> -            minimum: 1
> -            maximum: 2

And this to 4.

Then, you just need this to disallow the additional ports:

if:
  not:
    properties:
      compatible:
        contains:
          const: ti,j7200-cpswxg-nuss
then:
  patternProperties:
    '^port@[3-4]$': false


Rob

Re: [PATCH v3 1/3] dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J7200 CPSW5G

[Siddharth Vadapalli]

Hello Rob,

On 09/06/22 23:56, Rob Herring wrote:
> On Mon, Jun 06, 2022 at 04:34:41PM +0530, Siddharth Vadapalli wrote:
>> Update bindings for TI K3 J7200 SoC which contains 5 ports (4 external
>> ports) CPSW5G module and add compatible for it.
>>
>> Changes made:
>>     - Add new compatible ti,j7200-cpswxg-nuss for CPSW5G.
>>     - Extend pattern properties for new compatible.
>>     - Change maximum number of CPSW ports to 4 for new compatible.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>  .../bindings/net/ti,k3-am654-cpsw-nuss.yaml   | 135 ++++++++++++------
>>  1 file changed, 93 insertions(+), 42 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
>> index b8281d8be940..49f63aaf5a08 100644
>> --- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
>> +++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
>> @@ -57,6 +57,7 @@ properties:
>>        - ti,am654-cpsw-nuss
>>        - ti,j721e-cpsw-nuss
>>        - ti,am642-cpsw-nuss
>> +      - ti,j7200-cpswxg-nuss
>>  
>>    reg:
>>      maxItems: 1
>> @@ -108,48 +109,98 @@ properties:
>>          const: 1
>>        '#size-cells':
>>          const: 0
>> -
>> -    patternProperties:
>> -      port@[1-2]:
> 
> Just change this to 'port@[1-4]'.
> 
>> -        type: object
>> -        description: CPSWxG NUSS external ports
>> -
>> -        $ref: ethernet-controller.yaml#
>> -
>> -        properties:
>> -          reg:
>> -            minimum: 1
>> -            maximum: 2
> 
> And this to 4.
> 
> Then, you just need this to disallow the additional ports:
> 
> if:
>   not:
>     properties:
>       compatible:
>         contains:
>           const: ti,j7200-cpswxg-nuss
> then:
>   patternProperties:
>     '^port@[3-4]$': false

Thank you for the suggestion. I will implement this and send the v4 series.

Regards,
Siddharth.