* [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu
@ 2022-06-07 5:24 Zbigniew Kempczyński
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 5:24 UTC (permalink / raw)
To: igt-dev
Add crc32 calculation library on gpu (dg2).
v2: use predication instead of cond_bbe with memory access.
v3: migrate crc32 tables to separate file to avoid license clashes.
v4: move common definitions to intel_reg.h, add docs
v5: addressing missed review comments
Zbigniew Kempczyński (4):
lib/intel_reg: Add common MI_* macros to remove duplicates
lib/igt_crc: Introduce common place for crc tables and functions
lib/i915_crc: Introduce crc32 on gpu for DG2
tests/api_intel_bb: Add crc32 checking test for DG2
benchmarks/gem_wsim.c | 34 +-
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 2 +
lib/i915/i915_crc.c | 297 ++++++++++++++++++
lib/i915/i915_crc.h | 27 ++
lib/igt_crc.c | 107 +++++++
lib/igt_crc.h | 31 ++
lib/intel_reg.h | 45 +++
lib/meson.build | 2 +
tests/i915/api_intel_bb.c | 63 ++++
tests/i915/gem_exec_fair.c | 27 --
tests/i915/gem_exec_fence.c | 31 --
tests/i915/gem_watchdog.c | 27 --
tests/i915/gem_workarounds.c | 7 +-
tests/i915/gen7_exec_parse.c | 8 +-
tests/i915/gen9_exec_parse.c | 11 +-
15 files changed, 589 insertions(+), 130 deletions(-)
create mode 100644 lib/i915/i915_crc.c
create mode 100644 lib/i915/i915_crc.h
create mode 100644 lib/igt_crc.c
create mode 100644 lib/igt_crc.h
--
2.32.0
^ permalink raw reply [flat|nested] 24+ messages in thread
* [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
@ 2022-06-07 5:24 ` Zbigniew Kempczyński
2022-06-09 9:06 ` Petri Latvala
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions Zbigniew Kempczyński
` (5 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 5:24 UTC (permalink / raw)
To: igt-dev
In few tests we got some MI_* duplicates (MI_MATH for example).
Add common definitions in intel_reg.h and remove local definitions
in the tests.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
benchmarks/gem_wsim.c | 34 ++++-------------------------
lib/intel_reg.h | 42 ++++++++++++++++++++++++++++++++++++
tests/i915/gem_exec_fair.c | 27 -----------------------
tests/i915/gem_exec_fence.c | 31 --------------------------
tests/i915/gem_watchdog.c | 27 -----------------------
tests/i915/gem_workarounds.c | 7 +++---
tests/i915/gen7_exec_parse.c | 8 +++----
tests/i915/gen9_exec_parse.c | 11 ++++------
8 files changed, 57 insertions(+), 130 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index d14352225e..aadd2737cd 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -279,36 +279,7 @@ static uint64_t ns_to_ctx_ticks(uint64_t ns)
return div64_u64_round_up(ns * f, NSEC_PER_SEC);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_ARB_CHECK MI_INSTR(0x5, 0)
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
-#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 0)
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
#define MI_CS_MMIO_DST BIT(19)
#define MI_CS_MMIO_SRC BIT(18)
@@ -1487,7 +1458,10 @@ static unsigned int create_bb(struct w_step *w, int self)
*cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
/* Save delta for indirect read by COND_BBE */
- *cs++ = MI_STORE_REGISTER_MEM | (1 + use_64b) | MI_CS_MMIO_DST;
+ if (use_64b)
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_CS_MMIO_DST;
+ else
+ *cs++ = MI_STORE_REGISTER_MEM | MI_CS_MMIO_DST;
*cs++ = CS_GPR(NOW_TS);
w->reloc[r].target_handle = self;
w->reloc[r].offset = offset_in_page(cs);
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index cb62728896..b8d97a07c9 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2625,6 +2625,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
+#define MI_LOAD_REGISTER_REG ((0x2A << 23) | 1)
+#define MI_STORE_REGISTER_MEM ((0x24 << 23) | (3 - 2))
+#define MI_STORE_REGISTER_MEM_GEN8 ((0x24 << 23) | (4 - 2))
/* Flush */
#define MI_FLUSH (0x04<<23)
@@ -2642,6 +2645,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_NOOP_WRITE_ID (1<<22)
#define MI_NOOP_ID_MASK (1<<22 - 1)
+/* ARB Check */
+#define MI_ARB_CHECK (0x5 << 23)
+
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
/* Atomics */
@@ -2656,12 +2662,48 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
#define MI_BATCH_BUFFER_END (0xA << 23)
#define MI_COND_BATCH_BUFFER_END (0x36 << 23)
+#define MAD_GT_IDD (0 << 12)
+#define MAD_GT_OR_EQ_IDD (1 << 12)
+#define MAD_LT_IDD (2 << 12)
+#define MAD_LT_OR_EQ_IDD (3 << 12)
+#define MAD_EQ_IDD (4 << 12)
+#define MAD_NEQ_IDD (5 << 12)
#define MI_DO_COMPARE (1 << 21)
#define MI_BATCH_NON_SECURE (1)
#define MI_BATCH_NON_SECURE_I965 (1 << 8)
#define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */
+/* Math */
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
+/* DG2+ */
+#define MI_MATH_SHL MI_MATH_INSTR(0x105, 0x0, 0x0)
+#define MI_MATH_SHR MI_MATH_INSTR(0x106, 0x0, 0x0)
+#define MI_MATH_SAR MI_MATH_INSTR(0x107, 0x0, 0x0)
+
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x) (x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF 0x32
+#define MI_MATH_REG_CF 0x33
+
#define MAX_DISPLAY_PIPES 2
typedef enum {
diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
index 935f9c4a0b..89921697f7 100644
--- a/tests/i915/gem_exec_fair.c
+++ b/tests/i915/gem_exec_fair.c
@@ -112,33 +112,6 @@ static uint64_t ticks_to_ns(int i915, uint64_t ticks)
read_timestamp_frequency(i915));
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
static void delay(int i915,
const struct intel_execution_engine2 *e,
uint32_t handle,
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 47ddf3083d..f20d7d94ff 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -2366,37 +2366,6 @@ static void test_syncobj_timeline_multiple_ext_nodes(int fd)
syncobj_destroy(fd, syncobjs[i]);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-/* #define MI_LOAD_REGISTER_MEM (MI_INSTR(0x29, 1) */
-/* #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) */
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
-#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
-#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x00, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x80, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
#define HSW_CS_GPR(n) (0x600 + 8*(n))
#define RING_TIMESTAMP (0x358)
#define MI_PREDICATE_RESULT_1 (0x41c)
diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
index fc1ba00712..01eb007694 100644
--- a/tests/i915/gem_watchdog.c
+++ b/tests/i915/gem_watchdog.c
@@ -270,33 +270,6 @@ static void virtual(int i915, const intel_ctx_cfg_t *base_cfg)
igt_assert_eq(count, expect);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
static unsigned int offset_in_page(void *addr)
{
return (uintptr_t)addr & 4095;
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 70967b3ff5..12c70b2011 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -83,8 +83,6 @@ static bool write_only(const uint32_t addr)
return false;
}
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
-
static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
{
struct drm_i915_gem_exec_object2 obj[2];
@@ -122,7 +120,10 @@ static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
out = base =
gem_mmap__cpu(i915, obj[1].handle, 0, batch_sz, PROT_WRITE);
for (int i = 0; i < num_wa_regs; i++) {
- *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
+ if (gen >= 8)
+ *out++ = MI_STORE_REGISTER_MEM_GEN8;
+ else
+ *out++ = MI_STORE_REGISTER_MEM;
*out++ = wa_regs[i].addr;
reloc[i].target_handle = obj[0].handle;
reloc[i].offset = (out - base) * sizeof(*out);
diff --git a/tests/i915/gen7_exec_parse.c b/tests/i915/gen7_exec_parse.c
index c83a791126..c3c2a7a296 100644
--- a/tests/i915/gen7_exec_parse.c
+++ b/tests/i915/gen7_exec_parse.c
@@ -48,8 +48,6 @@
#define INSTR_CLIENT_SHIFT 29
#define INSTR_INVALID_CLIENT 0x7
-#define MI_LOAD_REGISTER_REG (0x2a << 23)
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
#define MI_ARB_ON_OFF (0x8 << 23)
#define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
@@ -374,19 +372,19 @@ static void test_allocations(int fd)
static void hsw_load_register_reg(void)
{
uint32_t init_gpr0[16] = {
- MI_LOAD_REGISTER_IMM | (3 - 2),
+ MI_LOAD_REGISTER_IMM,
HSW_CS_GPR0,
0xabcdabc0, /* leave [1:0] zero */
MI_BATCH_BUFFER_END,
};
uint32_t store_gpr0[16] = {
- MI_STORE_REGISTER_MEM | (3 - 2),
+ MI_STORE_REGISTER_MEM,
HSW_CS_GPR0,
0, /* reloc*/
MI_BATCH_BUFFER_END,
};
uint32_t do_lrr[16] = {
- MI_LOAD_REGISTER_REG | (3 - 2),
+ MI_LOAD_REGISTER_REG,
0, /* [1] = src */
HSW_CS_GPR0, /* dst */
MI_BATCH_BUFFER_END,
diff --git a/tests/i915/gen9_exec_parse.c b/tests/i915/gen9_exec_parse.c
index fa61693cfc..1d9cd37104 100644
--- a/tests/i915/gen9_exec_parse.c
+++ b/tests/i915/gen9_exec_parse.c
@@ -38,12 +38,9 @@
#define INSTR_CLIENT_SHIFT 29
#define INSTR_INVALID_CLIENT 0x7
-#define MI_LOAD_REGISTER_REG (0x2a << 23)
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
#define MI_ARB_ON_OFF (0x8 << 23)
#define MI_USER_INTERRUPT (0x02 << 23)
#define MI_FLUSH_DW (0x26 << 23)
-#define MI_ARB_CHECK (0x05 << 23)
#define MI_REPORT_HEAD (0x07 << 23)
#define MI_SUSPEND_FLUSH (0x0b << 23)
#define MI_LOAD_SCAN_LINES_EXCL (0x13 << 23)
@@ -689,7 +686,7 @@ static void test_cmd_crossing_page(const int i915, const uint32_t handle)
MI_BATCH_BUFFER_END,
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
BCS_GPR(0),
0, /* reloc */
0, /* reloc */
@@ -728,7 +725,7 @@ static void test_invalid_length(const int i915, const uint32_t handle)
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
BCS_GPR(0),
0, /* reloc */
0, /* reloc */
@@ -841,7 +838,7 @@ static void test_register(const int i915, const uint32_t handle,
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
r->addr,
0, /* reloc */
0, /* reloc */
@@ -880,7 +877,7 @@ static long int read_reg(const int i915, const uint32_t handle,
const uint32_t addr)
{
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
addr,
0, /* reloc */
0, /* reloc */
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
@ 2022-06-07 5:24 ` Zbigniew Kempczyński
2022-06-09 9:44 ` Petri Latvala
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 3/4] lib/i915_crc: Introduce crc32 on gpu for DG2 Zbigniew Kempczyński
` (4 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 5:24 UTC (permalink / raw)
To: igt-dev
Add crc32 table for on-cpu crc calculation function. Other tables and
algorithms should be added here allowing reuse tables for in-gpu crc
calculation.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
lib/igt_crc.c | 107 ++++++++++++++++++
lib/igt_crc.h | 31 +++++
lib/meson.build | 1 +
4 files changed, 140 insertions(+)
create mode 100644 lib/igt_crc.c
create mode 100644 lib/igt_crc.h
diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index 1774256530..b78f1eb6ff 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -22,6 +22,7 @@
<xi:include href="xml/igt_chamelium.xml"/>
<xi:include href="xml/igt_collection.xml"/>
<xi:include href="xml/igt_core.xml"/>
+ <xi:include href="xml/igt_crc.xml"/>
<xi:include href="xml/igt_debugfs.xml"/>
<xi:include href="xml/igt_device.xml"/>
<xi:include href="xml/igt_device_scan.xml"/>
diff --git a/lib/igt_crc.c b/lib/igt_crc.c
new file mode 100644
index 0000000000..e634f5cf27
--- /dev/null
+++ b/lib/igt_crc.c
@@ -0,0 +1,107 @@
+/*-
+ * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
+ * code or tables extracted from it, as desired without restriction.
+ */
+
+/*
+ * First, the polynomial itself and its table of feedback terms. The
+ * polynomial is
+ * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
+ *
+ * Note that we take it "backwards" and put the highest-order term in
+ * the lowest-order bit. The X^32 term is "implied"; the LSB is the
+ * X^31 term, etc. The X^0 term (usually shown as "+1") results in
+ * the MSB being 1
+ *
+ * Note that the usual hardware shift register implementation, which
+ * is what we're using (we're merely optimizing it by doing eight-bit
+ * chunks at a time) shifts bits into the lowest-order term. In our
+ * implementation, that means shifting towards the right. Why do we
+ * do it this way? Because the calculated CRC must be transmitted in
+ * order from highest-order term to lowest-order term. UARTs transmit
+ * characters in order from LSB to MSB. By storing the CRC this way
+ * we hand it to the UART in the order low-byte to high-byte; the UART
+ * sends each low-bit to hight-bit; and the result is transmission bit
+ * by bit from highest- to lowest-order term without requiring any bit
+ * shuffling on our part. Reception works similarly
+ *
+ * The feedback terms table consists of 256, 32-bit entries. Notes
+ *
+ * The table can be generated at runtime if desired; code to do so
+ * is shown later. It might not be obvious, but the feedback
+ * terms simply represent the results of eight shift/xor opera
+ * tions for all combinations of data and CRC register values
+ *
+ * The values must be right-shifted by eight bits by the "updcrc
+ * logic; the shift must be unsigned (bring in zeroes). On some
+ * hardware you could probably optimize the shift in assembler by
+ * using byte-swap instructions
+ * polynomial $edb88320
+ *
+ *
+ * CRC32 code derived from work by Gary S. Brown.
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include "igt_crc.h"
+
+const uint32_t igt_crc32_tab[256] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
+ 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
+ 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
+ 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
+ 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
+ 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
+ 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
+ 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
+ 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
+ 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
+ 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
+ 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
+ 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
+ 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
+ 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
+ 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
+ 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
+ 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
+ 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
+ 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
+ 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
+ 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
+ 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
+ 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
+ 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
+ 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
+ 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
+ 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
+ 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
+};
+
+uint32_t igt_cpu_crc32(const void *buf, size_t size)
+{
+
+ const uint8_t *p = buf;
+ uint32_t crc;
+
+ crc = ~0U;
+
+ while (size--)
+ crc = igt_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
+
+ return crc ^ ~0U;
+}
diff --git a/lib/igt_crc.h b/lib/igt_crc.h
new file mode 100644
index 0000000000..5c0b934ea5
--- /dev/null
+++ b/lib/igt_crc.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __IGT_CRC_H__
+#define __IGT_CRC_H__
+
+#include <stddef.h>
+#include <stdint.h>
+
+/**
+ * SECTION:igt_crc
+ * @short_description: igt crc tables and calculation functions
+ * @title: CRC
+ * @include: igt_crc.h
+ *
+ * # Introduction
+ *
+ * Providing vendor agnostic crc calculation is useful to avoid code
+ * duplication. Especially if vendor will decide to do on-gpu crc calculation
+ * it will need to inject crc table to gpu.
+ *
+ * All crc tables are globals to allow direct in-code use.
+ */
+
+const uint32_t igt_crc32_tab[256];
+
+uint32_t igt_cpu_crc32(const void *buf, size_t size);
+
+#endif
diff --git a/lib/meson.build b/lib/meson.build
index 0a173c1fc6..cc2b2abee6 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -15,6 +15,7 @@ lib_sources = [
'i915/i915_blt.c',
'igt_collection.c',
'igt_color_encoding.c',
+ 'igt_crc.c',
'igt_debugfs.c',
'igt_device.c',
'igt_device_scan.c',
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [igt-dev] [PATCH i-g-t 3/4] lib/i915_crc: Introduce crc32 on gpu for DG2
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions Zbigniew Kempczyński
@ 2022-06-07 5:24 ` Zbigniew Kempczyński
2022-06-09 9:47 ` Petri Latvala
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test " Zbigniew Kempczyński
` (3 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 5:24 UTC (permalink / raw)
To: igt-dev
Adding crc32 calculation on gpu gives us new possibility to verify data
integrity without relying on trust cpu mapping is correct.
Patch introduces calculating crc32 on DG2 only. On older gens ALU
(MI_MATH) doesn't support bit-shifting instructions as well as multiply
or divide. Emulating n-bit shifts cost hundred of instructions with
predicated SRM (works on render engine only). Another limitation is lack
of indexed load / store. On DG2 we can use WPARID and CS_MI_ADDRESS_OFFSET
to achieve indexed operation on memory.
Due to performance reasons (cpu crc32 calculation even on WC memory is
still much faster than on gpu, also depends on calculated object memory
region) calculation will complete in reasonable of time only for few MiB.
v2: - use registers relative to engine to allow run on all engines (Chris)
- use predication instead of memory access to get better performance
(Chris)
- add location where crc32 implementation comes from (Petri)
v4: - use common crc32 table from igt_crc
- add docs
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
.../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
lib/i915/i915_crc.c | 297 ++++++++++++++++++
lib/i915/i915_crc.h | 27 ++
lib/intel_reg.h | 3 +
lib/meson.build | 1 +
5 files changed, 329 insertions(+)
create mode 100644 lib/i915/i915_crc.c
create mode 100644 lib/i915/i915_crc.h
diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
index b78f1eb6ff..a19f786e84 100644
--- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
+++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
@@ -63,6 +63,7 @@
<xi:include href="xml/gem_scheduler.xml"/>
<xi:include href="xml/gem_submission.xml"/>
<xi:include href="xml/i915_blt.xml"/>
+ <xi:include href="xml/i915_crc.xml"/>
<xi:include href="xml/intel_ctx.xml"/>
</chapter>
<xi:include href="xml/igt_test_programs.xml"/>
diff --git a/lib/i915/i915_crc.c b/lib/i915/i915_crc.c
new file mode 100644
index 0000000000..4c6e488c23
--- /dev/null
+++ b/lib/i915/i915_crc.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include "drmtest.h"
+#include "gem_create.h"
+#include "gem_engine_topology.h"
+#include "gem_mman.h"
+#include "i830_reg.h"
+#include "i915_drm.h"
+#include "intel_reg.h"
+#include "intel_chipset.h"
+#include "ioctl_wrappers.h"
+#include "intel_allocator.h"
+#include "igt_crc.h"
+#include "i915/i915_crc.h"
+
+#define CS_GPR(x) (0x600 + 8 * (x))
+#define GPR(x) CS_GPR(x)
+#define R(x) (x)
+#define USERDATA(offset, idx) ((offset) + (0x100 + (idx)) * 4)
+#define OFFSET(obj_offset, current, start) \
+ ((obj_offset) + (current - start) * 4)
+
+#define MI_PREDICATE_RESULT 0x3B8
+#define WPARID 0x21C
+#define CS_MI_ADDRESS_OFFSET 0x3B4
+
+#define LOAD_REGISTER_REG(__reg_src, __reg_dst) do { \
+ *bb++ = MI_LOAD_REGISTER_REG | BIT(19) | BIT(18); \
+ *bb++ = (__reg_src); \
+ *bb++ = (__reg_dst); \
+ } while (0)
+
+#define LOAD_REGISTER_IMM32(__reg, __imm1) do { \
+ *bb++ = MI_LOAD_REGISTER_IMM | BIT(19); \
+ *bb++ = (__reg); \
+ *bb++ = (__imm1); \
+ } while (0)
+
+#define LOAD_REGISTER_IMM64(__reg, __imm1, __imm2) do { \
+ *bb++ = (MI_LOAD_REGISTER_IMM + 2) | BIT(19); \
+ *bb++ = (__reg); \
+ *bb++ = (__imm1); \
+ *bb++ = (__reg) + 4; \
+ *bb++ = (__imm2); \
+ } while (0)
+
+#define LOAD_REGISTER_MEM(__reg, __offset) do { \
+ *bb++ = MI_LOAD_REGISTER_MEM_GEN8 | BIT(19); \
+ *bb++ = (__reg); \
+ *bb++ = (__offset); \
+ *bb++ = (__offset) >> 32; \
+ } while (0)
+
+#define LOAD_REGISTER_MEM_WPARID(__reg, __offset) do { \
+ *bb++ = MI_LOAD_REGISTER_MEM_GEN8 | BIT(19) | BIT(16); \
+ *bb++ = (__reg); \
+ *bb++ = (__offset); \
+ *bb++ = (__offset) >> 32; \
+ } while (0)
+
+#define STORE_REGISTER_MEM(__reg, __offset) do { \
+ *bb++ = MI_STORE_REGISTER_MEM_GEN8 | BIT(19); \
+ *bb++ = (__reg); \
+ *bb++ = (__offset); \
+ *bb++ = (__offset) >> 32; \
+ } while (0)
+
+#define STORE_REGISTER_MEM_PREDICATED(__reg, __offset) do { \
+ *bb++ = MI_STORE_REGISTER_MEM_GEN8 | BIT(19) | (BIT(21); \
+ *bb++ = (__reg); \
+ *bb++ = (__offset); \
+ *bb++ = (__offset) >> 32; \
+ } while (0)
+
+#define COND_BBE(__value, __offset, __condition) do { \
+ *bb++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (__condition) | 2; \
+ *bb++ = (__value); \
+ *bb++ = (__offset); \
+ *bb++ = (__offset) >> 32; \
+ } while (0)
+
+#define MATH_4_STORE(__r1, __r2, __op, __r3) do { \
+ *bb++ = MI_MATH(4); \
+ *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(__r1)); \
+ *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(__r2)); \
+ *bb++ = (__op); \
+ *bb++ = MI_MATH_STORE(MI_MATH_REG(__r3), MI_MATH_REG_ACCU); \
+ } while (0)
+
+#define BBSIZE 4096
+
+/* Aliasing for easier refactoring */
+#define GPR_SIZE GPR(0)
+#define R_SIZE R(0)
+
+#define GPR_CRC GPR(1)
+#define R_CRC R(1)
+
+#define GPR_INDATA_IDX GPR(2)
+#define R_INDATA_IDX R(2)
+
+#define GPR_TABLE_IDX GPR(3)
+#define R_TABLE_IDX R(3)
+
+#define GPR_CURR_DW GPR(4)
+#define R_CURR_DW R(4)
+
+#define GPR_CONST_2 GPR(5)
+#define R_CONST_2 R(5)
+
+#define GPR_CONST_4 GPR(6)
+#define R_CONST_4 R(6)
+
+#define GPR_CONST_8 GPR(7)
+#define R_CONST_8 R(7)
+
+#define GPR_CONST_ff GPR(8)
+#define R_CONST_ff R(8)
+
+#define GPR_ffffffff GPR(9)
+#define R_ffffffff R(9)
+
+#define GPR_TMP_1 GPR(10)
+#define R_TMP_1 R(10)
+
+#define GPR_TMP_2 GPR(11)
+#define R_TMP_2 R(11)
+
+static void fill_batch(int i915, uint32_t bb_handle, uint64_t bb_offset,
+ uint64_t table_offset, uint64_t data_offset, uint32_t data_size)
+{
+ uint32_t *bb, *batch, *jmp;
+ const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
+ const int use_64b = gen >= 8;
+ uint64_t offset;
+ uint64_t crc = USERDATA(table_offset, 0);
+
+ igt_assert(data_size % 4 == 0);
+
+ batch = gem_mmap__device_coherent(i915, bb_handle, 0, BBSIZE,
+ PROT_READ | PROT_WRITE);
+ memset(batch, 0, BBSIZE);
+
+ bb = batch;
+
+ LOAD_REGISTER_IMM64(GPR_SIZE, data_size, 0);
+ LOAD_REGISTER_IMM64(GPR_CRC, ~0U, 0); /* crc start - 0xffffffff */
+ LOAD_REGISTER_IMM64(GPR_INDATA_IDX, 0, 0); /* data_offset index (0) */
+ LOAD_REGISTER_IMM64(GPR_CONST_2, 2, 0); /* const value 2 */
+ LOAD_REGISTER_IMM64(GPR_CONST_4, 4, 0); /* const value 4 */
+ LOAD_REGISTER_IMM64(GPR_CONST_8, 8, 0); /* const value 8 */
+ LOAD_REGISTER_IMM64(GPR_CONST_ff, 0xff, 0); /* const value 0xff */
+ LOAD_REGISTER_IMM64(GPR_ffffffff, ~0U, 0); /* const value 0xffffffff */
+
+ /* for indexed reads from memory */
+ LOAD_REGISTER_IMM32(WPARID, 1);
+
+ jmp = bb;
+
+ *bb++ = MI_SET_PREDICATE;
+ *bb++ = MI_ARB_CHECK;
+
+ LOAD_REGISTER_REG(GPR_INDATA_IDX, CS_MI_ADDRESS_OFFSET);
+ LOAD_REGISTER_MEM_WPARID(GPR_CURR_DW, data_offset);
+
+ for (int byte = 0; byte < 4; byte++) {
+ if (byte != 0)
+ MATH_4_STORE(R_CURR_DW, R_CONST_8,
+ MI_MATH_SHR, R_CURR_DW); /* dw >> 8 */
+
+ /* crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); */
+ MATH_4_STORE(R_CURR_DW, R_CONST_ff,
+ MI_MATH_AND, R_TMP_1); /* dw & 0xff */
+ MATH_4_STORE(R_CRC, R_TMP_1,
+ MI_MATH_XOR, R_TMP_1); /* crc ^ tmp */
+ MATH_4_STORE(R_TMP_1, R_CONST_ff,
+ MI_MATH_AND, R_TMP_1); /* tmp & 0xff */
+ MATH_4_STORE(R_TMP_1, R_CONST_2,
+ MI_MATH_SHL, R_TABLE_IDX); /* tmp << 2 (crc idx) */
+
+ LOAD_REGISTER_REG(GPR_TABLE_IDX, CS_MI_ADDRESS_OFFSET);
+ LOAD_REGISTER_MEM_WPARID(GPR_TMP_1, table_offset);
+
+ MATH_4_STORE(R_CRC, R_CONST_8,
+ MI_MATH_SHR, R_TMP_2); /* crc >> 8 (shift) */
+ MATH_4_STORE(R_TMP_2, R_TMP_1,
+ MI_MATH_XOR, R_CRC); /* crc = tab[v] ^ shift */
+ }
+
+ /* increment data index */
+ MATH_4_STORE(R_INDATA_IDX, R_CONST_4, MI_MATH_ADD, R_INDATA_IDX);
+
+ /* loop until R_SIZE == 0, R_SIZE = R_SIZE - R_CONST_4 */
+
+ *bb++ = MI_MATH(5);
+ *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(R_SIZE));
+ *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(R_CONST_4));
+ *bb++ = MI_MATH_SUB;
+ *bb++ = MI_MATH_STORE(MI_MATH_REG(R_SIZE), MI_MATH_REG_ACCU);
+ *bb++ = MI_MATH_STORE(MI_MATH_REG(R_TMP_2), MI_MATH_REG_ZF);
+ LOAD_REGISTER_REG(GPR_TMP_2, MI_PREDICATE_RESULT);
+
+ *bb++ = MI_BATCH_BUFFER_START | BIT(15) | BIT(8) | use_64b;
+ offset = OFFSET(bb_offset, jmp, batch);
+ *bb++ = offset;
+ *bb++ = offset >> 32;
+
+ *bb++ = MI_SET_PREDICATE;
+
+ MATH_4_STORE(R_CRC, R_ffffffff, MI_MATH_XOR, R_TMP_1);
+ STORE_REGISTER_MEM(GPR_TMP_1, crc);
+
+ *bb++ = MI_BATCH_BUFFER_END;
+
+ gem_munmap(batch, BBSIZE);
+}
+
+/**
+ * i915_crc32:
+ * @i915: drm fd
+ * @ahnd: allocator handle
+ * @ctx: intel context
+ * @e: engine on which crc32 calculation will be executed
+ * @data_handle: bo which is subject of crc32 calculation
+ * @data_size: length of bo data to calculate (must be multiple of 4)
+ *
+ * Function calculates crc32 for @data_handle with size @data_size.
+ *
+ * Returns: uint32_t crc32.
+ *
+ **/
+uint32_t i915_crc32(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t data_handle, uint32_t data_size)
+{
+ struct drm_i915_gem_execbuffer2 execbuf = {};
+ struct drm_i915_gem_exec_object2 obj[3] = {};
+ uint64_t bb_offset, table_offset, data_offset;
+ uint32_t bb, table, crc, table_size = 4096;
+ uint32_t *ptr;
+
+ igt_assert(data_size % 4 == 0);
+
+ table = gem_create_in_memory_regions(i915, table_size, REGION_LMEM(0));
+ gem_write(i915, table, 0, igt_crc32_tab, sizeof(igt_crc32_tab));
+
+ table_offset = get_offset(ahnd, table, table_size, 0);
+ data_offset = get_offset(ahnd, data_handle, data_size, 0);
+
+ obj[0].offset = table_offset;
+ obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
+ obj[0].handle = table;
+
+ obj[1].offset = data_offset;
+ obj[1].flags = EXEC_OBJECT_PINNED;
+ obj[1].handle = data_handle;
+
+ bb = gem_create_in_memory_regions(i915, BBSIZE, REGION_LMEM(0));
+ bb_offset = get_offset(ahnd, bb, BBSIZE, 0);
+ fill_batch(i915, bb, bb_offset, table_offset, data_offset, data_size);
+ obj[2].offset = bb_offset;
+ obj[2].flags = EXEC_OBJECT_PINNED;
+ obj[2].handle = bb;
+ execbuf.buffer_count = 3;
+ execbuf.buffers_ptr = to_user_pointer(obj);
+ execbuf.flags = e->flags;
+ execbuf.rsvd1 = ctx->id;
+ gem_execbuf(i915, &execbuf);
+ gem_sync(i915, table);
+
+ ptr = gem_mmap__device_coherent(i915, table, 0, table_size, PROT_READ);
+ crc = ptr[0x100];
+ gem_munmap(ptr, table_size);
+ gem_close(i915, table);
+ gem_close(i915, bb);
+
+ return crc;
+}
+
+/**
+ * supports_i915_crc32:
+ * @i915: drm fd
+ *
+ * Returns: flag if i915_crc32() is able to generate crc32 on gpu.
+ *
+ **/
+bool supports_i915_crc32(int i915)
+{
+ uint16_t devid = intel_get_drm_devid(i915);
+
+ return IS_DG2(devid);
+}
diff --git a/lib/i915/i915_crc.h b/lib/i915/i915_crc.h
new file mode 100644
index 0000000000..3bd7411690
--- /dev/null
+++ b/lib/i915/i915_crc.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+#ifndef _I915_CRC_H_
+#define _I915_CRC_H_
+
+#include <stdint.h>
+#include "intel_ctx.h"
+
+/**
+ * SECTION:i915_crc
+ * @short_description: i915 gpu crc
+ * @title: I915 GPU CRC
+ * @include: i915_crc.h
+ *
+ * # Introduction
+ *
+ * Intel gpu crc calculation implementation.
+ */
+
+uint32_t i915_crc32(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ uint32_t data_handle, uint32_t data_size);
+bool supports_i915_crc32(int i915);
+
+#endif /* _I915_CRC_ */
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index b8d97a07c9..104a73f073 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2704,6 +2704,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_MATH_REG_ZF 0x32
#define MI_MATH_REG_CF 0x33
+/* DG2+ */
+#define MI_SET_PREDICATE MI_INSTR(0x1, 0)
+
#define MAX_DISPLAY_PIPES 2
typedef enum {
diff --git a/lib/meson.build b/lib/meson.build
index cc2b2abee6..12b2cc5d78 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -13,6 +13,7 @@ lib_sources = [
'i915/intel_memory_region.c',
'i915/intel_mocs.c',
'i915/i915_blt.c',
+ 'i915/i915_crc.c',
'igt_collection.c',
'igt_color_encoding.c',
'igt_crc.c',
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test for DG2
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
` (2 preceding siblings ...)
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 3/4] lib/i915_crc: Introduce crc32 on gpu for DG2 Zbigniew Kempczyński
@ 2022-06-07 5:24 ` Zbigniew Kempczyński
2022-06-09 9:52 ` Petri Latvala
2022-06-07 6:14 ` [igt-dev] ✓ Fi.CI.BAT: success for Add crc32 calculation on dg2 gpu (rev5) Patchwork
` (2 subsequent siblings)
6 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 5:24 UTC (permalink / raw)
To: igt-dev
Add simple test which compares crc32 sums and calculation times on cpu
and gpu.
v2: - addressing review comments - igt_debug + igt_time_elapsed (Kamil)
- exercise crc for size smaller than page size
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
tests/i915/api_intel_bb.c | 63 +++++++++++++++++++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
index 92f44cecf4..d6998af692 100644
--- a/tests/i915/api_intel_bb.c
+++ b/tests/i915/api_intel_bb.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "igt_crc.h"
#include "i915/gem.h"
#include "i915/gem_create.h"
#include <unistd.h>
@@ -38,6 +39,7 @@
#include <zlib.h>
#include "intel_bufops.h"
#include "i915/gem_vm.h"
+#include "i915/i915_crc.h"
#define PAGE_SIZE 4096
@@ -1395,6 +1397,51 @@ static void render_ccs(struct buf_ops *bops)
igt_assert_f(fails == 0, "render-ccs fails: %d\n", fails);
}
+static void test_crc32(int i915, const intel_ctx_t *ctx,
+ const struct intel_execution_engine2 *e,
+ struct drm_i915_gem_memory_class_instance *r)
+{
+ uint64_t ahnd = get_reloc_ahnd(i915, ctx->id);
+ uint32_t data, *ptr;
+
+ uint32_t region = INTEL_MEMORY_REGION_ID(r->memory_class,
+ r->memory_instance);
+
+ igt_debug("[engine: %s, region: %s]\n", e->name,
+ region == REGION_SMEM ? "smem" : "lmem");
+ for (int i = 2; i < 21; i += 2) {
+ struct timespec start, end;
+ uint64_t size = 1 << i;
+ uint32_t cpu_crc, gpu_crc;
+
+ double cpu_time, gpu_time;
+
+ data = gem_create_in_memory_regions(i915, size, region);
+ ptr = gem_mmap__device_coherent(i915, data, 0, size, PROT_WRITE);
+ for (int j = 0; j < size / sizeof(*ptr); j++)
+ ptr[j] = j;
+
+ clock_gettime(CLOCK_MONOTONIC, &start);
+ cpu_crc = igt_cpu_crc32(ptr, size);
+ clock_gettime(CLOCK_MONOTONIC, &end);
+ cpu_time = igt_time_elapsed(&start, &end);
+ munmap(ptr, size);
+
+ clock_gettime(CLOCK_MONOTONIC, &start);
+ gpu_crc = i915_crc32(i915, ahnd, ctx, e, data, size);
+ clock_gettime(CLOCK_MONOTONIC, &end);
+ gpu_time = igt_time_elapsed(&start, &end);
+ igt_debug("size: %10lld, cpu crc: 0x%08x (time: %.3f), "
+ "gpu crc: 0x%08x (time: %.3f) [ %s ]\n",
+ (long long) size, cpu_crc, cpu_time, gpu_crc, gpu_time,
+ cpu_crc == gpu_crc ? "EQUAL" : "DIFFERENT");
+ gem_close(i915, data);
+ igt_assert(cpu_crc == gpu_crc);
+ }
+
+ put_ahnd(ahnd);
+}
+
static int opt_handler(int opt, int opt_index, void *data)
{
switch (opt) {
@@ -1552,6 +1599,22 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
igt_subtest("render-ccs")
render_ccs(bops);
+ igt_describe("Compare cpu and gpu crc32 sums on input object");
+ igt_subtest_with_dynamic_f("crc32") {
+ const intel_ctx_t *ctx;
+ const struct intel_execution_engine2 *e;
+
+ igt_require(supports_i915_crc32(i915));
+
+ ctx = intel_ctx_create_all_physical(i915);
+ for_each_ctx_engine(i915, ctx, e) {
+ for_each_memory_region(r, i915) {
+ igt_dynamic_f("%s-%s", e->name, r->name)
+ test_crc32(i915, ctx, e, &r->ci);
+ }
+ }
+ }
+
igt_fixture {
buf_ops_destroy(bops);
close(i915);
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add crc32 calculation on dg2 gpu (rev5)
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
` (3 preceding siblings ...)
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test " Zbigniew Kempczyński
@ 2022-06-07 6:14 ` Patchwork
2022-06-07 7:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2022-06-07 14:58 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
6 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-06-07 6:14 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 3103 bytes --]
== Series Details ==
Series: Add crc32 calculation on dg2 gpu (rev5)
URL : https://patchwork.freedesktop.org/series/104657/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11729 -> IGTPW_7240
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
Participating hosts (41 -> 40)
------------------------------
Additional (1): fi-kbl-soraka
Missing (2): bat-dg2-9 fi-bdw-samus
Known issues
------------
Here are the changes found in IGTPW_7240 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][3] ([i915#1886])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +7 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6509 -> IGTPW_7240
CI-20190529: 20190529
CI_DRM_11729: fb41937d097981b11a2856d507c2f1b9064bef76 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7240: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
IGT_6509: 24bad3ce51c57c907307f84aa9202d04b80ad2a3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@api_intel_bb@crc32
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
[-- Attachment #2: Type: text/html, Size: 4094 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add crc32 calculation on dg2 gpu (rev5)
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
` (4 preceding siblings ...)
2022-06-07 6:14 ` [igt-dev] ✓ Fi.CI.BAT: success for Add crc32 calculation on dg2 gpu (rev5) Patchwork
@ 2022-06-07 7:22 ` Patchwork
2022-06-07 8:34 ` Zbigniew Kempczyński
2022-06-07 14:58 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
6 siblings, 1 reply; 24+ messages in thread
From: Patchwork @ 2022-06-07 7:22 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 53346 bytes --]
== Series Details ==
Series: Add crc32 calculation on dg2 gpu (rev5)
URL : https://patchwork.freedesktop.org/series/104657/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11729_full -> IGTPW_7240_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_7240_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_7240_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
Participating hosts (13 -> 10)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7240_full:
### IGT changes ###
#### Possible regressions ####
* {igt@api_intel_bb@crc32} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@api_intel_bb@crc32.html
- shard-iclb: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@api_intel_bb@crc32.html
- {shard-rkl}: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-2/igt@api_intel_bb@crc32.html
- {shard-dg1}: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-dg1-15/igt@api_intel_bb@crc32.html
- {shard-tglu}: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglu-6/igt@api_intel_bb@crc32.html
* igt@i915_pm_rpm@fences-dpms:
- shard-iclb: [PASS][6] -> [INCOMPLETE][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb8/igt@i915_pm_rpm@fences-dpms.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@i915_pm_rpm@fences-dpms.html
New tests
---------
New tests have been introduced between CI_DRM_11729_full and IGTPW_7240_full:
### New IGT tests (1) ###
* igt@api_intel_bb@crc32:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_7240_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ccs@suspend-resume:
- shard-iclb: NOTRUN -> [SKIP][8] ([i915#5327])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb5/igt@gem_ccs@suspend-resume.html
- shard-tglb: NOTRUN -> [SKIP][9] ([i915#5325])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_ccs@suspend-resume.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][10] ([i915#180]) +5 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#1099])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb6/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][12] ([i915#3354])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb7/igt@gem_eio@unwedge-stress.html
- shard-tglb: NOTRUN -> [FAIL][13] ([i915#5784])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][14] -> [SKIP][15] ([i915#4525])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-snb: [PASS][25] -> [SKIP][26] ([fdo#109271])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-snb4/igt@gem_exec_flush@basic-wb-rw-before-default.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb6/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_lmem_swapping@basic:
- shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#4613])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl8/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#4613]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-tglb: NOTRUN -> [SKIP][29] ([i915#4613])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@gem_lmem_swapping@verify-random.html
- shard-glk: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#4613])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@gem_lmem_swapping@verify-random.html
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#4613])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@gem_lmem_swapping@verify-random.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][32] ([i915#3318])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@gem_userptr_blits@vma-merge.html
- shard-kbl: NOTRUN -> [FAIL][33] ([i915#3318])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_mixed_blits:
- shard-tglb: NOTRUN -> [SKIP][34] ([fdo#109289])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@gen3_render_mixed_blits.html
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109289])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@gen3_render_mixed_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][36] -> [DMESG-WARN][37] ([i915#5566] / [i915#716])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk8/igt@gen9_exec_parse@allowed-single.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][38] -> [SKIP][39] ([i915#4281])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271]) +218 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#5286]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
- shard-iclb: NOTRUN -> [SKIP][44] ([i915#5286]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111614])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#110725] / [fdo#111614])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#110723])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#2705])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][49] ([i915#2705])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#6095]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3886]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk9/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278] / [i915#3886]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3886]) +9 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#3886]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl2/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#3689]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-mode-timings:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#109284] / [fdo#111827]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_chamelium@dp-mode-timings.html
- shard-glk: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk6/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +9 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +6 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_color_chamelium@pipe-c-degamma.html
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb2/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#3116])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#3116] / [i915#3299])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][64] ([i915#1319])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3359]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-32x10-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271]) +106 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#109274] / [fdo#111825]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109274] / [fdo#109278]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#5287])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled.html
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#5287])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109274]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [PASS][72] -> [FAIL][73] ([i915#79])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl6/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl1/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
- shard-glk: [PASS][74] -> [FAIL][75] ([i915#2122])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk4/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk6/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109280]) +7 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#109280] / [fdo#111825]) +7 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#1839])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#1839])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#533]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [PASS][83] -> [DMESG-WARN][84] ([i915#180]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][85] ([i915#265])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][86] ([fdo#108145] / [i915#265])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][88] ([i915#3536])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-none.html
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#3536])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-4:
- shard-glk: NOTRUN -> [SKIP][90] ([fdo#109271]) +44 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk7/igt@kms_plane_multiple@atomic-pipe-b-tiling-4.html
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278]) +14 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@kms_plane_multiple@atomic-pipe-b-tiling-4.html
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#5288])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_plane_multiple@atomic-pipe-b-tiling-4.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#111615]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][94] ([fdo#109271]) +90 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb6/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-tglb: NOTRUN -> [SKIP][95] ([i915#2920])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-glk: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#658])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#658])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#658])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl4/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#658]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][100] -> [SKIP][101] ([fdo#109441]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109441])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
- shard-tglb: NOTRUN -> [FAIL][103] ([i915#132] / [i915#3467])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#3555])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_setmode@invalid-clone-single-crtc.html
- shard-tglb: NOTRUN -> [SKIP][105] ([i915#3555])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb6/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2437])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-tglb: NOTRUN -> [SKIP][107] ([i915#2530])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
- shard-iclb: NOTRUN -> [SKIP][108] ([i915#2530])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb6/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109291]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb7/igt@prime_nv_api@nv_self_import_to_different_fd.html
* igt@prime_nv_test@i915_blt_fill_nv_read:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#109291]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@prime_nv_test@i915_blt_fill_nv_read.html
* igt@sysfs_clients@busy:
- shard-apl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@sysfs_clients@busy.html
* igt@sysfs_clients@sema-10:
- shard-glk: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk6/igt@sysfs_clients@sema-10.html
- shard-iclb: NOTRUN -> [SKIP][113] ([i915#2994])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@sysfs_clients@sema-10.html
- shard-kbl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#2994]) +4 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@sysfs_clients@sema-10.html
- shard-tglb: NOTRUN -> [SKIP][115] ([i915#2994])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][118] ([i915#2842]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-snb: [SKIP][120] ([fdo#109271]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-snb6/igt@gem_exec_flush@basic-wb-pro-default.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb5/igt@gem_exec_flush@basic-wb-pro-default.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][122] ([i915#2190]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-single:
- shard-kbl: [DMESG-WARN][124] ([i915#5566] / [i915#716]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@gen9_exec_parse@allowed-single.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][126] ([i915#454]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-dg1}: [SKIP][128] ([i915#1397]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-dg1-18/igt@i915_pm_rpm@dpms-lpsp.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-dg1-12/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}: [SKIP][130] ([i915#1397]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rps@min-max-config-idle:
- {shard-rkl}: [FAIL][132] ([i915#4016]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-6/igt@i915_pm_rps@min-max-config-idle.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-5/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [DMESG-WARN][134] ([i915#180]) -> [PASS][135] +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@i915_suspend@debugfs-reader.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- {shard-rkl}: [SKIP][136] ([i915#1845] / [i915#4098]) -> [PASS][137] +9 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen:
- {shard-rkl}: [SKIP][138] ([fdo#112022] / [i915#4070]) -> [PASS][139] +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-5/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- {shard-rkl}: [SKIP][140] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
- shard-glk: [DMESG-WARN][142] ([i915#118] / [i915#1888]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][144] ([i915#2346] / [i915#533]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
- {shard-rkl}: [SKIP][146] ([fdo#111825] / [i915#4070]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-2/igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-glk: [FAIL][148] ([i915#1888] / [i915#5160]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- {shard-rkl}: [SKIP][150] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: [FAIL][152] ([i915#2546]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- {shard-rkl}: [SKIP][154] ([i915#1849] / [i915#4098]) -> [PASS][155] +6 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- shard-glk: [FAIL][156] ([i915#1888]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_psr@cursor_mmap_gtt:
- {shard-rkl}: [SKIP][158] ([i915#1072]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_psr@cursor_mmap_gtt.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_psr@cursor_mmap_gtt.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][160] ([fdo#109441]) -> [PASS][161] +1 similar issue
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
- {shard-rkl}: [SKIP][162] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-2/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
* igt@kms_vblank@pipe-b-wait-idle:
- {shard-dg1}: [SKIP][164] ([i915#2575]) -> [PASS][165] +35 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-dg1-17/igt@kms_vblank@pipe-b-wait-idle.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-dg1-13/igt@kms_vblank@pipe-b-wait-idle.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][166] ([i915#4525]) -> [FAIL][167] ([i915#6117])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][168] ([i915#2920]) -> [SKIP][169] ([fdo#111068] / [i915#658])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][170] ([i915#658]) -> [SKIP][171] ([i915#2920])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [SKIP][172] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][173] ([i915#5939])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb4/igt@kms_psr2_su@page_flip-nv12.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl7/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl3/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl8/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl1/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl6/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl6/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl1/igt@runner@aborted.html
- shard-kbl: ([FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#716]) -> ([FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl1/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl6/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl6/igt@runner@aborted.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl7/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl6/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl3/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3354]: https://gitlab.freedesktop.org/drm/intel/issues/3354
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3963]: https://gitlab.freedesktop.org/drm/intel/issues/3963
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
[i915#5160]: https://gitlab.freedesktop.org/drm/intel/issues/5160
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6139]: https://gitlab.freedesktop.org/drm/intel/issues/6139
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6509 -> IGTPW_7240
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_11729: fb41937d097981b11a2856d507c2f1b9064bef76 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7240: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
IGT_6509: 24bad3ce51c57c907307f84aa9202d04b80ad2a3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
[-- Attachment #2: Type: text/html, Size: 59241 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Add crc32 calculation on dg2 gpu (rev5)
2022-06-07 7:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-06-07 8:34 ` Zbigniew Kempczyński
2022-06-07 15:25 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 8:34 UTC (permalink / raw)
To: igt-dev; +Cc: Vudum, Lakshminarayana
On Tue, Jun 07, 2022 at 07:22:02AM +0000, Patchwork wrote:
> Patch Details
>
> Series: Add crc32 calculation on dg2 gpu (rev5)
> URL: https://patchwork.freedesktop.org/series/104657/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
>
> CI Bug Log - changes from CI_DRM_11729_full -> IGTPW_7240_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_7240_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_7240_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
>
> Participating hosts (13 -> 10)
>
> Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> IGTPW_7240_full:
>
> IGT changes
>
> Possible regressions
>
> * {igt@api_intel_bb@crc32} (NEW):
>
> * shard-tglb: NOTRUN -> SKIP
>
> * shard-iclb: NOTRUN -> SKIP
>
> * {shard-rkl}: NOTRUN -> SKIP
>
> * {shard-dg1}: NOTRUN -> SKIP
>
> * {shard-tglu}: NOTRUN -> SKIP
>
> * igt@i915_pm_rpm@fences-dpms:
>
> * shard-iclb: PASS -> INCOMPLETE
>
> New tests
>
> New tests have been introduced between CI_DRM_11729_full and
> IGTPW_7240_full:
>
> New IGT tests (1)
>
> * igt@api_intel_bb@crc32:
> * Statuses : 8 skip(s)
> * Exec time: [0.0] s
Test is correct for dg2, so skips for other gens are expected.
--
Zbigniew
>
> Known issues
>
> Here are the changes found in IGTPW_7240_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@gem_ccs@suspend-resume:
>
> * shard-iclb: NOTRUN -> SKIP (i915#5327)
>
> * shard-tglb: NOTRUN -> SKIP (i915#5325)
>
> * igt@gem_ctx_isolation@preservation-s3@vecs0:
>
> * shard-kbl: NOTRUN -> DMESG-WARN (i915#180) +5 similar issues
> * igt@gem_ctx_persistence@engines-hang:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / i915#1099)
> * igt@gem_eio@unwedge-stress:
>
> * shard-snb: NOTRUN -> FAIL (i915#3354)
>
> * shard-tglb: NOTRUN -> FAIL (i915#5784)
>
> * igt@gem_exec_balancer@parallel-out-fence:
>
> * shard-iclb: PASS -> SKIP (i915#4525)
> * igt@gem_exec_fair@basic-flow@rcs0:
>
> * shard-tglb: PASS -> FAIL (i915#2842)
> * igt@gem_exec_fair@basic-none-rrul@rcs0:
>
> * shard-kbl: NOTRUN -> FAIL (i915#2842)
> * igt@gem_exec_fair@basic-none-share@rcs0:
>
> * shard-iclb: PASS -> FAIL (i915#2842)
> * igt@gem_exec_fair@basic-none@vcs0:
>
> * shard-glk: PASS -> FAIL (i915#2842) +1 similar issue
> * igt@gem_exec_fair@basic-pace-share@rcs0:
>
> * shard-apl: PASS -> FAIL (i915#2842)
> * igt@gem_exec_flush@basic-wb-rw-before-default:
>
> * shard-snb: PASS -> SKIP (fdo#109271)
> * igt@gem_lmem_swapping@basic:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#4613)
> * igt@gem_lmem_swapping@heavy-verify-random:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#4613) +2 similar
> issues
> * igt@gem_lmem_swapping@verify-random:
>
> * shard-tglb: NOTRUN -> SKIP (i915#4613)
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#4613)
>
> * shard-iclb: NOTRUN -> SKIP (i915#4613)
>
> * igt@gem_userptr_blits@vma-merge:
>
> * shard-apl: NOTRUN -> FAIL (i915#3318)
>
> * shard-kbl: NOTRUN -> FAIL (i915#3318)
>
> * igt@gen3_render_mixed_blits:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109289)
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109289)
>
> * igt@gen9_exec_parse@allowed-single:
>
> * shard-glk: PASS -> DMESG-WARN (i915#5566 / i915#716)
> * igt@i915_pm_dc@dc9-dpms:
>
> * shard-iclb: PASS -> SKIP (i915#4281)
> * igt@i915_pm_rpm@dpms-lpsp:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271) +218 similar issues
> * igt@i915_suspend@fence-restore-untiled:
>
> * shard-kbl: PASS -> DMESG-WARN (i915#180) +3 similar issues
> * igt@kms_big_fb@4-tiled-8bpp-rotate-0:
>
> * shard-tglb: NOTRUN -> SKIP (i915#5286) +1 similar issue
>
> * shard-iclb: NOTRUN -> SKIP (i915#5286) +1 similar issue
>
> * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#111614)
>
> * shard-iclb: NOTRUN -> SKIP (fdo#110725 / fdo#111614)
>
> * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#110723)
> * igt@kms_big_joiner@basic:
>
> * shard-tglb: NOTRUN -> SKIP (i915#2705)
>
> * shard-iclb: NOTRUN -> SKIP (i915#2705)
>
> * igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_mc_ccs:
>
> * shard-tglb: NOTRUN -> SKIP (i915#6095) +2 similar issues
> * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#3886) +2 similar
> issues
> * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109278 / i915#3886) +2 similar
> issues
> * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#3886) +9 similar
> issues
> * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#3886) +4 similar
> issues
> * igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
>
> * shard-tglb: NOTRUN -> SKIP (i915#3689) +1 similar issue
> * igt@kms_chamelium@dp-mode-timings:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109284 / fdo#111827) +2 similar
> issues
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +2 similar
> issues
>
> * igt@kms_color_chamelium@pipe-a-degamma:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +9 similar
> issues
> * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +6 similar
> issues
> * igt@kms_color_chamelium@pipe-c-degamma:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109284 / fdo#111827) +2 similar
> issues
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +2 similar
> issues
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
>
> * shard-iclb: NOTRUN -> SKIP (i915#3116)
>
> * shard-tglb: NOTRUN -> SKIP (i915#3116 / i915#3299)
>
> * igt@kms_content_protection@legacy:
>
> * shard-kbl: NOTRUN -> TIMEOUT (i915#1319)
> * igt@kms_cursor_crc@pipe-d-cursor-32x10-rapid-movement:
>
> * shard-tglb: NOTRUN -> SKIP (i915#3359) +3 similar issues
> * igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271) +106 similar issues
> * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109274 / fdo#111825) +3 similar
> issues
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109274 / fdo#109278) +1 similar
> issue
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled:
>
> * shard-tglb: NOTRUN -> SKIP (i915#5287)
>
> * shard-iclb: NOTRUN -> SKIP (i915#5287)
>
> * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109274) +1 similar issue
> * igt@kms_flip@flip-vs-expired-vblank@c-dp1:
>
> * shard-apl: PASS -> FAIL (i915#79)
> * igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
>
> * shard-glk: PASS -> FAIL (i915#2122)
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109280) +7 similar issues
> * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109280 / fdo#111825) +7 similar
> issues
> * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
>
> * shard-tglb: NOTRUN -> SKIP (i915#1839)
>
> * shard-iclb: NOTRUN -> SKIP (i915#1839)
>
> * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#533) +1 similar
> issue
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#533)
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#533)
>
> * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
>
> * shard-apl: PASS -> DMESG-WARN (i915#180) +2 similar issues
> * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
>
> * shard-kbl: NOTRUN -> FAIL (i915#265)
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
>
> * shard-glk: NOTRUN -> FAIL (fdo#108145 / i915#265)
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
>
> * shard-kbl: NOTRUN -> FAIL (fdo#108145 / i915#265)
> * igt@kms_plane_lowres@pipe-b-tiling-none:
>
> * shard-tglb: NOTRUN -> SKIP (i915#3536)
>
> * shard-iclb: NOTRUN -> SKIP (i915#3536)
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-4:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271) +44 similar issues
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109278) +14 similar issues
>
> * shard-tglb: NOTRUN -> SKIP (i915#5288)
>
> * igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#111615) +1 similar issue
> * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271) +90 similar issues
> * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
>
> * shard-tglb: NOTRUN -> SKIP (i915#2920)
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#658)
>
> * shard-iclb: NOTRUN -> SKIP (i915#658)
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#658)
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#658) +1 similar
> issue
> * igt@kms_psr@psr2_primary_mmap_gtt:
>
> * shard-iclb: PASS -> SKIP (fdo#109441) +2 similar issues
> * igt@kms_psr@psr2_sprite_mmap_gtt:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109441)
>
> * shard-tglb: NOTRUN -> FAIL (i915#132 / i915#3467)
>
> * igt@kms_setmode@invalid-clone-single-crtc:
>
> * shard-iclb: NOTRUN -> SKIP (i915#3555)
>
> * shard-tglb: NOTRUN -> SKIP (i915#3555)
>
> * igt@kms_writeback@writeback-fb-id:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#2437)
> * igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
>
> * shard-tglb: NOTRUN -> SKIP (i915#2530)
>
> * shard-iclb: NOTRUN -> SKIP (i915#2530)
>
> * igt@prime_nv_api@nv_self_import_to_different_fd:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109291) +1 similar issue
> * igt@prime_nv_test@i915_blt_fill_nv_read:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109291) +1 similar issue
> * igt@sysfs_clients@busy:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#2994) +2 similar
> issues
> * igt@sysfs_clients@sema-10:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#2994)
>
> * shard-iclb: NOTRUN -> SKIP (i915#2994)
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#2994) +4 similar
> issues
>
> * shard-tglb: NOTRUN -> SKIP (i915#2994)
>
> Possible fixes
>
> * igt@gem_ctx_isolation@preservation-s3@vecs0:
>
> * shard-apl: DMESG-WARN (i915#180) -> PASS +2 similar issues
> * igt@gem_exec_fair@basic-none-share@rcs0:
>
> * shard-tglb: FAIL (i915#2842) -> PASS
> * igt@gem_exec_flush@basic-wb-pro-default:
>
> * shard-snb: SKIP (fdo#109271) -> PASS +1 similar issue
> * igt@gem_huc_copy@huc-copy:
>
> * shard-tglb: SKIP (i915#2190) -> PASS
> * igt@gen9_exec_parse@allowed-single:
>
> * shard-kbl: DMESG-WARN (i915#5566 / i915#716) -> PASS
> * igt@i915_pm_dc@dc6-psr:
>
> * shard-iclb: FAIL (i915#454) -> PASS
> * igt@i915_pm_rpm@dpms-lpsp:
>
> * {shard-dg1}: SKIP (i915#1397) -> PASS
> * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
>
> * {shard-rkl}: SKIP (i915#1397) -> PASS
> * igt@i915_pm_rps@min-max-config-idle:
>
> * {shard-rkl}: FAIL (i915#4016) -> PASS
> * igt@i915_suspend@debugfs-reader:
>
> * shard-kbl: DMESG-WARN (i915#180) -> PASS +1 similar issue
> * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
>
> * {shard-rkl}: SKIP (i915#1845 / i915#4098) -> PASS +9 similar
> issues
> * igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen:
>
> * {shard-rkl}: SKIP (fdo#112022 / i915#4070) -> PASS +1 similar
> issue
> * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
>
> * {shard-rkl}: SKIP (i915#1849 / i915#4070 / i915#4098) -> PASS +1
> similar issue
> * igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
>
> * shard-glk: DMESG-WARN (i915#118 / i915#1888) -> PASS
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-glk: FAIL (i915#2346 / i915#533) -> PASS
> * igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
>
> * {shard-rkl}: SKIP (fdo#111825 / i915#4070) -> PASS
> * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
>
> * shard-glk: FAIL (i915#1888 / i915#5160) -> PASS
> * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
>
> * {shard-rkl}: SKIP (fdo#111314 / i915#4098 / i915#4369) -> PASS
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
>
> * shard-glk: FAIL (i915#2546) -> PASS
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
>
> * {shard-rkl}: SKIP (i915#1849 / i915#4098) -> PASS +6 similar
> issues
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
>
> * shard-glk: FAIL (i915#1888) -> PASS
> * igt@kms_psr@cursor_mmap_gtt:
>
> * {shard-rkl}: SKIP (i915#1072) -> PASS
> * igt@kms_psr@psr2_no_drrs:
>
> * shard-iclb: SKIP (fdo#109441) -> PASS +1 similar issue
> * igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
>
> * {shard-rkl}: SKIP (i915#1845 / i915#4070 / i915#4098) -> PASS
> * igt@kms_vblank@pipe-b-wait-idle:
>
> * {shard-dg1}: SKIP (i915#2575) -> PASS +35 similar issues
>
> Warnings
>
> * igt@gem_exec_balancer@parallel-ordering:
>
> * shard-iclb: SKIP (i915#4525) -> FAIL (i915#6117)
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
>
> * shard-iclb: SKIP (i915#2920) -> SKIP (fdo#111068 / i915#658)
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
>
> * shard-iclb: SKIP (i915#658) -> SKIP (i915#2920)
> * igt@kms_psr2_su@page_flip-nv12:
>
> * shard-iclb: SKIP (fdo#109642 / fdo#111068 / i915#658) -> FAIL
> (i915#5939)
> * igt@runner@aborted:
>
> * shard-apl: (FAIL, FAIL, FAIL, FAIL) (i915#180 / i915#3002 /
> i915#4312 / i915#5257) -> (FAIL, FAIL, FAIL, FAIL, FAIL)
> (fdo#109271 / i915#180 / i915#3002 / i915#4312 / i915#5257)
>
> * shard-kbl: (FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL,
> FAIL) (fdo#109271 / i915#180 / i915#3002 / i915#4312 / i915#5257
> / i915#716) -> (FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL,
> FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL) (i915#180 / i915#3002 /
> i915#4312 / i915#5257)
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_6509 -> IGTPW_7240
> * Piglit: piglit_4509 -> None
>
> CI-20190529: 20190529
> CI_DRM_11729: fb41937d097981b11a2856d507c2f1b9064bef76 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_7240: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
> IGT_6509: 24bad3ce51c57c907307f84aa9202d04b80ad2a3 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
^ permalink raw reply [flat|nested] 24+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Add crc32 calculation on dg2 gpu (rev5)
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
` (5 preceding siblings ...)
2022-06-07 7:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-06-07 14:58 ` Patchwork
6 siblings, 0 replies; 24+ messages in thread
From: Patchwork @ 2022-06-07 14:58 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 53127 bytes --]
== Series Details ==
Series: Add crc32 calculation on dg2 gpu (rev5)
URL : https://patchwork.freedesktop.org/series/104657/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11729_full -> IGTPW_7240_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
Participating hosts (13 -> 10)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7240_full:
### IGT changes ###
#### Possible regressions ####
* {igt@api_intel_bb@crc32} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@api_intel_bb@crc32.html
- shard-iclb: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@api_intel_bb@crc32.html
- {shard-rkl}: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-2/igt@api_intel_bb@crc32.html
- {shard-dg1}: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-dg1-15/igt@api_intel_bb@crc32.html
- {shard-tglu}: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglu-6/igt@api_intel_bb@crc32.html
New tests
---------
New tests have been introduced between CI_DRM_11729_full and IGTPW_7240_full:
### New IGT tests (1) ###
* igt@api_intel_bb@crc32:
- Statuses : 8 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_7240_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ccs@suspend-resume:
- shard-iclb: NOTRUN -> [SKIP][6] ([i915#5327])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb5/igt@gem_ccs@suspend-resume.html
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#5325])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_ccs@suspend-resume.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][8] ([i915#180]) +5 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb6/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][10] ([i915#3354])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb7/igt@gem_eio@unwedge-stress.html
- shard-tglb: NOTRUN -> [FAIL][11] ([i915#5784])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][12] -> [SKIP][13] ([i915#4525])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-kbl: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-snb: [PASS][23] -> [SKIP][24] ([fdo#109271])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-snb4/igt@gem_exec_flush@basic-wb-rw-before-default.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb6/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_lmem_swapping@basic:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#4613])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl8/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#4613]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#4613])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@gem_lmem_swapping@verify-random.html
- shard-glk: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#4613])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@gem_lmem_swapping@verify-random.html
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#4613])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@gem_lmem_swapping@verify-random.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][30] ([i915#3318])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@gem_userptr_blits@vma-merge.html
- shard-kbl: NOTRUN -> [FAIL][31] ([i915#3318])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_mixed_blits:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109289])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@gen3_render_mixed_blits.html
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109289])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@gen3_render_mixed_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][34] -> [DMESG-WARN][35] ([i915#5566] / [i915#716])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk8/igt@gen9_exec_parse@allowed-single.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk1/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][36] -> [SKIP][37] ([i915#4281])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271]) +218 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@fences-dpms:
- shard-iclb: [PASS][39] -> [INCOMPLETE][40] ([i915#5712])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb8/igt@i915_pm_rpm@fences-dpms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@i915_pm_rpm@fences-dpms.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][41] -> [DMESG-WARN][42] ([i915#180]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#5286]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
- shard-iclb: NOTRUN -> [SKIP][44] ([i915#5286]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][45] ([fdo#111614])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#110725] / [fdo#111614])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#110723])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#2705])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_big_joiner@basic.html
- shard-iclb: NOTRUN -> [SKIP][49] ([i915#2705])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#6095]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3886]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk9/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109278] / [i915#3886]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3886]) +9 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#3886]) +4 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl2/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][55] ([i915#3689]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-mode-timings:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#109284] / [fdo#111827]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_chamelium@dp-mode-timings.html
- shard-glk: NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk6/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_color_chamelium@pipe-a-degamma:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +9 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@kms_color_chamelium@pipe-a-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +6 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_color_chamelium@pipe-c-degamma.html
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb2/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#3116])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#3116] / [i915#3299])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][64] ([i915#1319])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3359]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-32x10-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271]) +106 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#109274] / [fdo#111825]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109274] / [fdo#109278]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#5287])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled.html
- shard-iclb: NOTRUN -> [SKIP][70] ([i915#5287])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109274]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-apl: [PASS][72] -> [FAIL][73] ([i915#79])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl6/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl1/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
- shard-glk: [PASS][74] -> [FAIL][75] ([i915#2122])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk4/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk6/igt@kms_flip@plain-flip-ts-check@a-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109280]) +7 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#109280] / [fdo#111825]) +7 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglb: NOTRUN -> [SKIP][78] ([i915#1839])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#1839])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#533]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-glk: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [PASS][83] -> [DMESG-WARN][84] ([i915#180]) +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][85] ([i915#265])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][86] ([fdo#108145] / [i915#265])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][87] ([fdo#108145] / [i915#265])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][88] ([i915#3536])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-none.html
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#3536])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-4:
- shard-glk: NOTRUN -> [SKIP][90] ([fdo#109271]) +44 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk7/igt@kms_plane_multiple@atomic-pipe-b-tiling-4.html
- shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109278]) +14 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@kms_plane_multiple@atomic-pipe-b-tiling-4.html
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#5288])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_plane_multiple@atomic-pipe-b-tiling-4.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][93] ([fdo#111615]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][94] ([fdo#109271]) +90 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb6/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-tglb: NOTRUN -> [SKIP][95] ([i915#2920])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-glk: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#658])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#658])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#658])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl4/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#658]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][100] -> [SKIP][101] ([fdo#109441]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109441])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
- shard-tglb: NOTRUN -> [FAIL][103] ([i915#132] / [i915#3467])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_setmode@invalid-clone-single-crtc:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#3555])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_setmode@invalid-clone-single-crtc.html
- shard-tglb: NOTRUN -> [SKIP][105] ([i915#3555])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb6/igt@kms_setmode@invalid-clone-single-crtc.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2437])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-tglb: NOTRUN -> [SKIP][107] ([i915#2530])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
- shard-iclb: NOTRUN -> [SKIP][108] ([i915#2530])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb6/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109291]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb7/igt@prime_nv_api@nv_self_import_to_different_fd.html
* igt@prime_nv_test@i915_blt_fill_nv_read:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#109291]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@prime_nv_test@i915_blt_fill_nv_read.html
* igt@sysfs_clients@busy:
- shard-apl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#2994]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@sysfs_clients@busy.html
* igt@sysfs_clients@sema-10:
- shard-glk: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk6/igt@sysfs_clients@sema-10.html
- shard-iclb: NOTRUN -> [SKIP][113] ([i915#2994])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@sysfs_clients@sema-10.html
- shard-kbl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#2994]) +4 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@sysfs_clients@sema-10.html
- shard-tglb: NOTRUN -> [SKIP][115] ([i915#2994])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb3/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl8/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl7/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [FAIL][118] ([i915#2842]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_flush@basic-wb-pro-default:
- shard-snb: [SKIP][120] ([fdo#109271]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-snb6/igt@gem_exec_flush@basic-wb-pro-default.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-snb5/igt@gem_exec_flush@basic-wb-pro-default.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][122] ([i915#2190]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-tglb6/igt@gem_huc_copy@huc-copy.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-single:
- shard-kbl: [DMESG-WARN][124] ([i915#5566] / [i915#716]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@gen9_exec_parse@allowed-single.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][126] ([i915#454]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@dpms-lpsp:
- {shard-dg1}: [SKIP][128] ([i915#1397]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-dg1-18/igt@i915_pm_rpm@dpms-lpsp.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-dg1-12/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- {shard-rkl}: [SKIP][130] ([i915#1397]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rps@min-max-config-idle:
- {shard-rkl}: [FAIL][132] ([i915#4016]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-6/igt@i915_pm_rps@min-max-config-idle.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-5/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [DMESG-WARN][134] ([i915#180]) -> [PASS][135] +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@i915_suspend@debugfs-reader.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@i915_suspend@debugfs-reader.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- {shard-rkl}: [SKIP][136] ([i915#1845] / [i915#4098]) -> [PASS][137] +9 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen:
- {shard-rkl}: [SKIP][138] ([fdo#112022] / [i915#4070]) -> [PASS][139] +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-5/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
- {shard-rkl}: [SKIP][140] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
- shard-glk: [DMESG-WARN][142] ([i915#118] / [i915#1888]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk5/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][144] ([i915#2346] / [i915#533]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
- {shard-rkl}: [SKIP][146] ([fdo#111825] / [i915#4070]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-2/igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-glk: [FAIL][148] ([i915#1888] / [i915#5160]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
- {shard-rkl}: [SKIP][150] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: [FAIL][152] ([i915#2546]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- {shard-rkl}: [SKIP][154] ([i915#1849] / [i915#4098]) -> [PASS][155] +6 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- shard-glk: [FAIL][156] ([i915#1888]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-glk9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-glk4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_psr@cursor_mmap_gtt:
- {shard-rkl}: [SKIP][158] ([i915#1072]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-1/igt@kms_psr@cursor_mmap_gtt.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_psr@cursor_mmap_gtt.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][160] ([fdo#109441]) -> [PASS][161] +1 similar issue
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb7/igt@kms_psr@psr2_no_drrs.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
- {shard-rkl}: [SKIP][162] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-rkl-2/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-rkl-6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
* igt@kms_vblank@pipe-b-wait-idle:
- {shard-dg1}: [SKIP][164] ([i915#2575]) -> [PASS][165] +35 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-dg1-17/igt@kms_vblank@pipe-b-wait-idle.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-dg1-13/igt@kms_vblank@pipe-b-wait-idle.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][166] ([i915#4525]) -> [FAIL][167] ([i915#6117])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][168] ([i915#2920]) -> [SKIP][169] ([fdo#111068] / [i915#658])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][170] ([i915#658]) -> [SKIP][171] ([i915#2920])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [SKIP][172] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][173] ([i915#5939])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-iclb4/igt@kms_psr2_su@page_flip-nv12.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl7/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl3/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl8/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-apl1/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl6/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl6/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl3/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-apl1/igt@runner@aborted.html
- shard-kbl: ([FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#716]) -> ([FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196], [FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl1/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl6/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl6/igt@runner@aborted.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl4/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl7/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11729/shard-kbl6/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl1/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl6/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl3/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/shard-kbl4/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3354]: https://gitlab.freedesktop.org/drm/intel/issues/3354
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3963]: https://gitlab.freedesktop.org/drm/intel/issues/3963
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
[i915#5160]: https://gitlab.freedesktop.org/drm/intel/issues/5160
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5712]: https://gitlab.freedesktop.org/drm/intel/issues/5712
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6139]: https://gitlab.freedesktop.org/drm/intel/issues/6139
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6509 -> IGTPW_7240
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_11729: fb41937d097981b11a2856d507c2f1b9064bef76 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7240: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
IGT_6509: 24bad3ce51c57c907307f84aa9202d04b80ad2a3 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
[-- Attachment #2: Type: text/html, Size: 58995 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] ✗ Fi.CI.IGT: failure for Add crc32 calculation on dg2 gpu (rev5)
2022-06-07 8:34 ` Zbigniew Kempczyński
@ 2022-06-07 15:25 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 24+ messages in thread
From: Vudum, Lakshminarayana @ 2022-06-07 15:25 UTC (permalink / raw)
To: Kempczynski, Zbigniew, igt-dev
igt@api_intel_bb@crc32 is not yet in CI bug log. Otherwise, incomplete from igt@i915_pm_rpm@fences-dpms is related to https://gitlab.freedesktop.org/drm/intel/-/issues/5712.
Lakshmi.
-----Original Message-----
From: Kempczynski, Zbigniew <zbigniew.kempczynski@intel.com>
Sent: Tuesday, June 7, 2022 1:35 AM
To: igt-dev@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for Add crc32 calculation on dg2 gpu (rev5)
On Tue, Jun 07, 2022 at 07:22:02AM +0000, Patchwork wrote:
> Patch Details
>
> Series: Add crc32 calculation on dg2 gpu (rev5)
> URL: https://patchwork.freedesktop.org/series/104657/
> State: failure
> Details: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
>
> CI Bug Log - changes from CI_DRM_11729_full -> IGTPW_7240_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with IGTPW_7240_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_7240_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in
> CI.
>
> External URL:
> https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
>
> Participating hosts (13 -> 10)
>
> Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> IGTPW_7240_full:
>
> IGT changes
>
> Possible regressions
>
> * {igt@api_intel_bb@crc32} (NEW):
>
> * shard-tglb: NOTRUN -> SKIP
>
> * shard-iclb: NOTRUN -> SKIP
>
> * {shard-rkl}: NOTRUN -> SKIP
>
> * {shard-dg1}: NOTRUN -> SKIP
>
> * {shard-tglu}: NOTRUN -> SKIP
>
> * igt@i915_pm_rpm@fences-dpms:
>
> * shard-iclb: PASS -> INCOMPLETE
>
> New tests
>
> New tests have been introduced between CI_DRM_11729_full and
> IGTPW_7240_full:
>
> New IGT tests (1)
>
> * igt@api_intel_bb@crc32:
> * Statuses : 8 skip(s)
> * Exec time: [0.0] s
Test is correct for dg2, so skips for other gens are expected.
--
Zbigniew
>
> Known issues
>
> Here are the changes found in IGTPW_7240_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> * igt@gem_ccs@suspend-resume:
>
> * shard-iclb: NOTRUN -> SKIP (i915#5327)
>
> * shard-tglb: NOTRUN -> SKIP (i915#5325)
>
> * igt@gem_ctx_isolation@preservation-s3@vecs0:
>
> * shard-kbl: NOTRUN -> DMESG-WARN (i915#180) +5 similar issues
> * igt@gem_ctx_persistence@engines-hang:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / i915#1099)
> * igt@gem_eio@unwedge-stress:
>
> * shard-snb: NOTRUN -> FAIL (i915#3354)
>
> * shard-tglb: NOTRUN -> FAIL (i915#5784)
>
> * igt@gem_exec_balancer@parallel-out-fence:
>
> * shard-iclb: PASS -> SKIP (i915#4525)
> * igt@gem_exec_fair@basic-flow@rcs0:
>
> * shard-tglb: PASS -> FAIL (i915#2842)
> * igt@gem_exec_fair@basic-none-rrul@rcs0:
>
> * shard-kbl: NOTRUN -> FAIL (i915#2842)
> * igt@gem_exec_fair@basic-none-share@rcs0:
>
> * shard-iclb: PASS -> FAIL (i915#2842)
> * igt@gem_exec_fair@basic-none@vcs0:
>
> * shard-glk: PASS -> FAIL (i915#2842) +1 similar issue
> * igt@gem_exec_fair@basic-pace-share@rcs0:
>
> * shard-apl: PASS -> FAIL (i915#2842)
> * igt@gem_exec_flush@basic-wb-rw-before-default:
>
> * shard-snb: PASS -> SKIP (fdo#109271)
> * igt@gem_lmem_swapping@basic:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#4613)
> * igt@gem_lmem_swapping@heavy-verify-random:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#4613) +2 similar
> issues
> * igt@gem_lmem_swapping@verify-random:
>
> * shard-tglb: NOTRUN -> SKIP (i915#4613)
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#4613)
>
> * shard-iclb: NOTRUN -> SKIP (i915#4613)
>
> * igt@gem_userptr_blits@vma-merge:
>
> * shard-apl: NOTRUN -> FAIL (i915#3318)
>
> * shard-kbl: NOTRUN -> FAIL (i915#3318)
>
> * igt@gen3_render_mixed_blits:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109289)
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109289)
>
> * igt@gen9_exec_parse@allowed-single:
>
> * shard-glk: PASS -> DMESG-WARN (i915#5566 / i915#716)
> * igt@i915_pm_dc@dc9-dpms:
>
> * shard-iclb: PASS -> SKIP (i915#4281)
> * igt@i915_pm_rpm@dpms-lpsp:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271) +218 similar issues
> * igt@i915_suspend@fence-restore-untiled:
>
> * shard-kbl: PASS -> DMESG-WARN (i915#180) +3 similar issues
> * igt@kms_big_fb@4-tiled-8bpp-rotate-0:
>
> * shard-tglb: NOTRUN -> SKIP (i915#5286) +1 similar issue
>
> * shard-iclb: NOTRUN -> SKIP (i915#5286) +1 similar issue
>
> * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#111614)
>
> * shard-iclb: NOTRUN -> SKIP (fdo#110725 / fdo#111614)
>
> * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#110723)
> * igt@kms_big_joiner@basic:
>
> * shard-tglb: NOTRUN -> SKIP (i915#2705)
>
> * shard-iclb: NOTRUN -> SKIP (i915#2705)
>
> * igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_dg2_mc_ccs:
>
> * shard-tglb: NOTRUN -> SKIP (i915#6095) +2 similar issues
> * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#3886) +2 similar
> issues
> * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109278 / i915#3886) +2 similar
> issues
> * igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#3886) +9 similar
> issues
> * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#3886) +4 similar
> issues
> * igt@kms_ccs@pipe-d-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
>
> * shard-tglb: NOTRUN -> SKIP (i915#3689) +1 similar issue
> * igt@kms_chamelium@dp-mode-timings:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109284 / fdo#111827) +2 similar
> issues
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +2 similar
> issues
>
> * igt@kms_color_chamelium@pipe-a-degamma:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +9 similar
> issues
> * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +6 similar
> issues
> * igt@kms_color_chamelium@pipe-c-degamma:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109284 / fdo#111827) +2 similar
> issues
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271 / fdo#111827) +2 similar
> issues
>
> * igt@kms_content_protection@dp-mst-lic-type-1:
>
> * shard-iclb: NOTRUN -> SKIP (i915#3116)
>
> * shard-tglb: NOTRUN -> SKIP (i915#3116 / i915#3299)
>
> * igt@kms_content_protection@legacy:
>
> * shard-kbl: NOTRUN -> TIMEOUT (i915#1319)
> * igt@kms_cursor_crc@pipe-d-cursor-32x10-rapid-movement:
>
> * shard-tglb: NOTRUN -> SKIP (i915#3359) +3 similar issues
> * igt@kms_cursor_crc@pipe-d-cursor-64x64-sliding:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271) +106 similar issues
> * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109274 / fdo#111825) +3 similar
> issues
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109274 / fdo#109278) +1 similar
> issue
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled:
>
> * shard-tglb: NOTRUN -> SKIP (i915#5287)
>
> * shard-iclb: NOTRUN -> SKIP (i915#5287)
>
> * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109274) +1 similar issue
> * igt@kms_flip@flip-vs-expired-vblank@c-dp1:
>
> * shard-apl: PASS -> FAIL (i915#79)
> * igt@kms_flip@plain-flip-ts-check@a-hdmi-a1:
>
> * shard-glk: PASS -> FAIL (i915#2122)
> * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109280) +7 similar issues
> * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109280 / fdo#111825) +7 similar
> issues
> * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
>
> * shard-tglb: NOTRUN -> SKIP (i915#1839)
>
> * shard-iclb: NOTRUN -> SKIP (i915#1839)
>
> * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#533) +1 similar
> issue
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#533)
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#533)
>
> * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
>
> * shard-apl: PASS -> DMESG-WARN (i915#180) +2 similar issues
> * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
>
> * shard-kbl: NOTRUN -> FAIL (i915#265)
> * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
>
> * shard-glk: NOTRUN -> FAIL (fdo#108145 / i915#265)
> * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
>
> * shard-kbl: NOTRUN -> FAIL (fdo#108145 / i915#265)
> * igt@kms_plane_lowres@pipe-b-tiling-none:
>
> * shard-tglb: NOTRUN -> SKIP (i915#3536)
>
> * shard-iclb: NOTRUN -> SKIP (i915#3536)
>
> * igt@kms_plane_multiple@atomic-pipe-b-tiling-4:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271) +44 similar issues
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109278) +14 similar issues
>
> * shard-tglb: NOTRUN -> SKIP (i915#5288)
>
> * igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#111615) +1 similar issue
> * igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
>
> * shard-snb: NOTRUN -> SKIP (fdo#109271) +90 similar issues
> * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
>
> * shard-tglb: NOTRUN -> SKIP (i915#2920)
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#658)
>
> * shard-iclb: NOTRUN -> SKIP (i915#658)
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#658)
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#658) +1 similar
> issue
> * igt@kms_psr@psr2_primary_mmap_gtt:
>
> * shard-iclb: PASS -> SKIP (fdo#109441) +2 similar issues
> * igt@kms_psr@psr2_sprite_mmap_gtt:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109441)
>
> * shard-tglb: NOTRUN -> FAIL (i915#132 / i915#3467)
>
> * igt@kms_setmode@invalid-clone-single-crtc:
>
> * shard-iclb: NOTRUN -> SKIP (i915#3555)
>
> * shard-tglb: NOTRUN -> SKIP (i915#3555)
>
> * igt@kms_writeback@writeback-fb-id:
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#2437)
> * igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
>
> * shard-tglb: NOTRUN -> SKIP (i915#2530)
>
> * shard-iclb: NOTRUN -> SKIP (i915#2530)
>
> * igt@prime_nv_api@nv_self_import_to_different_fd:
>
> * shard-iclb: NOTRUN -> SKIP (fdo#109291) +1 similar issue
> * igt@prime_nv_test@i915_blt_fill_nv_read:
>
> * shard-tglb: NOTRUN -> SKIP (fdo#109291) +1 similar issue
> * igt@sysfs_clients@busy:
>
> * shard-apl: NOTRUN -> SKIP (fdo#109271 / i915#2994) +2 similar
> issues
> * igt@sysfs_clients@sema-10:
>
> * shard-glk: NOTRUN -> SKIP (fdo#109271 / i915#2994)
>
> * shard-iclb: NOTRUN -> SKIP (i915#2994)
>
> * shard-kbl: NOTRUN -> SKIP (fdo#109271 / i915#2994) +4 similar
> issues
>
> * shard-tglb: NOTRUN -> SKIP (i915#2994)
>
> Possible fixes
>
> * igt@gem_ctx_isolation@preservation-s3@vecs0:
>
> * shard-apl: DMESG-WARN (i915#180) -> PASS +2 similar issues
> * igt@gem_exec_fair@basic-none-share@rcs0:
>
> * shard-tglb: FAIL (i915#2842) -> PASS
> * igt@gem_exec_flush@basic-wb-pro-default:
>
> * shard-snb: SKIP (fdo#109271) -> PASS +1 similar issue
> * igt@gem_huc_copy@huc-copy:
>
> * shard-tglb: SKIP (i915#2190) -> PASS
> * igt@gen9_exec_parse@allowed-single:
>
> * shard-kbl: DMESG-WARN (i915#5566 / i915#716) -> PASS
> * igt@i915_pm_dc@dc6-psr:
>
> * shard-iclb: FAIL (i915#454) -> PASS
> * igt@i915_pm_rpm@dpms-lpsp:
>
> * {shard-dg1}: SKIP (i915#1397) -> PASS
> * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
>
> * {shard-rkl}: SKIP (i915#1397) -> PASS
> * igt@i915_pm_rps@min-max-config-idle:
>
> * {shard-rkl}: FAIL (i915#4016) -> PASS
> * igt@i915_suspend@debugfs-reader:
>
> * shard-kbl: DMESG-WARN (i915#180) -> PASS +1 similar issue
> * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
>
> * {shard-rkl}: SKIP (i915#1845 / i915#4098) -> PASS +9 similar
> issues
> * igt@kms_cursor_crc@pipe-a-cursor-256x256-onscreen:
>
> * {shard-rkl}: SKIP (fdo#112022 / i915#4070) -> PASS +1 similar
> issue
> * igt@kms_cursor_edge_walk@pipe-a-256x256-bottom-edge:
>
> * {shard-rkl}: SKIP (i915#1849 / i915#4070 / i915#4098) -> PASS +1
> similar issue
> * igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
>
> * shard-glk: DMESG-WARN (i915#118 / i915#1888) -> PASS
> * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
>
> * shard-glk: FAIL (i915#2346 / i915#533) -> PASS
> * igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
>
> * {shard-rkl}: SKIP (fdo#111825 / i915#4070) -> PASS
> * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
>
> * shard-glk: FAIL (i915#1888 / i915#5160) -> PASS
> * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled:
>
> * {shard-rkl}: SKIP (fdo#111314 / i915#4098 / i915#4369) -> PASS
> * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
>
> * shard-glk: FAIL (i915#2546) -> PASS
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
>
> * {shard-rkl}: SKIP (i915#1849 / i915#4098) -> PASS +6 similar
> issues
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
>
> * shard-glk: FAIL (i915#1888) -> PASS
> * igt@kms_psr@cursor_mmap_gtt:
>
> * {shard-rkl}: SKIP (i915#1072) -> PASS
> * igt@kms_psr@psr2_no_drrs:
>
> * shard-iclb: SKIP (fdo#109441) -> PASS +1 similar issue
> * igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
>
> * {shard-rkl}: SKIP (i915#1845 / i915#4070 / i915#4098) -> PASS
> * igt@kms_vblank@pipe-b-wait-idle:
>
> * {shard-dg1}: SKIP (i915#2575) -> PASS +35 similar issues
>
> Warnings
>
> * igt@gem_exec_balancer@parallel-ordering:
>
> * shard-iclb: SKIP (i915#4525) -> FAIL (i915#6117)
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
>
> * shard-iclb: SKIP (i915#2920) -> SKIP (fdo#111068 / i915#658)
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
>
> * shard-iclb: SKIP (i915#658) -> SKIP (i915#2920)
> * igt@kms_psr2_su@page_flip-nv12:
>
> * shard-iclb: SKIP (fdo#109642 / fdo#111068 / i915#658) -> FAIL
> (i915#5939)
> * igt@runner@aborted:
>
> * shard-apl: (FAIL, FAIL, FAIL, FAIL) (i915#180 / i915#3002 /
> i915#4312 / i915#5257) -> (FAIL, FAIL, FAIL, FAIL, FAIL)
> (fdo#109271 / i915#180 / i915#3002 / i915#4312 / i915#5257)
>
> * shard-kbl: (FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL,
> FAIL) (fdo#109271 / i915#180 / i915#3002 / i915#4312 / i915#5257
> / i915#716) -> (FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL,
> FAIL, FAIL, FAIL, FAIL, FAIL, FAIL, FAIL) (i915#180 / i915#3002 /
> i915#4312 / i915#5257)
>
> {name}: This element is suppressed. This means it is ignored when
> computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> Build changes
>
> * CI: CI-20190529 -> None
> * IGT: IGT_6509 -> IGTPW_7240
> * Piglit: piglit_4509 -> None
>
> CI-20190529: 20190529
> CI_DRM_11729: fb41937d097981b11a2856d507c2f1b9064bef76 @
> git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_7240: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7240/index.html
> IGT_6509: 24bad3ce51c57c907307f84aa9202d04b80ad2a3 @
> https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @
> git://anongit.freedesktop.org/piglit
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
@ 2022-06-09 9:06 ` Petri Latvala
0 siblings, 0 replies; 24+ messages in thread
From: Petri Latvala @ 2022-06-09 9:06 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Tue, Jun 07, 2022 at 07:24:08AM +0200, Zbigniew Kempczyński wrote:
> In few tests we got some MI_* duplicates (MI_MATH for example).
> Add common definitions in intel_reg.h and remove local definitions
> in the tests.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Old values of MI_STORE_REGISTER* and MI_LOAD_REGISTER* were a wild
west...
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
> ---
> benchmarks/gem_wsim.c | 34 ++++-------------------------
> lib/intel_reg.h | 42 ++++++++++++++++++++++++++++++++++++
> tests/i915/gem_exec_fair.c | 27 -----------------------
> tests/i915/gem_exec_fence.c | 31 --------------------------
> tests/i915/gem_watchdog.c | 27 -----------------------
> tests/i915/gem_workarounds.c | 7 +++---
> tests/i915/gen7_exec_parse.c | 8 +++----
> tests/i915/gen9_exec_parse.c | 11 ++++------
> 8 files changed, 57 insertions(+), 130 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index d14352225e..aadd2737cd 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -279,36 +279,7 @@ static uint64_t ns_to_ctx_ticks(uint64_t ns)
> return div64_u64_round_up(ns * f, NSEC_PER_SEC);
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -#define MI_ARB_CHECK MI_INSTR(0x5, 0)
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> -#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
> -#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 0)
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> #define MI_CS_MMIO_DST BIT(19)
> #define MI_CS_MMIO_SRC BIT(18)
>
> @@ -1487,7 +1458,10 @@ static unsigned int create_bb(struct w_step *w, int self)
> *cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
>
> /* Save delta for indirect read by COND_BBE */
> - *cs++ = MI_STORE_REGISTER_MEM | (1 + use_64b) | MI_CS_MMIO_DST;
> + if (use_64b)
> + *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_CS_MMIO_DST;
> + else
> + *cs++ = MI_STORE_REGISTER_MEM | MI_CS_MMIO_DST;
> *cs++ = CS_GPR(NOW_TS);
> w->reloc[r].target_handle = self;
> w->reloc[r].offset = offset_in_page(cs);
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index cb62728896..b8d97a07c9 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2625,6 +2625,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> #define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
> #define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
> #define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
> +#define MI_LOAD_REGISTER_REG ((0x2A << 23) | 1)
> +#define MI_STORE_REGISTER_MEM ((0x24 << 23) | (3 - 2))
> +#define MI_STORE_REGISTER_MEM_GEN8 ((0x24 << 23) | (4 - 2))
>
> /* Flush */
> #define MI_FLUSH (0x04<<23)
> @@ -2642,6 +2645,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> #define MI_NOOP_WRITE_ID (1<<22)
> #define MI_NOOP_ID_MASK (1<<22 - 1)
>
> +/* ARB Check */
> +#define MI_ARB_CHECK (0x5 << 23)
> +
> #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
>
> /* Atomics */
> @@ -2656,12 +2662,48 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> #define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
> #define MI_BATCH_BUFFER_END (0xA << 23)
> #define MI_COND_BATCH_BUFFER_END (0x36 << 23)
> +#define MAD_GT_IDD (0 << 12)
> +#define MAD_GT_OR_EQ_IDD (1 << 12)
> +#define MAD_LT_IDD (2 << 12)
> +#define MAD_LT_OR_EQ_IDD (3 << 12)
> +#define MAD_EQ_IDD (4 << 12)
> +#define MAD_NEQ_IDD (5 << 12)
> #define MI_DO_COMPARE (1 << 21)
>
> #define MI_BATCH_NON_SECURE (1)
> #define MI_BATCH_NON_SECURE_I965 (1 << 8)
> #define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */
>
> +/* Math */
> +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> +/* Opcodes for MI_MATH_INSTR */
> +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> +/* DG2+ */
> +#define MI_MATH_SHL MI_MATH_INSTR(0x105, 0x0, 0x0)
> +#define MI_MATH_SHR MI_MATH_INSTR(0x106, 0x0, 0x0)
> +#define MI_MATH_SAR MI_MATH_INSTR(0x107, 0x0, 0x0)
> +
> +/* Registers used as operands in MI_MATH_INSTR */
> +#define MI_MATH_REG(x) (x)
> +#define MI_MATH_REG_SRCA 0x20
> +#define MI_MATH_REG_SRCB 0x21
> +#define MI_MATH_REG_ACCU 0x31
> +#define MI_MATH_REG_ZF 0x32
> +#define MI_MATH_REG_CF 0x33
> +
> #define MAX_DISPLAY_PIPES 2
>
> typedef enum {
> diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
> index 935f9c4a0b..89921697f7 100644
> --- a/tests/i915/gem_exec_fair.c
> +++ b/tests/i915/gem_exec_fair.c
> @@ -112,33 +112,6 @@ static uint64_t ticks_to_ns(int i915, uint64_t ticks)
> read_timestamp_frequency(i915));
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> -#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -
> static void delay(int i915,
> const struct intel_execution_engine2 *e,
> uint32_t handle,
> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> index 47ddf3083d..f20d7d94ff 100644
> --- a/tests/i915/gem_exec_fence.c
> +++ b/tests/i915/gem_exec_fence.c
> @@ -2366,37 +2366,6 @@ static void test_syncobj_timeline_multiple_ext_nodes(int fd)
> syncobj_destroy(fd, syncobjs[i]);
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -/* #define MI_LOAD_REGISTER_MEM (MI_INSTR(0x29, 1) */
> -/* #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) */
> -
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -
> -#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
> -#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x00, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x80, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> #define HSW_CS_GPR(n) (0x600 + 8*(n))
> #define RING_TIMESTAMP (0x358)
> #define MI_PREDICATE_RESULT_1 (0x41c)
> diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
> index fc1ba00712..01eb007694 100644
> --- a/tests/i915/gem_watchdog.c
> +++ b/tests/i915/gem_watchdog.c
> @@ -270,33 +270,6 @@ static void virtual(int i915, const intel_ctx_cfg_t *base_cfg)
> igt_assert_eq(count, expect);
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> -#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -
> static unsigned int offset_in_page(void *addr)
> {
> return (uintptr_t)addr & 4095;
> diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> index 70967b3ff5..12c70b2011 100644
> --- a/tests/i915/gem_workarounds.c
> +++ b/tests/i915/gem_workarounds.c
> @@ -83,8 +83,6 @@ static bool write_only(const uint32_t addr)
> return false;
> }
>
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> -
> static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
> {
> struct drm_i915_gem_exec_object2 obj[2];
> @@ -122,7 +120,10 @@ static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
> out = base =
> gem_mmap__cpu(i915, obj[1].handle, 0, batch_sz, PROT_WRITE);
> for (int i = 0; i < num_wa_regs; i++) {
> - *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
> + if (gen >= 8)
> + *out++ = MI_STORE_REGISTER_MEM_GEN8;
> + else
> + *out++ = MI_STORE_REGISTER_MEM;
> *out++ = wa_regs[i].addr;
> reloc[i].target_handle = obj[0].handle;
> reloc[i].offset = (out - base) * sizeof(*out);
> diff --git a/tests/i915/gen7_exec_parse.c b/tests/i915/gen7_exec_parse.c
> index c83a791126..c3c2a7a296 100644
> --- a/tests/i915/gen7_exec_parse.c
> +++ b/tests/i915/gen7_exec_parse.c
> @@ -48,8 +48,6 @@
> #define INSTR_CLIENT_SHIFT 29
> #define INSTR_INVALID_CLIENT 0x7
>
> -#define MI_LOAD_REGISTER_REG (0x2a << 23)
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> #define MI_ARB_ON_OFF (0x8 << 23)
> #define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
>
> @@ -374,19 +372,19 @@ static void test_allocations(int fd)
> static void hsw_load_register_reg(void)
> {
> uint32_t init_gpr0[16] = {
> - MI_LOAD_REGISTER_IMM | (3 - 2),
> + MI_LOAD_REGISTER_IMM,
> HSW_CS_GPR0,
> 0xabcdabc0, /* leave [1:0] zero */
> MI_BATCH_BUFFER_END,
> };
> uint32_t store_gpr0[16] = {
> - MI_STORE_REGISTER_MEM | (3 - 2),
> + MI_STORE_REGISTER_MEM,
> HSW_CS_GPR0,
> 0, /* reloc*/
> MI_BATCH_BUFFER_END,
> };
> uint32_t do_lrr[16] = {
> - MI_LOAD_REGISTER_REG | (3 - 2),
> + MI_LOAD_REGISTER_REG,
> 0, /* [1] = src */
> HSW_CS_GPR0, /* dst */
> MI_BATCH_BUFFER_END,
> diff --git a/tests/i915/gen9_exec_parse.c b/tests/i915/gen9_exec_parse.c
> index fa61693cfc..1d9cd37104 100644
> --- a/tests/i915/gen9_exec_parse.c
> +++ b/tests/i915/gen9_exec_parse.c
> @@ -38,12 +38,9 @@
> #define INSTR_CLIENT_SHIFT 29
> #define INSTR_INVALID_CLIENT 0x7
>
> -#define MI_LOAD_REGISTER_REG (0x2a << 23)
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> #define MI_ARB_ON_OFF (0x8 << 23)
> #define MI_USER_INTERRUPT (0x02 << 23)
> #define MI_FLUSH_DW (0x26 << 23)
> -#define MI_ARB_CHECK (0x05 << 23)
> #define MI_REPORT_HEAD (0x07 << 23)
> #define MI_SUSPEND_FLUSH (0x0b << 23)
> #define MI_LOAD_SCAN_LINES_EXCL (0x13 << 23)
> @@ -689,7 +686,7 @@ static void test_cmd_crossing_page(const int i915, const uint32_t handle)
> MI_BATCH_BUFFER_END,
> };
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM_GEN8,
> BCS_GPR(0),
> 0, /* reloc */
> 0, /* reloc */
> @@ -728,7 +725,7 @@ static void test_invalid_length(const int i915, const uint32_t handle)
> };
>
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM_GEN8,
> BCS_GPR(0),
> 0, /* reloc */
> 0, /* reloc */
> @@ -841,7 +838,7 @@ static void test_register(const int i915, const uint32_t handle,
> };
>
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM_GEN8,
> r->addr,
> 0, /* reloc */
> 0, /* reloc */
> @@ -880,7 +877,7 @@ static long int read_reg(const int i915, const uint32_t handle,
> const uint32_t addr)
> {
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM_GEN8,
> addr,
> 0, /* reloc */
> 0, /* reloc */
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions Zbigniew Kempczyński
@ 2022-06-09 9:44 ` Petri Latvala
2022-06-10 5:24 ` Zbigniew Kempczyński
0 siblings, 1 reply; 24+ messages in thread
From: Petri Latvala @ 2022-06-09 9:44 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Tue, Jun 07, 2022 at 07:24:09AM +0200, Zbigniew Kempczyński wrote:
> Add crc32 table for on-cpu crc calculation function. Other tables and
> algorithms should be added here allowing reuse tables for in-gpu crc
> calculation.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> lib/igt_crc.c | 107 ++++++++++++++++++
> lib/igt_crc.h | 31 +++++
> lib/meson.build | 1 +
> 4 files changed, 140 insertions(+)
> create mode 100644 lib/igt_crc.c
> create mode 100644 lib/igt_crc.h
>
> diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> index 1774256530..b78f1eb6ff 100644
> --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> @@ -22,6 +22,7 @@
> <xi:include href="xml/igt_chamelium.xml"/>
> <xi:include href="xml/igt_collection.xml"/>
> <xi:include href="xml/igt_core.xml"/>
> + <xi:include href="xml/igt_crc.xml"/>
> <xi:include href="xml/igt_debugfs.xml"/>
> <xi:include href="xml/igt_device.xml"/>
> <xi:include href="xml/igt_device_scan.xml"/>
> diff --git a/lib/igt_crc.c b/lib/igt_crc.c
> new file mode 100644
> index 0000000000..e634f5cf27
> --- /dev/null
> +++ b/lib/igt_crc.c
> @@ -0,0 +1,107 @@
> +/*-
> + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
> + * code or tables extracted from it, as desired without restriction.
> + */
> +
> +/*
> + * First, the polynomial itself and its table of feedback terms. The
> + * polynomial is
> + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> + *
> + * Note that we take it "backwards" and put the highest-order term in
> + * the lowest-order bit. The X^32 term is "implied"; the LSB is the
> + * X^31 term, etc. The X^0 term (usually shown as "+1") results in
> + * the MSB being 1
> + *
> + * Note that the usual hardware shift register implementation, which
> + * is what we're using (we're merely optimizing it by doing eight-bit
> + * chunks at a time) shifts bits into the lowest-order term. In our
> + * implementation, that means shifting towards the right. Why do we
> + * do it this way? Because the calculated CRC must be transmitted in
> + * order from highest-order term to lowest-order term. UARTs transmit
> + * characters in order from LSB to MSB. By storing the CRC this way
> + * we hand it to the UART in the order low-byte to high-byte; the UART
> + * sends each low-bit to hight-bit; and the result is transmission bit
> + * by bit from highest- to lowest-order term without requiring any bit
> + * shuffling on our part. Reception works similarly
> + *
> + * The feedback terms table consists of 256, 32-bit entries. Notes
> + *
> + * The table can be generated at runtime if desired; code to do so
> + * is shown later. It might not be obvious, but the feedback
> + * terms simply represent the results of eight shift/xor opera
> + * tions for all combinations of data and CRC register values
> + *
> + * The values must be right-shifted by eight bits by the "updcrc
> + * logic; the shift must be unsigned (bring in zeroes). On some
> + * hardware you could probably optimize the shift in assembler by
> + * using byte-swap instructions
> + * polynomial $edb88320
This is also in the original code but... what?
Anyway,
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
> + *
> + *
> + * CRC32 code derived from work by Gary S. Brown.
> + */
> +
> +#include <stddef.h>
> +#include <stdint.h>
> +#include "igt_crc.h"
> +
> +const uint32_t igt_crc32_tab[256] = {
> + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
> + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
> + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
> + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
> + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
> + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
> + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
> + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
> + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
> + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
> + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
> + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
> + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
> + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
> + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
> + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
> + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
> + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
> + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
> + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
> + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
> + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
> + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
> + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
> + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
> + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
> + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
> + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
> + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
> + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
> + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
> + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
> + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
> + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
> + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
> + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
> + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
> + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
> + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
> + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
> + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
> + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
> + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
> +};
> +
> +uint32_t igt_cpu_crc32(const void *buf, size_t size)
> +{
> +
> + const uint8_t *p = buf;
> + uint32_t crc;
> +
> + crc = ~0U;
> +
> + while (size--)
> + crc = igt_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
> +
> + return crc ^ ~0U;
> +}
> diff --git a/lib/igt_crc.h b/lib/igt_crc.h
> new file mode 100644
> index 0000000000..5c0b934ea5
> --- /dev/null
> +++ b/lib/igt_crc.h
> @@ -0,0 +1,31 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __IGT_CRC_H__
> +#define __IGT_CRC_H__
> +
> +#include <stddef.h>
> +#include <stdint.h>
> +
> +/**
> + * SECTION:igt_crc
> + * @short_description: igt crc tables and calculation functions
> + * @title: CRC
> + * @include: igt_crc.h
> + *
> + * # Introduction
> + *
> + * Providing vendor agnostic crc calculation is useful to avoid code
> + * duplication. Especially if vendor will decide to do on-gpu crc calculation
> + * it will need to inject crc table to gpu.
> + *
> + * All crc tables are globals to allow direct in-code use.
> + */
> +
> +const uint32_t igt_crc32_tab[256];
> +
> +uint32_t igt_cpu_crc32(const void *buf, size_t size);
> +
> +#endif
> diff --git a/lib/meson.build b/lib/meson.build
> index 0a173c1fc6..cc2b2abee6 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -15,6 +15,7 @@ lib_sources = [
> 'i915/i915_blt.c',
> 'igt_collection.c',
> 'igt_color_encoding.c',
> + 'igt_crc.c',
> 'igt_debugfs.c',
> 'igt_device.c',
> 'igt_device_scan.c',
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 3/4] lib/i915_crc: Introduce crc32 on gpu for DG2
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 3/4] lib/i915_crc: Introduce crc32 on gpu for DG2 Zbigniew Kempczyński
@ 2022-06-09 9:47 ` Petri Latvala
0 siblings, 0 replies; 24+ messages in thread
From: Petri Latvala @ 2022-06-09 9:47 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Tue, Jun 07, 2022 at 07:24:10AM +0200, Zbigniew Kempczyński wrote:
> Adding crc32 calculation on gpu gives us new possibility to verify data
> integrity without relying on trust cpu mapping is correct.
>
> Patch introduces calculating crc32 on DG2 only. On older gens ALU
> (MI_MATH) doesn't support bit-shifting instructions as well as multiply
> or divide. Emulating n-bit shifts cost hundred of instructions with
> predicated SRM (works on render engine only). Another limitation is lack
> of indexed load / store. On DG2 we can use WPARID and CS_MI_ADDRESS_OFFSET
> to achieve indexed operation on memory.
>
> Due to performance reasons (cpu crc32 calculation even on WC memory is
> still much faster than on gpu, also depends on calculated object memory
> region) calculation will complete in reasonable of time only for few MiB.
>
> v2: - use registers relative to engine to allow run on all engines (Chris)
> - use predication instead of memory access to get better performance
> (Chris)
> - add location where crc32 implementation comes from (Petri)
>
> v4: - use common crc32 table from igt_crc
> - add docs
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
I'm unable to judge whether the gpu code is correct or not, but otherwise
Acked-by: Petri Latvala <petri.latvala@intel.com>
> ---
> .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> lib/i915/i915_crc.c | 297 ++++++++++++++++++
> lib/i915/i915_crc.h | 27 ++
> lib/intel_reg.h | 3 +
> lib/meson.build | 1 +
> 5 files changed, 329 insertions(+)
> create mode 100644 lib/i915/i915_crc.c
> create mode 100644 lib/i915/i915_crc.h
>
> diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> index b78f1eb6ff..a19f786e84 100644
> --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> @@ -63,6 +63,7 @@
> <xi:include href="xml/gem_scheduler.xml"/>
> <xi:include href="xml/gem_submission.xml"/>
> <xi:include href="xml/i915_blt.xml"/>
> + <xi:include href="xml/i915_crc.xml"/>
> <xi:include href="xml/intel_ctx.xml"/>
> </chapter>
> <xi:include href="xml/igt_test_programs.xml"/>
> diff --git a/lib/i915/i915_crc.c b/lib/i915/i915_crc.c
> new file mode 100644
> index 0000000000..4c6e488c23
> --- /dev/null
> +++ b/lib/i915/i915_crc.c
> @@ -0,0 +1,297 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include <stddef.h>
> +#include <stdint.h>
> +#include "drmtest.h"
> +#include "gem_create.h"
> +#include "gem_engine_topology.h"
> +#include "gem_mman.h"
> +#include "i830_reg.h"
> +#include "i915_drm.h"
> +#include "intel_reg.h"
> +#include "intel_chipset.h"
> +#include "ioctl_wrappers.h"
> +#include "intel_allocator.h"
> +#include "igt_crc.h"
> +#include "i915/i915_crc.h"
> +
> +#define CS_GPR(x) (0x600 + 8 * (x))
> +#define GPR(x) CS_GPR(x)
> +#define R(x) (x)
> +#define USERDATA(offset, idx) ((offset) + (0x100 + (idx)) * 4)
> +#define OFFSET(obj_offset, current, start) \
> + ((obj_offset) + (current - start) * 4)
> +
> +#define MI_PREDICATE_RESULT 0x3B8
> +#define WPARID 0x21C
> +#define CS_MI_ADDRESS_OFFSET 0x3B4
> +
> +#define LOAD_REGISTER_REG(__reg_src, __reg_dst) do { \
> + *bb++ = MI_LOAD_REGISTER_REG | BIT(19) | BIT(18); \
> + *bb++ = (__reg_src); \
> + *bb++ = (__reg_dst); \
> + } while (0)
> +
> +#define LOAD_REGISTER_IMM32(__reg, __imm1) do { \
> + *bb++ = MI_LOAD_REGISTER_IMM | BIT(19); \
> + *bb++ = (__reg); \
> + *bb++ = (__imm1); \
> + } while (0)
> +
> +#define LOAD_REGISTER_IMM64(__reg, __imm1, __imm2) do { \
> + *bb++ = (MI_LOAD_REGISTER_IMM + 2) | BIT(19); \
> + *bb++ = (__reg); \
> + *bb++ = (__imm1); \
> + *bb++ = (__reg) + 4; \
> + *bb++ = (__imm2); \
> + } while (0)
> +
> +#define LOAD_REGISTER_MEM(__reg, __offset) do { \
> + *bb++ = MI_LOAD_REGISTER_MEM_GEN8 | BIT(19); \
> + *bb++ = (__reg); \
> + *bb++ = (__offset); \
> + *bb++ = (__offset) >> 32; \
> + } while (0)
> +
> +#define LOAD_REGISTER_MEM_WPARID(__reg, __offset) do { \
> + *bb++ = MI_LOAD_REGISTER_MEM_GEN8 | BIT(19) | BIT(16); \
> + *bb++ = (__reg); \
> + *bb++ = (__offset); \
> + *bb++ = (__offset) >> 32; \
> + } while (0)
> +
> +#define STORE_REGISTER_MEM(__reg, __offset) do { \
> + *bb++ = MI_STORE_REGISTER_MEM_GEN8 | BIT(19); \
> + *bb++ = (__reg); \
> + *bb++ = (__offset); \
> + *bb++ = (__offset) >> 32; \
> + } while (0)
> +
> +#define STORE_REGISTER_MEM_PREDICATED(__reg, __offset) do { \
> + *bb++ = MI_STORE_REGISTER_MEM_GEN8 | BIT(19) | (BIT(21); \
> + *bb++ = (__reg); \
> + *bb++ = (__offset); \
> + *bb++ = (__offset) >> 32; \
> + } while (0)
> +
> +#define COND_BBE(__value, __offset, __condition) do { \
> + *bb++ = MI_COND_BATCH_BUFFER_END | MI_DO_COMPARE | (__condition) | 2; \
> + *bb++ = (__value); \
> + *bb++ = (__offset); \
> + *bb++ = (__offset) >> 32; \
> + } while (0)
> +
> +#define MATH_4_STORE(__r1, __r2, __op, __r3) do { \
> + *bb++ = MI_MATH(4); \
> + *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(__r1)); \
> + *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(__r2)); \
> + *bb++ = (__op); \
> + *bb++ = MI_MATH_STORE(MI_MATH_REG(__r3), MI_MATH_REG_ACCU); \
> + } while (0)
> +
> +#define BBSIZE 4096
> +
> +/* Aliasing for easier refactoring */
> +#define GPR_SIZE GPR(0)
> +#define R_SIZE R(0)
> +
> +#define GPR_CRC GPR(1)
> +#define R_CRC R(1)
> +
> +#define GPR_INDATA_IDX GPR(2)
> +#define R_INDATA_IDX R(2)
> +
> +#define GPR_TABLE_IDX GPR(3)
> +#define R_TABLE_IDX R(3)
> +
> +#define GPR_CURR_DW GPR(4)
> +#define R_CURR_DW R(4)
> +
> +#define GPR_CONST_2 GPR(5)
> +#define R_CONST_2 R(5)
> +
> +#define GPR_CONST_4 GPR(6)
> +#define R_CONST_4 R(6)
> +
> +#define GPR_CONST_8 GPR(7)
> +#define R_CONST_8 R(7)
> +
> +#define GPR_CONST_ff GPR(8)
> +#define R_CONST_ff R(8)
> +
> +#define GPR_ffffffff GPR(9)
> +#define R_ffffffff R(9)
> +
> +#define GPR_TMP_1 GPR(10)
> +#define R_TMP_1 R(10)
> +
> +#define GPR_TMP_2 GPR(11)
> +#define R_TMP_2 R(11)
> +
> +static void fill_batch(int i915, uint32_t bb_handle, uint64_t bb_offset,
> + uint64_t table_offset, uint64_t data_offset, uint32_t data_size)
> +{
> + uint32_t *bb, *batch, *jmp;
> + const unsigned int gen = intel_gen(intel_get_drm_devid(i915));
> + const int use_64b = gen >= 8;
> + uint64_t offset;
> + uint64_t crc = USERDATA(table_offset, 0);
> +
> + igt_assert(data_size % 4 == 0);
> +
> + batch = gem_mmap__device_coherent(i915, bb_handle, 0, BBSIZE,
> + PROT_READ | PROT_WRITE);
> + memset(batch, 0, BBSIZE);
> +
> + bb = batch;
> +
> + LOAD_REGISTER_IMM64(GPR_SIZE, data_size, 0);
> + LOAD_REGISTER_IMM64(GPR_CRC, ~0U, 0); /* crc start - 0xffffffff */
> + LOAD_REGISTER_IMM64(GPR_INDATA_IDX, 0, 0); /* data_offset index (0) */
> + LOAD_REGISTER_IMM64(GPR_CONST_2, 2, 0); /* const value 2 */
> + LOAD_REGISTER_IMM64(GPR_CONST_4, 4, 0); /* const value 4 */
> + LOAD_REGISTER_IMM64(GPR_CONST_8, 8, 0); /* const value 8 */
> + LOAD_REGISTER_IMM64(GPR_CONST_ff, 0xff, 0); /* const value 0xff */
> + LOAD_REGISTER_IMM64(GPR_ffffffff, ~0U, 0); /* const value 0xffffffff */
> +
> + /* for indexed reads from memory */
> + LOAD_REGISTER_IMM32(WPARID, 1);
> +
> + jmp = bb;
> +
> + *bb++ = MI_SET_PREDICATE;
> + *bb++ = MI_ARB_CHECK;
> +
> + LOAD_REGISTER_REG(GPR_INDATA_IDX, CS_MI_ADDRESS_OFFSET);
> + LOAD_REGISTER_MEM_WPARID(GPR_CURR_DW, data_offset);
> +
> + for (int byte = 0; byte < 4; byte++) {
> + if (byte != 0)
> + MATH_4_STORE(R_CURR_DW, R_CONST_8,
> + MI_MATH_SHR, R_CURR_DW); /* dw >> 8 */
> +
> + /* crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); */
> + MATH_4_STORE(R_CURR_DW, R_CONST_ff,
> + MI_MATH_AND, R_TMP_1); /* dw & 0xff */
> + MATH_4_STORE(R_CRC, R_TMP_1,
> + MI_MATH_XOR, R_TMP_1); /* crc ^ tmp */
> + MATH_4_STORE(R_TMP_1, R_CONST_ff,
> + MI_MATH_AND, R_TMP_1); /* tmp & 0xff */
> + MATH_4_STORE(R_TMP_1, R_CONST_2,
> + MI_MATH_SHL, R_TABLE_IDX); /* tmp << 2 (crc idx) */
> +
> + LOAD_REGISTER_REG(GPR_TABLE_IDX, CS_MI_ADDRESS_OFFSET);
> + LOAD_REGISTER_MEM_WPARID(GPR_TMP_1, table_offset);
> +
> + MATH_4_STORE(R_CRC, R_CONST_8,
> + MI_MATH_SHR, R_TMP_2); /* crc >> 8 (shift) */
> + MATH_4_STORE(R_TMP_2, R_TMP_1,
> + MI_MATH_XOR, R_CRC); /* crc = tab[v] ^ shift */
> + }
> +
> + /* increment data index */
> + MATH_4_STORE(R_INDATA_IDX, R_CONST_4, MI_MATH_ADD, R_INDATA_IDX);
> +
> + /* loop until R_SIZE == 0, R_SIZE = R_SIZE - R_CONST_4 */
> +
> + *bb++ = MI_MATH(5);
> + *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(R_SIZE));
> + *bb++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(R_CONST_4));
> + *bb++ = MI_MATH_SUB;
> + *bb++ = MI_MATH_STORE(MI_MATH_REG(R_SIZE), MI_MATH_REG_ACCU);
> + *bb++ = MI_MATH_STORE(MI_MATH_REG(R_TMP_2), MI_MATH_REG_ZF);
> + LOAD_REGISTER_REG(GPR_TMP_2, MI_PREDICATE_RESULT);
> +
> + *bb++ = MI_BATCH_BUFFER_START | BIT(15) | BIT(8) | use_64b;
> + offset = OFFSET(bb_offset, jmp, batch);
> + *bb++ = offset;
> + *bb++ = offset >> 32;
> +
> + *bb++ = MI_SET_PREDICATE;
> +
> + MATH_4_STORE(R_CRC, R_ffffffff, MI_MATH_XOR, R_TMP_1);
> + STORE_REGISTER_MEM(GPR_TMP_1, crc);
> +
> + *bb++ = MI_BATCH_BUFFER_END;
> +
> + gem_munmap(batch, BBSIZE);
> +}
> +
> +/**
> + * i915_crc32:
> + * @i915: drm fd
> + * @ahnd: allocator handle
> + * @ctx: intel context
> + * @e: engine on which crc32 calculation will be executed
> + * @data_handle: bo which is subject of crc32 calculation
> + * @data_size: length of bo data to calculate (must be multiple of 4)
> + *
> + * Function calculates crc32 for @data_handle with size @data_size.
> + *
> + * Returns: uint32_t crc32.
> + *
> + **/
> +uint32_t i915_crc32(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t data_handle, uint32_t data_size)
> +{
> + struct drm_i915_gem_execbuffer2 execbuf = {};
> + struct drm_i915_gem_exec_object2 obj[3] = {};
> + uint64_t bb_offset, table_offset, data_offset;
> + uint32_t bb, table, crc, table_size = 4096;
> + uint32_t *ptr;
> +
> + igt_assert(data_size % 4 == 0);
> +
> + table = gem_create_in_memory_regions(i915, table_size, REGION_LMEM(0));
> + gem_write(i915, table, 0, igt_crc32_tab, sizeof(igt_crc32_tab));
> +
> + table_offset = get_offset(ahnd, table, table_size, 0);
> + data_offset = get_offset(ahnd, data_handle, data_size, 0);
> +
> + obj[0].offset = table_offset;
> + obj[0].flags = EXEC_OBJECT_PINNED | EXEC_OBJECT_WRITE;
> + obj[0].handle = table;
> +
> + obj[1].offset = data_offset;
> + obj[1].flags = EXEC_OBJECT_PINNED;
> + obj[1].handle = data_handle;
> +
> + bb = gem_create_in_memory_regions(i915, BBSIZE, REGION_LMEM(0));
> + bb_offset = get_offset(ahnd, bb, BBSIZE, 0);
> + fill_batch(i915, bb, bb_offset, table_offset, data_offset, data_size);
> + obj[2].offset = bb_offset;
> + obj[2].flags = EXEC_OBJECT_PINNED;
> + obj[2].handle = bb;
> + execbuf.buffer_count = 3;
> + execbuf.buffers_ptr = to_user_pointer(obj);
> + execbuf.flags = e->flags;
> + execbuf.rsvd1 = ctx->id;
> + gem_execbuf(i915, &execbuf);
> + gem_sync(i915, table);
> +
> + ptr = gem_mmap__device_coherent(i915, table, 0, table_size, PROT_READ);
> + crc = ptr[0x100];
> + gem_munmap(ptr, table_size);
> + gem_close(i915, table);
> + gem_close(i915, bb);
> +
> + return crc;
> +}
> +
> +/**
> + * supports_i915_crc32:
> + * @i915: drm fd
> + *
> + * Returns: flag if i915_crc32() is able to generate crc32 on gpu.
> + *
> + **/
> +bool supports_i915_crc32(int i915)
> +{
> + uint16_t devid = intel_get_drm_devid(i915);
> +
> + return IS_DG2(devid);
> +}
> diff --git a/lib/i915/i915_crc.h b/lib/i915/i915_crc.h
> new file mode 100644
> index 0000000000..3bd7411690
> --- /dev/null
> +++ b/lib/i915/i915_crc.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +#ifndef _I915_CRC_H_
> +#define _I915_CRC_H_
> +
> +#include <stdint.h>
> +#include "intel_ctx.h"
> +
> +/**
> + * SECTION:i915_crc
> + * @short_description: i915 gpu crc
> + * @title: I915 GPU CRC
> + * @include: i915_crc.h
> + *
> + * # Introduction
> + *
> + * Intel gpu crc calculation implementation.
> + */
> +
> +uint32_t i915_crc32(int i915, uint64_t ahnd, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + uint32_t data_handle, uint32_t data_size);
> +bool supports_i915_crc32(int i915);
> +
> +#endif /* _I915_CRC_ */
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index b8d97a07c9..104a73f073 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2704,6 +2704,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> #define MI_MATH_REG_ZF 0x32
> #define MI_MATH_REG_CF 0x33
>
> +/* DG2+ */
> +#define MI_SET_PREDICATE MI_INSTR(0x1, 0)
> +
> #define MAX_DISPLAY_PIPES 2
>
> typedef enum {
> diff --git a/lib/meson.build b/lib/meson.build
> index cc2b2abee6..12b2cc5d78 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -13,6 +13,7 @@ lib_sources = [
> 'i915/intel_memory_region.c',
> 'i915/intel_mocs.c',
> 'i915/i915_blt.c',
> + 'i915/i915_crc.c',
> 'igt_collection.c',
> 'igt_color_encoding.c',
> 'igt_crc.c',
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test for DG2
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test " Zbigniew Kempczyński
@ 2022-06-09 9:52 ` Petri Latvala
2022-06-10 4:34 ` Zbigniew Kempczyński
0 siblings, 1 reply; 24+ messages in thread
From: Petri Latvala @ 2022-06-09 9:52 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Tue, Jun 07, 2022 at 07:24:11AM +0200, Zbigniew Kempczyński wrote:
> Add simple test which compares crc32 sums and calculation times on cpu
> and gpu.
>
> v2: - addressing review comments - igt_debug + igt_time_elapsed (Kamil)
> - exercise crc for size smaller than page size
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> ---
> tests/i915/api_intel_bb.c | 63 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 63 insertions(+)
>
> diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
> index 92f44cecf4..d6998af692 100644
> --- a/tests/i915/api_intel_bb.c
> +++ b/tests/i915/api_intel_bb.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "igt_crc.h"
> #include "i915/gem.h"
> #include "i915/gem_create.h"
> #include <unistd.h>
> @@ -38,6 +39,7 @@
> #include <zlib.h>
> #include "intel_bufops.h"
> #include "i915/gem_vm.h"
> +#include "i915/i915_crc.h"
>
> #define PAGE_SIZE 4096
>
> @@ -1395,6 +1397,51 @@ static void render_ccs(struct buf_ops *bops)
> igt_assert_f(fails == 0, "render-ccs fails: %d\n", fails);
> }
>
> +static void test_crc32(int i915, const intel_ctx_t *ctx,
> + const struct intel_execution_engine2 *e,
> + struct drm_i915_gem_memory_class_instance *r)
> +{
> + uint64_t ahnd = get_reloc_ahnd(i915, ctx->id);
> + uint32_t data, *ptr;
> +
> + uint32_t region = INTEL_MEMORY_REGION_ID(r->memory_class,
> + r->memory_instance);
> +
> + igt_debug("[engine: %s, region: %s]\n", e->name,
> + region == REGION_SMEM ? "smem" : "lmem");
> + for (int i = 2; i < 21; i += 2) {
> + struct timespec start, end;
> + uint64_t size = 1 << i;
> + uint32_t cpu_crc, gpu_crc;
> +
> + double cpu_time, gpu_time;
> +
> + data = gem_create_in_memory_regions(i915, size, region);
> + ptr = gem_mmap__device_coherent(i915, data, 0, size, PROT_WRITE);
> + for (int j = 0; j < size / sizeof(*ptr); j++)
> + ptr[j] = j;
> +
> + clock_gettime(CLOCK_MONOTONIC, &start);
> + cpu_crc = igt_cpu_crc32(ptr, size);
> + clock_gettime(CLOCK_MONOTONIC, &end);
> + cpu_time = igt_time_elapsed(&start, &end);
> + munmap(ptr, size);
> +
> + clock_gettime(CLOCK_MONOTONIC, &start);
> + gpu_crc = i915_crc32(i915, ahnd, ctx, e, data, size);
> + clock_gettime(CLOCK_MONOTONIC, &end);
> + gpu_time = igt_time_elapsed(&start, &end);
Mandatory question: Explain choice of CLOCK_MONOTONIC
vs. CLOCK_MONOTONIC_RAW vs. CLOCK_MONOTONIC_COARSE. And as a
corollary, why igt_gettime's choice of monotonic clock type is not
sufficient.
--
Petri Latvala
> + igt_debug("size: %10lld, cpu crc: 0x%08x (time: %.3f), "
> + "gpu crc: 0x%08x (time: %.3f) [ %s ]\n",
> + (long long) size, cpu_crc, cpu_time, gpu_crc, gpu_time,
> + cpu_crc == gpu_crc ? "EQUAL" : "DIFFERENT");
> + gem_close(i915, data);
> + igt_assert(cpu_crc == gpu_crc);
> + }
> +
> + put_ahnd(ahnd);
> +}
> +
> static int opt_handler(int opt, int opt_index, void *data)
> {
> switch (opt) {
> @@ -1552,6 +1599,22 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
> igt_subtest("render-ccs")
> render_ccs(bops);
>
> + igt_describe("Compare cpu and gpu crc32 sums on input object");
> + igt_subtest_with_dynamic_f("crc32") {
> + const intel_ctx_t *ctx;
> + const struct intel_execution_engine2 *e;
> +
> + igt_require(supports_i915_crc32(i915));
> +
> + ctx = intel_ctx_create_all_physical(i915);
> + for_each_ctx_engine(i915, ctx, e) {
> + for_each_memory_region(r, i915) {
> + igt_dynamic_f("%s-%s", e->name, r->name)
> + test_crc32(i915, ctx, e, &r->ci);
> + }
> + }
> + }
> +
> igt_fixture {
> buf_ops_destroy(bops);
> close(i915);
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test for DG2
2022-06-09 9:52 ` Petri Latvala
@ 2022-06-10 4:34 ` Zbigniew Kempczyński
2022-06-10 8:34 ` Petri Latvala
0 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-10 4:34 UTC (permalink / raw)
To: Petri Latvala; +Cc: igt-dev
On Thu, Jun 09, 2022 at 12:52:22PM +0300, Petri Latvala wrote:
> On Tue, Jun 07, 2022 at 07:24:11AM +0200, Zbigniew Kempczyński wrote:
> > Add simple test which compares crc32 sums and calculation times on cpu
> > and gpu.
> >
> > v2: - addressing review comments - igt_debug + igt_time_elapsed (Kamil)
> > - exercise crc for size smaller than page size
> >
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> > tests/i915/api_intel_bb.c | 63 +++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 63 insertions(+)
> >
> > diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
> > index 92f44cecf4..d6998af692 100644
> > --- a/tests/i915/api_intel_bb.c
> > +++ b/tests/i915/api_intel_bb.c
> > @@ -22,6 +22,7 @@
> > */
> >
> > #include "igt.h"
> > +#include "igt_crc.h"
> > #include "i915/gem.h"
> > #include "i915/gem_create.h"
> > #include <unistd.h>
> > @@ -38,6 +39,7 @@
> > #include <zlib.h>
> > #include "intel_bufops.h"
> > #include "i915/gem_vm.h"
> > +#include "i915/i915_crc.h"
> >
> > #define PAGE_SIZE 4096
> >
> > @@ -1395,6 +1397,51 @@ static void render_ccs(struct buf_ops *bops)
> > igt_assert_f(fails == 0, "render-ccs fails: %d\n", fails);
> > }
> >
> > +static void test_crc32(int i915, const intel_ctx_t *ctx,
> > + const struct intel_execution_engine2 *e,
> > + struct drm_i915_gem_memory_class_instance *r)
> > +{
> > + uint64_t ahnd = get_reloc_ahnd(i915, ctx->id);
> > + uint32_t data, *ptr;
> > +
> > + uint32_t region = INTEL_MEMORY_REGION_ID(r->memory_class,
> > + r->memory_instance);
> > +
> > + igt_debug("[engine: %s, region: %s]\n", e->name,
> > + region == REGION_SMEM ? "smem" : "lmem");
> > + for (int i = 2; i < 21; i += 2) {
> > + struct timespec start, end;
> > + uint64_t size = 1 << i;
> > + uint32_t cpu_crc, gpu_crc;
> > +
> > + double cpu_time, gpu_time;
> > +
> > + data = gem_create_in_memory_regions(i915, size, region);
> > + ptr = gem_mmap__device_coherent(i915, data, 0, size, PROT_WRITE);
> > + for (int j = 0; j < size / sizeof(*ptr); j++)
> > + ptr[j] = j;
> > +
> > + clock_gettime(CLOCK_MONOTONIC, &start);
> > + cpu_crc = igt_cpu_crc32(ptr, size);
> > + clock_gettime(CLOCK_MONOTONIC, &end);
> > + cpu_time = igt_time_elapsed(&start, &end);
> > + munmap(ptr, size);
> > +
> > + clock_gettime(CLOCK_MONOTONIC, &start);
> > + gpu_crc = i915_crc32(i915, ahnd, ctx, e, data, size);
> > + clock_gettime(CLOCK_MONOTONIC, &end);
> > + gpu_time = igt_time_elapsed(&start, &end);
>
> Mandatory question: Explain choice of CLOCK_MONOTONIC
> vs. CLOCK_MONOTONIC_RAW vs. CLOCK_MONOTONIC_COARSE. And as a
> corollary, why igt_gettime's choice of monotonic clock type is not
> sufficient.
Ok, I've read the git log of igt_gettime() + man page and it seems
the effect which we want to avoid is adjusting the time during test
run. Especially if result of test may depend on time comparison.
Why then there were no global replacement of clock_gettime(MONOTONIC)
broadly used in many tests?
Of course I'm going to use igt_gettime() now, so thanks for the review
and comment.
--
Zbigniew
>
>
> --
> Petri Latvala
>
>
>
> > + igt_debug("size: %10lld, cpu crc: 0x%08x (time: %.3f), "
> > + "gpu crc: 0x%08x (time: %.3f) [ %s ]\n",
> > + (long long) size, cpu_crc, cpu_time, gpu_crc, gpu_time,
> > + cpu_crc == gpu_crc ? "EQUAL" : "DIFFERENT");
> > + gem_close(i915, data);
> > + igt_assert(cpu_crc == gpu_crc);
> > + }
> > +
> > + put_ahnd(ahnd);
> > +}
> > +
> > static int opt_handler(int opt, int opt_index, void *data)
> > {
> > switch (opt) {
> > @@ -1552,6 +1599,22 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
> > igt_subtest("render-ccs")
> > render_ccs(bops);
> >
> > + igt_describe("Compare cpu and gpu crc32 sums on input object");
> > + igt_subtest_with_dynamic_f("crc32") {
> > + const intel_ctx_t *ctx;
> > + const struct intel_execution_engine2 *e;
> > +
> > + igt_require(supports_i915_crc32(i915));
> > +
> > + ctx = intel_ctx_create_all_physical(i915);
> > + for_each_ctx_engine(i915, ctx, e) {
> > + for_each_memory_region(r, i915) {
> > + igt_dynamic_f("%s-%s", e->name, r->name)
> > + test_crc32(i915, ctx, e, &r->ci);
> > + }
> > + }
> > + }
> > +
> > igt_fixture {
> > buf_ops_destroy(bops);
> > close(i915);
> > --
> > 2.32.0
> >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-09 9:44 ` Petri Latvala
@ 2022-06-10 5:24 ` Zbigniew Kempczyński
2022-06-10 7:53 ` Petri Latvala
0 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-10 5:24 UTC (permalink / raw)
To: Petri Latvala; +Cc: igt-dev
On Thu, Jun 09, 2022 at 12:44:11PM +0300, Petri Latvala wrote:
> On Tue, Jun 07, 2022 at 07:24:09AM +0200, Zbigniew Kempczyński wrote:
> > Add crc32 table for on-cpu crc calculation function. Other tables and
> > algorithms should be added here allowing reuse tables for in-gpu crc
> > calculation.
> >
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > ---
> > .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> > lib/igt_crc.c | 107 ++++++++++++++++++
> > lib/igt_crc.h | 31 +++++
> > lib/meson.build | 1 +
> > 4 files changed, 140 insertions(+)
> > create mode 100644 lib/igt_crc.c
> > create mode 100644 lib/igt_crc.h
> >
> > diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > index 1774256530..b78f1eb6ff 100644
> > --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > @@ -22,6 +22,7 @@
> > <xi:include href="xml/igt_chamelium.xml"/>
> > <xi:include href="xml/igt_collection.xml"/>
> > <xi:include href="xml/igt_core.xml"/>
> > + <xi:include href="xml/igt_crc.xml"/>
> > <xi:include href="xml/igt_debugfs.xml"/>
> > <xi:include href="xml/igt_device.xml"/>
> > <xi:include href="xml/igt_device_scan.xml"/>
> > diff --git a/lib/igt_crc.c b/lib/igt_crc.c
> > new file mode 100644
> > index 0000000000..e634f5cf27
> > --- /dev/null
> > +++ b/lib/igt_crc.c
> > @@ -0,0 +1,107 @@
> > +/*-
> > + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
> > + * code or tables extracted from it, as desired without restriction.
> > + */
> > +
> > +/*
> > + * First, the polynomial itself and its table of feedback terms. The
> > + * polynomial is
> > + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > + *
> > + * Note that we take it "backwards" and put the highest-order term in
> > + * the lowest-order bit. The X^32 term is "implied"; the LSB is the
> > + * X^31 term, etc. The X^0 term (usually shown as "+1") results in
> > + * the MSB being 1
> > + *
> > + * Note that the usual hardware shift register implementation, which
> > + * is what we're using (we're merely optimizing it by doing eight-bit
> > + * chunks at a time) shifts bits into the lowest-order term. In our
> > + * implementation, that means shifting towards the right. Why do we
> > + * do it this way? Because the calculated CRC must be transmitted in
> > + * order from highest-order term to lowest-order term. UARTs transmit
> > + * characters in order from LSB to MSB. By storing the CRC this way
> > + * we hand it to the UART in the order low-byte to high-byte; the UART
> > + * sends each low-bit to hight-bit; and the result is transmission bit
> > + * by bit from highest- to lowest-order term without requiring any bit
> > + * shuffling on our part. Reception works similarly
> > + *
> > + * The feedback terms table consists of 256, 32-bit entries. Notes
> > + *
> > + * The table can be generated at runtime if desired; code to do so
> > + * is shown later. It might not be obvious, but the feedback
> > + * terms simply represent the results of eight shift/xor opera
> > + * tions for all combinations of data and CRC register values
> > + *
> > + * The values must be right-shifted by eight bits by the "updcrc
> > + * logic; the shift must be unsigned (bring in zeroes). On some
> > + * hardware you could probably optimize the shift in assembler by
> > + * using byte-swap instructions
> > + * polynomial $edb88320
>
> This is also in the original code but... what?
For of writing coefficients:
X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
bin(0xedb88320)
0b 1110 1101 1011 1000 1000 0011 0010 0000
012 45 7 8 22 23 26
10
11
12 16
Here it is well explained:
https://www.greenend.org.uk/rjk/tech/crc.html
--
Zbigniew
>
>
> Anyway,
> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
>
>
> > + *
> > + *
> > + * CRC32 code derived from work by Gary S. Brown.
> > + */
> > +
> > +#include <stddef.h>
> > +#include <stdint.h>
> > +#include "igt_crc.h"
> > +
> > +const uint32_t igt_crc32_tab[256] = {
> > + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
> > + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
> > + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
> > + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
> > + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
> > + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
> > + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
> > + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
> > + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
> > + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
> > + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
> > + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
> > + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
> > + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
> > + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
> > + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
> > + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
> > + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
> > + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
> > + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
> > + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
> > + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
> > + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
> > + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
> > + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
> > + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
> > + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
> > + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
> > + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
> > + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
> > + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
> > + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
> > + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
> > + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
> > + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
> > + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
> > + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
> > + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
> > + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
> > + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
> > + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
> > + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
> > + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
> > +};
> > +
> > +uint32_t igt_cpu_crc32(const void *buf, size_t size)
> > +{
> > +
> > + const uint8_t *p = buf;
> > + uint32_t crc;
> > +
> > + crc = ~0U;
> > +
> > + while (size--)
> > + crc = igt_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
> > +
> > + return crc ^ ~0U;
> > +}
> > diff --git a/lib/igt_crc.h b/lib/igt_crc.h
> > new file mode 100644
> > index 0000000000..5c0b934ea5
> > --- /dev/null
> > +++ b/lib/igt_crc.h
> > @@ -0,0 +1,31 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#ifndef __IGT_CRC_H__
> > +#define __IGT_CRC_H__
> > +
> > +#include <stddef.h>
> > +#include <stdint.h>
> > +
> > +/**
> > + * SECTION:igt_crc
> > + * @short_description: igt crc tables and calculation functions
> > + * @title: CRC
> > + * @include: igt_crc.h
> > + *
> > + * # Introduction
> > + *
> > + * Providing vendor agnostic crc calculation is useful to avoid code
> > + * duplication. Especially if vendor will decide to do on-gpu crc calculation
> > + * it will need to inject crc table to gpu.
> > + *
> > + * All crc tables are globals to allow direct in-code use.
> > + */
> > +
> > +const uint32_t igt_crc32_tab[256];
> > +
> > +uint32_t igt_cpu_crc32(const void *buf, size_t size);
> > +
> > +#endif
> > diff --git a/lib/meson.build b/lib/meson.build
> > index 0a173c1fc6..cc2b2abee6 100644
> > --- a/lib/meson.build
> > +++ b/lib/meson.build
> > @@ -15,6 +15,7 @@ lib_sources = [
> > 'i915/i915_blt.c',
> > 'igt_collection.c',
> > 'igt_color_encoding.c',
> > + 'igt_crc.c',
> > 'igt_debugfs.c',
> > 'igt_device.c',
> > 'igt_device_scan.c',
> > --
> > 2.32.0
> >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-10 5:24 ` Zbigniew Kempczyński
@ 2022-06-10 7:53 ` Petri Latvala
2022-06-13 3:57 ` Zbigniew Kempczyński
0 siblings, 1 reply; 24+ messages in thread
From: Petri Latvala @ 2022-06-10 7:53 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Fri, Jun 10, 2022 at 07:24:39AM +0200, Zbigniew Kempczyński wrote:
> On Thu, Jun 09, 2022 at 12:44:11PM +0300, Petri Latvala wrote:
> > On Tue, Jun 07, 2022 at 07:24:09AM +0200, Zbigniew Kempczyński wrote:
> > > Add crc32 table for on-cpu crc calculation function. Other tables and
> > > algorithms should be added here allowing reuse tables for in-gpu crc
> > > calculation.
> > >
> > > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > ---
> > > .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> > > lib/igt_crc.c | 107 ++++++++++++++++++
> > > lib/igt_crc.h | 31 +++++
> > > lib/meson.build | 1 +
> > > 4 files changed, 140 insertions(+)
> > > create mode 100644 lib/igt_crc.c
> > > create mode 100644 lib/igt_crc.h
> > >
> > > diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > index 1774256530..b78f1eb6ff 100644
> > > --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > @@ -22,6 +22,7 @@
> > > <xi:include href="xml/igt_chamelium.xml"/>
> > > <xi:include href="xml/igt_collection.xml"/>
> > > <xi:include href="xml/igt_core.xml"/>
> > > + <xi:include href="xml/igt_crc.xml"/>
> > > <xi:include href="xml/igt_debugfs.xml"/>
> > > <xi:include href="xml/igt_device.xml"/>
> > > <xi:include href="xml/igt_device_scan.xml"/>
> > > diff --git a/lib/igt_crc.c b/lib/igt_crc.c
> > > new file mode 100644
> > > index 0000000000..e634f5cf27
> > > --- /dev/null
> > > +++ b/lib/igt_crc.c
> > > @@ -0,0 +1,107 @@
> > > +/*-
> > > + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
> > > + * code or tables extracted from it, as desired without restriction.
> > > + */
> > > +
> > > +/*
> > > + * First, the polynomial itself and its table of feedback terms. The
> > > + * polynomial is
> > > + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > > + *
> > > + * Note that we take it "backwards" and put the highest-order term in
> > > + * the lowest-order bit. The X^32 term is "implied"; the LSB is the
> > > + * X^31 term, etc. The X^0 term (usually shown as "+1") results in
> > > + * the MSB being 1
> > > + *
> > > + * Note that the usual hardware shift register implementation, which
> > > + * is what we're using (we're merely optimizing it by doing eight-bit
> > > + * chunks at a time) shifts bits into the lowest-order term. In our
> > > + * implementation, that means shifting towards the right. Why do we
> > > + * do it this way? Because the calculated CRC must be transmitted in
> > > + * order from highest-order term to lowest-order term. UARTs transmit
> > > + * characters in order from LSB to MSB. By storing the CRC this way
> > > + * we hand it to the UART in the order low-byte to high-byte; the UART
> > > + * sends each low-bit to hight-bit; and the result is transmission bit
> > > + * by bit from highest- to lowest-order term without requiring any bit
> > > + * shuffling on our part. Reception works similarly
> > > + *
> > > + * The feedback terms table consists of 256, 32-bit entries. Notes
> > > + *
> > > + * The table can be generated at runtime if desired; code to do so
> > > + * is shown later. It might not be obvious, but the feedback
> > > + * terms simply represent the results of eight shift/xor opera
> > > + * tions for all combinations of data and CRC register values
> > > + *
> > > + * The values must be right-shifted by eight bits by the "updcrc
> > > + * logic; the shift must be unsigned (bring in zeroes). On some
> > > + * hardware you could probably optimize the shift in assembler by
> > > + * using byte-swap instructions
> > > + * polynomial $edb88320
> >
> > This is also in the original code but... what?
>
> For of writing coefficients:
>
> X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
>
> bin(0xedb88320)
> 0b 1110 1101 1011 1000 1000 0011 0010 0000
> 012 45 7 8 22 23 26
> 10
> 11
> 12 16
>
> Here it is well explained:
> https://www.greenend.org.uk/rjk/tech/crc.html
Can the last sentence of the comment be restructured to be more
English? In the current form it's like
"While driving a car you could probably avoid obstacles
steering wheel"
--
Petri Latvala
>
> --
> Zbigniew
>
> >
> >
> > Anyway,
> > Reviewed-by: Petri Latvala <petri.latvala@intel.com>
> >
> >
> > > + *
> > > + *
> > > + * CRC32 code derived from work by Gary S. Brown.
> > > + */
> > > +
> > > +#include <stddef.h>
> > > +#include <stdint.h>
> > > +#include "igt_crc.h"
> > > +
> > > +const uint32_t igt_crc32_tab[256] = {
> > > + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
> > > + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
> > > + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
> > > + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
> > > + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
> > > + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
> > > + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
> > > + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
> > > + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
> > > + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
> > > + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
> > > + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
> > > + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
> > > + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
> > > + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
> > > + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
> > > + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
> > > + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
> > > + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
> > > + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
> > > + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
> > > + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
> > > + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
> > > + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
> > > + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
> > > + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
> > > + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
> > > + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
> > > + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
> > > + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
> > > + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
> > > + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
> > > + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
> > > + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
> > > + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
> > > + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
> > > + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
> > > + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
> > > + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
> > > + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
> > > + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
> > > + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
> > > + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
> > > +};
> > > +
> > > +uint32_t igt_cpu_crc32(const void *buf, size_t size)
> > > +{
> > > +
> > > + const uint8_t *p = buf;
> > > + uint32_t crc;
> > > +
> > > + crc = ~0U;
> > > +
> > > + while (size--)
> > > + crc = igt_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
> > > +
> > > + return crc ^ ~0U;
> > > +}
> > > diff --git a/lib/igt_crc.h b/lib/igt_crc.h
> > > new file mode 100644
> > > index 0000000000..5c0b934ea5
> > > --- /dev/null
> > > +++ b/lib/igt_crc.h
> > > @@ -0,0 +1,31 @@
> > > +// SPDX-License-Identifier: MIT
> > > +/*
> > > + * Copyright © 2022 Intel Corporation
> > > + */
> > > +
> > > +#ifndef __IGT_CRC_H__
> > > +#define __IGT_CRC_H__
> > > +
> > > +#include <stddef.h>
> > > +#include <stdint.h>
> > > +
> > > +/**
> > > + * SECTION:igt_crc
> > > + * @short_description: igt crc tables and calculation functions
> > > + * @title: CRC
> > > + * @include: igt_crc.h
> > > + *
> > > + * # Introduction
> > > + *
> > > + * Providing vendor agnostic crc calculation is useful to avoid code
> > > + * duplication. Especially if vendor will decide to do on-gpu crc calculation
> > > + * it will need to inject crc table to gpu.
> > > + *
> > > + * All crc tables are globals to allow direct in-code use.
> > > + */
> > > +
> > > +const uint32_t igt_crc32_tab[256];
> > > +
> > > +uint32_t igt_cpu_crc32(const void *buf, size_t size);
> > > +
> > > +#endif
> > > diff --git a/lib/meson.build b/lib/meson.build
> > > index 0a173c1fc6..cc2b2abee6 100644
> > > --- a/lib/meson.build
> > > +++ b/lib/meson.build
> > > @@ -15,6 +15,7 @@ lib_sources = [
> > > 'i915/i915_blt.c',
> > > 'igt_collection.c',
> > > 'igt_color_encoding.c',
> > > + 'igt_crc.c',
> > > 'igt_debugfs.c',
> > > 'igt_device.c',
> > > 'igt_device_scan.c',
> > > --
> > > 2.32.0
> > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test for DG2
2022-06-10 4:34 ` Zbigniew Kempczyński
@ 2022-06-10 8:34 ` Petri Latvala
0 siblings, 0 replies; 24+ messages in thread
From: Petri Latvala @ 2022-06-10 8:34 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Fri, Jun 10, 2022 at 06:34:51AM +0200, Zbigniew Kempczyński wrote:
> On Thu, Jun 09, 2022 at 12:52:22PM +0300, Petri Latvala wrote:
> > On Tue, Jun 07, 2022 at 07:24:11AM +0200, Zbigniew Kempczyński wrote:
> > > Add simple test which compares crc32 sums and calculation times on cpu
> > > and gpu.
> > >
> > > v2: - addressing review comments - igt_debug + igt_time_elapsed (Kamil)
> > > - exercise crc for size smaller than page size
> > >
> > > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > ---
> > > tests/i915/api_intel_bb.c | 63 +++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 63 insertions(+)
> > >
> > > diff --git a/tests/i915/api_intel_bb.c b/tests/i915/api_intel_bb.c
> > > index 92f44cecf4..d6998af692 100644
> > > --- a/tests/i915/api_intel_bb.c
> > > +++ b/tests/i915/api_intel_bb.c
> > > @@ -22,6 +22,7 @@
> > > */
> > >
> > > #include "igt.h"
> > > +#include "igt_crc.h"
> > > #include "i915/gem.h"
> > > #include "i915/gem_create.h"
> > > #include <unistd.h>
> > > @@ -38,6 +39,7 @@
> > > #include <zlib.h>
> > > #include "intel_bufops.h"
> > > #include "i915/gem_vm.h"
> > > +#include "i915/i915_crc.h"
> > >
> > > #define PAGE_SIZE 4096
> > >
> > > @@ -1395,6 +1397,51 @@ static void render_ccs(struct buf_ops *bops)
> > > igt_assert_f(fails == 0, "render-ccs fails: %d\n", fails);
> > > }
> > >
> > > +static void test_crc32(int i915, const intel_ctx_t *ctx,
> > > + const struct intel_execution_engine2 *e,
> > > + struct drm_i915_gem_memory_class_instance *r)
> > > +{
> > > + uint64_t ahnd = get_reloc_ahnd(i915, ctx->id);
> > > + uint32_t data, *ptr;
> > > +
> > > + uint32_t region = INTEL_MEMORY_REGION_ID(r->memory_class,
> > > + r->memory_instance);
> > > +
> > > + igt_debug("[engine: %s, region: %s]\n", e->name,
> > > + region == REGION_SMEM ? "smem" : "lmem");
> > > + for (int i = 2; i < 21; i += 2) {
> > > + struct timespec start, end;
> > > + uint64_t size = 1 << i;
> > > + uint32_t cpu_crc, gpu_crc;
> > > +
> > > + double cpu_time, gpu_time;
> > > +
> > > + data = gem_create_in_memory_regions(i915, size, region);
> > > + ptr = gem_mmap__device_coherent(i915, data, 0, size, PROT_WRITE);
> > > + for (int j = 0; j < size / sizeof(*ptr); j++)
> > > + ptr[j] = j;
> > > +
> > > + clock_gettime(CLOCK_MONOTONIC, &start);
> > > + cpu_crc = igt_cpu_crc32(ptr, size);
> > > + clock_gettime(CLOCK_MONOTONIC, &end);
> > > + cpu_time = igt_time_elapsed(&start, &end);
> > > + munmap(ptr, size);
> > > +
> > > + clock_gettime(CLOCK_MONOTONIC, &start);
> > > + gpu_crc = i915_crc32(i915, ahnd, ctx, e, data, size);
> > > + clock_gettime(CLOCK_MONOTONIC, &end);
> > > + gpu_time = igt_time_elapsed(&start, &end);
> >
> > Mandatory question: Explain choice of CLOCK_MONOTONIC
> > vs. CLOCK_MONOTONIC_RAW vs. CLOCK_MONOTONIC_COARSE. And as a
> > corollary, why igt_gettime's choice of monotonic clock type is not
> > sufficient.
>
> Ok, I've read the git log of igt_gettime() + man page and it seems
> the effect which we want to avoid is adjusting the time during test
> run. Especially if result of test may depend on time comparison.
>
> Why then there were no global replacement of clock_gettime(MONOTONIC)
> broadly used in many tests?
The typical reason: Legacy.
--
Petri Latvala
>
> Of course I'm going to use igt_gettime() now, so thanks for the review
> and comment.
>
> --
> Zbigniew
>
> >
> >
> > --
> > Petri Latvala
> >
> >
> >
> > > + igt_debug("size: %10lld, cpu crc: 0x%08x (time: %.3f), "
> > > + "gpu crc: 0x%08x (time: %.3f) [ %s ]\n",
> > > + (long long) size, cpu_crc, cpu_time, gpu_crc, gpu_time,
> > > + cpu_crc == gpu_crc ? "EQUAL" : "DIFFERENT");
> > > + gem_close(i915, data);
> > > + igt_assert(cpu_crc == gpu_crc);
> > > + }
> > > +
> > > + put_ahnd(ahnd);
> > > +}
> > > +
> > > static int opt_handler(int opt, int opt_index, void *data)
> > > {
> > > switch (opt) {
> > > @@ -1552,6 +1599,22 @@ igt_main_args("dpib", NULL, help_str, opt_handler, NULL)
> > > igt_subtest("render-ccs")
> > > render_ccs(bops);
> > >
> > > + igt_describe("Compare cpu and gpu crc32 sums on input object");
> > > + igt_subtest_with_dynamic_f("crc32") {
> > > + const intel_ctx_t *ctx;
> > > + const struct intel_execution_engine2 *e;
> > > +
> > > + igt_require(supports_i915_crc32(i915));
> > > +
> > > + ctx = intel_ctx_create_all_physical(i915);
> > > + for_each_ctx_engine(i915, ctx, e) {
> > > + for_each_memory_region(r, i915) {
> > > + igt_dynamic_f("%s-%s", e->name, r->name)
> > > + test_crc32(i915, ctx, e, &r->ci);
> > > + }
> > > + }
> > > + }
> > > +
> > > igt_fixture {
> > > buf_ops_destroy(bops);
> > > close(i915);
> > > --
> > > 2.32.0
> > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-10 7:53 ` Petri Latvala
@ 2022-06-13 3:57 ` Zbigniew Kempczyński
2022-06-13 5:26 ` Petri Latvala
0 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-13 3:57 UTC (permalink / raw)
To: Petri Latvala; +Cc: igt-dev
On Fri, Jun 10, 2022 at 10:53:48AM +0300, Petri Latvala wrote:
> On Fri, Jun 10, 2022 at 07:24:39AM +0200, Zbigniew Kempczyński wrote:
> > On Thu, Jun 09, 2022 at 12:44:11PM +0300, Petri Latvala wrote:
> > > On Tue, Jun 07, 2022 at 07:24:09AM +0200, Zbigniew Kempczyński wrote:
> > > > Add crc32 table for on-cpu crc calculation function. Other tables and
> > > > algorithms should be added here allowing reuse tables for in-gpu crc
> > > > calculation.
> > > >
> > > > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > > ---
> > > > .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> > > > lib/igt_crc.c | 107 ++++++++++++++++++
> > > > lib/igt_crc.h | 31 +++++
> > > > lib/meson.build | 1 +
> > > > 4 files changed, 140 insertions(+)
> > > > create mode 100644 lib/igt_crc.c
> > > > create mode 100644 lib/igt_crc.h
> > > >
> > > > diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > index 1774256530..b78f1eb6ff 100644
> > > > --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > @@ -22,6 +22,7 @@
> > > > <xi:include href="xml/igt_chamelium.xml"/>
> > > > <xi:include href="xml/igt_collection.xml"/>
> > > > <xi:include href="xml/igt_core.xml"/>
> > > > + <xi:include href="xml/igt_crc.xml"/>
> > > > <xi:include href="xml/igt_debugfs.xml"/>
> > > > <xi:include href="xml/igt_device.xml"/>
> > > > <xi:include href="xml/igt_device_scan.xml"/>
> > > > diff --git a/lib/igt_crc.c b/lib/igt_crc.c
> > > > new file mode 100644
> > > > index 0000000000..e634f5cf27
> > > > --- /dev/null
> > > > +++ b/lib/igt_crc.c
> > > > @@ -0,0 +1,107 @@
> > > > +/*-
> > > > + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
> > > > + * code or tables extracted from it, as desired without restriction.
> > > > + */
> > > > +
> > > > +/*
> > > > + * First, the polynomial itself and its table of feedback terms. The
> > > > + * polynomial is
> > > > + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > > > + *
> > > > + * Note that we take it "backwards" and put the highest-order term in
> > > > + * the lowest-order bit. The X^32 term is "implied"; the LSB is the
> > > > + * X^31 term, etc. The X^0 term (usually shown as "+1") results in
> > > > + * the MSB being 1
> > > > + *
> > > > + * Note that the usual hardware shift register implementation, which
> > > > + * is what we're using (we're merely optimizing it by doing eight-bit
> > > > + * chunks at a time) shifts bits into the lowest-order term. In our
> > > > + * implementation, that means shifting towards the right. Why do we
> > > > + * do it this way? Because the calculated CRC must be transmitted in
> > > > + * order from highest-order term to lowest-order term. UARTs transmit
> > > > + * characters in order from LSB to MSB. By storing the CRC this way
> > > > + * we hand it to the UART in the order low-byte to high-byte; the UART
> > > > + * sends each low-bit to hight-bit; and the result is transmission bit
> > > > + * by bit from highest- to lowest-order term without requiring any bit
> > > > + * shuffling on our part. Reception works similarly
> > > > + *
> > > > + * The feedback terms table consists of 256, 32-bit entries. Notes
> > > > + *
> > > > + * The table can be generated at runtime if desired; code to do so
> > > > + * is shown later. It might not be obvious, but the feedback
> > > > + * terms simply represent the results of eight shift/xor opera
> > > > + * tions for all combinations of data and CRC register values
> > > > + *
> > > > + * The values must be right-shifted by eight bits by the "updcrc
> > > > + * logic; the shift must be unsigned (bring in zeroes). On some
> > > > + * hardware you could probably optimize the shift in assembler by
> > > > + * using byte-swap instructions
> > > > + * polynomial $edb88320
> > >
> > > This is also in the original code but... what?
> >
> > For of writing coefficients:
> >
> > X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> >
> > bin(0xedb88320)
> > 0b 1110 1101 1011 1000 1000 0011 0010 0000
> > 012 45 7 8 22 23 26
> > 10
> > 11
> > 12 16
> >
> > Here it is well explained:
> > https://www.greenend.org.uk/rjk/tech/crc.html
>
> Can the last sentence of the comment be restructured to be more
> English? In the current form it's like
You mean in-code comment or my comment? If above I just copied it 1:1
and I would like to keep this intact. If mine I will send this in
next version.
--
Zbigniew
>
> "While driving a car you could probably avoid obstacles
> steering wheel"
>
>
>
> --
> Petri Latvala
>
>
> >
> > --
> > Zbigniew
> >
> > >
> > >
> > > Anyway,
> > > Reviewed-by: Petri Latvala <petri.latvala@intel.com>
> > >
> > >
> > > > + *
> > > > + *
> > > > + * CRC32 code derived from work by Gary S. Brown.
> > > > + */
> > > > +
> > > > +#include <stddef.h>
> > > > +#include <stdint.h>
> > > > +#include "igt_crc.h"
> > > > +
> > > > +const uint32_t igt_crc32_tab[256] = {
> > > > + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
> > > > + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
> > > > + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
> > > > + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
> > > > + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
> > > > + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
> > > > + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
> > > > + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
> > > > + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
> > > > + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
> > > > + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
> > > > + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
> > > > + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
> > > > + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
> > > > + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
> > > > + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
> > > > + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
> > > > + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
> > > > + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
> > > > + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
> > > > + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
> > > > + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
> > > > + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
> > > > + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
> > > > + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
> > > > + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
> > > > + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
> > > > + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
> > > > + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
> > > > + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
> > > > + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
> > > > + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
> > > > + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
> > > > + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
> > > > + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
> > > > + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
> > > > + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
> > > > + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
> > > > + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
> > > > + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
> > > > + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
> > > > + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
> > > > + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
> > > > +};
> > > > +
> > > > +uint32_t igt_cpu_crc32(const void *buf, size_t size)
> > > > +{
> > > > +
> > > > + const uint8_t *p = buf;
> > > > + uint32_t crc;
> > > > +
> > > > + crc = ~0U;
> > > > +
> > > > + while (size--)
> > > > + crc = igt_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
> > > > +
> > > > + return crc ^ ~0U;
> > > > +}
> > > > diff --git a/lib/igt_crc.h b/lib/igt_crc.h
> > > > new file mode 100644
> > > > index 0000000000..5c0b934ea5
> > > > --- /dev/null
> > > > +++ b/lib/igt_crc.h
> > > > @@ -0,0 +1,31 @@
> > > > +// SPDX-License-Identifier: MIT
> > > > +/*
> > > > + * Copyright © 2022 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef __IGT_CRC_H__
> > > > +#define __IGT_CRC_H__
> > > > +
> > > > +#include <stddef.h>
> > > > +#include <stdint.h>
> > > > +
> > > > +/**
> > > > + * SECTION:igt_crc
> > > > + * @short_description: igt crc tables and calculation functions
> > > > + * @title: CRC
> > > > + * @include: igt_crc.h
> > > > + *
> > > > + * # Introduction
> > > > + *
> > > > + * Providing vendor agnostic crc calculation is useful to avoid code
> > > > + * duplication. Especially if vendor will decide to do on-gpu crc calculation
> > > > + * it will need to inject crc table to gpu.
> > > > + *
> > > > + * All crc tables are globals to allow direct in-code use.
> > > > + */
> > > > +
> > > > +const uint32_t igt_crc32_tab[256];
> > > > +
> > > > +uint32_t igt_cpu_crc32(const void *buf, size_t size);
> > > > +
> > > > +#endif
> > > > diff --git a/lib/meson.build b/lib/meson.build
> > > > index 0a173c1fc6..cc2b2abee6 100644
> > > > --- a/lib/meson.build
> > > > +++ b/lib/meson.build
> > > > @@ -15,6 +15,7 @@ lib_sources = [
> > > > 'i915/i915_blt.c',
> > > > 'igt_collection.c',
> > > > 'igt_color_encoding.c',
> > > > + 'igt_crc.c',
> > > > 'igt_debugfs.c',
> > > > 'igt_device.c',
> > > > 'igt_device_scan.c',
> > > > --
> > > > 2.32.0
> > > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-13 3:57 ` Zbigniew Kempczyński
@ 2022-06-13 5:26 ` Petri Latvala
2022-06-13 6:23 ` Petri Latvala
0 siblings, 1 reply; 24+ messages in thread
From: Petri Latvala @ 2022-06-13 5:26 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Mon, Jun 13, 2022 at 05:57:02AM +0200, Zbigniew Kempczyński wrote:
> On Fri, Jun 10, 2022 at 10:53:48AM +0300, Petri Latvala wrote:
> > On Fri, Jun 10, 2022 at 07:24:39AM +0200, Zbigniew Kempczyński wrote:
> > > On Thu, Jun 09, 2022 at 12:44:11PM +0300, Petri Latvala wrote:
> > > > On Tue, Jun 07, 2022 at 07:24:09AM +0200, Zbigniew Kempczyński wrote:
> > > > > Add crc32 table for on-cpu crc calculation function. Other tables and
> > > > > algorithms should be added here allowing reuse tables for in-gpu crc
> > > > > calculation.
> > > > >
> > > > > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > > > ---
> > > > > .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> > > > > lib/igt_crc.c | 107 ++++++++++++++++++
> > > > > lib/igt_crc.h | 31 +++++
> > > > > lib/meson.build | 1 +
> > > > > 4 files changed, 140 insertions(+)
> > > > > create mode 100644 lib/igt_crc.c
> > > > > create mode 100644 lib/igt_crc.h
> > > > >
> > > > > diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > > index 1774256530..b78f1eb6ff 100644
> > > > > --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > > +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > > @@ -22,6 +22,7 @@
> > > > > <xi:include href="xml/igt_chamelium.xml"/>
> > > > > <xi:include href="xml/igt_collection.xml"/>
> > > > > <xi:include href="xml/igt_core.xml"/>
> > > > > + <xi:include href="xml/igt_crc.xml"/>
> > > > > <xi:include href="xml/igt_debugfs.xml"/>
> > > > > <xi:include href="xml/igt_device.xml"/>
> > > > > <xi:include href="xml/igt_device_scan.xml"/>
> > > > > diff --git a/lib/igt_crc.c b/lib/igt_crc.c
> > > > > new file mode 100644
> > > > > index 0000000000..e634f5cf27
> > > > > --- /dev/null
> > > > > +++ b/lib/igt_crc.c
> > > > > @@ -0,0 +1,107 @@
> > > > > +/*-
> > > > > + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
> > > > > + * code or tables extracted from it, as desired without restriction.
> > > > > + */
> > > > > +
> > > > > +/*
> > > > > + * First, the polynomial itself and its table of feedback terms. The
> > > > > + * polynomial is
> > > > > + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > > > > + *
> > > > > + * Note that we take it "backwards" and put the highest-order term in
> > > > > + * the lowest-order bit. The X^32 term is "implied"; the LSB is the
> > > > > + * X^31 term, etc. The X^0 term (usually shown as "+1") results in
> > > > > + * the MSB being 1
> > > > > + *
> > > > > + * Note that the usual hardware shift register implementation, which
> > > > > + * is what we're using (we're merely optimizing it by doing eight-bit
> > > > > + * chunks at a time) shifts bits into the lowest-order term. In our
> > > > > + * implementation, that means shifting towards the right. Why do we
> > > > > + * do it this way? Because the calculated CRC must be transmitted in
> > > > > + * order from highest-order term to lowest-order term. UARTs transmit
> > > > > + * characters in order from LSB to MSB. By storing the CRC this way
> > > > > + * we hand it to the UART in the order low-byte to high-byte; the UART
> > > > > + * sends each low-bit to hight-bit; and the result is transmission bit
> > > > > + * by bit from highest- to lowest-order term without requiring any bit
> > > > > + * shuffling on our part. Reception works similarly
> > > > > + *
> > > > > + * The feedback terms table consists of 256, 32-bit entries. Notes
> > > > > + *
> > > > > + * The table can be generated at runtime if desired; code to do so
> > > > > + * is shown later. It might not be obvious, but the feedback
> > > > > + * terms simply represent the results of eight shift/xor opera
> > > > > + * tions for all combinations of data and CRC register values
> > > > > + *
> > > > > + * The values must be right-shifted by eight bits by the "updcrc
> > > > > + * logic; the shift must be unsigned (bring in zeroes). On some
> > > > > + * hardware you could probably optimize the shift in assembler by
> > > > > + * using byte-swap instructions
> > > > > + * polynomial $edb88320
> > > >
> > > > This is also in the original code but... what?
> > >
> > > For of writing coefficients:
> > >
> > > X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > >
> > > bin(0xedb88320)
> > > 0b 1110 1101 1011 1000 1000 0011 0010 0000
> > > 012 45 7 8 22 23 26
> > > 10
> > > 11
> > > 12 16
> > >
> > > Here it is well explained:
> > > https://www.greenend.org.uk/rjk/tech/crc.html
> >
> > Can the last sentence of the comment be restructured to be more
> > English? In the current form it's like
>
> You mean in-code comment or my comment? If above I just copied it 1:1
> and I would like to keep this intact. If mine I will send this in
> next version.
The comment in the code.
--
Petri Latvala
>
> --
> Zbigniew
>
> >
> > "While driving a car you could probably avoid obstacles
> > steering wheel"
> >
> >
> >
> > --
> > Petri Latvala
> >
> >
> > >
> > > --
> > > Zbigniew
> > >
> > > >
> > > >
> > > > Anyway,
> > > > Reviewed-by: Petri Latvala <petri.latvala@intel.com>
> > > >
> > > >
> > > > > + *
> > > > > + *
> > > > > + * CRC32 code derived from work by Gary S. Brown.
> > > > > + */
> > > > > +
> > > > > +#include <stddef.h>
> > > > > +#include <stdint.h>
> > > > > +#include "igt_crc.h"
> > > > > +
> > > > > +const uint32_t igt_crc32_tab[256] = {
> > > > > + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
> > > > > + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
> > > > > + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
> > > > > + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
> > > > > + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
> > > > > + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
> > > > > + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
> > > > > + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
> > > > > + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
> > > > > + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
> > > > > + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
> > > > > + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
> > > > > + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
> > > > > + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
> > > > > + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
> > > > > + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
> > > > > + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
> > > > > + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
> > > > > + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
> > > > > + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
> > > > > + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
> > > > > + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
> > > > > + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
> > > > > + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
> > > > > + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
> > > > > + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
> > > > > + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
> > > > > + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
> > > > > + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
> > > > > + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
> > > > > + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
> > > > > + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
> > > > > + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
> > > > > + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
> > > > > + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
> > > > > + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
> > > > > + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
> > > > > + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
> > > > > + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
> > > > > + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
> > > > > + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
> > > > > + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
> > > > > + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
> > > > > +};
> > > > > +
> > > > > +uint32_t igt_cpu_crc32(const void *buf, size_t size)
> > > > > +{
> > > > > +
> > > > > + const uint8_t *p = buf;
> > > > > + uint32_t crc;
> > > > > +
> > > > > + crc = ~0U;
> > > > > +
> > > > > + while (size--)
> > > > > + crc = igt_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8);
> > > > > +
> > > > > + return crc ^ ~0U;
> > > > > +}
> > > > > diff --git a/lib/igt_crc.h b/lib/igt_crc.h
> > > > > new file mode 100644
> > > > > index 0000000000..5c0b934ea5
> > > > > --- /dev/null
> > > > > +++ b/lib/igt_crc.h
> > > > > @@ -0,0 +1,31 @@
> > > > > +// SPDX-License-Identifier: MIT
> > > > > +/*
> > > > > + * Copyright © 2022 Intel Corporation
> > > > > + */
> > > > > +
> > > > > +#ifndef __IGT_CRC_H__
> > > > > +#define __IGT_CRC_H__
> > > > > +
> > > > > +#include <stddef.h>
> > > > > +#include <stdint.h>
> > > > > +
> > > > > +/**
> > > > > + * SECTION:igt_crc
> > > > > + * @short_description: igt crc tables and calculation functions
> > > > > + * @title: CRC
> > > > > + * @include: igt_crc.h
> > > > > + *
> > > > > + * # Introduction
> > > > > + *
> > > > > + * Providing vendor agnostic crc calculation is useful to avoid code
> > > > > + * duplication. Especially if vendor will decide to do on-gpu crc calculation
> > > > > + * it will need to inject crc table to gpu.
> > > > > + *
> > > > > + * All crc tables are globals to allow direct in-code use.
> > > > > + */
> > > > > +
> > > > > +const uint32_t igt_crc32_tab[256];
> > > > > +
> > > > > +uint32_t igt_cpu_crc32(const void *buf, size_t size);
> > > > > +
> > > > > +#endif
> > > > > diff --git a/lib/meson.build b/lib/meson.build
> > > > > index 0a173c1fc6..cc2b2abee6 100644
> > > > > --- a/lib/meson.build
> > > > > +++ b/lib/meson.build
> > > > > @@ -15,6 +15,7 @@ lib_sources = [
> > > > > 'i915/i915_blt.c',
> > > > > 'igt_collection.c',
> > > > > 'igt_color_encoding.c',
> > > > > + 'igt_crc.c',
> > > > > 'igt_debugfs.c',
> > > > > 'igt_device.c',
> > > > > 'igt_device_scan.c',
> > > > > --
> > > > > 2.32.0
> > > > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions
2022-06-13 5:26 ` Petri Latvala
@ 2022-06-13 6:23 ` Petri Latvala
0 siblings, 0 replies; 24+ messages in thread
From: Petri Latvala @ 2022-06-13 6:23 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Mon, Jun 13, 2022 at 08:26:36AM +0300, Petri Latvala wrote:
> On Mon, Jun 13, 2022 at 05:57:02AM +0200, Zbigniew Kempczyński wrote:
> > On Fri, Jun 10, 2022 at 10:53:48AM +0300, Petri Latvala wrote:
> > > On Fri, Jun 10, 2022 at 07:24:39AM +0200, Zbigniew Kempczyński wrote:
> > > > On Thu, Jun 09, 2022 at 12:44:11PM +0300, Petri Latvala wrote:
> > > > > On Tue, Jun 07, 2022 at 07:24:09AM +0200, Zbigniew Kempczyński wrote:
> > > > > > Add crc32 table for on-cpu crc calculation function. Other tables and
> > > > > > algorithms should be added here allowing reuse tables for in-gpu crc
> > > > > > calculation.
> > > > > >
> > > > > > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > > > > > ---
> > > > > > .../igt-gpu-tools/igt-gpu-tools-docs.xml | 1 +
> > > > > > lib/igt_crc.c | 107 ++++++++++++++++++
> > > > > > lib/igt_crc.h | 31 +++++
> > > > > > lib/meson.build | 1 +
> > > > > > 4 files changed, 140 insertions(+)
> > > > > > create mode 100644 lib/igt_crc.c
> > > > > > create mode 100644 lib/igt_crc.h
> > > > > >
> > > > > > diff --git a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > > > index 1774256530..b78f1eb6ff 100644
> > > > > > --- a/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > > > +++ b/docs/reference/igt-gpu-tools/igt-gpu-tools-docs.xml
> > > > > > @@ -22,6 +22,7 @@
> > > > > > <xi:include href="xml/igt_chamelium.xml"/>
> > > > > > <xi:include href="xml/igt_collection.xml"/>
> > > > > > <xi:include href="xml/igt_core.xml"/>
> > > > > > + <xi:include href="xml/igt_crc.xml"/>
> > > > > > <xi:include href="xml/igt_debugfs.xml"/>
> > > > > > <xi:include href="xml/igt_device.xml"/>
> > > > > > <xi:include href="xml/igt_device_scan.xml"/>
> > > > > > diff --git a/lib/igt_crc.c b/lib/igt_crc.c
> > > > > > new file mode 100644
> > > > > > index 0000000000..e634f5cf27
> > > > > > --- /dev/null
> > > > > > +++ b/lib/igt_crc.c
> > > > > > @@ -0,0 +1,107 @@
> > > > > > +/*-
> > > > > > + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or
> > > > > > + * code or tables extracted from it, as desired without restriction.
> > > > > > + */
> > > > > > +
> > > > > > +/*
> > > > > > + * First, the polynomial itself and its table of feedback terms. The
> > > > > > + * polynomial is
> > > > > > + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > > > > > + *
> > > > > > + * Note that we take it "backwards" and put the highest-order term in
> > > > > > + * the lowest-order bit. The X^32 term is "implied"; the LSB is the
> > > > > > + * X^31 term, etc. The X^0 term (usually shown as "+1") results in
> > > > > > + * the MSB being 1
> > > > > > + *
> > > > > > + * Note that the usual hardware shift register implementation, which
> > > > > > + * is what we're using (we're merely optimizing it by doing eight-bit
> > > > > > + * chunks at a time) shifts bits into the lowest-order term. In our
> > > > > > + * implementation, that means shifting towards the right. Why do we
> > > > > > + * do it this way? Because the calculated CRC must be transmitted in
> > > > > > + * order from highest-order term to lowest-order term. UARTs transmit
> > > > > > + * characters in order from LSB to MSB. By storing the CRC this way
> > > > > > + * we hand it to the UART in the order low-byte to high-byte; the UART
> > > > > > + * sends each low-bit to hight-bit; and the result is transmission bit
> > > > > > + * by bit from highest- to lowest-order term without requiring any bit
> > > > > > + * shuffling on our part. Reception works similarly
> > > > > > + *
> > > > > > + * The feedback terms table consists of 256, 32-bit entries. Notes
> > > > > > + *
> > > > > > + * The table can be generated at runtime if desired; code to do so
> > > > > > + * is shown later. It might not be obvious, but the feedback
> > > > > > + * terms simply represent the results of eight shift/xor opera
> > > > > > + * tions for all combinations of data and CRC register values
> > > > > > + *
> > > > > > + * The values must be right-shifted by eight bits by the "updcrc
> > > > > > + * logic; the shift must be unsigned (bring in zeroes). On some
> > > > > > + * hardware you could probably optimize the shift in assembler by
> > > > > > + * using byte-swap instructions
> > > > > > + * polynomial $edb88320
> > > > >
> > > > > This is also in the original code but... what?
> > > >
> > > > For of writing coefficients:
> > > >
> > > > X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0
> > > >
> > > > bin(0xedb88320)
> > > > 0b 1110 1101 1011 1000 1000 0011 0010 0000
> > > > 012 45 7 8 22 23 26
> > > > 10
> > > > 11
> > > > 12 16
> > > >
> > > > Here it is well explained:
> > > > https://www.greenend.org.uk/rjk/tech/crc.html
> > >
> > > Can the last sentence of the comment be restructured to be more
> > > English? In the current form it's like
> >
> > You mean in-code comment or my comment? If above I just copied it 1:1
> > and I would like to keep this intact. If mine I will send this in
> > next version.
>
> The comment in the code.
Meh, everyone who copies the code seems to be just carrying the
comment as is. Might as well do the same here.
--
Petri Latvala
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates
2022-06-10 7:07 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
@ 2022-06-10 11:19 ` Petri Latvala
0 siblings, 0 replies; 24+ messages in thread
From: Petri Latvala @ 2022-06-10 11:19 UTC (permalink / raw)
To: Zbigniew Kempczyński; +Cc: igt-dev
On Fri, Jun 10, 2022 at 09:07:48AM +0200, Zbigniew Kempczyński wrote:
> In few tests we got some MI_* duplicates (MI_MATH for example).
> Add common definitions in intel_reg.h and remove local definitions
> in the tests.
>
> v2: Definitions MI_LOAD_REGISTER_MEM_GEN8 was removed so from now
> on user will need to encode length on it own. :
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
> ---
> benchmarks/gem_wsim.c | 31 ------------------------
> lib/intel_aux_pgtable.c | 4 +--
> lib/intel_reg.h | 47 +++++++++++++++++++++++++++++++++++-
> tests/i915/gem_exec_fair.c | 27 ---------------------
> tests/i915/gem_exec_fence.c | 43 +++++----------------------------
> tests/i915/gem_watchdog.c | 27 ---------------------
> tests/i915/gem_workarounds.c | 4 +--
> tests/i915/gen7_exec_parse.c | 6 ++---
> tests/i915/gen9_exec_parse.c | 11 +++------
> 9 files changed, 61 insertions(+), 139 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index d14352225e..2d60135817 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -279,38 +279,7 @@ static uint64_t ns_to_ctx_ticks(uint64_t ns)
> return div64_u64_round_up(ns * f, NSEC_PER_SEC);
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -#define MI_ARB_CHECK MI_INSTR(0x5, 0)
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> -#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
> -#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 0)
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -#define MI_CS_MMIO_DST BIT(19)
> -#define MI_CS_MMIO_SRC BIT(18)
>
> static unsigned int offset_in_page(void *addr)
> {
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> index e31a6c343d..7556351a02 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -644,11 +644,11 @@ gen12_emit_aux_pgtable_state(struct intel_bb *ibb, uint32_t state, bool render)
> if (!state)
> return;
>
> - intel_bb_out(ibb, MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
> + intel_bb_out(ibb, MI_LOAD_REGISTER_MEM | MI_MMIO_REMAP_ENABLE_GEN12 | 2);
> intel_bb_out(ibb, table_base_reg);
> intel_bb_emit_reloc(ibb, ibb->handle, 0, 0, state, ibb->batch_offset);
>
> - intel_bb_out(ibb, MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
> + intel_bb_out(ibb, MI_LOAD_REGISTER_MEM | MI_MMIO_REMAP_ENABLE_GEN12 | 2);
> intel_bb_out(ibb, table_base_reg + 4);
> intel_bb_emit_reloc(ibb, ibb->handle, 0, 0, state + 4, ibb->batch_offset);
> }
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index e26ee82a5b..e4d1f1c263 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2623,8 +2623,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
>
> #define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
> #define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
> -#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
> +#define MI_LOAD_REGISTER_REG ((0x2A << 23) | 1)
> +#define MI_LOAD_REGISTER_MEM (0x29 << 23)
> +#define MI_CS_MMIO_DST (1 << 19)
> +#define MI_CS_MMIO_SRC (1 << 18)
> #define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
> +#define MI_WPARID_ENABLE_GEN12 (1 << 16)
> +#define MI_STORE_REGISTER_MEM (0x24 << 23)
> +#define MI_STORE_PREDICATE_ENABLE_GEN12 (1 << 21)
>
> /* Flush */
> #define MI_FLUSH (0x04<<23)
> @@ -2642,6 +2648,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> #define MI_NOOP_WRITE_ID (1<<22)
> #define MI_NOOP_ID_MASK (1<<22 - 1)
>
> +/* ARB Check */
> +#define MI_ARB_CHECK (0x5 << 23)
> +
> #define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
>
> /* Atomics */
> @@ -2657,12 +2666,48 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> #define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
> #define MI_BATCH_BUFFER_END (0xA << 23)
> #define MI_COND_BATCH_BUFFER_END (0x36 << 23)
> +#define MAD_GT_IDD (0 << 12)
> +#define MAD_GT_OR_EQ_IDD (1 << 12)
> +#define MAD_LT_IDD (2 << 12)
> +#define MAD_LT_OR_EQ_IDD (3 << 12)
> +#define MAD_EQ_IDD (4 << 12)
> +#define MAD_NEQ_IDD (5 << 12)
> #define MI_DO_COMPARE (1 << 21)
>
> #define MI_BATCH_NON_SECURE (1)
> #define MI_BATCH_NON_SECURE_I965 (1 << 8)
> #define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */
>
> +/* Math */
> +#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> +#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> +#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> +/* Opcodes for MI_MATH_INSTR */
> +#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> +#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> +#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> +#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> +#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> +#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> +#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> +#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> +#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> +#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> +#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> +#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> +/* DG2+ */
> +#define MI_MATH_SHL MI_MATH_INSTR(0x105, 0x0, 0x0)
> +#define MI_MATH_SHR MI_MATH_INSTR(0x106, 0x0, 0x0)
> +#define MI_MATH_SAR MI_MATH_INSTR(0x107, 0x0, 0x0)
> +
> +/* Registers used as operands in MI_MATH_INSTR */
> +#define MI_MATH_REG(x) (x)
> +#define MI_MATH_REG_SRCA 0x20
> +#define MI_MATH_REG_SRCB 0x21
> +#define MI_MATH_REG_ACCU 0x31
> +#define MI_MATH_REG_ZF 0x32
> +#define MI_MATH_REG_CF 0x33
> +
> #define MAX_DISPLAY_PIPES 2
>
> typedef enum {
> diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
> index 935f9c4a0b..89921697f7 100644
> --- a/tests/i915/gem_exec_fair.c
> +++ b/tests/i915/gem_exec_fair.c
> @@ -112,33 +112,6 @@ static uint64_t ticks_to_ns(int i915, uint64_t ticks)
> read_timestamp_frequency(i915));
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> -#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -
> static void delay(int i915,
> const struct intel_execution_engine2 *e,
> uint32_t handle,
> diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
> index 47ddf3083d..b7ce425d81 100644
> --- a/tests/i915/gem_exec_fence.c
> +++ b/tests/i915/gem_exec_fence.c
> @@ -2366,37 +2366,6 @@ static void test_syncobj_timeline_multiple_ext_nodes(int fd)
> syncobj_destroy(fd, syncobjs[i]);
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -/* #define MI_LOAD_REGISTER_MEM (MI_INSTR(0x29, 1) */
> -/* #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) */
> -
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -
> -#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
> -#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x00, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x80, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> #define HSW_CS_GPR(n) (0x600 + 8*(n))
> #define RING_TIMESTAMP (0x358)
> #define MI_PREDICATE_RESULT_1 (0x41c)
> @@ -2610,23 +2579,23 @@ static void build_increment_engine_bb(struct inter_engine_batches *batch,
> {
> uint32_t *bb = batch->increment_bb = calloc(1, 4096);
>
> - *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
> + *bb++ = MI_LOAD_REGISTER_MEM | 2;
> *bb++ = mmio_base + HSW_CS_GPR(0);
> batch->read0_ptrs[0] = bb;
> *bb++ = 0;
> *bb++ = 0;
> - *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
> + *bb++ = MI_LOAD_REGISTER_MEM | 2;
> *bb++ = mmio_base + HSW_CS_GPR(0) + 4;
> batch->read0_ptrs[1] = bb;
> *bb++ = 0;
> *bb++ = 0;
>
> - *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
> + *bb++ = MI_LOAD_REGISTER_MEM | 2;
> *bb++ = mmio_base + HSW_CS_GPR(1);
> batch->read1_ptrs[0] = bb;
> *bb++ = 0;
> *bb++ = 0;
> - *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
> + *bb++ = MI_LOAD_REGISTER_MEM | 2;
> *bb++ = mmio_base + HSW_CS_GPR(1) + 4;
> batch->read1_ptrs[1] = bb;
> *bb++ = 0;
> @@ -2638,12 +2607,12 @@ static void build_increment_engine_bb(struct inter_engine_batches *batch,
> *bb++ = MI_MATH_ADD;
> *bb++ = MI_MATH_STORE(MI_MATH_REG(0), MI_MATH_REG_ACCU);
>
> - *bb++ = MI_STORE_REGISTER_MEM_GEN8;
> + *bb++ = MI_STORE_REGISTER_MEM | 2;
> *bb++ = mmio_base + HSW_CS_GPR(0);
> batch->write_ptrs[0] = bb;
> *bb++ = 0;
> *bb++ = 0;
> - *bb++ = MI_STORE_REGISTER_MEM_GEN8;
> + *bb++ = MI_STORE_REGISTER_MEM | 2;
> *bb++ = mmio_base + HSW_CS_GPR(0) + 4;
> batch->write_ptrs[1] = bb;
> *bb++ = 0;
> diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
> index fc1ba00712..01eb007694 100644
> --- a/tests/i915/gem_watchdog.c
> +++ b/tests/i915/gem_watchdog.c
> @@ -270,33 +270,6 @@ static void virtual(int i915, const intel_ctx_cfg_t *base_cfg)
> igt_assert_eq(count, expect);
> }
>
> -#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
> -
> -#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
> -#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
> -/* Opcodes for MI_MATH_INSTR */
> -#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
> -#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
> -#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
> -#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
> -#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
> -#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
> -#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
> -#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
> -#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
> -#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
> -#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
> -#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
> -/* Registers used as operands in MI_MATH_INSTR */
> -#define MI_MATH_REG(x) (x)
> -#define MI_MATH_REG_SRCA 0x20
> -#define MI_MATH_REG_SRCB 0x21
> -#define MI_MATH_REG_ACCU 0x31
> -#define MI_MATH_REG_ZF 0x32
> -#define MI_MATH_REG_CF 0x33
> -
> -#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
> -
> static unsigned int offset_in_page(void *addr)
> {
> return (uintptr_t)addr & 4095;
> diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
> index 70967b3ff5..fc5184925a 100644
> --- a/tests/i915/gem_workarounds.c
> +++ b/tests/i915/gem_workarounds.c
> @@ -83,8 +83,6 @@ static bool write_only(const uint32_t addr)
> return false;
> }
>
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> -
> static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
> {
> struct drm_i915_gem_exec_object2 obj[2];
> @@ -122,7 +120,7 @@ static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
> out = base =
> gem_mmap__cpu(i915, obj[1].handle, 0, batch_sz, PROT_WRITE);
> for (int i = 0; i < num_wa_regs; i++) {
> - *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
> + *out++ = MI_STORE_REGISTER_MEM | (1 + (gen >= 8));
> *out++ = wa_regs[i].addr;
> reloc[i].target_handle = obj[0].handle;
> reloc[i].offset = (out - base) * sizeof(*out);
> diff --git a/tests/i915/gen7_exec_parse.c b/tests/i915/gen7_exec_parse.c
> index c83a791126..69b768ed29 100644
> --- a/tests/i915/gen7_exec_parse.c
> +++ b/tests/i915/gen7_exec_parse.c
> @@ -48,8 +48,6 @@
> #define INSTR_CLIENT_SHIFT 29
> #define INSTR_INVALID_CLIENT 0x7
>
> -#define MI_LOAD_REGISTER_REG (0x2a << 23)
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> #define MI_ARB_ON_OFF (0x8 << 23)
> #define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
>
> @@ -374,7 +372,7 @@ static void test_allocations(int fd)
> static void hsw_load_register_reg(void)
> {
> uint32_t init_gpr0[16] = {
> - MI_LOAD_REGISTER_IMM | (3 - 2),
> + MI_LOAD_REGISTER_IMM,
> HSW_CS_GPR0,
> 0xabcdabc0, /* leave [1:0] zero */
> MI_BATCH_BUFFER_END,
> @@ -386,7 +384,7 @@ static void hsw_load_register_reg(void)
> MI_BATCH_BUFFER_END,
> };
> uint32_t do_lrr[16] = {
> - MI_LOAD_REGISTER_REG | (3 - 2),
> + MI_LOAD_REGISTER_REG,
> 0, /* [1] = src */
> HSW_CS_GPR0, /* dst */
> MI_BATCH_BUFFER_END,
> diff --git a/tests/i915/gen9_exec_parse.c b/tests/i915/gen9_exec_parse.c
> index fa61693cfc..c8743a78a0 100644
> --- a/tests/i915/gen9_exec_parse.c
> +++ b/tests/i915/gen9_exec_parse.c
> @@ -38,12 +38,9 @@
> #define INSTR_CLIENT_SHIFT 29
> #define INSTR_INVALID_CLIENT 0x7
>
> -#define MI_LOAD_REGISTER_REG (0x2a << 23)
> -#define MI_STORE_REGISTER_MEM (0x24 << 23)
> #define MI_ARB_ON_OFF (0x8 << 23)
> #define MI_USER_INTERRUPT (0x02 << 23)
> #define MI_FLUSH_DW (0x26 << 23)
> -#define MI_ARB_CHECK (0x05 << 23)
> #define MI_REPORT_HEAD (0x07 << 23)
> #define MI_SUSPEND_FLUSH (0x0b << 23)
> #define MI_LOAD_SCAN_LINES_EXCL (0x13 << 23)
> @@ -689,7 +686,7 @@ static void test_cmd_crossing_page(const int i915, const uint32_t handle)
> MI_BATCH_BUFFER_END,
> };
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM | 2,
> BCS_GPR(0),
> 0, /* reloc */
> 0, /* reloc */
> @@ -728,7 +725,7 @@ static void test_invalid_length(const int i915, const uint32_t handle)
> };
>
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM | 2,
> BCS_GPR(0),
> 0, /* reloc */
> 0, /* reloc */
> @@ -841,7 +838,7 @@ static void test_register(const int i915, const uint32_t handle,
> };
>
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM | 2,
> r->addr,
> 0, /* reloc */
> 0, /* reloc */
> @@ -880,7 +877,7 @@ static long int read_reg(const int i915, const uint32_t handle,
> const uint32_t addr)
> {
> const uint32_t store_reg[] = {
> - MI_STORE_REGISTER_MEM | (4 - 2),
> + MI_STORE_REGISTER_MEM | 2,
> addr,
> 0, /* reloc */
> 0, /* reloc */
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates
2022-06-10 7:07 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
@ 2022-06-10 7:07 ` Zbigniew Kempczyński
2022-06-10 11:19 ` Petri Latvala
0 siblings, 1 reply; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-10 7:07 UTC (permalink / raw)
To: igt-dev
In few tests we got some MI_* duplicates (MI_MATH for example).
Add common definitions in intel_reg.h and remove local definitions
in the tests.
v2: Definitions MI_LOAD_REGISTER_MEM_GEN8 was removed so from now
on user will need to encode length on it own. :
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
benchmarks/gem_wsim.c | 31 ------------------------
lib/intel_aux_pgtable.c | 4 +--
lib/intel_reg.h | 47 +++++++++++++++++++++++++++++++++++-
tests/i915/gem_exec_fair.c | 27 ---------------------
tests/i915/gem_exec_fence.c | 43 +++++----------------------------
tests/i915/gem_watchdog.c | 27 ---------------------
tests/i915/gem_workarounds.c | 4 +--
tests/i915/gen7_exec_parse.c | 6 ++---
tests/i915/gen9_exec_parse.c | 11 +++------
9 files changed, 61 insertions(+), 139 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index d14352225e..2d60135817 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -279,38 +279,7 @@ static uint64_t ns_to_ctx_ticks(uint64_t ns)
return div64_u64_round_up(ns * f, NSEC_PER_SEC);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_ARB_CHECK MI_INSTR(0x5, 0)
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
-#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 0)
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-#define MI_CS_MMIO_DST BIT(19)
-#define MI_CS_MMIO_SRC BIT(18)
static unsigned int offset_in_page(void *addr)
{
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index e31a6c343d..7556351a02 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -644,11 +644,11 @@ gen12_emit_aux_pgtable_state(struct intel_bb *ibb, uint32_t state, bool render)
if (!state)
return;
- intel_bb_out(ibb, MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
+ intel_bb_out(ibb, MI_LOAD_REGISTER_MEM | MI_MMIO_REMAP_ENABLE_GEN12 | 2);
intel_bb_out(ibb, table_base_reg);
intel_bb_emit_reloc(ibb, ibb->handle, 0, 0, state, ibb->batch_offset);
- intel_bb_out(ibb, MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
+ intel_bb_out(ibb, MI_LOAD_REGISTER_MEM | MI_MMIO_REMAP_ENABLE_GEN12 | 2);
intel_bb_out(ibb, table_base_reg + 4);
intel_bb_emit_reloc(ibb, ibb->handle, 0, 0, state + 4, ibb->batch_offset);
}
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index e26ee82a5b..e4d1f1c263 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2623,8 +2623,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
-#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
+#define MI_LOAD_REGISTER_REG ((0x2A << 23) | 1)
+#define MI_LOAD_REGISTER_MEM (0x29 << 23)
+#define MI_CS_MMIO_DST (1 << 19)
+#define MI_CS_MMIO_SRC (1 << 18)
#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
+#define MI_WPARID_ENABLE_GEN12 (1 << 16)
+#define MI_STORE_REGISTER_MEM (0x24 << 23)
+#define MI_STORE_PREDICATE_ENABLE_GEN12 (1 << 21)
/* Flush */
#define MI_FLUSH (0x04<<23)
@@ -2642,6 +2648,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_NOOP_WRITE_ID (1<<22)
#define MI_NOOP_ID_MASK (1<<22 - 1)
+/* ARB Check */
+#define MI_ARB_CHECK (0x5 << 23)
+
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
/* Atomics */
@@ -2657,12 +2666,48 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
#define MI_BATCH_BUFFER_END (0xA << 23)
#define MI_COND_BATCH_BUFFER_END (0x36 << 23)
+#define MAD_GT_IDD (0 << 12)
+#define MAD_GT_OR_EQ_IDD (1 << 12)
+#define MAD_LT_IDD (2 << 12)
+#define MAD_LT_OR_EQ_IDD (3 << 12)
+#define MAD_EQ_IDD (4 << 12)
+#define MAD_NEQ_IDD (5 << 12)
#define MI_DO_COMPARE (1 << 21)
#define MI_BATCH_NON_SECURE (1)
#define MI_BATCH_NON_SECURE_I965 (1 << 8)
#define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */
+/* Math */
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
+/* DG2+ */
+#define MI_MATH_SHL MI_MATH_INSTR(0x105, 0x0, 0x0)
+#define MI_MATH_SHR MI_MATH_INSTR(0x106, 0x0, 0x0)
+#define MI_MATH_SAR MI_MATH_INSTR(0x107, 0x0, 0x0)
+
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x) (x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF 0x32
+#define MI_MATH_REG_CF 0x33
+
#define MAX_DISPLAY_PIPES 2
typedef enum {
diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
index 935f9c4a0b..89921697f7 100644
--- a/tests/i915/gem_exec_fair.c
+++ b/tests/i915/gem_exec_fair.c
@@ -112,33 +112,6 @@ static uint64_t ticks_to_ns(int i915, uint64_t ticks)
read_timestamp_frequency(i915));
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
static void delay(int i915,
const struct intel_execution_engine2 *e,
uint32_t handle,
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 47ddf3083d..b7ce425d81 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -2366,37 +2366,6 @@ static void test_syncobj_timeline_multiple_ext_nodes(int fd)
syncobj_destroy(fd, syncobjs[i]);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-/* #define MI_LOAD_REGISTER_MEM (MI_INSTR(0x29, 1) */
-/* #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) */
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
-#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
-#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x00, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x80, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
#define HSW_CS_GPR(n) (0x600 + 8*(n))
#define RING_TIMESTAMP (0x358)
#define MI_PREDICATE_RESULT_1 (0x41c)
@@ -2610,23 +2579,23 @@ static void build_increment_engine_bb(struct inter_engine_batches *batch,
{
uint32_t *bb = batch->increment_bb = calloc(1, 4096);
- *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
+ *bb++ = MI_LOAD_REGISTER_MEM | 2;
*bb++ = mmio_base + HSW_CS_GPR(0);
batch->read0_ptrs[0] = bb;
*bb++ = 0;
*bb++ = 0;
- *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
+ *bb++ = MI_LOAD_REGISTER_MEM | 2;
*bb++ = mmio_base + HSW_CS_GPR(0) + 4;
batch->read0_ptrs[1] = bb;
*bb++ = 0;
*bb++ = 0;
- *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
+ *bb++ = MI_LOAD_REGISTER_MEM | 2;
*bb++ = mmio_base + HSW_CS_GPR(1);
batch->read1_ptrs[0] = bb;
*bb++ = 0;
*bb++ = 0;
- *bb++ = MI_LOAD_REGISTER_MEM_GEN8;
+ *bb++ = MI_LOAD_REGISTER_MEM | 2;
*bb++ = mmio_base + HSW_CS_GPR(1) + 4;
batch->read1_ptrs[1] = bb;
*bb++ = 0;
@@ -2638,12 +2607,12 @@ static void build_increment_engine_bb(struct inter_engine_batches *batch,
*bb++ = MI_MATH_ADD;
*bb++ = MI_MATH_STORE(MI_MATH_REG(0), MI_MATH_REG_ACCU);
- *bb++ = MI_STORE_REGISTER_MEM_GEN8;
+ *bb++ = MI_STORE_REGISTER_MEM | 2;
*bb++ = mmio_base + HSW_CS_GPR(0);
batch->write_ptrs[0] = bb;
*bb++ = 0;
*bb++ = 0;
- *bb++ = MI_STORE_REGISTER_MEM_GEN8;
+ *bb++ = MI_STORE_REGISTER_MEM | 2;
*bb++ = mmio_base + HSW_CS_GPR(0) + 4;
batch->write_ptrs[1] = bb;
*bb++ = 0;
diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
index fc1ba00712..01eb007694 100644
--- a/tests/i915/gem_watchdog.c
+++ b/tests/i915/gem_watchdog.c
@@ -270,33 +270,6 @@ static void virtual(int i915, const intel_ctx_cfg_t *base_cfg)
igt_assert_eq(count, expect);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
static unsigned int offset_in_page(void *addr)
{
return (uintptr_t)addr & 4095;
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 70967b3ff5..fc5184925a 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -83,8 +83,6 @@ static bool write_only(const uint32_t addr)
return false;
}
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
-
static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
{
struct drm_i915_gem_exec_object2 obj[2];
@@ -122,7 +120,7 @@ static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
out = base =
gem_mmap__cpu(i915, obj[1].handle, 0, batch_sz, PROT_WRITE);
for (int i = 0; i < num_wa_regs; i++) {
- *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
+ *out++ = MI_STORE_REGISTER_MEM | (1 + (gen >= 8));
*out++ = wa_regs[i].addr;
reloc[i].target_handle = obj[0].handle;
reloc[i].offset = (out - base) * sizeof(*out);
diff --git a/tests/i915/gen7_exec_parse.c b/tests/i915/gen7_exec_parse.c
index c83a791126..69b768ed29 100644
--- a/tests/i915/gen7_exec_parse.c
+++ b/tests/i915/gen7_exec_parse.c
@@ -48,8 +48,6 @@
#define INSTR_CLIENT_SHIFT 29
#define INSTR_INVALID_CLIENT 0x7
-#define MI_LOAD_REGISTER_REG (0x2a << 23)
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
#define MI_ARB_ON_OFF (0x8 << 23)
#define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
@@ -374,7 +372,7 @@ static void test_allocations(int fd)
static void hsw_load_register_reg(void)
{
uint32_t init_gpr0[16] = {
- MI_LOAD_REGISTER_IMM | (3 - 2),
+ MI_LOAD_REGISTER_IMM,
HSW_CS_GPR0,
0xabcdabc0, /* leave [1:0] zero */
MI_BATCH_BUFFER_END,
@@ -386,7 +384,7 @@ static void hsw_load_register_reg(void)
MI_BATCH_BUFFER_END,
};
uint32_t do_lrr[16] = {
- MI_LOAD_REGISTER_REG | (3 - 2),
+ MI_LOAD_REGISTER_REG,
0, /* [1] = src */
HSW_CS_GPR0, /* dst */
MI_BATCH_BUFFER_END,
diff --git a/tests/i915/gen9_exec_parse.c b/tests/i915/gen9_exec_parse.c
index fa61693cfc..c8743a78a0 100644
--- a/tests/i915/gen9_exec_parse.c
+++ b/tests/i915/gen9_exec_parse.c
@@ -38,12 +38,9 @@
#define INSTR_CLIENT_SHIFT 29
#define INSTR_INVALID_CLIENT 0x7
-#define MI_LOAD_REGISTER_REG (0x2a << 23)
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
#define MI_ARB_ON_OFF (0x8 << 23)
#define MI_USER_INTERRUPT (0x02 << 23)
#define MI_FLUSH_DW (0x26 << 23)
-#define MI_ARB_CHECK (0x05 << 23)
#define MI_REPORT_HEAD (0x07 << 23)
#define MI_SUSPEND_FLUSH (0x0b << 23)
#define MI_LOAD_SCAN_LINES_EXCL (0x13 << 23)
@@ -689,7 +686,7 @@ static void test_cmd_crossing_page(const int i915, const uint32_t handle)
MI_BATCH_BUFFER_END,
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM | 2,
BCS_GPR(0),
0, /* reloc */
0, /* reloc */
@@ -728,7 +725,7 @@ static void test_invalid_length(const int i915, const uint32_t handle)
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM | 2,
BCS_GPR(0),
0, /* reloc */
0, /* reloc */
@@ -841,7 +838,7 @@ static void test_register(const int i915, const uint32_t handle,
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM | 2,
r->addr,
0, /* reloc */
0, /* reloc */
@@ -880,7 +877,7 @@ static long int read_reg(const int i915, const uint32_t handle,
const uint32_t addr)
{
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM | 2,
addr,
0, /* reloc */
0, /* reloc */
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates
2022-06-07 5:04 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
@ 2022-06-07 5:04 ` Zbigniew Kempczyński
0 siblings, 0 replies; 24+ messages in thread
From: Zbigniew Kempczyński @ 2022-06-07 5:04 UTC (permalink / raw)
To: igt-dev
In few tests we got some MI_* duplicates (MI_MATH for example).
Add common definitions in intel_reg.h and remove local definitions
in the tests.
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
---
benchmarks/gem_wsim.c | 34 ++++-------------------------
lib/intel_reg.h | 42 ++++++++++++++++++++++++++++++++++++
tests/i915/gem_exec_fair.c | 27 -----------------------
tests/i915/gem_exec_fence.c | 31 --------------------------
tests/i915/gem_watchdog.c | 27 -----------------------
tests/i915/gem_workarounds.c | 7 +++---
tests/i915/gen7_exec_parse.c | 8 +++----
tests/i915/gen9_exec_parse.c | 11 ++++------
8 files changed, 57 insertions(+), 130 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index d14352225e..aadd2737cd 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -279,36 +279,7 @@ static uint64_t ns_to_ctx_ticks(uint64_t ns)
return div64_u64_round_up(ns * f, NSEC_PER_SEC);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_ARB_CHECK MI_INSTR(0x5, 0)
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
-#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 0)
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
#define MI_CS_MMIO_DST BIT(19)
#define MI_CS_MMIO_SRC BIT(18)
@@ -1487,7 +1458,10 @@ static unsigned int create_bb(struct w_step *w, int self)
*cs++ = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
/* Save delta for indirect read by COND_BBE */
- *cs++ = MI_STORE_REGISTER_MEM | (1 + use_64b) | MI_CS_MMIO_DST;
+ if (use_64b)
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_CS_MMIO_DST;
+ else
+ *cs++ = MI_STORE_REGISTER_MEM | MI_CS_MMIO_DST;
*cs++ = CS_GPR(NOW_TS);
w->reloc[r].target_handle = self;
w->reloc[r].offset = offset_in_page(cs);
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index cb62728896..b8d97a07c9 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2625,6 +2625,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
+#define MI_LOAD_REGISTER_REG ((0x2A << 23) | 1)
+#define MI_STORE_REGISTER_MEM ((0x24 << 23) | (3 - 2))
+#define MI_STORE_REGISTER_MEM_GEN8 ((0x24 << 23) | (4 - 2))
/* Flush */
#define MI_FLUSH (0x04<<23)
@@ -2642,6 +2645,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_NOOP_WRITE_ID (1<<22)
#define MI_NOOP_ID_MASK (1<<22 - 1)
+/* ARB Check */
+#define MI_ARB_CHECK (0x5 << 23)
+
#define STATE3D_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x01<<16))
/* Atomics */
@@ -2656,12 +2662,48 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
#define MI_BATCH_BUFFER_END (0xA << 23)
#define MI_COND_BATCH_BUFFER_END (0x36 << 23)
+#define MAD_GT_IDD (0 << 12)
+#define MAD_GT_OR_EQ_IDD (1 << 12)
+#define MAD_LT_IDD (2 << 12)
+#define MAD_LT_OR_EQ_IDD (3 << 12)
+#define MAD_EQ_IDD (4 << 12)
+#define MAD_NEQ_IDD (5 << 12)
#define MI_DO_COMPARE (1 << 21)
#define MI_BATCH_NON_SECURE (1)
#define MI_BATCH_NON_SECURE_I965 (1 << 8)
#define MI_BATCH_NON_SECURE_HSW (1<<13) /* Additional bit for RCS */
+/* Math */
+#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
+#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
+#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
+/* Opcodes for MI_MATH_INSTR */
+#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
+#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
+#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
+#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
+#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
+#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
+#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
+#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
+#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
+#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
+#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
+#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
+/* DG2+ */
+#define MI_MATH_SHL MI_MATH_INSTR(0x105, 0x0, 0x0)
+#define MI_MATH_SHR MI_MATH_INSTR(0x106, 0x0, 0x0)
+#define MI_MATH_SAR MI_MATH_INSTR(0x107, 0x0, 0x0)
+
+/* Registers used as operands in MI_MATH_INSTR */
+#define MI_MATH_REG(x) (x)
+#define MI_MATH_REG_SRCA 0x20
+#define MI_MATH_REG_SRCB 0x21
+#define MI_MATH_REG_ACCU 0x31
+#define MI_MATH_REG_ZF 0x32
+#define MI_MATH_REG_CF 0x33
+
#define MAX_DISPLAY_PIPES 2
typedef enum {
diff --git a/tests/i915/gem_exec_fair.c b/tests/i915/gem_exec_fair.c
index 935f9c4a0b..89921697f7 100644
--- a/tests/i915/gem_exec_fair.c
+++ b/tests/i915/gem_exec_fair.c
@@ -112,33 +112,6 @@ static uint64_t ticks_to_ns(int i915, uint64_t ticks)
read_timestamp_frequency(i915));
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
static void delay(int i915,
const struct intel_execution_engine2 *e,
uint32_t handle,
diff --git a/tests/i915/gem_exec_fence.c b/tests/i915/gem_exec_fence.c
index 47ddf3083d..f20d7d94ff 100644
--- a/tests/i915/gem_exec_fence.c
+++ b/tests/i915/gem_exec_fence.c
@@ -2366,37 +2366,6 @@ static void test_syncobj_timeline_multiple_ext_nodes(int fd)
syncobj_destroy(fd, syncobjs[i]);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-/* #define MI_LOAD_REGISTER_MEM (MI_INSTR(0x29, 1) */
-/* #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) */
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
-#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
-#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x00, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x80, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
#define HSW_CS_GPR(n) (0x600 + 8*(n))
#define RING_TIMESTAMP (0x358)
#define MI_PREDICATE_RESULT_1 (0x41c)
diff --git a/tests/i915/gem_watchdog.c b/tests/i915/gem_watchdog.c
index fc1ba00712..01eb007694 100644
--- a/tests/i915/gem_watchdog.c
+++ b/tests/i915/gem_watchdog.c
@@ -270,33 +270,6 @@ static void virtual(int i915, const intel_ctx_cfg_t *base_cfg)
igt_assert_eq(count, expect);
}
-#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
-
-#define MI_MATH(x) MI_INSTR(0x1a, (x) - 1)
-#define MI_MATH_INSTR(opcode, op1, op2) ((opcode) << 20 | (op1) << 10 | (op2))
-/* Opcodes for MI_MATH_INSTR */
-#define MI_MATH_NOOP MI_MATH_INSTR(0x000, 0x0, 0x0)
-#define MI_MATH_LOAD(op1, op2) MI_MATH_INSTR(0x080, op1, op2)
-#define MI_MATH_LOADINV(op1, op2) MI_MATH_INSTR(0x480, op1, op2)
-#define MI_MATH_LOAD0(op1) MI_MATH_INSTR(0x081, op1)
-#define MI_MATH_LOAD1(op1) MI_MATH_INSTR(0x481, op1)
-#define MI_MATH_ADD MI_MATH_INSTR(0x100, 0x0, 0x0)
-#define MI_MATH_SUB MI_MATH_INSTR(0x101, 0x0, 0x0)
-#define MI_MATH_AND MI_MATH_INSTR(0x102, 0x0, 0x0)
-#define MI_MATH_OR MI_MATH_INSTR(0x103, 0x0, 0x0)
-#define MI_MATH_XOR MI_MATH_INSTR(0x104, 0x0, 0x0)
-#define MI_MATH_STORE(op1, op2) MI_MATH_INSTR(0x180, op1, op2)
-#define MI_MATH_STOREINV(op1, op2) MI_MATH_INSTR(0x580, op1, op2)
-/* Registers used as operands in MI_MATH_INSTR */
-#define MI_MATH_REG(x) (x)
-#define MI_MATH_REG_SRCA 0x20
-#define MI_MATH_REG_SRCB 0x21
-#define MI_MATH_REG_ACCU 0x31
-#define MI_MATH_REG_ZF 0x32
-#define MI_MATH_REG_CF 0x33
-
-#define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 1)
-
static unsigned int offset_in_page(void *addr)
{
return (uintptr_t)addr & 4095;
diff --git a/tests/i915/gem_workarounds.c b/tests/i915/gem_workarounds.c
index 70967b3ff5..12c70b2011 100644
--- a/tests/i915/gem_workarounds.c
+++ b/tests/i915/gem_workarounds.c
@@ -83,8 +83,6 @@ static bool write_only(const uint32_t addr)
return false;
}
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
-
static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
{
struct drm_i915_gem_exec_object2 obj[2];
@@ -122,7 +120,10 @@ static int workaround_fail_count(int i915, const intel_ctx_t *ctx)
out = base =
gem_mmap__cpu(i915, obj[1].handle, 0, batch_sz, PROT_WRITE);
for (int i = 0; i < num_wa_regs; i++) {
- *out++ = MI_STORE_REGISTER_MEM | ((gen >= 8 ? 4 : 2) - 2);
+ if (gen >= 8)
+ *out++ = MI_STORE_REGISTER_MEM_GEN8;
+ else
+ *out++ = MI_STORE_REGISTER_MEM;
*out++ = wa_regs[i].addr;
reloc[i].target_handle = obj[0].handle;
reloc[i].offset = (out - base) * sizeof(*out);
diff --git a/tests/i915/gen7_exec_parse.c b/tests/i915/gen7_exec_parse.c
index c83a791126..c3c2a7a296 100644
--- a/tests/i915/gen7_exec_parse.c
+++ b/tests/i915/gen7_exec_parse.c
@@ -48,8 +48,6 @@
#define INSTR_CLIENT_SHIFT 29
#define INSTR_INVALID_CLIENT 0x7
-#define MI_LOAD_REGISTER_REG (0x2a << 23)
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
#define MI_ARB_ON_OFF (0x8 << 23)
#define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
@@ -374,19 +372,19 @@ static void test_allocations(int fd)
static void hsw_load_register_reg(void)
{
uint32_t init_gpr0[16] = {
- MI_LOAD_REGISTER_IMM | (3 - 2),
+ MI_LOAD_REGISTER_IMM,
HSW_CS_GPR0,
0xabcdabc0, /* leave [1:0] zero */
MI_BATCH_BUFFER_END,
};
uint32_t store_gpr0[16] = {
- MI_STORE_REGISTER_MEM | (3 - 2),
+ MI_STORE_REGISTER_MEM,
HSW_CS_GPR0,
0, /* reloc*/
MI_BATCH_BUFFER_END,
};
uint32_t do_lrr[16] = {
- MI_LOAD_REGISTER_REG | (3 - 2),
+ MI_LOAD_REGISTER_REG,
0, /* [1] = src */
HSW_CS_GPR0, /* dst */
MI_BATCH_BUFFER_END,
diff --git a/tests/i915/gen9_exec_parse.c b/tests/i915/gen9_exec_parse.c
index fa61693cfc..1d9cd37104 100644
--- a/tests/i915/gen9_exec_parse.c
+++ b/tests/i915/gen9_exec_parse.c
@@ -38,12 +38,9 @@
#define INSTR_CLIENT_SHIFT 29
#define INSTR_INVALID_CLIENT 0x7
-#define MI_LOAD_REGISTER_REG (0x2a << 23)
-#define MI_STORE_REGISTER_MEM (0x24 << 23)
#define MI_ARB_ON_OFF (0x8 << 23)
#define MI_USER_INTERRUPT (0x02 << 23)
#define MI_FLUSH_DW (0x26 << 23)
-#define MI_ARB_CHECK (0x05 << 23)
#define MI_REPORT_HEAD (0x07 << 23)
#define MI_SUSPEND_FLUSH (0x0b << 23)
#define MI_LOAD_SCAN_LINES_EXCL (0x13 << 23)
@@ -689,7 +686,7 @@ static void test_cmd_crossing_page(const int i915, const uint32_t handle)
MI_BATCH_BUFFER_END,
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
BCS_GPR(0),
0, /* reloc */
0, /* reloc */
@@ -728,7 +725,7 @@ static void test_invalid_length(const int i915, const uint32_t handle)
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
BCS_GPR(0),
0, /* reloc */
0, /* reloc */
@@ -841,7 +838,7 @@ static void test_register(const int i915, const uint32_t handle,
};
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
r->addr,
0, /* reloc */
0, /* reloc */
@@ -880,7 +877,7 @@ static long int read_reg(const int i915, const uint32_t handle,
const uint32_t addr)
{
const uint32_t store_reg[] = {
- MI_STORE_REGISTER_MEM | (4 - 2),
+ MI_STORE_REGISTER_MEM_GEN8,
addr,
0, /* reloc */
0, /* reloc */
--
2.32.0
^ permalink raw reply related [flat|nested] 24+ messages in thread
end of thread, other threads:[~2022-06-13 6:28 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-07 5:24 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
2022-06-09 9:06 ` Petri Latvala
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 2/4] lib/igt_crc: Introduce common place for crc tables and functions Zbigniew Kempczyński
2022-06-09 9:44 ` Petri Latvala
2022-06-10 5:24 ` Zbigniew Kempczyński
2022-06-10 7:53 ` Petri Latvala
2022-06-13 3:57 ` Zbigniew Kempczyński
2022-06-13 5:26 ` Petri Latvala
2022-06-13 6:23 ` Petri Latvala
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 3/4] lib/i915_crc: Introduce crc32 on gpu for DG2 Zbigniew Kempczyński
2022-06-09 9:47 ` Petri Latvala
2022-06-07 5:24 ` [igt-dev] [PATCH i-g-t 4/4] tests/api_intel_bb: Add crc32 checking test " Zbigniew Kempczyński
2022-06-09 9:52 ` Petri Latvala
2022-06-10 4:34 ` Zbigniew Kempczyński
2022-06-10 8:34 ` Petri Latvala
2022-06-07 6:14 ` [igt-dev] ✓ Fi.CI.BAT: success for Add crc32 calculation on dg2 gpu (rev5) Patchwork
2022-06-07 7:22 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2022-06-07 8:34 ` Zbigniew Kempczyński
2022-06-07 15:25 ` Vudum, Lakshminarayana
2022-06-07 14:58 ` [igt-dev] ✓ Fi.CI.IGT: success " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-06-10 7:07 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
2022-06-10 7:07 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
2022-06-10 11:19 ` Petri Latvala
2022-06-07 5:04 [igt-dev] [PATCH i-g-t 0/4] Add crc32 calculation on dg2 gpu Zbigniew Kempczyński
2022-06-07 5:04 ` [igt-dev] [PATCH i-g-t 1/4] lib/intel_reg: Add common MI_* macros to remove duplicates Zbigniew Kempczyński
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