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* [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
@ 2022-05-31 12:39 ` Jonathan Cameron via
  0 siblings, 0 replies; 5+ messages in thread
From: Jonathan Cameron @ 2022-05-31 12:39 UTC (permalink / raw)
  To: qemu-devel, Michael S . Tsirkin
  Cc: Paolo Bonzini, linux-cxl, linuxarm, alex.bennee,
	Marcel Apfelbaum, Igor Mammedov, Markus Armbruster,
	Mark Cave-Ayland, Adam Manzanares, Tong Zhang, Ben Widawsky,
	Shameerali Kolothum Thodi

Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/cxl/cxl-component-utils.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 7985c9bfca..993248b5c0 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
         write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
         write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
         write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
+        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
+        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
     }
 }
 
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
@ 2022-05-31 12:39 ` Jonathan Cameron via
  0 siblings, 0 replies; 5+ messages in thread
From: Jonathan Cameron via @ 2022-05-31 12:39 UTC (permalink / raw)
  To: qemu-devel, Michael S . Tsirkin
  Cc: Paolo Bonzini, linux-cxl, linuxarm, alex.bennee,
	Marcel Apfelbaum, Igor Mammedov, Markus Armbruster,
	Mark Cave-Ayland, Adam Manzanares, Tong Zhang, Ben Widawsky,
	Shameerali Kolothum Thodi

Without being able to write these registers, no interleaving is possible.
More refined checks of HDM register state on commit to follow.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/cxl/cxl-component-utils.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 7985c9bfca..993248b5c0 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
         write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
         write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
         write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
+        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
+        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;
     }
 }
 
-- 
2.32.0



^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
  2022-05-31 12:39 ` Jonathan Cameron via
  (?)
@ 2022-06-06 17:39 ` Ben Widawsky
  2022-06-07 10:42     ` Jonathan Cameron via
  -1 siblings, 1 reply; 5+ messages in thread
From: Ben Widawsky @ 2022-06-06 17:39 UTC (permalink / raw)
  To: Jonathan Cameron
  Cc: qemu-devel, Michael S . Tsirkin, Paolo Bonzini, linux-cxl,
	linuxarm, alex.bennee, Marcel Apfelbaum, Igor Mammedov,
	Markus Armbruster, Mark Cave-Ayland, Adam Manzanares, Tong Zhang,
	Shameerali Kolothum Thodi

On 22-05-31 13:39:53, Jonathan Cameron wrote:
> Without being able to write these registers, no interleaving is possible.
> More refined checks of HDM register state on commit to follow.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  hw/cxl/cxl-component-utils.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> index 7985c9bfca..993248b5c0 100644
> --- a/hw/cxl/cxl-component-utils.c
> +++ b/hw/cxl/cxl-component-utils.c
> @@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
>          write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
>          write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
>          write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
> +        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
> +        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;

I wonder if this should be 0. It will be weird for endpoints to have a skip
value of 0xff.

>      }
>  }
>  
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
  2022-06-06 17:39 ` Ben Widawsky
@ 2022-06-07 10:42     ` Jonathan Cameron via
  0 siblings, 0 replies; 5+ messages in thread
From: Jonathan Cameron @ 2022-06-07 10:42 UTC (permalink / raw)
  To: Ben Widawsky
  Cc: qemu-devel, Michael S . Tsirkin, Paolo Bonzini, linux-cxl,
	linuxarm, alex.bennee, Marcel Apfelbaum, Igor Mammedov,
	Markus Armbruster, Mark Cave-Ayland, Adam Manzanares, Tong Zhang,
	Shameerali Kolothum Thodi

On Mon, 6 Jun 2022 10:39:52 -0700
Ben Widawsky <bwidawsk@kernel.org> wrote:

> On 22-05-31 13:39:53, Jonathan Cameron wrote:
> > Without being able to write these registers, no interleaving is possible.
> > More refined checks of HDM register state on commit to follow.
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  hw/cxl/cxl-component-utils.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > index 7985c9bfca..993248b5c0 100644
> > --- a/hw/cxl/cxl-component-utils.c
> > +++ b/hw/cxl/cxl-component-utils.c
> > @@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
> >          write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
> >          write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
> >          write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
> > +        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
> > +        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;  
> 
> I wonder if this should be 0. It will be weird for endpoints to have a skip
> value of 0xff.

For EP _LO should be 0xf0000000. But we haven't implemented skip yet IIRC.

It should be all bits set for host bridges (or switches) and that's the
bug this is fixing.

We have access to the device type at the caller of this function, so I can make it
right for both changes with a trivial change.

Will send a v2 shortly...

Thanks,

Jonathan

> 
> >      }
> >  }
> >  
> > -- 
> > 2.32.0
> >   


^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers
@ 2022-06-07 10:42     ` Jonathan Cameron via
  0 siblings, 0 replies; 5+ messages in thread
From: Jonathan Cameron via @ 2022-06-07 10:42 UTC (permalink / raw)
  To: Ben Widawsky
  Cc: qemu-devel, Michael S . Tsirkin, Paolo Bonzini, linux-cxl,
	linuxarm, alex.bennee, Marcel Apfelbaum, Igor Mammedov,
	Markus Armbruster, Mark Cave-Ayland, Adam Manzanares, Tong Zhang,
	Shameerali Kolothum Thodi

On Mon, 6 Jun 2022 10:39:52 -0700
Ben Widawsky <bwidawsk@kernel.org> wrote:

> On 22-05-31 13:39:53, Jonathan Cameron wrote:
> > Without being able to write these registers, no interleaving is possible.
> > More refined checks of HDM register state on commit to follow.
> > 
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  hw/cxl/cxl-component-utils.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > index 7985c9bfca..993248b5c0 100644
> > --- a/hw/cxl/cxl-component-utils.c
> > +++ b/hw/cxl/cxl-component-utils.c
> > @@ -174,6 +174,8 @@ static void hdm_init_common(uint32_t *reg_state, uint32_t *write_msk)
> >          write_msk[R_CXL_HDM_DECODER0_SIZE_LO + i * 0x20] = 0xf0000000;
> >          write_msk[R_CXL_HDM_DECODER0_SIZE_HI + i * 0x20] = 0xffffffff;
> >          write_msk[R_CXL_HDM_DECODER0_CTRL + i * 0x20] = 0x13ff;
> > +        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_LO + i * 0x20] = 0xffffffff;
> > +        write_msk[R_CXL_HDM_DECODER0_TARGET_LIST_HI + i * 0x20] = 0xffffffff;  
> 
> I wonder if this should be 0. It will be weird for endpoints to have a skip
> value of 0xff.

For EP _LO should be 0xf0000000. But we haven't implemented skip yet IIRC.

It should be all bits set for host bridges (or switches) and that's the
bug this is fixing.

We have access to the device type at the caller of this function, so I can make it
right for both changes with a trivial change.

Will send a v2 shortly...

Thanks,

Jonathan

> 
> >      }
> >  }
> >  
> > -- 
> > 2.32.0
> >   



^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-06-07 10:57 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-31 12:39 [PATCH] hw/cxl: Fix missing write mask for HDM decoder target list registers Jonathan Cameron
2022-05-31 12:39 ` Jonathan Cameron via
2022-06-06 17:39 ` Ben Widawsky
2022-06-07 10:42   ` Jonathan Cameron
2022-06-07 10:42     ` Jonathan Cameron via

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