* [Intel-gfx] [PATCH v6 i-g-t 0/3] Update DRM UAPI and add test for new hw info query
@ 2022-06-07 21:17 ` John.C.Harrison
0 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-06-07 21:17 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.
Also, update to the latest DRM UAPI header file that contains the new
query enums.
Lastly, none of the query tests had description entries. So made some
up.
v2: Rebased to newer baseline.
v3: Update UAPI header file.
v4: Use correct method for updating header file.
v5: Add descriptions to all the query tests.
v6: Fix typo in description.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (2):
include/drm-uapi: Update to latest i915_drm.h
tests/i915/query: Add descriptions to existing tests
Rodrigo Vivi (1):
tests/i915/query: Query, parse and validate the hwconfig table
include/drm-uapi/i915_drm.h | 398 ++++++++++++++++++++++++++++--------
lib/intel_hwconfig_types.h | 118 +++++++++++
tests/i915/i915_query.c | 192 +++++++++++++++++
3 files changed, 622 insertions(+), 86 deletions(-)
create mode 100644 lib/intel_hwconfig_types.h
--
2.36.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH v6 i-g-t 0/3] Update DRM UAPI and add test for new hw info query
@ 2022-06-07 21:17 ` John.C.Harrison
0 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-06-07 21:17 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.
Also, update to the latest DRM UAPI header file that contains the new
query enums.
Lastly, none of the query tests had description entries. So made some
up.
v2: Rebased to newer baseline.
v3: Update UAPI header file.
v4: Use correct method for updating header file.
v5: Add descriptions to all the query tests.
v6: Fix typo in description.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (2):
include/drm-uapi: Update to latest i915_drm.h
tests/i915/query: Add descriptions to existing tests
Rodrigo Vivi (1):
tests/i915/query: Query, parse and validate the hwconfig table
include/drm-uapi/i915_drm.h | 398 ++++++++++++++++++++++++++++--------
lib/intel_hwconfig_types.h | 118 +++++++++++
tests/i915/i915_query.c | 192 +++++++++++++++++
3 files changed, 622 insertions(+), 86 deletions(-)
create mode 100644 lib/intel_hwconfig_types.h
--
2.36.0
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH v6 i-g-t 1/3] include/drm-uapi: Update to latest i915_drm.h
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
(?)
@ 2022-06-07 21:17 ` John.C.Harrison
-1 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-06-07 21:17 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Update to the latest master version of the DRM UAPI header file from
git://anongit.freedesktop.org/git/drm/drm:
c4955d9cd2fc Merge tag 'drm-intel-next-fixes-2022-05-24' of
git://anongit.freedesktop.org/drm/drm-intel into drm-next
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
include/drm-uapi/i915_drm.h | 398 ++++++++++++++++++++++++++++--------
1 file changed, 312 insertions(+), 86 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 9c9e1afa61ba..b4efc96c2edc 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
-/*
+/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
* There may be more than one engine fulfilling any role within the system.
* Each engine of a class is given a unique instance number and therefore
* any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
* for this identification.
*/
struct i915_engine_class_instance {
- __u16 engine_class; /* see enum drm_i915_gem_engine_class */
- __u16 engine_instance;
+ /**
+ * @engine_class:
+ *
+ * Engine class from enum drm_i915_gem_engine_class
+ */
+ __u16 engine_class;
#define I915_ENGINE_CLASS_INVALID_NONE -1
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+ /**
+ * @engine_instance:
+ *
+ * Engine instance.
+ */
+ __u16 engine_instance;
};
/**
@@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
/**
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
* the user with the GTT offset at which this object will be pinned.
+ *
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
* presumed_offset of the object.
+ *
* During execbuffer2 the kernel populates it with the value of the
* current GTT offset of the object, for future presumed_offset writes.
+ *
+ * See struct drm_i915_gem_create_ext for the rules when dealing with
+ * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+ * minimum page sizes, like DG2.
*/
__u64 offset;
@@ -2651,24 +2720,65 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
-/*
+/**
+ * struct drm_i915_perf_oa_config
+ *
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
- /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
+ /**
+ * @uuid:
+ *
+ * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
+ */
char uuid[36];
+ /**
+ * @n_mux_regs:
+ *
+ * Number of mux regs in &mux_regs_ptr.
+ */
__u32 n_mux_regs;
+
+ /**
+ * @n_boolean_regs:
+ *
+ * Number of boolean regs in &boolean_regs_ptr.
+ */
__u32 n_boolean_regs;
+
+ /**
+ * @n_flex_regs:
+ *
+ * Number of flex regs in &flex_regs_ptr.
+ */
__u32 n_flex_regs;
- /*
- * These fields are pointers to tuples of u32 values (register address,
- * value). For example the expected length of the buffer pointed by
- * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+ /**
+ * @mux_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_mux_regs).
*/
__u64 mux_regs_ptr;
+
+ /**
+ * @boolean_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_boolean_regs).
+ */
__u64 boolean_regs_ptr;
+
+ /**
+ * @flex_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_flex_regs).
+ */
__u64 flex_regs_ptr;
};
@@ -2679,12 +2789,24 @@ struct drm_i915_perf_oa_config {
* @data_ptr is also depends on the specific @query_id.
*/
struct drm_i915_query_item {
- /** @query_id: The id for this query */
+ /**
+ * @query_id:
+ *
+ * The id for this query. Currently accepted query IDs are:
+ * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
+ * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
+ * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
+ * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
+ * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
+ * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
+ */
__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO 1
-#define DRM_I915_QUERY_ENGINE_INFO 2
-#define DRM_I915_QUERY_PERF_CONFIG 3
-#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_PERF_CONFIG 3
+#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_BLOB 5
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
/* Must be kept compact -- no holes and well documented */
/**
@@ -2700,14 +2822,17 @@ struct drm_i915_query_item {
/**
* @flags:
*
- * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+ * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+ * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
* following:
*
- * - DRM_I915_QUERY_PERF_CONFIG_LIST
- * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
- * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ * - %DRM_I915_QUERY_PERF_CONFIG_LIST
+ * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+ * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ *
+ * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
+ * a struct i915_engine_class_instance that references a render engine.
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
@@ -2765,66 +2890,112 @@ struct drm_i915_query {
__u64 items_ptr;
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
- *
- * data: contains the 3 pieces of information :
- *
- * - the slice mask with one bit per slice telling whether a slice is
- * available. The availability of slice X can be queried with the following
- * formula :
- *
- * (data[X / 8] >> (X % 8)) & 1
- *
- * - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. Gen12 has dual-subslices, which are
- * similar to two gen11 subslices. For gen12, this array represents dual-
- * subslices. The availability of subslice Y in slice X can be queried
- * with the following formula :
- *
- * (data[subslice_offset +
- * X * subslice_stride +
- * Y / 8] >> (Y % 8)) & 1
- *
- * - the EU mask for each subslice in each slice with one bit per EU telling
- * whether an EU is available. The availability of EU Z in subslice Y in
- * slice X can be queried with the following formula :
+/**
+ * struct drm_i915_query_topology_info
*
- * (data[eu_offset +
- * (X * max_subslices + Y) * eu_stride +
- * Z / 8] >> (Z % 8)) & 1
+ * Describes slice/subslice/EU information queried by
+ * %DRM_I915_QUERY_TOPOLOGY_INFO
*/
struct drm_i915_query_topology_info {
- /*
+ /**
+ * @flags:
+ *
* Unused for now. Must be cleared to zero.
*/
__u16 flags;
+ /**
+ * @max_slices:
+ *
+ * The number of bits used to express the slice mask.
+ */
__u16 max_slices;
+
+ /**
+ * @max_subslices:
+ *
+ * The number of bits used to express the subslice mask.
+ */
__u16 max_subslices;
+
+ /**
+ * @max_eus_per_subslice:
+ *
+ * The number of bits in the EU mask that correspond to a single
+ * subslice's EUs.
+ */
__u16 max_eus_per_subslice;
- /*
+ /**
+ * @subslice_offset:
+ *
* Offset in data[] at which the subslice masks are stored.
*/
__u16 subslice_offset;
- /*
+ /**
+ * @subslice_stride:
+ *
* Stride at which each of the subslice masks for each slice are
* stored.
*/
__u16 subslice_stride;
- /*
+ /**
+ * @eu_offset:
+ *
* Offset in data[] at which the EU masks are stored.
*/
__u16 eu_offset;
- /*
+ /**
+ * @eu_stride:
+ *
* Stride at which each of the EU masks for each subslice are stored.
*/
__u16 eu_stride;
+ /**
+ * @data:
+ *
+ * Contains 3 pieces of information :
+ *
+ * - The slice mask with one bit per slice telling whether a slice is
+ * available. The availability of slice X can be queried with the
+ * following formula :
+ *
+ * .. code:: c
+ *
+ * (data[X / 8] >> (X % 8)) & 1
+ *
+ * Starting with Xe_HP platforms, Intel hardware no longer has
+ * traditional slices so i915 will always report a single slice
+ * (hardcoded slicemask = 0x1) which contains all of the platform's
+ * subslices. I.e., the mask here does not reflect any of the newer
+ * hardware concepts such as "gslices" or "cslices" since userspace
+ * is capable of inferring those from the subslice mask.
+ *
+ * - The subslice mask for each slice with one bit per subslice telling
+ * whether a subslice is available. Starting with Gen12 we use the
+ * term "subslice" to refer to what the hardware documentation
+ * describes as a "dual-subslices." The availability of subslice Y
+ * in slice X can be queried with the following formula :
+ *
+ * .. code:: c
+ *
+ * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
+ *
+ * - The EU mask for each subslice in each slice, with one bit per EU
+ * telling whether an EU is available. The availability of EU Z in
+ * subslice Y in slice X can be queried with the following formula :
+ *
+ * .. code:: c
+ *
+ * (data[eu_offset +
+ * (X * max_subslices + Y) * eu_stride +
+ * Z / 8
+ * ] >> (Z % 8)) & 1
+ */
__u8 data[];
};
@@ -2945,52 +3116,68 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+/**
+ * struct drm_i915_query_perf_config
+ *
+ * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
+ * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
*/
struct drm_i915_query_perf_config {
union {
- /*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
- * this fields to the number of configurations available.
+ /**
+ * @n_configs:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
+ * the number of configurations available.
*/
__u64 n_configs;
- /*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
- * i915 will use the value in this field as configuration
- * identifier to decide what data to write into config_ptr.
+ /**
+ * @config:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
+ * value in this field as configuration identifier to decide
+ * what data to write into config_ptr.
*/
__u64 config;
- /*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
- * i915 will use the value in this field as configuration
- * identifier to decide what data to write into config_ptr.
+ /**
+ * @uuid:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
+ * value in this field as configuration identifier to decide
+ * what data to write into config_ptr.
*
* String formatted like "%08x-%04x-%04x-%04x-%012x"
*/
char uuid[36];
};
- /*
+ /**
+ * @flags:
+ *
* Unused for now. Must be cleared to zero.
*/
__u32 flags;
- /*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
- * write an array of __u64 of configuration identifiers.
+ /**
+ * @data:
*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
- * write a struct drm_i915_perf_oa_config. If the following fields of
- * drm_i915_perf_oa_config are set not set to 0, i915 will write into
- * the associated pointers the values of submitted when the
+ * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
+ * i915 will write an array of __u64 of configuration identifiers.
+ *
+ * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
+ * i915 will write a struct drm_i915_perf_oa_config. If the following
+ * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
+ * write into the associated pointers the values of submitted when the
* configuration was created :
*
- * - n_mux_regs
- * - n_boolean_regs
- * - n_flex_regs
+ * - &drm_i915_perf_oa_config.n_mux_regs
+ * - &drm_i915_perf_oa_config.n_boolean_regs
+ * - &drm_i915_perf_oa_config.n_flex_regs
*/
__u8 data[];
};
@@ -3128,6 +3315,16 @@ struct drm_i915_query_memory_regions {
struct drm_i915_memory_region_info regions[];
};
+/**
+ * DOC: GuC HWCONFIG blob uAPI
+ *
+ * The GuC produces a blob with information about the current device.
+ * i915 reads this blob from GuC and makes it available via this uAPI.
+ *
+ * The format and meaning of the blob content are documented in the
+ * Programmer's Reference Manual.
+ */
+
/**
* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
* extension support using struct i915_user_extension.
@@ -3144,11 +3341,40 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
- * Note that for some devices we have might have further minimum
- * page-size restrictions(larger than 4K), like for device local-memory.
- * However in general the final size here should always reflect any
- * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
- * extension to place the object in device local-memory.
+ *
+ * DG2 64K min page size implications:
+ *
+ * On discrete platforms, starting from DG2, we have to contend with GTT
+ * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+ * objects. Specifically the hardware only supports 64K or larger GTT
+ * page sizes for such memory. The kernel will already ensure that all
+ * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+ * sizes underneath.
+ *
+ * Note that the returned size here will always reflect any required
+ * rounding up done by the kernel, i.e 4K will now become 64K on devices
+ * such as DG2.
+ *
+ * Special DG2 GTT address alignment requirement:
+ *
+ * The GTT alignment will also need to be at least 2M for such objects.
+ *
+ * Note that due to how the hardware implements 64K GTT page support, we
+ * have some further complications:
+ *
+ * 1) The entire PDE (which covers a 2MB virtual address range), must
+ * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+ * PDE is forbidden by the hardware.
+ *
+ * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+ * objects.
+ *
+ * To keep things simple for userland, we mandate that any GTT mappings
+ * must be aligned to and rounded up to 2MB. The kernel will internally
+ * pad them out to the next 2MB boundary. As this only wastes virtual
+ * address space and avoids userland having to copy any needlessly
+ * complicated PDE sharing scheme (coloring) and only affects DG2, this
+ * is deemed to be a good compromise.
*/
__u64 size;
/**
--
2.36.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH v6 i-g-t 2/3] tests/i915/query: Add descriptions to existing tests
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
(?)
(?)
@ 2022-06-07 21:17 ` John.C.Harrison
-1 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-06-07 21:17 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
None of the query tests had a description. So make some up.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Kamil Konieczny <kamil.konieczny@linux.intel.com>
---
tests/i915/i915_query.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 246a979af72a..6c73f60aedcd 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -923,34 +923,41 @@ igt_main
devid = intel_get_drm_devid(fd);
}
+ igt_describe("Test response to an invalid query call");
igt_subtest("query-garbage")
test_query_garbage(fd);
+ igt_describe("Test response to invalid DRM_I915_QUERY_TOPOLOGY_INFO query");
igt_subtest("query-topology-garbage-items") {
igt_require(query_topology_supported(fd));
test_query_topology_garbage_items(fd);
}
+ igt_describe("Guardband test for DRM_I915_QUERY_TOPOLOGY_INFO query");
igt_subtest("query-topology-kernel-writes") {
igt_require(query_topology_supported(fd));
test_query_topology_kernel_writes(fd);
}
+ igt_describe("Verify DRM_I915_QUERY_TOPOLOGY_INFO query fails when it is not supported");
igt_subtest("query-topology-unsupported") {
igt_require(!query_topology_supported(fd));
test_query_topology_unsupported(fd);
}
+ igt_describe("Compare new DRM_I915_QUERY_TOPOLOGY_INFO query with legacy (sub)slice getparams");
igt_subtest("query-topology-coherent-slice-mask") {
igt_require(query_topology_supported(fd));
test_query_topology_coherent_slice_mask(fd);
}
+ igt_describe("More compare new DRM_I915_QUERY_TOPOLOGY_INFO query with legacy (sub)slice getparams");
igt_subtest("query-topology-matches-eu-total") {
igt_require(query_topology_supported(fd));
test_query_topology_matches_eu_total(fd);
}
+ igt_describe("Verify DRM_I915_QUERY_TOPOLOGY_INFO query against hardcoded known values for certain platforms");
igt_subtest("query-topology-known-pci-ids") {
igt_require(query_topology_supported(fd));
igt_require(IS_HASWELL(devid) || IS_BROADWELL(devid) ||
@@ -959,16 +966,19 @@ igt_main
test_query_topology_known_pci_ids(fd, devid);
}
+ igt_describe("Test DRM_I915_QUERY_GEOMETRY_SUBSLICES query");
igt_subtest("test-query-geometry-subslices") {
igt_require(query_geometry_subslices_supported(fd));
test_query_geometry_subslices(fd);
}
+ igt_describe("Dodgy returned data tests for DRM_I915_QUERY_MEMORY_REGIONS");
igt_subtest("query-regions-garbage-items") {
igt_require(query_regions_supported(fd));
test_query_regions_garbage_items(fd);
}
+ igt_describe("Basic tests for DRM_I915_QUERY_MEMORY_REGIONS");
igt_subtest("query-regions-sanity-check") {
igt_require(query_regions_supported(fd));
test_query_regions_sanity_check(fd);
@@ -979,9 +989,11 @@ igt_main
igt_require(query_engine_info_supported(fd));
}
+ igt_describe("Negative tests for DRM_I915_QUERY_ENGINE_INFO");
igt_subtest("engine-info-invalid")
engines_invalid(fd);
+ igt_describe("Positive tests for DRM_I915_QUERY_ENGINE_INFO");
igt_subtest("engine-info")
engines(fd);
}
--
2.36.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [PATCH v6 i-g-t 3/3] tests/i915/query: Query, parse and validate the hwconfig table
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
@ 2022-06-07 21:17 ` John.C.Harrison
-1 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-06-07 21:17 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
lib/intel_hwconfig_types.h | 118 ++++++++++++++++++++++++
tests/i915/i915_query.c | 180 +++++++++++++++++++++++++++++++++++++
2 files changed, 298 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000000..d5db217afba2
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */
+ INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */
+ INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */
+ INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */
+ INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */
+ INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */
+ INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */
+ __INTEL_HWCONFIG_KEY_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+ INTEL_HWCONFIG_MEMORY_TYPE_HBM2,
+ INTEL_HWCONFIG_MEMORY_TYPE_HBM2e,
+ INTEL_HWCONFIG_MEMORY_TYPE_GDDR6,
+ __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_CACHE_TYPE_L3 = 0,
+ INTEL_HWCONFIG_CACHE_TYPE_LLC,
+ INTEL_HWCONFIG_CACHE_TYPE_EDRAM,
+ __INTEL_HWCONFIG_CACHE_TYPE_LIMIT
+};
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 6c73f60aedcd..b545fb4aebbf 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -912,6 +913,181 @@ static void test_query_geometry_subslices(int fd)
}
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+ [INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE] = "Num HBM Stacks Per Tile",
+ [INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK] = "Num Channels Per HBM Stack",
+ [INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES] = "HBM Channel Width (in bytes)",
+ [INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES] = "Min Task URB Entries",
+ [INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES] = "Max Task URB Entries",
+ [INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES] = "Min Mesh URB Entries",
+ [INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES] = "Max Mesh URB Entries",
+};
+
+static const char * const hwconfig_memtypes[] = {
+ [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4] = "LPDDR4",
+ [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5] = "LPDDR5",
+ [INTEL_HWCONFIG_MEMORY_TYPE_HBM2] = "HBM2",
+ [INTEL_HWCONFIG_MEMORY_TYPE_HBM2e] = "HBM2e",
+ [INTEL_HWCONFIG_MEMORY_TYPE_GDDR6] = "GDDR6",
+};
+
+static const char * const hwconfig_cachetypes[] = {
+ [INTEL_HWCONFIG_CACHE_TYPE_L3] = "L3",
+ [INTEL_HWCONFIG_CACHE_TYPE_LLC] = "LLC",
+ [INTEL_HWCONFIG_CACHE_TYPE_EDRAM] = "EDRAM",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_BLOB,
+ };
+ uint32_t *data, value;
+ int i = 0;
+ int len, j, max_words, table_size;
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_KEY_LIMIT);
+ igt_assert(ARRAY_SIZE(hwconfig_memtypes) == __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
+ igt_assert(ARRAY_SIZE(hwconfig_cachetypes) == __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ table_size = item.length;
+ igt_require(table_size > 0);
+
+ data = malloc(table_size);
+ igt_assert(data);
+ memset(data, 0, table_size);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_assert(item.length == table_size);
+ igt_info("Table size = %d bytes\n", table_size);
+ igt_assert(table_size > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = table_size / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == table_size);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT);
+
+ len = data[i + 1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
+
+ value = data[i + 2];
+ switch (data[i]) {
+ case INTEL_HWCONFIG_MEMORY_TYPE:
+ igt_assert(len == 1);
+ igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
+ igt_info("%s\n", hwconfig_memtypes[value]);
+ break;
+
+ case INTEL_HWCONFIG_CACHE_TYPES:
+ igt_assert(len == 1);
+
+ if (!value)
+ igt_info("-\n");
+
+ j = 0;
+ while (value) {
+ if (value & BIT(j)) {
+ value &= ~BIT(j);
+ igt_assert(j < __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
+ igt_info("%s%s", hwconfig_cachetypes[j], value ? ", " : "\n");
+ }
+ }
+ break;
+
+ default:
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info("%d, ", data[j]);
+ igt_info("%d\n", data[j]);
+ }
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -998,6 +1174,10 @@ igt_main
engines(fd);
}
+ igt_describe("Test DRM_I915_QUERY_HWCONFIG_BLOB query");
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.36.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] [PATCH v6 i-g-t 3/3] tests/i915/query: Query, parse and validate the hwconfig table
@ 2022-06-07 21:17 ` John.C.Harrison
0 siblings, 0 replies; 8+ messages in thread
From: John.C.Harrison @ 2022-06-07 21:17 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
lib/intel_hwconfig_types.h | 118 ++++++++++++++++++++++++
tests/i915/i915_query.c | 180 +++++++++++++++++++++++++++++++++++++
2 files changed, 298 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000000..d5db217afba2
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */
+ INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */
+ INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */
+ INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */
+ INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */
+ INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */
+ INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */
+ __INTEL_HWCONFIG_KEY_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+ INTEL_HWCONFIG_MEMORY_TYPE_HBM2,
+ INTEL_HWCONFIG_MEMORY_TYPE_HBM2e,
+ INTEL_HWCONFIG_MEMORY_TYPE_GDDR6,
+ __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_CACHE_TYPE_L3 = 0,
+ INTEL_HWCONFIG_CACHE_TYPE_LLC,
+ INTEL_HWCONFIG_CACHE_TYPE_EDRAM,
+ __INTEL_HWCONFIG_CACHE_TYPE_LIMIT
+};
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 6c73f60aedcd..b545fb4aebbf 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -912,6 +913,181 @@ static void test_query_geometry_subslices(int fd)
}
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+ [INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE] = "Num HBM Stacks Per Tile",
+ [INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK] = "Num Channels Per HBM Stack",
+ [INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES] = "HBM Channel Width (in bytes)",
+ [INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES] = "Min Task URB Entries",
+ [INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES] = "Max Task URB Entries",
+ [INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES] = "Min Mesh URB Entries",
+ [INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES] = "Max Mesh URB Entries",
+};
+
+static const char * const hwconfig_memtypes[] = {
+ [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4] = "LPDDR4",
+ [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5] = "LPDDR5",
+ [INTEL_HWCONFIG_MEMORY_TYPE_HBM2] = "HBM2",
+ [INTEL_HWCONFIG_MEMORY_TYPE_HBM2e] = "HBM2e",
+ [INTEL_HWCONFIG_MEMORY_TYPE_GDDR6] = "GDDR6",
+};
+
+static const char * const hwconfig_cachetypes[] = {
+ [INTEL_HWCONFIG_CACHE_TYPE_L3] = "L3",
+ [INTEL_HWCONFIG_CACHE_TYPE_LLC] = "LLC",
+ [INTEL_HWCONFIG_CACHE_TYPE_EDRAM] = "EDRAM",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_BLOB,
+ };
+ uint32_t *data, value;
+ int i = 0;
+ int len, j, max_words, table_size;
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_KEY_LIMIT);
+ igt_assert(ARRAY_SIZE(hwconfig_memtypes) == __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
+ igt_assert(ARRAY_SIZE(hwconfig_cachetypes) == __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ table_size = item.length;
+ igt_require(table_size > 0);
+
+ data = malloc(table_size);
+ igt_assert(data);
+ memset(data, 0, table_size);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_assert(item.length == table_size);
+ igt_info("Table size = %d bytes\n", table_size);
+ igt_assert(table_size > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = table_size / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == table_size);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT);
+
+ len = data[i + 1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
+
+ value = data[i + 2];
+ switch (data[i]) {
+ case INTEL_HWCONFIG_MEMORY_TYPE:
+ igt_assert(len == 1);
+ igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
+ igt_info("%s\n", hwconfig_memtypes[value]);
+ break;
+
+ case INTEL_HWCONFIG_CACHE_TYPES:
+ igt_assert(len == 1);
+
+ if (!value)
+ igt_info("-\n");
+
+ j = 0;
+ while (value) {
+ if (value & BIT(j)) {
+ value &= ~BIT(j);
+ igt_assert(j < __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
+ igt_info("%s%s", hwconfig_cachetypes[j], value ? ", " : "\n");
+ }
+ }
+ break;
+
+ default:
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info("%d, ", data[j]);
+ igt_info("%d\n", data[j]);
+ }
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -998,6 +1174,10 @@ igt_main
engines(fd);
}
+ igt_describe("Test DRM_I915_QUERY_HWCONFIG_BLOB query");
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.36.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Update DRM UAPI and add test for new hw info query (rev4)
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
` (3 preceding siblings ...)
(?)
@ 2022-06-08 0:51 ` Patchwork
-1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-06-08 0:51 UTC (permalink / raw)
To: John Harrison; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 9312 bytes --]
== Series Details ==
Series: Update DRM UAPI and add test for new hw info query (rev4)
URL : https://patchwork.freedesktop.org/series/104693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11732 -> IGTPW_7249
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/index.html
Participating hosts (44 -> 46)
------------------------------
Additional (4): fi-kbl-soraka bat-adlm-1 fi-icl-u2 bat-adlp-6
Missing (2): fi-bdw-5557u fi-bdw-samus
Known issues
------------
Here are the changes found in IGTPW_7249 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][1] ([i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@gem_lmem_swapping@random-engines.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [PASS][5] -> [INCOMPLETE][6] ([i915#4418])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bdw-gvtdvm: NOTRUN -> [INCOMPLETE][8] ([i915#4817])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-bdw-gvtdvm/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-skl-6700k2: [PASS][9] -> [INCOMPLETE][10] ([i915#4817])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/fi-skl-6700k2/igt@i915_suspend@basic-s3-without-i915.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-skl-6700k2/igt@i915_suspend@basic-s3-without-i915.html
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#5903])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-kbl-soraka: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +7 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271]) +9 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-connector-state:
- fi-icl-u2: NOTRUN -> [WARN][15] ([i915#6008])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@kms_force_connector_basic@force-connector-state.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u2: NOTRUN -> [SKIP][16] ([fdo#109285])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-icl-u2: NOTRUN -> [SKIP][17] ([fdo#109278]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#533])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][19] ([i915#3555])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-icl-u2: NOTRUN -> [SKIP][20] ([fdo#109295] / [i915#3301])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-icl-u2/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [DMESG-FAIL][21] ([i915#62]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gem:
- fi-bdw-gvtdvm: [DMESG-FAIL][23] -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/fi-bdw-gvtdvm/igt@i915_selftest@live@gem.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-bdw-gvtdvm/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [DMESG-WARN][25] ([i915#5904]) -> [PASS][26] +11 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][27] ([i915#5904] / [i915#62]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [DMESG-WARN][29] ([i915#62]) -> [PASS][30] +15 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#6008]: https://gitlab.freedesktop.org/drm/intel/issues/6008
[i915#6132]: https://gitlab.freedesktop.org/drm/intel/issues/6132
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6512 -> IGTPW_7249
CI-20190529: 20190529
CI_DRM_11732: ea6c9f614fb2d6a5da6d417cdce31d925786275c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7249: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/index.html
IGT_6512: 5efc64e9b93a2df85581ea425ee7d0f435855f13 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@i915_query@hwconfig_table
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/index.html
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Update DRM UAPI and add test for new hw info query (rev4)
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
` (4 preceding siblings ...)
(?)
@ 2022-06-08 6:51 ` Patchwork
-1 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2022-06-08 6:51 UTC (permalink / raw)
To: John Harrison; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 52568 bytes --]
== Series Details ==
Series: Update DRM UAPI and add test for new hw info query (rev4)
URL : https://patchwork.freedesktop.org/series/104693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11732_full -> IGTPW_7249_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/index.html
Participating hosts (10 -> 10)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7249_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_query@hwconfig_table} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb7/igt@i915_query@hwconfig_table.html
- shard-iclb: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb7/igt@i915_query@hwconfig_table.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@small-bo:
- {shard-dg1}: NOTRUN -> [WARN][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-dg1-18/igt@kms_addfb_basic@small-bo.html
* igt@kms_cursor_legacy@cursora-vs-flipa-varying-size:
- {shard-dg1}: NOTRUN -> [FAIL][4] +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-dg1-18/igt@kms_cursor_legacy@cursora-vs-flipa-varying-size.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-c-hdmi-a-3:
- {shard-dg1}: NOTRUN -> [SKIP][5] +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-c-hdmi-a-3.html
New tests
---------
New tests have been introduced between CI_DRM_11732_full and IGTPW_7249_full:
### New IGT tests (1) ###
* igt@i915_query@hwconfig_table:
- Statuses : 4 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_7249_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-2x:
- shard-tglb: NOTRUN -> [SKIP][6] ([i915#1839])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb3/igt@feature_discovery@display-2x.html
* igt@gem_ctx_persistence@engines-queued:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb7/igt@gem_ctx_persistence@engines-queued.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#5784])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-tglb6/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][10] -> [SKIP][11] ([i915#4525]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk9/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl1/igt@gem_exec_fair@basic-none-vip@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-tglb: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#118])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk6/igt@gem_exec_whisper@basic-queues-all.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk7/igt@gem_exec_whisper@basic-queues-all.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-apl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl8/igt@gem_lmem_swapping@verify-random-ccs.html
- shard-tglb: NOTRUN -> [SKIP][23] ([i915#4613])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@gem_lmem_swapping@verify-random-ccs.html
- shard-glk: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#4613]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk5/igt@gem_lmem_swapping@verify-random-ccs.html
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#4613])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb2/igt@gem_lmem_swapping@verify-random-ccs.html
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#4613])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_media_vme:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#284])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@gem_media_vme.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#4270])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#768])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][30] ([i915#3297])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen3_render_tiledy_blits:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#109289]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@gen3_render_tiledy_blits.html
* igt@gen9_exec_parse@allowed-single:
- shard-kbl: [PASS][32] -> [DMESG-WARN][33] ([i915#5566] / [i915#716])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl3/igt@gen9_exec_parse@allowed-single.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#1904])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglb: NOTRUN -> [SKIP][35] ([i915#4281])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][36] ([i915#1759])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-iclb: NOTRUN -> [SKIP][37] ([i915#5286]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#5286]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#111614])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb3/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271]) +142 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111615]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +6 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk5/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [i915#3886]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb7/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#3689]) +4 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb7/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +4 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl4/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][46] ([i915#3689] / [i915#3886])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +7 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl4/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#111615] / [i915#3689]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109278]) +8 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb6/igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271]) +158 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl4/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium@dp-crc-single:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +7 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl8/igt@kms_chamelium@dp-crc-single.html
* igt@kms_chamelium@hdmi-audio-edid:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +7 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@kms_chamelium@hdmi-audio-edid.html
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +8 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk5/igt@kms_chamelium@hdmi-audio-edid.html
* igt@kms_color_chamelium@pipe-a-ctm-max:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +14 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-max.html
* igt@kms_color_chamelium@pipe-b-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109284] / [fdo#111827]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb2/igt@kms_color_chamelium@pipe-b-ctm-negative.html
* igt@kms_color_chamelium@pipe-c-ctm-0-75:
- shard-snb: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +9 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb2/igt@kms_color_chamelium@pipe-c-ctm-0-75.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][57] ([i915#1319])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][58] ([i915#2105])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
- shard-snb: [PASS][59] -> [SKIP][60] ([fdo#109271])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][61] ([fdo#109278] / [fdo#109279])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb5/igt@kms_cursor_crc@pipe-a-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3319])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#109279] / [i915#3359]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen:
- shard-snb: NOTRUN -> [SKIP][64] ([fdo#109271]) +188 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb7/igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen.html
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3359]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#109274] / [fdo#109278])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-iclb: [PASS][67] -> [FAIL][68] ([i915#2346])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl4/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#5287])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb6/igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled.html
- shard-iclb: NOTRUN -> [SKIP][71] ([i915#5287])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb8/igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][72] ([fdo#109274]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb3/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-tglb: NOTRUN -> [SKIP][73] ([fdo#109274] / [fdo#111825]) +4 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb3/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][74] -> [DMESG-WARN][75] ([i915#180]) +5 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-glk: [PASS][76] -> [FAIL][77] ([i915#4911])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109280]) +10 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][79] ([i915#5439])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-glk: NOTRUN -> [SKIP][80] ([fdo#109271]) +83 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][81] ([fdo#109280] / [fdo#111825]) +16 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_hdr@bpc-switch:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3555]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl: [PASS][83] -> [FAIL][84] ([i915#1188])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl1/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-1:
- shard-kbl: NOTRUN -> [FAIL][85] ([i915#1188])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl7/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
* igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c:
- shard-tglb: NOTRUN -> [SKIP][86] ([fdo#109289]) +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb6/igt@kms_pipe_b_c_ivb@disable-pipe-b-enable-pipe-c.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#533])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk7/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][89] ([i915#265])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-a-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][90] ([fdo#111615] / [fdo#112054]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb7/igt@kms_plane_lowres@pipe-a-tiling-yf.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-iclb: NOTRUN -> [SKIP][91] ([i915#3536]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_plane_lowres@pipe-c-tiling-none:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#3536]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb3/igt@kms_plane_lowres@pipe-c-tiling-none.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658]) +3 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@kms_psr2_sf@cursor-plane-update-sf.html
- shard-tglb: NOTRUN -> [SKIP][94] ([i915#2920]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#111068] / [i915#658])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb6/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: NOTRUN -> [SKIP][96] ([i915#658])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#658]) +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#658]) +3 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][99] -> [SKIP][100] ([fdo#109642] / [fdo#111068] / [i915#658])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [PASS][101] -> [SKIP][102] ([fdo#109441]) +2 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb5/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][103] ([i915#132] / [i915#3467])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb7/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-iclb: [PASS][104] -> [SKIP][105] ([i915#5519])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [PASS][106] -> [DMESG-WARN][107] ([i915#180])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][108] ([i915#3555]) +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb1/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-glk: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2437])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk6/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-b-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][110] ([i915#2530])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb7/igt@nouveau_crc@pipe-b-source-outp-complete.html
- shard-tglb: NOTRUN -> [SKIP][111] ([i915#2530])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@nouveau_crc@pipe-b-source-outp-complete.html
* igt@prime_nv_test@i915_blt_fill_nv_read:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109291]) +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@prime_nv_test@i915_blt_fill_nv_read.html
* igt@prime_udl:
- shard-tglb: NOTRUN -> [SKIP][113] ([fdo#109291]) +4 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb6/igt@prime_udl.html
* igt@prime_vgem@fence-read-hang:
- shard-iclb: NOTRUN -> [SKIP][114] ([fdo#109295])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb3/igt@prime_vgem@fence-read-hang.html
- shard-tglb: NOTRUN -> [SKIP][115] ([fdo#109295])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@prime_vgem@fence-read-hang.html
* igt@sw_sync@sync_merge_same:
- shard-kbl: NOTRUN -> [FAIL][116] ([i915#6140])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@sw_sync@sync_merge_same.html
- shard-snb: NOTRUN -> [FAIL][117] ([i915#6140])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb5/igt@sw_sync@sync_merge_same.html
- shard-tglb: NOTRUN -> [FAIL][118] ([i915#6140])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb5/igt@sw_sync@sync_merge_same.html
* igt@sysfs_clients@recycle:
- shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2994])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl7/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-snb: [DMESG-WARN][120] ([i915#4528]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-snb5/igt@core_hotunplug@unbind-rebind.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb7/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][122] ([i915#4525]) -> [PASS][123] +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb7/igt@gem_exec_balancer@parallel-bb-first.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb4/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-kbl: [FAIL][124] ([i915#2842]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl3/igt@gem_exec_fair@basic-none-share@rcs0.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][126] ([i915#2842]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_schedule@wide@rcs0:
- shard-glk: [FAIL][128] ([i915#5965]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk7/igt@gem_exec_schedule@wide@rcs0.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk6/igt@gem_exec_schedule@wide@rcs0.html
* igt@gem_exec_whisper@basic-queues-forked-all:
- shard-glk: [DMESG-WARN][130] ([i915#118]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-glk4/igt@gem_exec_whisper@basic-queues-forked-all.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-glk5/igt@gem_exec_whisper@basic-queues-forked-all.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [SKIP][132] ([i915#2190]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-tglb7/igt@gem_huc_copy@huc-copy.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb1/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][134] ([i915#454]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb3/igt@i915_pm_dc@dc6-psr.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@i915_selftest@live@gt_mocs:
- shard-tglb: [INCOMPLETE][136] -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-tglb1/igt@i915_selftest@live@gt_mocs.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-tglb2/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][138] ([i915#3921]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-snb5/igt@i915_selftest@live@hangcheck.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-snb4/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][140] ([i915#180]) -> [PASS][141] +2 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [DMESG-WARN][142] ([i915#180]) -> [PASS][143] +2 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [SKIP][144] ([i915#5235]) -> [PASS][145] +2 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][146] ([fdo#109441]) -> [PASS][147] +2 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb6/igt@kms_psr@psr2_sprite_plane_move.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][148] ([i915#4525]) -> [FAIL][149] ([i915#6117])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [FAIL][150] ([i915#4767]) -> [INCOMPLETE][151] ([i915#180])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: [FAIL][152] ([i915#1188]) -> [DMESG-WARN][153] ([i915#180])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl4/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][154] ([i915#658]) -> [SKIP][155] ([i915#2920])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-iclb7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][161], [FAIL][162], [FAIL][163]) ([i915#3002] / [i915#4312] / [i915#5257])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl1/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl8/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl6/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl6/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-apl1/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl1/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl6/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-apl7/igt@runner@aborted.html
- shard-kbl: ([FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#716] / [i915#92])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl3/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl6/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl6/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl6/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl7/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl6/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl6/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11732/shard-kbl1/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl7/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl6/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@runner@aborted.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/shard-kbl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1904]: https://gitlab.freedesktop.org/drm/intel/issues/1904
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4241]: https://gitlab.freedesktop.org/drm/intel/issues/4241
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5353]: https://gitlab.freedesktop.org/drm/intel/issues/5353
[i915#5357]: https://gitlab.freedesktop.org/drm/intel/issues/5357
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5923]: https://gitlab.freedesktop.org/drm/intel/issues/5923
[i915#5965]: https://gitlab.freedesktop.org/drm/intel/issues/5965
[i915#5971]: https://gitlab.freedesktop.org/drm/intel/issues/5971
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6139]: https://gitlab.freedesktop.org/drm/intel/issues/6139
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6512 -> IGTPW_7249
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_11732: ea6c9f614fb2d6a5da6d417cdce31d925786275c @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7249: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/index.html
IGT_6512: 5efc64e9b93a2df85581ea425ee7d0f435855f13 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7249/index.html
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-06-08 6:51 UTC | newest]
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-- links below jump to the message on this page --
2022-06-07 21:17 [Intel-gfx] [PATCH v6 i-g-t 0/3] Update DRM UAPI and add test for new hw info query John.C.Harrison
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
2022-06-07 21:17 ` [Intel-gfx] [PATCH v6 i-g-t 1/3] include/drm-uapi: Update to latest i915_drm.h John.C.Harrison
2022-06-07 21:17 ` [Intel-gfx] [PATCH v6 i-g-t 2/3] tests/i915/query: Add descriptions to existing tests John.C.Harrison
2022-06-07 21:17 ` [Intel-gfx] [PATCH v6 i-g-t 3/3] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2022-06-07 21:17 ` [igt-dev] " John.C.Harrison
2022-06-08 0:51 ` [igt-dev] ✓ Fi.CI.BAT: success for Update DRM UAPI and add test for new hw info query (rev4) Patchwork
2022-06-08 6:51 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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