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From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: kernel@collabora.com,
	"Robert Beckett" <bob.beckett@collabora.com>,
	"Matthew Auld" <matthew.auld@intel.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 7/8] drm/i915/ttm: trust snooping when gen 6+ when deciding default cache_level
Date: Wed,  8 Jun 2022 20:51:30 +0000	[thread overview]
Message-ID: <20220608205132.438596-8-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220608205132.438596-1-bob.beckett@collabora.com>

By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
this is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable, so limit to
gen6+

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..e6cce35edb65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
 i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
 		     struct ttm_tt *ttm)
 {
-	return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+	bool can_snoop = HAS_SNOOP(i915) && (GRAPHICS_VER(i915) > 5);
+
+	return ((HAS_LLC(i915) || can_snoop) &&
 		!i915_ttm_gtt_binds_lmem(res) &&
 		ttm->caching == ttm_cached) ? I915_CACHE_LLC :
 		I915_CACHE_NONE;
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: "Robert Beckett" <bob.beckett@collabora.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	kernel@collabora.com, "Matthew Auld" <matthew.auld@intel.com>,
	linux-kernel@vger.kernel.org
Subject: [PATCH v2 7/8] drm/i915/ttm: trust snooping when gen 6+ when deciding default cache_level
Date: Wed,  8 Jun 2022 20:51:30 +0000	[thread overview]
Message-ID: <20220608205132.438596-8-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220608205132.438596-1-bob.beckett@collabora.com>

By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
this is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable, so limit to
gen6+

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..e6cce35edb65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
 i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
 		     struct ttm_tt *ttm)
 {
-	return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+	bool can_snoop = HAS_SNOOP(i915) && (GRAPHICS_VER(i915) > 5);
+
+	return ((HAS_LLC(i915) || can_snoop) &&
 		!i915_ttm_gtt_binds_lmem(res) &&
 		ttm->caching == ttm_cached) ? I915_CACHE_LLC :
 		I915_CACHE_NONE;
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Robert Beckett <bob.beckett@collabora.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	kernel@collabora.com, "Matthew Auld" <matthew.auld@intel.com>,
	linux-kernel@vger.kernel.org
Subject: [Intel-gfx] [PATCH v2 7/8] drm/i915/ttm: trust snooping when gen 6+ when deciding default cache_level
Date: Wed,  8 Jun 2022 20:51:30 +0000	[thread overview]
Message-ID: <20220608205132.438596-8-bob.beckett@collabora.com> (raw)
In-Reply-To: <20220608205132.438596-1-bob.beckett@collabora.com>

By default i915_ttm_cache_level() decides I915_CACHE_LLC if HAS_SNOOP.
this is divergent from existing backends code which only considers
HAS_LLC.
Testing shows that trusting snooping on gen5- is unreliable, so limit to
gen6+

Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
index 4c1de0b4a10f..e6cce35edb65 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_move.c
@@ -46,7 +46,9 @@ static enum i915_cache_level
 i915_ttm_cache_level(struct drm_i915_private *i915, struct ttm_resource *res,
 		     struct ttm_tt *ttm)
 {
-	return ((HAS_LLC(i915) || HAS_SNOOP(i915)) &&
+	bool can_snoop = HAS_SNOOP(i915) && (GRAPHICS_VER(i915) > 5);
+
+	return ((HAS_LLC(i915) || can_snoop) &&
 		!i915_ttm_gtt_binds_lmem(res) &&
 		ttm->caching == ttm_cached) ? I915_CACHE_LLC :
 		I915_CACHE_NONE;
-- 
2.25.1


  parent reply	other threads:[~2022-06-08 20:53 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-08 20:51 [PATCH v2 0/8] drm/i915: ttm for internal Robert Beckett
2022-06-08 20:51 ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51 ` [PATCH v2 1/8] drm/i915/ttm: dont trample cache_level overrides during ttm move Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` [PATCH v2 2/8] drm/i915: add gen6 ppgtt dummy creation function Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` [PATCH v2 3/8] drm/i915: setup ggtt scratch page after memory regions Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` [PATCH v2 4/8] drm/i915: allow volatile buffers to use ttm pool allocator Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` [PATCH v2 5/8] drm/i915: limit ttm to dma32 for i965G[M] Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` [PATCH v2 6/8] drm/i915/gem: further fix mman selftest Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` Robert Beckett [this message]
2022-06-08 20:51   ` [Intel-gfx] [PATCH v2 7/8] drm/i915/ttm: trust snooping when gen 6+ when deciding default cache_level Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51 ` [PATCH v2 8/8] drm/i915: internal buffers use ttm backend Robert Beckett
2022-06-08 20:51   ` Robert Beckett
2022-06-08 20:51   ` [Intel-gfx] " Robert Beckett
2022-06-08 22:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for internal Patchwork
2022-06-09  1:08 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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