All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v2  0/3] Miscellaneous fixes for PMU driver
@ 2022-05-13  1:55 ` Atish Patra
  0 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Atish Patra, Anup Patel, Jisheng Zhang, linux-riscv,
	Palmer Dabbelt, Paul Walmsley, Rob Herring

This series fixes issues PMU driver code.
PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
user page update issue during counter start.

Changes from v1->v2:
1. Add proper compile time rv32 checks.

Atish Patra (3):
RISC-V: Fix counter restart during overflow for RV32
RISC-V: Update user page mapping only once during start
RISC-V: Fix SBI PMU calls for RV32

drivers/perf/riscv_pmu.c     |  1 -
drivers/perf/riscv_pmu_sbi.c | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)

--
2.25.1


^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH v2  0/3] Miscellaneous fixes for PMU driver
@ 2022-05-13  1:55 ` Atish Patra
  0 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Atish Patra, Anup Patel, Jisheng Zhang, linux-riscv,
	Palmer Dabbelt, Paul Walmsley, Rob Herring

This series fixes issues PMU driver code.
PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
user page update issue during counter start.

Changes from v1->v2:
1. Add proper compile time rv32 checks.

Atish Patra (3):
RISC-V: Fix counter restart during overflow for RV32
RISC-V: Update user page mapping only once during start
RISC-V: Fix SBI PMU calls for RV32

drivers/perf/riscv_pmu.c     |  1 -
drivers/perf/riscv_pmu_sbi.c | 16 ++++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)

--
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 14+ messages in thread
* [PATCH v2  1/3] RISC-V: Fix counter restart during overflow for RV32
  2022-05-13  1:55 ` Atish Patra
@ 2022-05-13  1:55   ` Atish Patra
  -1 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, Atish Patra,
	Jisheng Zhang, linux-riscv, Palmer Dabbelt, Paul Walmsley,
	Rob Herring

Pass the upper half of the initial value of the counter correctly
for RV32.

Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu_sbi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index a1317a483512..1e6c150c892a 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 			hwc = &event->hw;
 			max_period = riscv_pmu_ctr_get_width_mask(event);
 			init_val = local64_read(&hwc->prev_count) & max_period;
+#if defined(CONFIG_32BIT)
+			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
+				  flag, init_val, init_val >> 32, 0);
+#else
 			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 				  flag, init_val, 0, 0);
+#endif
 		}
 		ctr_ovf_mask = ctr_ovf_mask >> 1;
 		idx++;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v2  1/3] RISC-V: Fix counter restart during overflow for RV32
@ 2022-05-13  1:55   ` Atish Patra
  0 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Heiko Stuebner, Anup Patel, Atish Patra,
	Jisheng Zhang, linux-riscv, Palmer Dabbelt, Paul Walmsley,
	Rob Herring

Pass the upper half of the initial value of the counter correctly
for RV32.

Fixes: 4905ec2fb7e6 ("RISC-V: Add sscofpmf extension support")

Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu_sbi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index a1317a483512..1e6c150c892a 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -525,8 +525,13 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 			hwc = &event->hw;
 			max_period = riscv_pmu_ctr_get_width_mask(event);
 			init_val = local64_read(&hwc->prev_count) & max_period;
+#if defined(CONFIG_32BIT)
+			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
+				  flag, init_val, init_val >> 32, 0);
+#else
 			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 				  flag, init_val, 0, 0);
+#endif
 		}
 		ctr_ovf_mask = ctr_ovf_mask >> 1;
 		idx++;
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v2  2/3] RISC-V: Update user page mapping only once during start
  2022-05-13  1:55 ` Atish Patra
@ 2022-05-13  1:55   ` Atish Patra
  -1 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Anup Patel, Atish Patra, Jisheng Zhang, linux-riscv,
	Palmer Dabbelt, Paul Walmsley, Rob Herring

Currently, riscv_pmu_event_set_period updates the userpage mapping.
However, the caller of riscv_pmu_event_set_period should update
the userpage mapping because the counter can not be updated/started
from set_period function in counter overflow path.

Invoke the perf_event_update_userpage at the caller so that it
doesn't get invoked twice during counter start path.

Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers")

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu.c     | 1 -
 drivers/perf/riscv_pmu_sbi.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index b2b8d2074ed0..130b9f1a40e0 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event)
 		left = (max_period >> 1);
 
 	local64_set(&hwc->prev_count, (u64)-left);
-	perf_event_update_userpage(event);
 
 	return overflow;
 }
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 1e6c150c892a..7ad92039a718 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -532,6 +532,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 				  flag, init_val, 0, 0);
 #endif
+			perf_event_update_userpage(event);
 		}
 		ctr_ovf_mask = ctr_ovf_mask >> 1;
 		idx++;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v2 2/3] RISC-V: Update user page mapping only once during start
@ 2022-05-13  1:55   ` Atish Patra
  0 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Anup Patel, Atish Patra, Jisheng Zhang, linux-riscv,
	Palmer Dabbelt, Paul Walmsley, Rob Herring

Currently, riscv_pmu_event_set_period updates the userpage mapping.
However, the caller of riscv_pmu_event_set_period should update
the userpage mapping because the counter can not be updated/started
from set_period function in counter overflow path.

Invoke the perf_event_update_userpage at the caller so that it
doesn't get invoked twice during counter start path.

Fixes: f5bfa23f576f ("RISC-V: Add a perf core library for pmu drivers")

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu.c     | 1 -
 drivers/perf/riscv_pmu_sbi.c | 1 +
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index b2b8d2074ed0..130b9f1a40e0 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -170,7 +170,6 @@ int riscv_pmu_event_set_period(struct perf_event *event)
 		left = (max_period >> 1);
 
 	local64_set(&hwc->prev_count, (u64)-left);
-	perf_event_update_userpage(event);
 
 	return overflow;
 }
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 1e6c150c892a..7ad92039a718 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -532,6 +532,7 @@ static inline void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
 			sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1,
 				  flag, init_val, 0, 0);
 #endif
+			perf_event_update_userpage(event);
 		}
 		ctr_ovf_mask = ctr_ovf_mask >> 1;
 		idx++;
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v2  3/3] RISC-V: Fix SBI PMU calls for RV32
  2022-05-13  1:55 ` Atish Patra
@ 2022-05-13  1:55   ` Atish Patra
  -1 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Atish Patra, Anup Patel, Jisheng Zhang, linux-riscv,
	Palmer Dabbelt, Paul Walmsley, Rob Herring

Some of the SBI PMU calls does not pass 64bit arguments
correctly and not under RV32 compile time flags. Currently,
this doesn't create any incorrect results as RV64 ignores
any value in the additional register and qemu doesn't support
raw events.

Fix those SBI calls in order to set correct values for RV32.

Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 7ad92039a718..fab0dd497393 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
 		cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
 
 	/* retrieve the available counter index */
+#if defined(CONFIG_32BIT)
+	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
+			cflags, hwc->event_base, hwc->config, hwc->config >> 32);
+#else
 	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
 			cflags, hwc->event_base, hwc->config, 0);
+#endif
 	if (ret.error) {
 		pr_debug("Not able to find a counter for event %lx config %llx\n",
 			hwc->event_base, hwc->config);
@@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
 	struct hw_perf_event *hwc = &event->hw;
 	unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
 
+#if defined(CONFIG_32BIT)
 	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
 			1, flag, ival, ival >> 32, 0);
+#else
+	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
+			1, flag, ival, 0, 0);
+#endif
 	if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
 		pr_err("Starting counter idx %d failed with error %d\n",
 			hwc->idx, sbi_err_map_linux_errno(ret.error));
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread
* [PATCH v2  3/3] RISC-V: Fix SBI PMU calls for RV32
@ 2022-05-13  1:55   ` Atish Patra
  0 siblings, 0 replies; 14+ messages in thread
From: Atish Patra @ 2022-05-13  1:55 UTC (permalink / raw)
  To: linux-kernel
  Cc: Atish Patra, Atish Patra, Anup Patel, Jisheng Zhang, linux-riscv,
	Palmer Dabbelt, Paul Walmsley, Rob Herring

Some of the SBI PMU calls does not pass 64bit arguments
correctly and not under RV32 compile time flags. Currently,
this doesn't create any incorrect results as RV64 ignores
any value in the additional register and qemu doesn't support
raw events.

Fix those SBI calls in order to set correct values for RV32.

Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index 7ad92039a718..fab0dd497393 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
 		cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
 
 	/* retrieve the available counter index */
+#if defined(CONFIG_32BIT)
+	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
+			cflags, hwc->event_base, hwc->config, hwc->config >> 32);
+#else
 	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
 			cflags, hwc->event_base, hwc->config, 0);
+#endif
 	if (ret.error) {
 		pr_debug("Not able to find a counter for event %lx config %llx\n",
 			hwc->event_base, hwc->config);
@@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
 	struct hw_perf_event *hwc = &event->hw;
 	unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
 
+#if defined(CONFIG_32BIT)
 	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
 			1, flag, ival, ival >> 32, 0);
+#else
+	ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
+			1, flag, ival, 0, 0);
+#endif
 	if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
 		pr_err("Starting counter idx %d failed with error %d\n",
 			hwc->idx, sbi_err_map_linux_errno(ret.error));
-- 
2.25.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply related	[flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: Fix SBI PMU calls for RV32
  2022-05-13  1:55   ` Atish Patra
@ 2022-05-24 11:22     ` Anup Patel
  -1 siblings, 0 replies; 14+ messages in thread
From: Anup Patel @ 2022-05-24 11:22 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-kernel@vger.kernel.org List, Atish Patra, Jisheng Zhang,
	linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring

On Fri, May 13, 2022 at 7:25 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Some of the SBI PMU calls does not pass 64bit arguments
> correctly and not under RV32 compile time flags. Currently,
> this doesn't create any incorrect results as RV64 ignores
> any value in the additional register and qemu doesn't support
> raw events.
>
> Fix those SBI calls in order to set correct values for RV32.
>
> Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 7ad92039a718..fab0dd497393 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
>                 cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
>
>         /* retrieve the available counter index */
> +#if defined(CONFIG_32BIT)
> +       ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
> +                       cflags, hwc->event_base, hwc->config, hwc->config >> 32);
> +#else
>         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
>                         cflags, hwc->event_base, hwc->config, 0);
> +#endif
>         if (ret.error) {
>                 pr_debug("Not able to find a counter for event %lx config %llx\n",
>                         hwc->event_base, hwc->config);
> @@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
>         struct hw_perf_event *hwc = &event->hw;
>         unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
>
> +#if defined(CONFIG_32BIT)
>         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
>                         1, flag, ival, ival >> 32, 0);
> +#else
> +       ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
> +                       1, flag, ival, 0, 0);
> +#endif
>         if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
>                 pr_err("Starting counter idx %d failed with error %d\n",
>                         hwc->idx, sbi_err_map_linux_errno(ret.error));
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/3] RISC-V: Fix SBI PMU calls for RV32
@ 2022-05-24 11:22     ` Anup Patel
  0 siblings, 0 replies; 14+ messages in thread
From: Anup Patel @ 2022-05-24 11:22 UTC (permalink / raw)
  To: Atish Patra
  Cc: linux-kernel@vger.kernel.org List, Atish Patra, Jisheng Zhang,
	linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring

On Fri, May 13, 2022 at 7:25 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> Some of the SBI PMU calls does not pass 64bit arguments
> correctly and not under RV32 compile time flags. Currently,
> this doesn't create any incorrect results as RV64 ignores
> any value in the additional register and qemu doesn't support
> raw events.
>
> Fix those SBI calls in order to set correct values for RV32.
>
> Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Regards,
Anup

> ---
>  drivers/perf/riscv_pmu_sbi.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 7ad92039a718..fab0dd497393 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -274,8 +274,13 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event)
>                 cflags |= SBI_PMU_CFG_FLAG_SET_UINH;
>
>         /* retrieve the available counter index */
> +#if defined(CONFIG_32BIT)
> +       ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
> +                       cflags, hwc->event_base, hwc->config, hwc->config >> 32);
> +#else
>         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, cmask,
>                         cflags, hwc->event_base, hwc->config, 0);
> +#endif
>         if (ret.error) {
>                 pr_debug("Not able to find a counter for event %lx config %llx\n",
>                         hwc->event_base, hwc->config);
> @@ -417,8 +422,13 @@ static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival)
>         struct hw_perf_event *hwc = &event->hw;
>         unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE;
>
> +#if defined(CONFIG_32BIT)
>         ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
>                         1, flag, ival, ival >> 32, 0);
> +#else
> +       ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx,
> +                       1, flag, ival, 0, 0);
> +#endif
>         if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED))
>                 pr_err("Starting counter idx %d failed with error %d\n",
>                         hwc->idx, sbi_err_map_linux_errno(ret.error));
> --
> 2.25.1
>

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v2  0/3] Miscellaneous fixes for PMU driver
  2022-05-13  1:55 ` Atish Patra
@ 2022-06-02  5:58   ` Palmer Dabbelt
  -1 siblings, 0 replies; 14+ messages in thread
From: Palmer Dabbelt @ 2022-06-02  5:58 UTC (permalink / raw)
  To: Atish Patra, Will Deacon, mark.rutland
  Cc: linux-kernel, Atish Patra, atishp, anup, jszhang, linux-riscv,
	Paul Walmsley, robh+dt

On Thu, 12 May 2022 18:55:19 PDT (-0700), Atish Patra wrote:
> This series fixes issues PMU driver code.
> PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
> user page update issue during counter start.
>
> Changes from v1->v2:
> 1. Add proper compile time rv32 checks.
>
> Atish Patra (3):
> RISC-V: Fix counter restart during overflow for RV32
> RISC-V: Update user page mapping only once during start
> RISC-V: Fix SBI PMU calls for RV32
>
> drivers/perf/riscv_pmu.c     |  1 -
> drivers/perf/riscv_pmu_sbi.c | 16 ++++++++++++++++
> 2 files changed, 16 insertions(+), 1 deletion(-)

+Will and Mark.

Will recently took some stuff for drivers/perf/riscv_* into his 
for-next/perf tree (which I didn't even know about until then, oops), 
but the previous stuff I took through the RISC-V tree.  Always happy to 
get stuff out of my tree, just LMK what you want me to do here.

I did some minor cleanups to the commit text and put them over at 
palmer/riscv-pmu_fixes, it's all passing my tests.  These generally look 
fine to me and they're all stable backports, so no big rush on the merge 
window (which I still have stuff for).

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v2  0/3] Miscellaneous fixes for PMU driver
@ 2022-06-02  5:58   ` Palmer Dabbelt
  0 siblings, 0 replies; 14+ messages in thread
From: Palmer Dabbelt @ 2022-06-02  5:58 UTC (permalink / raw)
  To: Atish Patra, Will Deacon, mark.rutland
  Cc: linux-kernel, Atish Patra, atishp, anup, jszhang, linux-riscv,
	Paul Walmsley, robh+dt

On Thu, 12 May 2022 18:55:19 PDT (-0700), Atish Patra wrote:
> This series fixes issues PMU driver code.
> PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
> user page update issue during counter start.
>
> Changes from v1->v2:
> 1. Add proper compile time rv32 checks.
>
> Atish Patra (3):
> RISC-V: Fix counter restart during overflow for RV32
> RISC-V: Update user page mapping only once during start
> RISC-V: Fix SBI PMU calls for RV32
>
> drivers/perf/riscv_pmu.c     |  1 -
> drivers/perf/riscv_pmu_sbi.c | 16 ++++++++++++++++
> 2 files changed, 16 insertions(+), 1 deletion(-)

+Will and Mark.

Will recently took some stuff for drivers/perf/riscv_* into his 
for-next/perf tree (which I didn't even know about until then, oops), 
but the previous stuff I took through the RISC-V tree.  Always happy to 
get stuff out of my tree, just LMK what you want me to do here.

I did some minor cleanups to the commit text and put them over at 
palmer/riscv-pmu_fixes, it's all passing my tests.  These generally look 
fine to me and they're all stable backports, so no big rush on the merge 
window (which I still have stuff for).

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v2  0/3] Miscellaneous fixes for PMU driver
  2022-06-02  5:58   ` Palmer Dabbelt
@ 2022-06-09 13:51     ` Will Deacon
  -1 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2022-06-09 13:51 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: Atish Patra, mark.rutland, linux-kernel, atishp, anup, jszhang,
	linux-riscv, Paul Walmsley, robh+dt

Hey Palmer,

On Wed, Jun 01, 2022 at 10:58:08PM -0700, Palmer Dabbelt wrote:
> On Thu, 12 May 2022 18:55:19 PDT (-0700), Atish Patra wrote:
> > This series fixes issues PMU driver code.
> > PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
> > user page update issue during counter start.
> > 
> > Changes from v1->v2:
> > 1. Add proper compile time rv32 checks.
> > 
> > Atish Patra (3):
> > RISC-V: Fix counter restart during overflow for RV32
> > RISC-V: Update user page mapping only once during start
> > RISC-V: Fix SBI PMU calls for RV32
> > 
> > drivers/perf/riscv_pmu.c     |  1 -
> > drivers/perf/riscv_pmu_sbi.c | 16 ++++++++++++++++
> > 2 files changed, 16 insertions(+), 1 deletion(-)
> 
> +Will and Mark.
> 
> Will recently took some stuff for drivers/perf/riscv_* into his
> for-next/perf tree (which I didn't even know about until then, oops), but
> the previous stuff I took through the RISC-V tree.  Always happy to get
> stuff out of my tree, just LMK what you want me to do here.
> 
> I did some minor cleanups to the commit text and put them over at
> palmer/riscv-pmu_fixes, it's all passing my tests.  These generally look
> fine to me and they're all stable backports, so no big rush on the merge
> window (which I still have stuff for).

I don't have any perf driver fixes queued at the moment, so please just
include these changes along with any other riscv fixes you have.

Thanks,

Will

^ permalink raw reply	[flat|nested] 14+ messages in thread
* Re: [PATCH v2  0/3] Miscellaneous fixes for PMU driver
@ 2022-06-09 13:51     ` Will Deacon
  0 siblings, 0 replies; 14+ messages in thread
From: Will Deacon @ 2022-06-09 13:51 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: Atish Patra, mark.rutland, linux-kernel, atishp, anup, jszhang,
	linux-riscv, Paul Walmsley, robh+dt

Hey Palmer,

On Wed, Jun 01, 2022 at 10:58:08PM -0700, Palmer Dabbelt wrote:
> On Thu, 12 May 2022 18:55:19 PDT (-0700), Atish Patra wrote:
> > This series fixes issues PMU driver code.
> > PATCH 1 & 3 are fixes for rv32 while PATCH 2 fixes a redundant
> > user page update issue during counter start.
> > 
> > Changes from v1->v2:
> > 1. Add proper compile time rv32 checks.
> > 
> > Atish Patra (3):
> > RISC-V: Fix counter restart during overflow for RV32
> > RISC-V: Update user page mapping only once during start
> > RISC-V: Fix SBI PMU calls for RV32
> > 
> > drivers/perf/riscv_pmu.c     |  1 -
> > drivers/perf/riscv_pmu_sbi.c | 16 ++++++++++++++++
> > 2 files changed, 16 insertions(+), 1 deletion(-)
> 
> +Will and Mark.
> 
> Will recently took some stuff for drivers/perf/riscv_* into his
> for-next/perf tree (which I didn't even know about until then, oops), but
> the previous stuff I took through the RISC-V tree.  Always happy to get
> stuff out of my tree, just LMK what you want me to do here.
> 
> I did some minor cleanups to the commit text and put them over at
> palmer/riscv-pmu_fixes, it's all passing my tests.  These generally look
> fine to me and they're all stable backports, so no big rush on the merge
> window (which I still have stuff for).

I don't have any perf driver fixes queued at the moment, so please just
include these changes along with any other riscv fixes you have.

Thanks,

Will

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

^ permalink raw reply	[flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-06-09 13:52 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-13  1:55 [PATCH v2 0/3] Miscellaneous fixes for PMU driver Atish Patra
2022-05-13  1:55 ` Atish Patra
2022-05-13  1:55 ` [PATCH v2 1/3] RISC-V: Fix counter restart during overflow for RV32 Atish Patra
2022-05-13  1:55   ` Atish Patra
2022-05-13  1:55 ` [PATCH v2 2/3] RISC-V: Update user page mapping only once during start Atish Patra
2022-05-13  1:55   ` Atish Patra
2022-05-13  1:55 ` [PATCH v2 3/3] RISC-V: Fix SBI PMU calls for RV32 Atish Patra
2022-05-13  1:55   ` Atish Patra
2022-05-24 11:22   ` Anup Patel
2022-05-24 11:22     ` Anup Patel
2022-06-02  5:58 ` [PATCH v2 0/3] Miscellaneous fixes for PMU driver Palmer Dabbelt
2022-06-02  5:58   ` Palmer Dabbelt
2022-06-09 13:51   ` Will Deacon
2022-06-09 13:51     ` Will Deacon

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.