[PATCH v2 0/9] DG2 VRAM_SR Support

[PATCH v2 0/9] DG2 VRAM_SR Support

[Anshuman Gupta]

This series add DG2 D3Cold VRAM_SR support.

TODO: GuC Interface state save/restore on VRAM_SR entry/exit.

Anshuman Gupta (8):
  drm/i915/dgfx: OpRegion VRAM Self Refresh Support
  drm/i915/dg1: OpRegion PCON DG1 MBD config support
  drm/i915/dg2: Add DG2_NB_MBD subplatform
  drm/i915/dg2: DG2 MBD config
  drm/i915/dgfx: Add has_lmem_sr
  drm/i915/dgfx: Setup VRAM SR with D3COLD
  drm/i915/rpm: Enable D3Cold VRAM SR Support
  drm/i915/rpm: d3cold Policy

Tvrtko Ursulin (1):
  drm/i915/xehpsdv: Store lmem region in gt

 drivers/gpu/drm/i915/display/intel_opregion.c | 107 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_opregion.h |  17 +++
 drivers/gpu/drm/i915/gt/intel_gt.c            |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |   3 +
 drivers/gpu/drm/i915/i915_driver.c            |  49 ++++++++
 drivers/gpu/drm/i915/i915_drv.h               |  20 ++++
 drivers/gpu/drm/i915/i915_params.c            |   4 +
 drivers/gpu/drm/i915/i915_params.h            |   3 +-
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |   4 +
 drivers/gpu/drm/i915/intel_device_info.c      |  21 ++++
 drivers/gpu/drm/i915/intel_device_info.h      |  12 +-
 drivers/gpu/drm/i915/intel_pcode.c            |  28 +++++
 drivers/gpu/drm/i915/intel_pcode.h            |   2 +
 drivers/gpu/drm/i915/intel_pm.c               |  43 +++++++
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c       |   3 +-
 include/drm/i915_pciids.h                     |  23 ++--
 18 files changed, 329 insertions(+), 15 deletions(-)

-- 
2.26.2

[Intel-gfx] [PATCH v2 0/9] DG2 VRAM_SR Support

[Anshuman Gupta]

This series add DG2 D3Cold VRAM_SR support.

TODO: GuC Interface state save/restore on VRAM_SR entry/exit.

Anshuman Gupta (8):
  drm/i915/dgfx: OpRegion VRAM Self Refresh Support
  drm/i915/dg1: OpRegion PCON DG1 MBD config support
  drm/i915/dg2: Add DG2_NB_MBD subplatform
  drm/i915/dg2: DG2 MBD config
  drm/i915/dgfx: Add has_lmem_sr
  drm/i915/dgfx: Setup VRAM SR with D3COLD
  drm/i915/rpm: Enable D3Cold VRAM SR Support
  drm/i915/rpm: d3cold Policy

Tvrtko Ursulin (1):
  drm/i915/xehpsdv: Store lmem region in gt

 drivers/gpu/drm/i915/display/intel_opregion.c | 107 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_opregion.h |  17 +++
 drivers/gpu/drm/i915/gt/intel_gt.c            |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |   3 +
 drivers/gpu/drm/i915/i915_driver.c            |  49 ++++++++
 drivers/gpu/drm/i915/i915_drv.h               |  20 ++++
 drivers/gpu/drm/i915/i915_params.c            |   4 +
 drivers/gpu/drm/i915/i915_params.h            |   3 +-
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/i915_reg.h               |   4 +
 drivers/gpu/drm/i915/intel_device_info.c      |  21 ++++
 drivers/gpu/drm/i915/intel_device_info.h      |  12 +-
 drivers/gpu/drm/i915/intel_pcode.c            |  28 +++++
 drivers/gpu/drm/i915/intel_pcode.h            |   2 +
 drivers/gpu/drm/i915/intel_pm.c               |  43 +++++++
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c       |   3 +-
 include/drm/i915_pciids.h                     |  23 ++--
 18 files changed, 329 insertions(+), 15 deletions(-)

-- 
2.26.2

[PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Anshuman Gupta]

Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.

Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver will evict
lmem objects without VRSR.

VRSR feature requires Host BIOS support, VRSR will be enable/disable
by HOST BIOS using ACPI OpRegion.

Adding OpRegion VRSR support in order to enable/disable
VRSR on discrete cards.

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_opregion.h | 11 ++++
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 6876ba30d5a9..11d8c5bb23ac 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 #define PCON_HEADLESS_SKU	BIT(13)
 
 struct opregion_header {
@@ -130,7 +132,8 @@ struct opregion_asle {
 	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
 			 * address of raw VBT data. */
 	u32 rvds;	/* Size of raw vbt data */
-	u8 rsvd[58];
+	u8 vrsr;	/* DGFX Video Ram Self Refresh */
+	u8 rsvd[57];
 } __packed;
 
 /* OpRegion mailbox #5: ASLE ext */
@@ -201,6 +204,9 @@ struct opregion_asle_ext {
 
 #define ASLE_PHED_EDID_VALID_MASK	0x3
 
+/* VRAM SR */
+#define ASLE_VRSR_ENABLE		BIT(0)
+
 /* Software System Control Interrupt (SWSCI) */
 #define SWSCI_SCIC_INDICATOR		(1 << 0)
 #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
@@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
 		opregion->header->over.minor,
 		opregion->header->over.revision);
 
+	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n", opregion->header->pcon);
+
 	mboxes = opregion->header->mboxes;
 	if (mboxes & MBOX_ACPI) {
 		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
@@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->vbt = NULL;
 	opregion->lid_state = NULL;
 }
+
+/**
+ * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
+ * Refresh capability support.
+ * @i915: pointer to i915 device.
+ *
+ * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
+ * capability support. It is only applocable to DGFX.
+ *
+ * Returns:
+ * true when bios supports vram_sr, or false if bios doesn't support.
+ */
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (!opregion)
+		return false;
+
+	if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
+		return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
+	else
+		return false;
+}
+
+/**
+ * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
+ * @i915: pointer to i915 device.
+ * @enable: Argument to enable/disable VRSR.
+ *
+ * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
+ * HOST BIOS will enables and disbales VRAM_SR during
+ * ACPI _PS3/_OFF and _PS/_ON glue method.
+ */
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!opregion)
+		return;
+
+	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
+		return;
+
+	if (enable)
+		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
+	else
+		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 2f261f985400..73c9d81d5ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
 				  pci_power_t state);
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
 	return false;
 }
 
+static bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+	return false;
+}
+
+static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.26.2

[Intel-gfx] [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Anshuman Gupta]

Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
opportunistic S0ix system wide suspend flow as well.

Without VRSR enablement i915 has to evict the lmem objects to
system memory. Depending on some heuristics driver will evict
lmem objects without VRSR.

VRSR feature requires Host BIOS support, VRSR will be enable/disable
by HOST BIOS using ACPI OpRegion.

Adding OpRegion VRSR support in order to enable/disable
VRSR on discrete cards.

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_opregion.h | 11 ++++
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 6876ba30d5a9..11d8c5bb23ac 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
+#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 #define PCON_HEADLESS_SKU	BIT(13)
 
 struct opregion_header {
@@ -130,7 +132,8 @@ struct opregion_asle {
 	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
 			 * address of raw VBT data. */
 	u32 rvds;	/* Size of raw vbt data */
-	u8 rsvd[58];
+	u8 vrsr;	/* DGFX Video Ram Self Refresh */
+	u8 rsvd[57];
 } __packed;
 
 /* OpRegion mailbox #5: ASLE ext */
@@ -201,6 +204,9 @@ struct opregion_asle_ext {
 
 #define ASLE_PHED_EDID_VALID_MASK	0x3
 
+/* VRAM SR */
+#define ASLE_VRSR_ENABLE		BIT(0)
+
 /* Software System Control Interrupt (SWSCI) */
 #define SWSCI_SCIC_INDICATOR		(1 << 0)
 #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
@@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
 		opregion->header->over.minor,
 		opregion->header->over.revision);
 
+	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n", opregion->header->pcon);
+
 	mboxes = opregion->header->mboxes;
 	if (mboxes & MBOX_ACPI) {
 		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
@@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->vbt = NULL;
 	opregion->lid_state = NULL;
 }
+
+/**
+ * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
+ * Refresh capability support.
+ * @i915: pointer to i915 device.
+ *
+ * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
+ * capability support. It is only applocable to DGFX.
+ *
+ * Returns:
+ * true when bios supports vram_sr, or false if bios doesn't support.
+ */
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (!opregion)
+		return false;
+
+	if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
+		return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
+	else
+		return false;
+}
+
+/**
+ * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
+ * @i915: pointer to i915 device.
+ * @enable: Argument to enable/disable VRSR.
+ *
+ * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
+ * HOST BIOS will enables and disbales VRAM_SR during
+ * ACPI _PS3/_OFF and _PS/_ON glue method.
+ */
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!opregion)
+		return;
+
+	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
+		return;
+
+	if (enable)
+		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
+	else
+		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 2f261f985400..73c9d81d5ee6 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
 				  pci_power_t state);
 int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
+bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
+void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
 	return false;
 }
 
+static bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
+{
+	return false;
+}
+
+static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.26.2

[PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Anshuman Gupta]

DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.

i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
VRSR.

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_opregion.h |  6 +++
 2 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 11d8c5bb23ac..c8cdcde89dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DG1_MBD_CONFIG				BIT(9)
+#define PCON_DG1_MBD_CONFIG_FIELD_VALID			BIT(10)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 #define PCON_HEADLESS_SKU	BIT(13)
@@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->lid_state = NULL;
 }
 
+static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!IS_DG1(i915))
+		return false;
+
+	if (!opregion)
+		return false;
+
+	if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
+		return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
+	else
+		return false;
+}
+
+/**
+ * intel_opregion_vram_sr_required().
+ * @i915 i915 device priv data.
+ *
+ * It checks whether a DGFX card is Mother Board Down config depending
+ * on respective discrete platform.
+ *
+ * Returns:
+ * It returns a boolean whether opregion vram_sr support is required.
+ */
+bool
+intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (IS_DG1(i915))
+		return intel_opregion_dg1_mbd_config(i915);
+
+	return false;
+}
+
 /**
  * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
  * Refresh capability support.
@@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
 	if (!opregion)
 		return;
 
+	if (!intel_opregion_vram_sr_required(i915))
+		return;
+
 	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 73c9d81d5ee6..ad40c97f9565 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
 bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
 void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
+bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
 {
 }
 
+static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	return false;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.26.2

[Intel-gfx] [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Anshuman Gupta]

DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
configs. MBD config requires HOST BIOS GPIO toggling support
in order to enable/disable VRAM SR using ACPI OpRegion.

i915 requires to check OpRegion PCON MBD Config bits to
discover whether Gfx Card is MBD config before enabling
VRSR.

BSpec: 53440
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_opregion.h |  6 +++
 2 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 11d8c5bb23ac..c8cdcde89dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -53,6 +53,8 @@
 #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
 #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
 
+#define PCON_DG1_MBD_CONFIG				BIT(9)
+#define PCON_DG1_MBD_CONFIG_FIELD_VALID			BIT(10)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
 #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
 #define PCON_HEADLESS_SKU	BIT(13)
@@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
 	opregion->lid_state = NULL;
 }
 
+static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
+{
+	struct intel_opregion *opregion = &i915->opregion;
+
+	if (!IS_DG1(i915))
+		return false;
+
+	if (!opregion)
+		return false;
+
+	if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
+		return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
+	else
+		return false;
+}
+
+/**
+ * intel_opregion_vram_sr_required().
+ * @i915 i915 device priv data.
+ *
+ * It checks whether a DGFX card is Mother Board Down config depending
+ * on respective discrete platform.
+ *
+ * Returns:
+ * It returns a boolean whether opregion vram_sr support is required.
+ */
+bool
+intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	if (!IS_DGFX(i915))
+		return false;
+
+	if (IS_DG1(i915))
+		return intel_opregion_dg1_mbd_config(i915);
+
+	return false;
+}
+
 /**
  * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
  * Refresh capability support.
@@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
 	if (!opregion)
 		return;
 
+	if (!intel_opregion_vram_sr_required(i915))
+		return;
+
 	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
index 73c9d81d5ee6..ad40c97f9565 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.h
+++ b/drivers/gpu/drm/i915/display/intel_opregion.h
@@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
 struct edid *intel_opregion_get_edid(struct intel_connector *connector);
 bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
 void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
+bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
 
 bool intel_opregion_headless_sku(struct drm_i915_private *i915);
 
@@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
 {
 }
 
+static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)
+{
+	return false;
+}
+
 #endif /* CONFIG_ACPI */
 
 #endif
-- 
2.26.2

[PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Anshuman Gupta]

DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  3 +++
 drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
 include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
 4 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5bc6a774c5a..f1f8699eedfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 
 #define IS_DG2_G10(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..93da555adc4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
 	INTEL_RPLP_IDS(0),
 };
 
+static const u16 subplatform_g10_mb_mbd_ids[] = {
+	INTEL_DG2_G10_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g11_mb_mbd_ids[] = {
+	INTEL_DG2_G11_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g12_mb_mbd_ids[] = {
+	INTEL_DG2_G12_NB_MBD_IDS(0),
+};
+
 static const u16 subplatform_g10_ids[] = {
 	INTEL_DG2_G10_IDS(0),
 	INTEL_ATS_M150_IDS(0),
@@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	} else if (find_devid(devid, subplatform_rpl_ids,
 			      ARRAY_SIZE(subplatform_rpl_ids))) {
 		mask = BIT(INTEL_SUBPLATFORM_RPL);
+	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
+			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
+	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
+			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
+	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
+			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
 	} else if (find_devid(devid, subplatform_g10_ids,
 			      ARRAY_SIZE(subplatform_g10_ids))) {
 		mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..c929e2d7e59c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -97,7 +97,7 @@ enum intel_platform {
  * it is fine for the same bit to be used on multiple parent platforms.
  */
 
-#define INTEL_SUBPLATFORM_BITS (3)
+#define INTEL_SUBPLATFORM_BITS (6)
 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 
 /* HSW/BDW/SKL/KBL/CFL */
@@ -111,9 +111,12 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_UY	(0)
 
 /* DG2 */
-#define INTEL_SUBPLATFORM_G10	0
-#define INTEL_SUBPLATFORM_G11	1
-#define INTEL_SUBPLATFORM_G12	2
+#define INTEL_SUBPLATFORM_G10_NB_MBD	0
+#define INTEL_SUBPLATFORM_G11_NB_MBD	1
+#define INTEL_SUBPLATFORM_G12_NB_MBD	2
+#define INTEL_SUBPLATFORM_G10	3
+#define INTEL_SUBPLATFORM_G11	4
+#define INTEL_SUBPLATFORM_G12	5
 
 /* ADL */
 #define INTEL_SUBPLATFORM_RPL	0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4585fed4e41e..198be417bb2d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -693,32 +693,41 @@
 	INTEL_VGA_DEVICE(0xA7A9, info)
 
 /* DG2 */
-#define INTEL_DG2_G10_IDS(info) \
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
 	INTEL_VGA_DEVICE(0x5690, info), \
 	INTEL_VGA_DEVICE(0x5691, info), \
-	INTEL_VGA_DEVICE(0x5692, info), \
+	INTEL_VGA_DEVICE(0x5692, info)
+
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5693, info), \
+	INTEL_VGA_DEVICE(0x5694, info), \
+	INTEL_VGA_DEVICE(0x5695, info)
+
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5696, info), \
+	INTEL_VGA_DEVICE(0x5697, info)
+
+#define INTEL_DG2_G10_IDS(info) \
 	INTEL_VGA_DEVICE(0x56A0, info), \
 	INTEL_VGA_DEVICE(0x56A1, info), \
 	INTEL_VGA_DEVICE(0x56A2, info)
 
 #define INTEL_DG2_G11_IDS(info) \
-	INTEL_VGA_DEVICE(0x5693, info), \
-	INTEL_VGA_DEVICE(0x5694, info), \
-	INTEL_VGA_DEVICE(0x5695, info), \
 	INTEL_VGA_DEVICE(0x56A5, info), \
 	INTEL_VGA_DEVICE(0x56A6, info), \
 	INTEL_VGA_DEVICE(0x56B0, info), \
 	INTEL_VGA_DEVICE(0x56B1, info)
 
 #define INTEL_DG2_G12_IDS(info) \
-	INTEL_VGA_DEVICE(0x5696, info), \
-	INTEL_VGA_DEVICE(0x5697, info), \
 	INTEL_VGA_DEVICE(0x56A3, info), \
 	INTEL_VGA_DEVICE(0x56A4, info), \
 	INTEL_VGA_DEVICE(0x56B2, info), \
 	INTEL_VGA_DEVICE(0x56B3, info)
 
 #define INTEL_DG2_IDS(info) \
+	INTEL_DG2_G10_NB_MBD_IDS(info), \
+	INTEL_DG2_G11_NB_MBD_IDS(info), \
+	INTEL_DG2_G12_NB_MBD_IDS(info), \
 	INTEL_DG2_G10_IDS(info), \
 	INTEL_DG2_G11_IDS(info), \
 	INTEL_DG2_G12_IDS(info)
-- 
2.26.2

[Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Anshuman Gupta]

DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  3 +++
 drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
 include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
 4 files changed, 47 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a5bc6a774c5a..f1f8699eedfd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 
 #define IS_DG2_G10(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
 #define IS_DG2_G11(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
 #define IS_DG2_G12(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
 #define IS_ADLS_RPLS(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index f0bf23726ed8..93da555adc4e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
 	INTEL_RPLP_IDS(0),
 };
 
+static const u16 subplatform_g10_mb_mbd_ids[] = {
+	INTEL_DG2_G10_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g11_mb_mbd_ids[] = {
+	INTEL_DG2_G11_NB_MBD_IDS(0),
+};
+
+static const u16 subplatform_g12_mb_mbd_ids[] = {
+	INTEL_DG2_G12_NB_MBD_IDS(0),
+};
+
 static const u16 subplatform_g10_ids[] = {
 	INTEL_DG2_G10_IDS(0),
 	INTEL_ATS_M150_IDS(0),
@@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	} else if (find_devid(devid, subplatform_rpl_ids,
 			      ARRAY_SIZE(subplatform_rpl_ids))) {
 		mask = BIT(INTEL_SUBPLATFORM_RPL);
+	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
+			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
+	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
+			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
+	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
+			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
+		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
 	} else if (find_devid(devid, subplatform_g10_ids,
 			      ARRAY_SIZE(subplatform_g10_ids))) {
 		mask = BIT(INTEL_SUBPLATFORM_G10);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 08341174ee0a..c929e2d7e59c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -97,7 +97,7 @@ enum intel_platform {
  * it is fine for the same bit to be used on multiple parent platforms.
  */
 
-#define INTEL_SUBPLATFORM_BITS (3)
+#define INTEL_SUBPLATFORM_BITS (6)
 #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
 
 /* HSW/BDW/SKL/KBL/CFL */
@@ -111,9 +111,12 @@ enum intel_platform {
 #define INTEL_SUBPLATFORM_UY	(0)
 
 /* DG2 */
-#define INTEL_SUBPLATFORM_G10	0
-#define INTEL_SUBPLATFORM_G11	1
-#define INTEL_SUBPLATFORM_G12	2
+#define INTEL_SUBPLATFORM_G10_NB_MBD	0
+#define INTEL_SUBPLATFORM_G11_NB_MBD	1
+#define INTEL_SUBPLATFORM_G12_NB_MBD	2
+#define INTEL_SUBPLATFORM_G10	3
+#define INTEL_SUBPLATFORM_G11	4
+#define INTEL_SUBPLATFORM_G12	5
 
 /* ADL */
 #define INTEL_SUBPLATFORM_RPL	0
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 4585fed4e41e..198be417bb2d 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -693,32 +693,41 @@
 	INTEL_VGA_DEVICE(0xA7A9, info)
 
 /* DG2 */
-#define INTEL_DG2_G10_IDS(info) \
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
 	INTEL_VGA_DEVICE(0x5690, info), \
 	INTEL_VGA_DEVICE(0x5691, info), \
-	INTEL_VGA_DEVICE(0x5692, info), \
+	INTEL_VGA_DEVICE(0x5692, info)
+
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5693, info), \
+	INTEL_VGA_DEVICE(0x5694, info), \
+	INTEL_VGA_DEVICE(0x5695, info)
+
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5696, info), \
+	INTEL_VGA_DEVICE(0x5697, info)
+
+#define INTEL_DG2_G10_IDS(info) \
 	INTEL_VGA_DEVICE(0x56A0, info), \
 	INTEL_VGA_DEVICE(0x56A1, info), \
 	INTEL_VGA_DEVICE(0x56A2, info)
 
 #define INTEL_DG2_G11_IDS(info) \
-	INTEL_VGA_DEVICE(0x5693, info), \
-	INTEL_VGA_DEVICE(0x5694, info), \
-	INTEL_VGA_DEVICE(0x5695, info), \
 	INTEL_VGA_DEVICE(0x56A5, info), \
 	INTEL_VGA_DEVICE(0x56A6, info), \
 	INTEL_VGA_DEVICE(0x56B0, info), \
 	INTEL_VGA_DEVICE(0x56B1, info)
 
 #define INTEL_DG2_G12_IDS(info) \
-	INTEL_VGA_DEVICE(0x5696, info), \
-	INTEL_VGA_DEVICE(0x5697, info), \
 	INTEL_VGA_DEVICE(0x56A3, info), \
 	INTEL_VGA_DEVICE(0x56A4, info), \
 	INTEL_VGA_DEVICE(0x56B2, info), \
 	INTEL_VGA_DEVICE(0x56B3, info)
 
 #define INTEL_DG2_IDS(info) \
+	INTEL_DG2_G10_NB_MBD_IDS(info), \
+	INTEL_DG2_G11_NB_MBD_IDS(info), \
+	INTEL_DG2_G12_NB_MBD_IDS(info), \
 	INTEL_DG2_G10_IDS(info), \
 	INTEL_DG2_G11_IDS(info), \
 	INTEL_DG2_G12_IDS(info)
-- 
2.26.2

[PATCH v2 4/9] drm/i915/dg2: DG2 MBD config

[Anshuman Gupta]

Add DG2 Motherboard Down Config check support.

v2:
- Don't use pciid to check DG2 MBD. [Jani]

BSpec: 44477
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.h               | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index c8cdcde89dfc..50dcd6d3558e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1291,6 +1291,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private *i915)
 
 	if (IS_DG1(i915))
 		return intel_opregion_dg1_mbd_config(i915);
+	else if (IS_DG2_MBD(i915))
+		return true;
 
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f8699eedfd..28eee8088822 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, INTEL_DG2)
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 
+#define IS_DG2_G10_NB_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD)
+#define IS_DG2_G11_NB_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD)
+#define IS_DG2_G12_NB_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD)
 #define IS_DG2_G10(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
@@ -1015,6 +1021,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2_G12(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+
+#define IS_DG2_MBD(dev_priv) (IS_DG2_G10_NB_MBD(dev_priv) || IS_DG2_G11_NB_MBD(dev_priv) || \
+			      IS_DG2_G12_NB_MBD(dev_priv))
 #define IS_ADLS_RPLS(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(dev_priv) \
-- 
2.26.2

[Intel-gfx] [PATCH v2 4/9] drm/i915/dg2: DG2 MBD config

[Anshuman Gupta]

Add DG2 Motherboard Down Config check support.

v2:
- Don't use pciid to check DG2 MBD. [Jani]

BSpec: 44477
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
 drivers/gpu/drm/i915/i915_drv.h               | 9 +++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index c8cdcde89dfc..50dcd6d3558e 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -1291,6 +1291,8 @@ intel_opregion_vram_sr_required(struct drm_i915_private *i915)
 
 	if (IS_DG1(i915))
 		return intel_opregion_dg1_mbd_config(i915);
+	else if (IS_DG2_MBD(i915))
+		return true;
 
 	return false;
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f8699eedfd..28eee8088822 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,6 +1006,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, INTEL_DG2)
 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
 
+#define IS_DG2_G10_NB_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD)
+#define IS_DG2_G11_NB_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD)
+#define IS_DG2_G12_NB_MBD(dev_priv) \
+	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD)
 #define IS_DG2_G10(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
@@ -1015,6 +1021,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define IS_DG2_G12(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
 	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+
+#define IS_DG2_MBD(dev_priv) (IS_DG2_G10_NB_MBD(dev_priv) || IS_DG2_G11_NB_MBD(dev_priv) || \
+			      IS_DG2_G12_NB_MBD(dev_priv))
 #define IS_ADLS_RPLS(dev_priv) \
 	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
 #define IS_ADLP_N(dev_priv) \
-- 
2.26.2

[PATCH v2 5/9] drm/i915/dgfx: Add has_lmem_sr

[Anshuman Gupta]

Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
is stable.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 1 +
 drivers/gpu/drm/i915/i915_pci.c          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28eee8088822..7983b36c1720 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1313,6 +1313,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr)
 
 /*
  * Platform has the dedicated compression control state for each lmem surfaces
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e51fc29bb8b..04aad54033dd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -917,6 +917,7 @@ static const struct intel_device_info dg1_info = {
 	DGFX_FEATURES,
 	.graphics.rel = 10,
 	PLATFORM(INTEL_DG1),
+	.has_lmem_sr = 0,
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.require_force_probe = 1,
 	.platform_engine_mask =
@@ -1074,6 +1075,7 @@ static const struct intel_device_info xehpsdv_info = {
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
 	XE_LPD_FEATURES,
+	.has_lmem_sr = 1,
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	.require_force_probe = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index c929e2d7e59c..db51cdb9e09a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,6 +157,7 @@ enum intel_ppgtt_type {
 	func(has_l3_ccs_read); \
 	func(has_l3_dpf); \
 	func(has_llc); \
+	func(has_lmem_sr); \
 	func(has_logical_ring_contexts); \
 	func(has_logical_ring_elsq); \
 	func(has_media_ratio_mode); \
-- 
2.26.2

[Intel-gfx] [PATCH v2 5/9] drm/i915/dgfx: Add has_lmem_sr

[Anshuman Gupta]

Add has_lmem_sr platform specific flag to know,
whether platform has VRAM self refresh support.
As of now both DG1 and DG2 client platforms supports VRAM self refresh
with D3Cold but let it enable first on DG2 as primary lead platform
for D3Cold support. Let it get enable on DG1 once this feature
is stable.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 1 +
 drivers/gpu/drm/i915/i915_pci.c          | 2 ++
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28eee8088822..7983b36c1720 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1313,6 +1313,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
+#define HAS_LMEM_SR(i915) (INTEL_INFO(i915)->has_lmem_sr)
 
 /*
  * Platform has the dedicated compression control state for each lmem surfaces
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 5e51fc29bb8b..04aad54033dd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -917,6 +917,7 @@ static const struct intel_device_info dg1_info = {
 	DGFX_FEATURES,
 	.graphics.rel = 10,
 	PLATFORM(INTEL_DG1),
+	.has_lmem_sr = 0,
 	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
 	.require_force_probe = 1,
 	.platform_engine_mask =
@@ -1074,6 +1075,7 @@ static const struct intel_device_info xehpsdv_info = {
 static const struct intel_device_info dg2_info = {
 	DG2_FEATURES,
 	XE_LPD_FEATURES,
+	.has_lmem_sr = 1,
 	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
 			       BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 	.require_force_probe = 1,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index c929e2d7e59c..db51cdb9e09a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -157,6 +157,7 @@ enum intel_ppgtt_type {
 	func(has_l3_ccs_read); \
 	func(has_l3_dpf); \
 	func(has_llc); \
+	func(has_lmem_sr); \
 	func(has_logical_ring_contexts); \
 	func(has_logical_ring_elsq); \
 	func(has_media_ratio_mode); \
-- 
2.26.2

[PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Anshuman Gupta]

Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h    |  7 +++++
 drivers/gpu/drm/i915/i915_reg.h    |  4 +++
 drivers/gpu/drm/i915/intel_pcode.c | 28 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_pcode.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c    | 43 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.h    |  2 ++
 7 files changed, 88 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..aa1fb15b1f11 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto err_msi;
 
+	intel_pm_vram_sr_setup(dev_priv);
+
 	/*
 	 * Fill the dram structure to get the system dram info. This will be
 	 * used for memory latency calculation.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7983b36c1720..09f53aeda8d0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,13 @@ struct drm_i915_private {
 	u32 bxt_phy_grc;
 
 	u32 suspend_count;
+
+	struct {
+		/* lock to protect vram_sr flags */
+		struct mutex lock;
+		bool supported;
+	} vram_sr;
+
 	struct i915_suspend_saved_registers regfile;
 	struct vlv_s0ix_state *vlv_s0ix_state;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 932bd6aa4a0a..0e3dc4a8846a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6766,6 +6766,8 @@
 #define   DG1_PCODE_STATUS			0x7E
 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
+#define   DG1_PCODE_D3_VRAM_SR                  0x71
+#define     DG1_ENABLE_SR                        0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
 #define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
 /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
@@ -6779,6 +6781,8 @@
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
+#define VRAM_CAPABILITY                         _MMIO(0x138144)
+#define   VRAM_SUPPORTED                        REG_BIT(0)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index a234d9b4ed14..88bd1f44cfb2 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
 
 	return err;
 }
+
+/**
+ * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
+ * @dev_priv: i915 device
+ *
+ * This function triggers the required pcode flow to enable vram_sr.
+ * This function stictly need to call from rpm handlers, as i915 is
+ * transitioning to rpm idle/suspend, it doesn't require to grab
+ * rpm wakeref.
+ *
+ * Returns:
+ * returns returned value from pcode mbox write.
+ */
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
+{
+	int ret = 0;
+
+	if (!HAS_LMEM_SR(i915))
+		return ret;
+
+	ret = snb_pcode_write(&i915->uncore,
+			      REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+			      DG1_PCODE_D3_VRAM_SR) |
+			      REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+			      DG1_ENABLE_SR), 0); /* no data needed for this cmd */
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8d2198e29422..295594514d49 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 struct intel_uncore;
+struct drm_i915_private;
 
 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
@@ -26,5 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
  */
 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915);
 
 #endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a61fc3f26c1..299fbc5375a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8166,6 +8166,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 	atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
 }
 
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915)
+{
+	if (!HAS_LMEM_SR(i915))
+		return;
+
+	mutex_init(&i915->vram_sr.lock);
+
+	i915->vram_sr.supported = intel_uncore_read(&i915->uncore,
+						    VRAM_CAPABILITY) & VRAM_SUPPORTED;
+	if (intel_opregion_vram_sr_required(i915))
+		i915->vram_sr.supported = i915->vram_sr.supported &&
+						intel_opregion_bios_supports_vram_sr(i915);
+}
+
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+	int ret = 0;
+
+	if (!HAS_LMEM_SR(i915))
+		return -EOPNOTSUPP;
+
+	mutex_lock(&i915->vram_sr.lock);
+	if (!i915->vram_sr.supported) {
+		drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n");
+		ret = -EOPNOTSUPP;
+		goto unlock;
+	}
+
+	drm_dbg(&i915->drm, "VRAM Self Refresh supported\n");
+	if (enable)
+		ret = intel_pcode_enable_vram_sr(i915);
+
+	if (ret)
+		goto unlock;
+
+	intel_opregion_vram_sr(i915, enable);
+
+unlock:
+	mutex_unlock(&i915->vram_sr.lock);
+
+	return ret;
+}
+
 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
 {
 	struct intel_dbuf_state *dbuf_state;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 50604cf7398c..0da85d6b9ea7 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
-- 
2.26.2

[Intel-gfx] [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Anshuman Gupta]

Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c |  2 ++
 drivers/gpu/drm/i915/i915_drv.h    |  7 +++++
 drivers/gpu/drm/i915/i915_reg.h    |  4 +++
 drivers/gpu/drm/i915/intel_pcode.c | 28 +++++++++++++++++++
 drivers/gpu/drm/i915/intel_pcode.h |  2 ++
 drivers/gpu/drm/i915/intel_pm.c    | 43 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.h    |  2 ++
 7 files changed, 88 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..aa1fb15b1f11 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 	if (ret)
 		goto err_msi;
 
+	intel_pm_vram_sr_setup(dev_priv);
+
 	/*
 	 * Fill the dram structure to get the system dram info. This will be
 	 * used for memory latency calculation.
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7983b36c1720..09f53aeda8d0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -624,6 +624,13 @@ struct drm_i915_private {
 	u32 bxt_phy_grc;
 
 	u32 suspend_count;
+
+	struct {
+		/* lock to protect vram_sr flags */
+		struct mutex lock;
+		bool supported;
+	} vram_sr;
+
 	struct i915_suspend_saved_registers regfile;
 	struct vlv_s0ix_state *vlv_s0ix_state;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 932bd6aa4a0a..0e3dc4a8846a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6766,6 +6766,8 @@
 #define   DG1_PCODE_STATUS			0x7E
 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
+#define   DG1_PCODE_D3_VRAM_SR                  0x71
+#define     DG1_ENABLE_SR                        0x1
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
 #define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
 /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
@@ -6779,6 +6781,8 @@
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
+#define VRAM_CAPABILITY                         _MMIO(0x138144)
+#define   VRAM_SUPPORTED                        REG_BIT(0)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index a234d9b4ed14..88bd1f44cfb2 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
 
 	return err;
 }
+
+/**
+ * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
+ * @dev_priv: i915 device
+ *
+ * This function triggers the required pcode flow to enable vram_sr.
+ * This function stictly need to call from rpm handlers, as i915 is
+ * transitioning to rpm idle/suspend, it doesn't require to grab
+ * rpm wakeref.
+ *
+ * Returns:
+ * returns returned value from pcode mbox write.
+ */
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
+{
+	int ret = 0;
+
+	if (!HAS_LMEM_SR(i915))
+		return ret;
+
+	ret = snb_pcode_write(&i915->uncore,
+			      REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+			      DG1_PCODE_D3_VRAM_SR) |
+			      REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+			      DG1_ENABLE_SR), 0); /* no data needed for this cmd */
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index 8d2198e29422..295594514d49 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -9,6 +9,7 @@
 #include <linux/types.h>
 
 struct intel_uncore;
+struct drm_i915_private;
 
 int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
 int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
@@ -26,5 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
  */
 int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
 int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
+int intel_pcode_enable_vram_sr(struct drm_i915_private *i915);
 
 #endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a61fc3f26c1..299fbc5375a9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8166,6 +8166,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
 	atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
 }
 
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915)
+{
+	if (!HAS_LMEM_SR(i915))
+		return;
+
+	mutex_init(&i915->vram_sr.lock);
+
+	i915->vram_sr.supported = intel_uncore_read(&i915->uncore,
+						    VRAM_CAPABILITY) & VRAM_SUPPORTED;
+	if (intel_opregion_vram_sr_required(i915))
+		i915->vram_sr.supported = i915->vram_sr.supported &&
+						intel_opregion_bios_supports_vram_sr(i915);
+}
+
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
+{
+	int ret = 0;
+
+	if (!HAS_LMEM_SR(i915))
+		return -EOPNOTSUPP;
+
+	mutex_lock(&i915->vram_sr.lock);
+	if (!i915->vram_sr.supported) {
+		drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n");
+		ret = -EOPNOTSUPP;
+		goto unlock;
+	}
+
+	drm_dbg(&i915->drm, "VRAM Self Refresh supported\n");
+	if (enable)
+		ret = intel_pcode_enable_vram_sr(i915);
+
+	if (ret)
+		goto unlock;
+
+	intel_opregion_vram_sr(i915, enable);
+
+unlock:
+	mutex_unlock(&i915->vram_sr.lock);
+
+	return ret;
+}
+
 static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
 {
 	struct intel_dbuf_state *dbuf_state;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 50604cf7398c..0da85d6b9ea7 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
+void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
+int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
 void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
-- 
2.26.2

[PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Anshuman Gupta]

Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.

i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with additional power cost which required to retain
the lmem.

Adding intel_runtime_idle (runtime_idle callback) to enable
VRAM_SR, it will be used for policy to choose
between D3Cold-off vs D3Cold-VRAM_SR.

Since we have introduced i915 runtime_idle callback.
It need to be warranted that Runtime PM Core invokes runtime_idle
callback when runtime usages count becomes zero. That requires
to use pm_runtime_put instead of pm_runtime_put_autosuspend.

TODO: GuC interface state save/restore.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c      | 26 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index aa1fb15b1f11..fcff5f3fe05e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
 	return i915_pm_resume(kdev);
 }
 
+static int intel_runtime_idle(struct device *kdev)
+{
+	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+	int ret = 1;
+
+	if (!HAS_LMEM_SR(dev_priv)) {
+		/*TODO: Prepare for D3Cold-Off */
+		goto out;
+	}
+
+	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+
+	ret = intel_pm_vram_sr(dev_priv, true);
+	if (!ret)
+		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
+
+	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+
+out:
+	pm_runtime_mark_last_busy(kdev);
+	pm_runtime_autosuspend(kdev);
+
+	return ret;
+}
+
 static int intel_runtime_suspend(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
@@ -1742,6 +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
 	.restore = i915_pm_restore,
 
 	/* S0ix (via runtime suspend) event handlers */
+	.runtime_idle = intel_runtime_idle,
 	.runtime_suspend = intel_runtime_suspend,
 	.runtime_resume = intel_runtime_resume,
 };
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6ed5786bcd29..4dade7e8a795 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm *rpm,
 
 	intel_runtime_pm_release(rpm, wakelock);
 
-	pm_runtime_mark_last_busy(kdev);
-	pm_runtime_put_autosuspend(kdev);
+	pm_runtime_put(kdev);
 }
 
 /**
-- 
2.26.2

[Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Anshuman Gupta]

Intel Client DGFX card supports D3Cold with two option.
D3Cold-off zero watt, D3Cold-VRAM Self Refresh.

i915 requires to evict the lmem objects to smem in order to
support D3Cold-Off, which increases i915 the suspend/resume
latency. Enabling VRAM Self Refresh feature optimize the
latency with additional power cost which required to retain
the lmem.

Adding intel_runtime_idle (runtime_idle callback) to enable
VRAM_SR, it will be used for policy to choose
between D3Cold-off vs D3Cold-VRAM_SR.

Since we have introduced i915 runtime_idle callback.
It need to be warranted that Runtime PM Core invokes runtime_idle
callback when runtime usages count becomes zero. That requires
to use pm_runtime_put instead of pm_runtime_put_autosuspend.

TODO: GuC interface state save/restore.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c      | 26 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index aa1fb15b1f11..fcff5f3fe05e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
 	return i915_pm_resume(kdev);
 }
 
+static int intel_runtime_idle(struct device *kdev)
+{
+	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+	int ret = 1;
+
+	if (!HAS_LMEM_SR(dev_priv)) {
+		/*TODO: Prepare for D3Cold-Off */
+		goto out;
+	}
+
+	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+
+	ret = intel_pm_vram_sr(dev_priv, true);
+	if (!ret)
+		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
+
+	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+
+out:
+	pm_runtime_mark_last_busy(kdev);
+	pm_runtime_autosuspend(kdev);
+
+	return ret;
+}
+
 static int intel_runtime_suspend(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
@@ -1742,6 +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
 	.restore = i915_pm_restore,
 
 	/* S0ix (via runtime suspend) event handlers */
+	.runtime_idle = intel_runtime_idle,
 	.runtime_suspend = intel_runtime_suspend,
 	.runtime_resume = intel_runtime_resume,
 };
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6ed5786bcd29..4dade7e8a795 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm *rpm,
 
 	intel_runtime_pm_release(rpm, wakelock);
 
-	pm_runtime_mark_last_busy(kdev);
-	pm_runtime_put_autosuspend(kdev);
+	pm_runtime_put(kdev);
 }
 
 /**
-- 
2.26.2

[Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Anshuman Gupta]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.

Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f33290358c51..7a535f670ae1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
 	GEM_BUG_ON(!HAS_REGION(i915, id));
 	GEM_BUG_ON(i915->mm.regions[id]);
 	i915->mm.regions[id] = mem;
+	gt->lmem = mem;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index df708802889d..cd7744eaaeaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
 #include "intel_llc_types.h"
+#include "intel_memory_region.h"
 #include "intel_reset_types.h"
 #include "intel_rc6_types.h"
 #include "intel_rps_types.h"
@@ -202,6 +203,8 @@ struct intel_gt {
 	 */
 	phys_addr_t phys_addr;
 
+	struct intel_memory_region *lmem;
+
 	struct intel_gt_info {
 		unsigned int id;
 
-- 
2.26.2

[PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Anshuman Gupta]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.

Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c       | 1 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f33290358c51..7a535f670ae1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
 	GEM_BUG_ON(!HAS_REGION(i915, id));
 	GEM_BUG_ON(i915->mm.regions[id]);
 	i915->mm.regions[id] = mem;
+	gt->lmem = mem;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index df708802889d..cd7744eaaeaa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -23,6 +23,7 @@
 #include "intel_gt_buffer_pool_types.h"
 #include "intel_hwconfig.h"
 #include "intel_llc_types.h"
+#include "intel_memory_region.h"
 #include "intel_reset_types.h"
 #include "intel_rc6_types.h"
 #include "intel_rps_types.h"
@@ -202,6 +203,8 @@ struct intel_gt {
 	 */
 	phys_addr_t phys_addr;
 
+	struct intel_memory_region *lmem;
+
 	struct intel_gt_info {
 		unsigned int id;
 
-- 
2.26.2

[PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Anshuman Gupta]

Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off.

If gfx root port is not capable of sending PME from d3cold
then i915 don't need to program d3cold-off/d3cold-vram_sr
sequence.

FIXME: Eviction of lmem objects in case of D3Cold off is wip.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_params.c |  4 ++++
 drivers/gpu/drm/i915/i915_params.h |  3 ++-
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index fcff5f3fe05e..aef4b17efdbe 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev)
 static int intel_runtime_idle(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	u64 lmem_total = to_gt(dev_priv)->lmem->total;
+	u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
+	u64 lmem_used = lmem_total - lmem_avail;
+	struct pci_dev *root_pdev;
 	int ret = 1;
 
-	if (!HAS_LMEM_SR(dev_priv)) {
-		/*TODO: Prepare for D3Cold-Off */
+	root_pdev = pcie_find_root_port(pdev);
+	if (!root_pdev)
+		goto out;
+
+	if (!pci_pme_capable(root_pdev, PCI_D3cold))
 		goto out;
-	}
 
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
+	if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 * 1024) {
+		drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n");
+		pci_d3cold_enable(root_pdev);
+		/* FIXME: Eviction of lmem objects and guc reset is wip */
+		intel_pm_vram_sr(dev_priv, false);
+		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+		goto out;
+	} else if (!HAS_LMEM_SR(dev_priv)) {
+		/* Disable D3Cold to reduce the eviction latency */
+		pci_d3cold_disable(root_pdev);
+		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+		goto out;
+	}
+
 	ret = intel_pm_vram_sr(dev_priv, true);
 	if (!ret)
 		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6c6b3c372d4d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
 	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
 #endif
 
+i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
+	"Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. "
+	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
+
 #if CONFIG_DRM_I915_REQUEST_TIMEOUT
 i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 			"Default request/fence/batch buffer expiration timeout.");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..28f20ebaf41f 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -83,7 +83,8 @@ struct drm_printer;
 	param(bool, verbose_state_checks, true, 0) \
 	param(bool, nuclear_pageflip, false, 0400) \
 	param(bool, enable_dp_mst, true, 0600) \
-	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0)
+	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \
+	param(int, d3cold_sr_lmem_threshold, 300, 0600) \
 
 #define MEMBER(T, member, ...) T member;
 struct i915_params {
-- 
2.26.2

[Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Anshuman Gupta]

Add d3cold_sr_lmem_threshold modparam to choose between
d3cold-off zero watt and d3cold-VRAM Self Refresh.
i915 requires to evict the lmem objects to smem in order to
support d3cold-Off.

If gfx root port is not capable of sending PME from d3cold
then i915 don't need to program d3cold-off/d3cold-vram_sr
sequence.

FIXME: Eviction of lmem objects in case of D3Cold off is wip.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++---
 drivers/gpu/drm/i915/i915_params.c |  4 ++++
 drivers/gpu/drm/i915/i915_params.h |  3 ++-
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index fcff5f3fe05e..aef4b17efdbe 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev)
 static int intel_runtime_idle(struct device *kdev)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+	u64 lmem_total = to_gt(dev_priv)->lmem->total;
+	u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
+	u64 lmem_used = lmem_total - lmem_avail;
+	struct pci_dev *root_pdev;
 	int ret = 1;
 
-	if (!HAS_LMEM_SR(dev_priv)) {
-		/*TODO: Prepare for D3Cold-Off */
+	root_pdev = pcie_find_root_port(pdev);
+	if (!root_pdev)
+		goto out;
+
+	if (!pci_pme_capable(root_pdev, PCI_D3cold))
 		goto out;
-	}
 
 	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
 
+	if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 * 1024) {
+		drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n");
+		pci_d3cold_enable(root_pdev);
+		/* FIXME: Eviction of lmem objects and guc reset is wip */
+		intel_pm_vram_sr(dev_priv, false);
+		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+		goto out;
+	} else if (!HAS_LMEM_SR(dev_priv)) {
+		/* Disable D3Cold to reduce the eviction latency */
+		pci_d3cold_disable(root_pdev);
+		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
+		goto out;
+	}
+
 	ret = intel_pm_vram_sr(dev_priv, true);
 	if (!ret)
 		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6c6b3c372d4d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
 	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
 #endif
 
+i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
+	"Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. "
+	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
+
 #if CONFIG_DRM_I915_REQUEST_TIMEOUT
 i915_param_named_unsafe(request_timeout_ms, uint, 0600,
 			"Default request/fence/batch buffer expiration timeout.");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..28f20ebaf41f 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -83,7 +83,8 @@ struct drm_printer;
 	param(bool, verbose_state_checks, true, 0) \
 	param(bool, nuclear_pageflip, false, 0400) \
 	param(bool, enable_dp_mst, true, 0600) \
-	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0)
+	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \
+	param(int, d3cold_sr_lmem_threshold, 300, 0600) \
 
 #define MEMBER(T, member, ...) T member;
 struct i915_params {
-- 
2.26.2

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Tvrtko Ursulin]

On 16/06/2022 13:01, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>   drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
>   include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
>   4 files changed, 47 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5bc6a774c5a..f1f8699eedfd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>   #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>   
>   #define IS_DG2_G10(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>   	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>   #define IS_DG2_G11(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>   	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>   #define IS_DG2_G12(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>   	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>   #define IS_ADLS_RPLS(dev_priv) \
>   	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..93da555adc4e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>   	INTEL_RPLP_IDS(0),
>   };
>   
> +static const u16 subplatform_g10_mb_mbd_ids[] = {
> +	INTEL_DG2_G10_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g11_mb_mbd_ids[] = {
> +	INTEL_DG2_G11_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g12_mb_mbd_ids[] = {
> +	INTEL_DG2_G12_NB_MBD_IDS(0),
> +};
> +
>   static const u16 subplatform_g10_ids[] = {
>   	INTEL_DG2_G10_IDS(0),
>   	INTEL_ATS_M150_IDS(0),
> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>   	} else if (find_devid(devid, subplatform_rpl_ids,
>   			      ARRAY_SIZE(subplatform_rpl_ids))) {
>   		mask = BIT(INTEL_SUBPLATFORM_RPL);
> +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
>   	} else if (find_devid(devid, subplatform_g10_ids,
>   			      ARRAY_SIZE(subplatform_g10_ids))) {
>   		mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 08341174ee0a..c929e2d7e59c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -97,7 +97,7 @@ enum intel_platform {
>    * it is fine for the same bit to be used on multiple parent platforms.
>    */
>   
> -#define INTEL_SUBPLATFORM_BITS (3)
> +#define INTEL_SUBPLATFORM_BITS (6)
>   #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>   
>   /* HSW/BDW/SKL/KBL/CFL */
> @@ -111,9 +111,12 @@ enum intel_platform {
>   #define INTEL_SUBPLATFORM_UY	(0)
>   
>   /* DG2 */
> -#define INTEL_SUBPLATFORM_G10	0
> -#define INTEL_SUBPLATFORM_G11	1
> -#define INTEL_SUBPLATFORM_G12	2
> +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
> +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
> +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
> +#define INTEL_SUBPLATFORM_G10	3
> +#define INTEL_SUBPLATFORM_G11	4
> +#define INTEL_SUBPLATFORM_G12	5

Ugh I feel this "breaks" the subplatform idea.. feels like it is just 
too many bits when two separate sets of information get tracked (Gxx 
plus MBD).

How about a separate "is_mbd" flag in runtime_info? You can split the 
PCI IDs split as you have done, but do a search against the MBD ones and 
set the flag.

Regards,

Tvrtko

>   
>   /* ADL */
>   #define INTEL_SUBPLATFORM_RPL	0
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 4585fed4e41e..198be417bb2d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -693,32 +693,41 @@
>   	INTEL_VGA_DEVICE(0xA7A9, info)
>   
>   /* DG2 */
> -#define INTEL_DG2_G10_IDS(info) \
> +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
>   	INTEL_VGA_DEVICE(0x5690, info), \
>   	INTEL_VGA_DEVICE(0x5691, info), \
> -	INTEL_VGA_DEVICE(0x5692, info), \
> +	INTEL_VGA_DEVICE(0x5692, info)
> +
> +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5693, info), \
> +	INTEL_VGA_DEVICE(0x5694, info), \
> +	INTEL_VGA_DEVICE(0x5695, info)
> +
> +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5696, info), \
> +	INTEL_VGA_DEVICE(0x5697, info)
> +
> +#define INTEL_DG2_G10_IDS(info) \
>   	INTEL_VGA_DEVICE(0x56A0, info), \
>   	INTEL_VGA_DEVICE(0x56A1, info), \
>   	INTEL_VGA_DEVICE(0x56A2, info)
>   
>   #define INTEL_DG2_G11_IDS(info) \
> -	INTEL_VGA_DEVICE(0x5693, info), \
> -	INTEL_VGA_DEVICE(0x5694, info), \
> -	INTEL_VGA_DEVICE(0x5695, info), \
>   	INTEL_VGA_DEVICE(0x56A5, info), \
>   	INTEL_VGA_DEVICE(0x56A6, info), \
>   	INTEL_VGA_DEVICE(0x56B0, info), \
>   	INTEL_VGA_DEVICE(0x56B1, info)
>   
>   #define INTEL_DG2_G12_IDS(info) \
> -	INTEL_VGA_DEVICE(0x5696, info), \
> -	INTEL_VGA_DEVICE(0x5697, info), \
>   	INTEL_VGA_DEVICE(0x56A3, info), \
>   	INTEL_VGA_DEVICE(0x56A4, info), \
>   	INTEL_VGA_DEVICE(0x56B2, info), \
>   	INTEL_VGA_DEVICE(0x56B3, info)
>   
>   #define INTEL_DG2_IDS(info) \
> +	INTEL_DG2_G10_NB_MBD_IDS(info), \
> +	INTEL_DG2_G11_NB_MBD_IDS(info), \
> +	INTEL_DG2_G12_NB_MBD_IDS(info), \
>   	INTEL_DG2_G10_IDS(info), \
>   	INTEL_DG2_G11_IDS(info), \
>   	INTEL_DG2_G12_IDS(info)

Re: [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Setup VRAM Self Refresh with D3COLD state.
> VRAM Self Refresh will retain the context of VRAM, driver
> need to save any corresponding hardware state that needs
> to be restore on D3COLD exit, example PCI state.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_driver.c |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h    |  7 +++++
>  drivers/gpu/drm/i915/i915_reg.h    |  4 +++
>  drivers/gpu/drm/i915/intel_pcode.c | 28 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pcode.h |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c    | 43 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.h    |  2 ++
>  7 files changed, 88 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..aa1fb15b1f11 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>  	if (ret)
>  		goto err_msi;
>  
> +	intel_pm_vram_sr_setup(dev_priv);
> +
>  	/*
>  	 * Fill the dram structure to get the system dram info. This will be
>  	 * used for memory latency calculation.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7983b36c1720..09f53aeda8d0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -624,6 +624,13 @@ struct drm_i915_private {
>  	u32 bxt_phy_grc;
>  
>  	u32 suspend_count;
> +
> +	struct {
> +		/* lock to protect vram_sr flags */
> +		struct mutex lock;
> +		bool supported;
> +	} vram_sr;
> +
>  	struct i915_suspend_saved_registers regfile;
>  	struct vlv_s0ix_state *vlv_s0ix_state;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 932bd6aa4a0a..0e3dc4a8846a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6766,6 +6766,8 @@
>  #define   DG1_PCODE_STATUS			0x7E
>  #define     DG1_UNCORE_GET_INIT_STATUS		0x0
>  #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> +#define   DG1_PCODE_D3_VRAM_SR                  0x71
> +#define     DG1_ENABLE_SR                        0x1
>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>  #define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
>  /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> @@ -6779,6 +6781,8 @@
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
>  #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
> +#define VRAM_CAPABILITY                         _MMIO(0x138144)
> +#define   VRAM_SUPPORTED                        REG_BIT(0)
>  
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
> index a234d9b4ed14..88bd1f44cfb2 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.c
> +++ b/drivers/gpu/drm/i915/intel_pcode.c
> @@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
>  
>  	return err;
>  }
> +
> +/**
> + * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
> + * @dev_priv: i915 device
> + *
> + * This function triggers the required pcode flow to enable vram_sr.
> + * This function stictly need to call from rpm handlers, as i915 is
> + * transitioning to rpm idle/suspend, it doesn't require to grab
> + * rpm wakeref.
> + *
> + * Returns:
> + * returns returned value from pcode mbox write.
> + */
> +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
> +{
> +	int ret = 0;
> +
> +	if (!HAS_LMEM_SR(i915))
> +		return ret;
> +
> +	ret = snb_pcode_write(&i915->uncore,
> +			      REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
> +			      DG1_PCODE_D3_VRAM_SR) |
> +			      REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
> +			      DG1_ENABLE_SR), 0); /* no data needed for this cmd */
> +
> +	return ret;
> +}

This function doesn't belong here. intel_pcode.c provides the
*mechanisms* for pcode access, not specific stuff like this. Just put
this near the use in intel_pm.c I think.


> diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
> index 8d2198e29422..295594514d49 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.h
> +++ b/drivers/gpu/drm/i915/intel_pcode.h
> @@ -9,6 +9,7 @@
>  #include <linux/types.h>
>  
>  struct intel_uncore;
> +struct drm_i915_private;
>  
>  int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
>  int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
> @@ -26,5 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
>   */
>  int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
>  int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
> +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915);
>  
>  #endif /* _INTEL_PCODE_H */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5a61fc3f26c1..299fbc5375a9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8166,6 +8166,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
>  	atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
>  }
>  
> +void intel_pm_vram_sr_setup(struct drm_i915_private *i915)
> +{
> +	if (!HAS_LMEM_SR(i915))
> +		return;
> +
> +	mutex_init(&i915->vram_sr.lock);
> +
> +	i915->vram_sr.supported = intel_uncore_read(&i915->uncore,
> +						    VRAM_CAPABILITY) & VRAM_SUPPORTED;
> +	if (intel_opregion_vram_sr_required(i915))
> +		i915->vram_sr.supported = i915->vram_sr.supported &&
> +						intel_opregion_bios_supports_vram_sr(i915);
> +}
> +
> +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> +	int ret = 0;
> +
> +	if (!HAS_LMEM_SR(i915))
> +		return -EOPNOTSUPP;

You can drop this and only look at i915->vram_sr.supported.

> +
> +	mutex_lock(&i915->vram_sr.lock);
> +	if (!i915->vram_sr.supported) {
> +		drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n");
> +		ret = -EOPNOTSUPP;
> +		goto unlock;
> +	}

This part doesn't need the mutex protection. You don't actually change
i915->vram_sr.supported anywhere after initialization.

> +
> +	drm_dbg(&i915->drm, "VRAM Self Refresh supported\n");
> +	if (enable)
> +		ret = intel_pcode_enable_vram_sr(i915);
> +
> +	if (ret)
> +		goto unlock;
> +
> +	intel_opregion_vram_sr(i915, enable);
> +
> +unlock:
> +	mutex_unlock(&i915->vram_sr.lock);
> +
> +	return ret;
> +}
> +
>  static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
>  {
>  	struct intel_dbuf_state *dbuf_state;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 50604cf7398c..0da85d6b9ea7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
>  void intel_init_pm(struct drm_i915_private *dev_priv);
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
>  void intel_pm_setup(struct drm_i915_private *dev_priv);
> +void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
> +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
>  void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
>  void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
>  void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 6/9] drm/i915/dgfx: Setup VRAM SR with D3COLD

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Setup VRAM Self Refresh with D3COLD state.
> VRAM Self Refresh will retain the context of VRAM, driver
> need to save any corresponding hardware state that needs
> to be restore on D3COLD exit, example PCI state.
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_driver.c |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h    |  7 +++++
>  drivers/gpu/drm/i915/i915_reg.h    |  4 +++
>  drivers/gpu/drm/i915/intel_pcode.c | 28 +++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pcode.h |  2 ++
>  drivers/gpu/drm/i915/intel_pm.c    | 43 ++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.h    |  2 ++
>  7 files changed, 88 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..aa1fb15b1f11 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -649,6 +649,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>  	if (ret)
>  		goto err_msi;
>  
> +	intel_pm_vram_sr_setup(dev_priv);
> +
>  	/*
>  	 * Fill the dram structure to get the system dram info. This will be
>  	 * used for memory latency calculation.
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7983b36c1720..09f53aeda8d0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -624,6 +624,13 @@ struct drm_i915_private {
>  	u32 bxt_phy_grc;
>  
>  	u32 suspend_count;
> +
> +	struct {
> +		/* lock to protect vram_sr flags */
> +		struct mutex lock;
> +		bool supported;
> +	} vram_sr;
> +
>  	struct i915_suspend_saved_registers regfile;
>  	struct vlv_s0ix_state *vlv_s0ix_state;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 932bd6aa4a0a..0e3dc4a8846a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6766,6 +6766,8 @@
>  #define   DG1_PCODE_STATUS			0x7E
>  #define     DG1_UNCORE_GET_INIT_STATUS		0x0
>  #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> +#define   DG1_PCODE_D3_VRAM_SR                  0x71
> +#define     DG1_ENABLE_SR                        0x1
>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>  #define   XEHPSDV_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
>  /* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
> @@ -6779,6 +6781,8 @@
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
>  #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
> +#define VRAM_CAPABILITY                         _MMIO(0x138144)
> +#define   VRAM_SUPPORTED                        REG_BIT(0)
>  
>  /* IVYBRIDGE DPF */
>  #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
> diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
> index a234d9b4ed14..88bd1f44cfb2 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.c
> +++ b/drivers/gpu/drm/i915/intel_pcode.c
> @@ -246,3 +246,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
>  
>  	return err;
>  }
> +
> +/**
> + * intel_pcode_enable_vram_sr - Enable pcode vram_sr.
> + * @dev_priv: i915 device
> + *
> + * This function triggers the required pcode flow to enable vram_sr.
> + * This function stictly need to call from rpm handlers, as i915 is
> + * transitioning to rpm idle/suspend, it doesn't require to grab
> + * rpm wakeref.
> + *
> + * Returns:
> + * returns returned value from pcode mbox write.
> + */
> +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915)
> +{
> +	int ret = 0;
> +
> +	if (!HAS_LMEM_SR(i915))
> +		return ret;
> +
> +	ret = snb_pcode_write(&i915->uncore,
> +			      REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
> +			      DG1_PCODE_D3_VRAM_SR) |
> +			      REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
> +			      DG1_ENABLE_SR), 0); /* no data needed for this cmd */
> +
> +	return ret;
> +}

This function doesn't belong here. intel_pcode.c provides the
*mechanisms* for pcode access, not specific stuff like this. Just put
this near the use in intel_pm.c I think.


> diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
> index 8d2198e29422..295594514d49 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.h
> +++ b/drivers/gpu/drm/i915/intel_pcode.h
> @@ -9,6 +9,7 @@
>  #include <linux/types.h>
>  
>  struct intel_uncore;
> +struct drm_i915_private;
>  
>  int snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1);
>  int snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,
> @@ -26,5 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
>   */
>  int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
>  int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
> +int intel_pcode_enable_vram_sr(struct drm_i915_private *i915);
>  
>  #endif /* _INTEL_PCODE_H */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5a61fc3f26c1..299fbc5375a9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8166,6 +8166,49 @@ void intel_pm_setup(struct drm_i915_private *dev_priv)
>  	atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
>  }
>  
> +void intel_pm_vram_sr_setup(struct drm_i915_private *i915)
> +{
> +	if (!HAS_LMEM_SR(i915))
> +		return;
> +
> +	mutex_init(&i915->vram_sr.lock);
> +
> +	i915->vram_sr.supported = intel_uncore_read(&i915->uncore,
> +						    VRAM_CAPABILITY) & VRAM_SUPPORTED;
> +	if (intel_opregion_vram_sr_required(i915))
> +		i915->vram_sr.supported = i915->vram_sr.supported &&
> +						intel_opregion_bios_supports_vram_sr(i915);
> +}
> +
> +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> +	int ret = 0;
> +
> +	if (!HAS_LMEM_SR(i915))
> +		return -EOPNOTSUPP;

You can drop this and only look at i915->vram_sr.supported.

> +
> +	mutex_lock(&i915->vram_sr.lock);
> +	if (!i915->vram_sr.supported) {
> +		drm_dbg(&i915->drm, "VRAM Self Refresh is not supported\n");
> +		ret = -EOPNOTSUPP;
> +		goto unlock;
> +	}

This part doesn't need the mutex protection. You don't actually change
i915->vram_sr.supported anywhere after initialization.

> +
> +	drm_dbg(&i915->drm, "VRAM Self Refresh supported\n");
> +	if (enable)
> +		ret = intel_pcode_enable_vram_sr(i915);
> +
> +	if (ret)
> +		goto unlock;
> +
> +	intel_opregion_vram_sr(i915, enable);
> +
> +unlock:
> +	mutex_unlock(&i915->vram_sr.lock);
> +
> +	return ret;
> +}
> +
>  static struct intel_global_state *intel_dbuf_duplicate_state(struct intel_global_obj *obj)
>  {
>  	struct intel_dbuf_state *dbuf_state;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 50604cf7398c..0da85d6b9ea7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -31,6 +31,8 @@ int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
>  void intel_init_pm(struct drm_i915_private *dev_priv);
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
>  void intel_pm_setup(struct drm_i915_private *dev_priv);
> +void intel_pm_vram_sr_setup(struct drm_i915_private *i915);
> +int intel_pm_vram_sr(struct drm_i915_private *i915, bool enable);
>  void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
>  void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
>  void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> opportunistic S0ix system wide suspend flow as well.
>
> Without VRSR enablement i915 has to evict the lmem objects to
> system memory. Depending on some heuristics driver will evict
> lmem objects without VRSR.
>
> VRSR feature requires Host BIOS support, VRSR will be enable/disable
> by HOST BIOS using ACPI OpRegion.
>
> Adding OpRegion VRSR support in order to enable/disable
> VRSR on discrete cards.
>
> BSpec: 53440
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_opregion.h | 11 ++++
>  2 files changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 6876ba30d5a9..11d8c5bb23ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
>  #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
>  
> +#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
> +#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
>  #define PCON_HEADLESS_SKU	BIT(13)
>  
>  struct opregion_header {
> @@ -130,7 +132,8 @@ struct opregion_asle {
>  	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
>  			 * address of raw VBT data. */
>  	u32 rvds;	/* Size of raw vbt data */
> -	u8 rsvd[58];
> +	u8 vrsr;	/* DGFX Video Ram Self Refresh */
> +	u8 rsvd[57];
>  } __packed;
>  
>  /* OpRegion mailbox #5: ASLE ext */
> @@ -201,6 +204,9 @@ struct opregion_asle_ext {
>  
>  #define ASLE_PHED_EDID_VALID_MASK	0x3
>  
> +/* VRAM SR */
> +#define ASLE_VRSR_ENABLE		BIT(0)
> +
>  /* Software System Control Interrupt (SWSCI) */
>  #define SWSCI_SCIC_INDICATOR		(1 << 0)
>  #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
> @@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
>  		opregion->header->over.minor,
>  		opregion->header->over.revision);
>  
> +	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n", opregion->header->pcon);
> +
>  	mboxes = opregion->header->mboxes;
>  	if (mboxes & MBOX_ACPI) {
>  		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
> @@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
>  	opregion->vbt = NULL;
>  	opregion->lid_state = NULL;
>  }
> +
> +/**
> + * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
> + * Refresh capability support.
> + * @i915: pointer to i915 device.
> + *
> + * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
> + * capability support. It is only applocable to DGFX.
> + *
> + * Returns:
> + * true when bios supports vram_sr, or false if bios doesn't support.
> + */
> +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
> +{
> +	struct intel_opregion *opregion = &i915->opregion;
> +
> +	if (!IS_DGFX(i915))
> +		return false;
> +
> +	if (!opregion)

This is always true. You should check for !opregion->header.

> +		return false;
> +
> +	if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
> +		return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
> +	else
> +		return false;
> +}
> +
> +/**
> + * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
> + * @i915: pointer to i915 device.
> + * @enable: Argument to enable/disable VRSR.
> + *
> + * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
> + * HOST BIOS will enables and disbales VRAM_SR during
> + * ACPI _PS3/_OFF and _PS/_ON glue method.
> + */
> +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> +	struct intel_opregion *opregion = &i915->opregion;
> +
> +	if (!opregion)

Same as above.

> +		return;
> +
> +	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
> +		return;

I'd just bundle !opregion->asle into the early return.

> +
> +	if (enable)
> +		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
> +	else
> +		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 2f261f985400..73c9d81d5ee6 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
>  				  pci_power_t state);
>  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
>  struct edid *intel_opregion_get_edid(struct intel_connector *connector);
> +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
> +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
>  
>  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
>  
> @@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
>  	return false;
>  }
>  
> +static bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
> +{
> +	return false;
> +}
> +
> +static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> +}
> +

Both of these stubs need to be static inline.

BR,
Jani.

>  #endif /* CONFIG_ACPI */
>  
>  #endif

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> opportunistic S0ix system wide suspend flow as well.
>
> Without VRSR enablement i915 has to evict the lmem objects to
> system memory. Depending on some heuristics driver will evict
> lmem objects without VRSR.
>
> VRSR feature requires Host BIOS support, VRSR will be enable/disable
> by HOST BIOS using ACPI OpRegion.
>
> Adding OpRegion VRSR support in order to enable/disable
> VRSR on discrete cards.
>
> BSpec: 53440
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 62 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_opregion.h | 11 ++++
>  2 files changed, 72 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 6876ba30d5a9..11d8c5bb23ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
>  #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
>  
> +#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
> +#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
>  #define PCON_HEADLESS_SKU	BIT(13)
>  
>  struct opregion_header {
> @@ -130,7 +132,8 @@ struct opregion_asle {
>  	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
>  			 * address of raw VBT data. */
>  	u32 rvds;	/* Size of raw vbt data */
> -	u8 rsvd[58];
> +	u8 vrsr;	/* DGFX Video Ram Self Refresh */
> +	u8 rsvd[57];
>  } __packed;
>  
>  /* OpRegion mailbox #5: ASLE ext */
> @@ -201,6 +204,9 @@ struct opregion_asle_ext {
>  
>  #define ASLE_PHED_EDID_VALID_MASK	0x3
>  
> +/* VRAM SR */
> +#define ASLE_VRSR_ENABLE		BIT(0)
> +
>  /* Software System Control Interrupt (SWSCI) */
>  #define SWSCI_SCIC_INDICATOR		(1 << 0)
>  #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
> @@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
>  		opregion->header->over.minor,
>  		opregion->header->over.revision);
>  
> +	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n", opregion->header->pcon);
> +
>  	mboxes = opregion->header->mboxes;
>  	if (mboxes & MBOX_ACPI) {
>  		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
> @@ -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
>  	opregion->vbt = NULL;
>  	opregion->lid_state = NULL;
>  }
> +
> +/**
> + * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
> + * Refresh capability support.
> + * @i915: pointer to i915 device.
> + *
> + * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
> + * capability support. It is only applocable to DGFX.
> + *
> + * Returns:
> + * true when bios supports vram_sr, or false if bios doesn't support.
> + */
> +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
> +{
> +	struct intel_opregion *opregion = &i915->opregion;
> +
> +	if (!IS_DGFX(i915))
> +		return false;
> +
> +	if (!opregion)

This is always true. You should check for !opregion->header.

> +		return false;
> +
> +	if (opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
> +		return opregion->header->pcon & PCON_DGFX_BIOS_SUPPORTS_VRSR;
> +	else
> +		return false;
> +}
> +
> +/**
> + * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
> + * @i915: pointer to i915 device.
> + * @enable: Argument to enable/disable VRSR.
> + *
> + * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
> + * HOST BIOS will enables and disbales VRAM_SR during
> + * ACPI _PS3/_OFF and _PS/_ON glue method.
> + */
> +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> +	struct intel_opregion *opregion = &i915->opregion;
> +
> +	if (!opregion)

Same as above.

> +		return;
> +
> +	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
> +		return;

I'd just bundle !opregion->asle into the early return.

> +
> +	if (enable)
> +		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
> +	else
> +		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 2f261f985400..73c9d81d5ee6 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
>  				  pci_power_t state);
>  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
>  struct edid *intel_opregion_get_edid(struct intel_connector *connector);
> +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
> +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
>  
>  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
>  
> @@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct drm_i915_private *i915)
>  	return false;
>  }
>  
> +static bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915)
> +{
> +	return false;
> +}
> +
> +static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
> +{
> +}
> +

Both of these stubs need to be static inline.

BR,
Jani.

>  #endif /* CONFIG_ACPI */
>  
>  #endif

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
> configs. MBD config requires HOST BIOS GPIO toggling support
> in order to enable/disable VRAM SR using ACPI OpRegion.
>
> i915 requires to check OpRegion PCON MBD Config bits to
> discover whether Gfx Card is MBD config before enabling
> VRSR.
>
> BSpec: 53440
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_opregion.h |  6 +++
>  2 files changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 11d8c5bb23ac..c8cdcde89dfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
>  #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
>  
> +#define PCON_DG1_MBD_CONFIG				BIT(9)
> +#define PCON_DG1_MBD_CONFIG_FIELD_VALID			BIT(10)
>  #define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
>  #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
>  #define PCON_HEADLESS_SKU	BIT(13)
> @@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
>  	opregion->lid_state = NULL;
>  }
>  
> +static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
> +{
> +	struct intel_opregion *opregion = &i915->opregion;
> +
> +	if (!IS_DG1(i915))
> +		return false;
> +
> +	if (!opregion)

Like in previous patch, opregion is always non-NULL. Check for
!opregion->header.

> +		return false;
> +
> +	if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
> +		return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
> +	else
> +		return false;
> +}
> +
> +/**
> + * intel_opregion_vram_sr_required().
> + * @i915 i915 device priv data.
> + *
> + * It checks whether a DGFX card is Mother Board Down config depending
> + * on respective discrete platform.
> + *
> + * Returns:
> + * It returns a boolean whether opregion vram_sr support is required.
> + */
> +bool
> +intel_opregion_vram_sr_required(struct drm_i915_private *i915)
> +{
> +	if (!IS_DGFX(i915))
> +		return false;
> +
> +	if (IS_DG1(i915))
> +		return intel_opregion_dg1_mbd_config(i915);

Only check for IS_DG1() here or in the function being called, not both.

> +
> +	return false;
> +}
> +
>  /**
>   * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
>   * Refresh capability support.
> @@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
>  	if (!opregion)
>  		return;
>  
> +	if (!intel_opregion_vram_sr_required(i915))
> +		return;

Feels like maybe this patch should be combined with the previous patch
due to this dependency.

> +
>  	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 73c9d81d5ee6..ad40c97f9565 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
>  struct edid *intel_opregion_get_edid(struct intel_connector *connector);
>  bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
>  void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
> +bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
>  
>  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
>  
> @@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
>  {
>  }
>  
> +static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)

static inline.

BR,
Jani.

> +{
> +	return false;
> +}
> +
>  #endif /* CONFIG_ACPI */
>  
>  #endif

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 2/9] drm/i915/dg1: OpRegion PCON DG1 MBD config support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> DGFX cards support both Add in Card(AIC) and Mother Board Down(MBD)
> configs. MBD config requires HOST BIOS GPIO toggling support
> in order to enable/disable VRAM SR using ACPI OpRegion.
>
> i915 requires to check OpRegion PCON MBD Config bits to
> discover whether Gfx Card is MBD config before enabling
> VRSR.
>
> BSpec: 53440
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_opregion.h |  6 +++
>  2 files changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
> index 11d8c5bb23ac..c8cdcde89dfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> @@ -53,6 +53,8 @@
>  #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
>  #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x) */
>  
> +#define PCON_DG1_MBD_CONFIG				BIT(9)
> +#define PCON_DG1_MBD_CONFIG_FIELD_VALID			BIT(10)
>  #define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
>  #define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
>  #define PCON_HEADLESS_SKU	BIT(13)
> @@ -1255,6 +1257,44 @@ void intel_opregion_unregister(struct drm_i915_private *i915)
>  	opregion->lid_state = NULL;
>  }
>  
> +static bool intel_opregion_dg1_mbd_config(struct drm_i915_private *i915)
> +{
> +	struct intel_opregion *opregion = &i915->opregion;
> +
> +	if (!IS_DG1(i915))
> +		return false;
> +
> +	if (!opregion)

Like in previous patch, opregion is always non-NULL. Check for
!opregion->header.

> +		return false;
> +
> +	if (opregion->header->pcon & PCON_DG1_MBD_CONFIG_FIELD_VALID)
> +		return opregion->header->pcon & PCON_DG1_MBD_CONFIG;
> +	else
> +		return false;
> +}
> +
> +/**
> + * intel_opregion_vram_sr_required().
> + * @i915 i915 device priv data.
> + *
> + * It checks whether a DGFX card is Mother Board Down config depending
> + * on respective discrete platform.
> + *
> + * Returns:
> + * It returns a boolean whether opregion vram_sr support is required.
> + */
> +bool
> +intel_opregion_vram_sr_required(struct drm_i915_private *i915)
> +{
> +	if (!IS_DGFX(i915))
> +		return false;
> +
> +	if (IS_DG1(i915))
> +		return intel_opregion_dg1_mbd_config(i915);

Only check for IS_DG1() here or in the function being called, not both.

> +
> +	return false;
> +}
> +
>  /**
>   * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
>   * Refresh capability support.
> @@ -1298,6 +1338,9 @@ void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
>  	if (!opregion)
>  		return;
>  
> +	if (!intel_opregion_vram_sr_required(i915))
> +		return;

Feels like maybe this patch should be combined with the previous patch
due to this dependency.

> +
>  	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not available\n"))
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h
> index 73c9d81d5ee6..ad40c97f9565 100644
> --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> @@ -77,6 +77,7 @@ int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
>  struct edid *intel_opregion_get_edid(struct intel_connector *connector);
>  bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private *i915);
>  void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable);
> +bool intel_opregion_vram_sr_required(struct drm_i915_private *i915);
>  
>  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
>  
> @@ -145,6 +146,11 @@ static void intel_opregion_vram_sr(struct drm_i915_private *i915, bool enable)
>  {
>  }
>  
> +static bool intel_opregion_vram_sr_required(struct drm_i915_private *i915)

static inline.

BR,
Jani.

> +{
> +	return false;
> +}
> +
>  #endif /* CONFIG_ACPI */
>  
>  #endif

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Jani Nikula]

On Thu, 16 Jun 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 16/06/2022 13:01, Anshuman Gupta wrote:
>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>> the VRAM Self Refresh feature support. Adding those sub platform
>> accordingly.
>> 
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>>   drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
>>   include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
>>   4 files changed, 47 insertions(+), 11 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index a5bc6a774c5a..f1f8699eedfd 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>   #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>>   
>>   #define IS_DG2_G10(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>>   	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>>   #define IS_DG2_G11(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>>   	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>>   #define IS_DG2_G12(dev_priv) \
>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>>   	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>>   #define IS_ADLS_RPLS(dev_priv) \
>>   	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>> index f0bf23726ed8..93da555adc4e 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>>   	INTEL_RPLP_IDS(0),
>>   };
>>   
>> +static const u16 subplatform_g10_mb_mbd_ids[] = {
>> +	INTEL_DG2_G10_NB_MBD_IDS(0),
>> +};
>> +
>> +static const u16 subplatform_g11_mb_mbd_ids[] = {
>> +	INTEL_DG2_G11_NB_MBD_IDS(0),
>> +};
>> +
>> +static const u16 subplatform_g12_mb_mbd_ids[] = {
>> +	INTEL_DG2_G12_NB_MBD_IDS(0),
>> +};
>> +
>>   static const u16 subplatform_g10_ids[] = {
>>   	INTEL_DG2_G10_IDS(0),
>>   	INTEL_ATS_M150_IDS(0),
>> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>>   	} else if (find_devid(devid, subplatform_rpl_ids,
>>   			      ARRAY_SIZE(subplatform_rpl_ids))) {
>>   		mask = BIT(INTEL_SUBPLATFORM_RPL);
>> +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
>> +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
>> +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
>> +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
>> +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
>> +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
>> +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
>> +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
>> +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
>>   	} else if (find_devid(devid, subplatform_g10_ids,
>>   			      ARRAY_SIZE(subplatform_g10_ids))) {
>>   		mask = BIT(INTEL_SUBPLATFORM_G10);
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>> index 08341174ee0a..c929e2d7e59c 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -97,7 +97,7 @@ enum intel_platform {
>>    * it is fine for the same bit to be used on multiple parent platforms.
>>    */
>>   
>> -#define INTEL_SUBPLATFORM_BITS (3)
>> +#define INTEL_SUBPLATFORM_BITS (6)
>>   #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>>   
>>   /* HSW/BDW/SKL/KBL/CFL */
>> @@ -111,9 +111,12 @@ enum intel_platform {
>>   #define INTEL_SUBPLATFORM_UY	(0)
>>   
>>   /* DG2 */
>> -#define INTEL_SUBPLATFORM_G10	0
>> -#define INTEL_SUBPLATFORM_G11	1
>> -#define INTEL_SUBPLATFORM_G12	2
>> +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
>> +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
>> +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
>> +#define INTEL_SUBPLATFORM_G10	3
>> +#define INTEL_SUBPLATFORM_G11	4
>> +#define INTEL_SUBPLATFORM_G12	5
>
> Ugh I feel this "breaks" the subplatform idea.. feels like it is just 
> too many bits when two separate sets of information get tracked (Gxx 
> plus MBD).

I think they could be specified independent of each other, though. The
subplatform if-else ladder would have to be replaced with independent
ifs. You'd have the G10/G11/G12 and 1 bit separately for MBD.

Only the macros for PCI IDs need to be separate (MBD vs not). You'll
then have:

static const u16 subplatform_g10_ids[] = {
	INTEL_DG2_G10_IDS(0),
	INTEL_DG2_G10_NB_MBD_IDS(0),
	INTEL_ATS_M150_IDS(0),
};

Ditto for g11 and g12, and separately:

static const u16 subplatform_mbd_ids[] = {
	INTEL_DG2_G10_NB_MBD_IDS(0),
	INTEL_DG2_G11_NB_MBD_IDS(0),
	INTEL_DG2_G12_NB_MBD_IDS(0),
};

The IS_DG2_G10() etc. macros would remain unchanged. IS_DG2_MBD() would
only be IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_MBD).

Main point is, a platform could belong to multiple independent
subplatforms.

Unless I'm missing something. ;)

> How about a separate "is_mbd" flag in runtime_info? You can split the 
> PCI IDs split as you have done, but do a search against the MBD ones and 
> set the flag.

What I dislike about this is that it's really not *runtime* info in any
sense, and it adds another way to define platform features. And we
already have too many.

BR,
Jani.


>
> Regards,
>
> Tvrtko
>
>>   
>>   /* ADL */
>>   #define INTEL_SUBPLATFORM_RPL	0
>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>> index 4585fed4e41e..198be417bb2d 100644
>> --- a/include/drm/i915_pciids.h
>> +++ b/include/drm/i915_pciids.h
>> @@ -693,32 +693,41 @@
>>   	INTEL_VGA_DEVICE(0xA7A9, info)
>>   
>>   /* DG2 */
>> -#define INTEL_DG2_G10_IDS(info) \
>> +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
>>   	INTEL_VGA_DEVICE(0x5690, info), \
>>   	INTEL_VGA_DEVICE(0x5691, info), \
>> -	INTEL_VGA_DEVICE(0x5692, info), \
>> +	INTEL_VGA_DEVICE(0x5692, info)
>> +
>> +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
>> +	INTEL_VGA_DEVICE(0x5693, info), \
>> +	INTEL_VGA_DEVICE(0x5694, info), \
>> +	INTEL_VGA_DEVICE(0x5695, info)
>> +
>> +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
>> +	INTEL_VGA_DEVICE(0x5696, info), \
>> +	INTEL_VGA_DEVICE(0x5697, info)
>> +
>> +#define INTEL_DG2_G10_IDS(info) \
>>   	INTEL_VGA_DEVICE(0x56A0, info), \
>>   	INTEL_VGA_DEVICE(0x56A1, info), \
>>   	INTEL_VGA_DEVICE(0x56A2, info)
>>   
>>   #define INTEL_DG2_G11_IDS(info) \
>> -	INTEL_VGA_DEVICE(0x5693, info), \
>> -	INTEL_VGA_DEVICE(0x5694, info), \
>> -	INTEL_VGA_DEVICE(0x5695, info), \
>>   	INTEL_VGA_DEVICE(0x56A5, info), \
>>   	INTEL_VGA_DEVICE(0x56A6, info), \
>>   	INTEL_VGA_DEVICE(0x56B0, info), \
>>   	INTEL_VGA_DEVICE(0x56B1, info)
>>   
>>   #define INTEL_DG2_G12_IDS(info) \
>> -	INTEL_VGA_DEVICE(0x5696, info), \
>> -	INTEL_VGA_DEVICE(0x5697, info), \
>>   	INTEL_VGA_DEVICE(0x56A3, info), \
>>   	INTEL_VGA_DEVICE(0x56A4, info), \
>>   	INTEL_VGA_DEVICE(0x56B2, info), \
>>   	INTEL_VGA_DEVICE(0x56B3, info)
>>   
>>   #define INTEL_DG2_IDS(info) \
>> +	INTEL_DG2_G10_NB_MBD_IDS(info), \
>> +	INTEL_DG2_G11_NB_MBD_IDS(info), \
>> +	INTEL_DG2_G12_NB_MBD_IDS(info), \
>>   	INTEL_DG2_G10_IDS(info), \
>>   	INTEL_DG2_G11_IDS(info), \
>>   	INTEL_DG2_G12_IDS(info)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Add d3cold_sr_lmem_threshold modparam to choose between
> d3cold-off zero watt and d3cold-VRAM Self Refresh.
> i915 requires to evict the lmem objects to smem in order to
> support d3cold-Off.
>
> If gfx root port is not capable of sending PME from d3cold
> then i915 don't need to program d3cold-off/d3cold-vram_sr
> sequence.
>
> FIXME: Eviction of lmem objects in case of D3Cold off is wip.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++---
>  drivers/gpu/drm/i915/i915_params.c |  4 ++++
>  drivers/gpu/drm/i915/i915_params.h |  3 ++-
>  3 files changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index fcff5f3fe05e..aef4b17efdbe 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device *kdev)
>  static int intel_runtime_idle(struct device *kdev)
>  {
>  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> +	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> +	u64 lmem_total = to_gt(dev_priv)->lmem->total;
> +	u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
> +	u64 lmem_used = lmem_total - lmem_avail;
> +	struct pci_dev *root_pdev;
>  	int ret = 1;
>  
> -	if (!HAS_LMEM_SR(dev_priv)) {
> -		/*TODO: Prepare for D3Cold-Off */
> +	root_pdev = pcie_find_root_port(pdev);
> +	if (!root_pdev)
> +		goto out;
> +
> +	if (!pci_pme_capable(root_pdev, PCI_D3cold))
>  		goto out;
> -	}
>  
>  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
>  
> +	if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 * 1024) {
> +		drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n");
> +		pci_d3cold_enable(root_pdev);
> +		/* FIXME: Eviction of lmem objects and guc reset is wip */
> +		intel_pm_vram_sr(dev_priv, false);
> +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +		goto out;
> +	} else if (!HAS_LMEM_SR(dev_priv)) {
> +		/* Disable D3Cold to reduce the eviction latency */
> +		pci_d3cold_disable(root_pdev);
> +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +		goto out;
> +	}

This is *way* too low level code for such high level function. This
needs to be abstracted better.

> +
>  	ret = intel_pm_vram_sr(dev_priv, true);
>  	if (!ret)
>  		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 701fbc98afa0..6c6b3c372d4d 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
>  	"Enable support for Intel GVT-g graphics virtualization host support(default:false)");
>  #endif
>  
> +i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
> +	"Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. "
> +	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
> +
>  #if CONFIG_DRM_I915_REQUEST_TIMEOUT
>  i915_param_named_unsafe(request_timeout_ms, uint, 0600,
>  			"Default request/fence/batch buffer expiration timeout.");
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index b5e7ea45d191..28f20ebaf41f 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -83,7 +83,8 @@ struct drm_printer;
>  	param(bool, verbose_state_checks, true, 0) \
>  	param(bool, nuclear_pageflip, false, 0400) \
>  	param(bool, enable_dp_mst, true, 0600) \
> -	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0)
> +	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \
> +	param(int, d3cold_sr_lmem_threshold, 300, 0600) \

What's the point of the parameter?

Also, please read the comment /* leave bools at the end to not create
holes */ above.


BR,
Jani.


>  
>  #define MEMBER(T, member, ...) T member;
>  struct i915_params {

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c       | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
>  2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f33290358c51..7a535f670ae1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
>  	GEM_BUG_ON(!HAS_REGION(i915, id));
>  	GEM_BUG_ON(i915->mm.regions[id]);
>  	i915->mm.regions[id] = mem;
> +	gt->lmem = mem;
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index df708802889d..cd7744eaaeaa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
>  #include "intel_gt_buffer_pool_types.h"
>  #include "intel_hwconfig.h"
>  #include "intel_llc_types.h"
> +#include "intel_memory_region.h"

Please never add includes in headers when a forward declaration is
sufficient. I'm spending a lot of time trying to reduce the include
dependencies we have.

BR,
Jani.

>  #include "intel_reset_types.h"
>  #include "intel_rc6_types.h"
>  #include "intel_rps_types.h"
> @@ -202,6 +203,8 @@ struct intel_gt {
>  	 */
>  	phys_addr_t phys_addr;
>  
> +	struct intel_memory_region *lmem;
> +
>  	struct intel_gt_info {
>  		unsigned int id;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Jani Nikula]

On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Intel Client DGFX card supports D3Cold with two option.
> D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
>
> i915 requires to evict the lmem objects to smem in order to
> support D3Cold-Off, which increases i915 the suspend/resume
> latency. Enabling VRAM Self Refresh feature optimize the
> latency with additional power cost which required to retain
> the lmem.
>
> Adding intel_runtime_idle (runtime_idle callback) to enable
> VRAM_SR, it will be used for policy to choose
> between D3Cold-off vs D3Cold-VRAM_SR.
>
> Since we have introduced i915 runtime_idle callback.
> It need to be warranted that Runtime PM Core invokes runtime_idle
> callback when runtime usages count becomes zero. That requires
> to use pm_runtime_put instead of pm_runtime_put_autosuspend.
>
> TODO: GuC interface state save/restore.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris.p.wilson@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_driver.c      | 26 +++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
>  2 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index aa1fb15b1f11..fcff5f3fe05e 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
>  	return i915_pm_resume(kdev);
>  }
>  
> +static int intel_runtime_idle(struct device *kdev)
> +{
> +	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> +	int ret = 1;
> +
> +	if (!HAS_LMEM_SR(dev_priv)) {
> +		/*TODO: Prepare for D3Cold-Off */
> +		goto out;
> +	}
> +
> +	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +
> +	ret = intel_pm_vram_sr(dev_priv, true);
> +	if (!ret)
> +		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");

Please add the debug in the intel_pm_vram_sr() function instead.

BR,
Jani.

> +
> +	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> +
> +out:
> +	pm_runtime_mark_last_busy(kdev);
> +	pm_runtime_autosuspend(kdev);
> +
> +	return ret;
> +}
> +
>  static int intel_runtime_suspend(struct device *kdev)
>  {
>  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> @@ -1742,6 +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
>  	.restore = i915_pm_restore,
>  
>  	/* S0ix (via runtime suspend) event handlers */
> +	.runtime_idle = intel_runtime_idle,
>  	.runtime_suspend = intel_runtime_suspend,
>  	.runtime_resume = intel_runtime_resume,
>  };
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 6ed5786bcd29..4dade7e8a795 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct intel_runtime_pm *rpm,
>  
>  	intel_runtime_pm_release(rpm, wakelock);
>  
> -	pm_runtime_mark_last_busy(kdev);
> -	pm_runtime_put_autosuspend(kdev);
> +	pm_runtime_put(kdev);
>  }
>  
>  /**

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Tvrtko Ursulin]

On 16/06/2022 15:15, Jani Nikula wrote:
> On Thu, 16 Jun 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>> On 16/06/2022 13:01, Anshuman Gupta wrote:
>>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>>> the VRAM Self Refresh feature support. Adding those sub platform
>>> accordingly.
>>>
>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>>>    drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
>>>    drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
>>>    include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
>>>    4 files changed, 47 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index a5bc6a774c5a..f1f8699eedfd 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>>    #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>>>    
>>>    #define IS_DG2_G10(dev_priv) \
>>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>>>    	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>>>    #define IS_DG2_G11(dev_priv) \
>>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>>>    	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>>>    #define IS_DG2_G12(dev_priv) \
>>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>>>    	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>>>    #define IS_ADLS_RPLS(dev_priv) \
>>>    	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>>> index f0bf23726ed8..93da555adc4e 100644
>>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>>> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>>>    	INTEL_RPLP_IDS(0),
>>>    };
>>>    
>>> +static const u16 subplatform_g10_mb_mbd_ids[] = {
>>> +	INTEL_DG2_G10_NB_MBD_IDS(0),
>>> +};
>>> +
>>> +static const u16 subplatform_g11_mb_mbd_ids[] = {
>>> +	INTEL_DG2_G11_NB_MBD_IDS(0),
>>> +};
>>> +
>>> +static const u16 subplatform_g12_mb_mbd_ids[] = {
>>> +	INTEL_DG2_G12_NB_MBD_IDS(0),
>>> +};
>>> +
>>>    static const u16 subplatform_g10_ids[] = {
>>>    	INTEL_DG2_G10_IDS(0),
>>>    	INTEL_ATS_M150_IDS(0),
>>> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>>>    	} else if (find_devid(devid, subplatform_rpl_ids,
>>>    			      ARRAY_SIZE(subplatform_rpl_ids))) {
>>>    		mask = BIT(INTEL_SUBPLATFORM_RPL);
>>> +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
>>> +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
>>> +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
>>> +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
>>> +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
>>> +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
>>> +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
>>> +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
>>> +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
>>>    	} else if (find_devid(devid, subplatform_g10_ids,
>>>    			      ARRAY_SIZE(subplatform_g10_ids))) {
>>>    		mask = BIT(INTEL_SUBPLATFORM_G10);
>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>>> index 08341174ee0a..c929e2d7e59c 100644
>>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>>> @@ -97,7 +97,7 @@ enum intel_platform {
>>>     * it is fine for the same bit to be used on multiple parent platforms.
>>>     */
>>>    
>>> -#define INTEL_SUBPLATFORM_BITS (3)
>>> +#define INTEL_SUBPLATFORM_BITS (6)
>>>    #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>>>    
>>>    /* HSW/BDW/SKL/KBL/CFL */
>>> @@ -111,9 +111,12 @@ enum intel_platform {
>>>    #define INTEL_SUBPLATFORM_UY	(0)
>>>    
>>>    /* DG2 */
>>> -#define INTEL_SUBPLATFORM_G10	0
>>> -#define INTEL_SUBPLATFORM_G11	1
>>> -#define INTEL_SUBPLATFORM_G12	2
>>> +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
>>> +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
>>> +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
>>> +#define INTEL_SUBPLATFORM_G10	3
>>> +#define INTEL_SUBPLATFORM_G11	4
>>> +#define INTEL_SUBPLATFORM_G12	5
>>
>> Ugh I feel this "breaks" the subplatform idea.. feels like it is just
>> too many bits when two separate sets of information get tracked (Gxx
>> plus MBD).
> 
> I think they could be specified independent of each other, though. The
> subplatform if-else ladder would have to be replaced with independent
> ifs. You'd have the G10/G11/G12 and 1 bit separately for MBD.
> 
> Only the macros for PCI IDs need to be separate (MBD vs not). You'll
> then have:
> 
> static const u16 subplatform_g10_ids[] = {
> 	INTEL_DG2_G10_IDS(0),
> 	INTEL_DG2_G10_NB_MBD_IDS(0),
> 	INTEL_ATS_M150_IDS(0),
> };
> 
> Ditto for g11 and g12, and separately:
> 
> static const u16 subplatform_mbd_ids[] = {
> 	INTEL_DG2_G10_NB_MBD_IDS(0),
> 	INTEL_DG2_G11_NB_MBD_IDS(0),
> 	INTEL_DG2_G12_NB_MBD_IDS(0),
> };
> 
> The IS_DG2_G10() etc. macros would remain unchanged. IS_DG2_MBD() would
> only be IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_MBD).
> 
> Main point is, a platform could belong to multiple independent
> subplatforms.
> 
> Unless I'm missing something. ;)
> 
>> How about a separate "is_mbd" flag in runtime_info? You can split the
>> PCI IDs split as you have done, but do a search against the MBD ones and
>> set the flag.
> 
> What I dislike about this is that it's really not *runtime* info in any
> sense, and it adds another way to define platform features. And we
> already have too many.

I was reluctant to suggest extending usage of subplatform bits in this 
way but it would be acceptable. My reservation/uncertainty was whether 
MBP is a "proper" subplatform. I see it's separate PCI IDs and even 
separate HW features, as seen in this series, but wasn't sure. Anyway, 
your proposal works for me. Better 4 bits than 6 so as much as possible 
remain for platform bits.

Regards,

Tvrtko

> 
> BR,
> Jani.
> 
> 
>>
>> Regards,
>>
>> Tvrtko
>>
>>>    
>>>    /* ADL */
>>>    #define INTEL_SUBPLATFORM_RPL	0
>>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>>> index 4585fed4e41e..198be417bb2d 100644
>>> --- a/include/drm/i915_pciids.h
>>> +++ b/include/drm/i915_pciids.h
>>> @@ -693,32 +693,41 @@
>>>    	INTEL_VGA_DEVICE(0xA7A9, info)
>>>    
>>>    /* DG2 */
>>> -#define INTEL_DG2_G10_IDS(info) \
>>> +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
>>>    	INTEL_VGA_DEVICE(0x5690, info), \
>>>    	INTEL_VGA_DEVICE(0x5691, info), \
>>> -	INTEL_VGA_DEVICE(0x5692, info), \
>>> +	INTEL_VGA_DEVICE(0x5692, info)
>>> +
>>> +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
>>> +	INTEL_VGA_DEVICE(0x5693, info), \
>>> +	INTEL_VGA_DEVICE(0x5694, info), \
>>> +	INTEL_VGA_DEVICE(0x5695, info)
>>> +
>>> +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
>>> +	INTEL_VGA_DEVICE(0x5696, info), \
>>> +	INTEL_VGA_DEVICE(0x5697, info)
>>> +
>>> +#define INTEL_DG2_G10_IDS(info) \
>>>    	INTEL_VGA_DEVICE(0x56A0, info), \
>>>    	INTEL_VGA_DEVICE(0x56A1, info), \
>>>    	INTEL_VGA_DEVICE(0x56A2, info)
>>>    
>>>    #define INTEL_DG2_G11_IDS(info) \
>>> -	INTEL_VGA_DEVICE(0x5693, info), \
>>> -	INTEL_VGA_DEVICE(0x5694, info), \
>>> -	INTEL_VGA_DEVICE(0x5695, info), \
>>>    	INTEL_VGA_DEVICE(0x56A5, info), \
>>>    	INTEL_VGA_DEVICE(0x56A6, info), \
>>>    	INTEL_VGA_DEVICE(0x56B0, info), \
>>>    	INTEL_VGA_DEVICE(0x56B1, info)
>>>    
>>>    #define INTEL_DG2_G12_IDS(info) \
>>> -	INTEL_VGA_DEVICE(0x5696, info), \
>>> -	INTEL_VGA_DEVICE(0x5697, info), \
>>>    	INTEL_VGA_DEVICE(0x56A3, info), \
>>>    	INTEL_VGA_DEVICE(0x56A4, info), \
>>>    	INTEL_VGA_DEVICE(0x56B2, info), \
>>>    	INTEL_VGA_DEVICE(0x56B3, info)
>>>    
>>>    #define INTEL_DG2_IDS(info) \
>>> +	INTEL_DG2_G10_NB_MBD_IDS(info), \
>>> +	INTEL_DG2_G11_NB_MBD_IDS(info), \
>>> +	INTEL_DG2_G12_NB_MBD_IDS(info), \
>>>    	INTEL_DG2_G10_IDS(info), \
>>>    	INTEL_DG2_G11_IDS(info), \
>>>    	INTEL_DG2_G12_IDS(info)
> 

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Jani Nikula]

On Thu, 16 Jun 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
> On 16/06/2022 15:15, Jani Nikula wrote:
>> On Thu, 16 Jun 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote:
>>> On 16/06/2022 13:01, Anshuman Gupta wrote:
>>>> DG2 NB SKU need to distinguish between MBD and AIC to probe
>>>> the VRAM Self Refresh feature support. Adding those sub platform
>>>> accordingly.
>>>>
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>>>>    drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
>>>>    drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
>>>>    include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
>>>>    4 files changed, 47 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index a5bc6a774c5a..f1f8699eedfd 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>>>    #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>>>>    
>>>>    #define IS_DG2_G10(dev_priv) \
>>>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>>>>    	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>>>>    #define IS_DG2_G11(dev_priv) \
>>>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>>>>    	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>>>>    #define IS_DG2_G12(dev_priv) \
>>>> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>>>>    	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>>>>    #define IS_ADLS_RPLS(dev_priv) \
>>>>    	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
>>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>>>> index f0bf23726ed8..93da555adc4e 100644
>>>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>>>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>>>> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>>>>    	INTEL_RPLP_IDS(0),
>>>>    };
>>>>    
>>>> +static const u16 subplatform_g10_mb_mbd_ids[] = {
>>>> +	INTEL_DG2_G10_NB_MBD_IDS(0),
>>>> +};
>>>> +
>>>> +static const u16 subplatform_g11_mb_mbd_ids[] = {
>>>> +	INTEL_DG2_G11_NB_MBD_IDS(0),
>>>> +};
>>>> +
>>>> +static const u16 subplatform_g12_mb_mbd_ids[] = {
>>>> +	INTEL_DG2_G12_NB_MBD_IDS(0),
>>>> +};
>>>> +
>>>>    static const u16 subplatform_g10_ids[] = {
>>>>    	INTEL_DG2_G10_IDS(0),
>>>>    	INTEL_ATS_M150_IDS(0),
>>>> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>>>>    	} else if (find_devid(devid, subplatform_rpl_ids,
>>>>    			      ARRAY_SIZE(subplatform_rpl_ids))) {
>>>>    		mask = BIT(INTEL_SUBPLATFORM_RPL);
>>>> +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
>>>> +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
>>>> +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
>>>> +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
>>>> +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
>>>> +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
>>>> +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
>>>> +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
>>>> +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
>>>>    	} else if (find_devid(devid, subplatform_g10_ids,
>>>>    			      ARRAY_SIZE(subplatform_g10_ids))) {
>>>>    		mask = BIT(INTEL_SUBPLATFORM_G10);
>>>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>>>> index 08341174ee0a..c929e2d7e59c 100644
>>>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>>>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>>>> @@ -97,7 +97,7 @@ enum intel_platform {
>>>>     * it is fine for the same bit to be used on multiple parent platforms.
>>>>     */
>>>>    
>>>> -#define INTEL_SUBPLATFORM_BITS (3)
>>>> +#define INTEL_SUBPLATFORM_BITS (6)
>>>>    #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>>>>    
>>>>    /* HSW/BDW/SKL/KBL/CFL */
>>>> @@ -111,9 +111,12 @@ enum intel_platform {
>>>>    #define INTEL_SUBPLATFORM_UY	(0)
>>>>    
>>>>    /* DG2 */
>>>> -#define INTEL_SUBPLATFORM_G10	0
>>>> -#define INTEL_SUBPLATFORM_G11	1
>>>> -#define INTEL_SUBPLATFORM_G12	2
>>>> +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
>>>> +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
>>>> +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
>>>> +#define INTEL_SUBPLATFORM_G10	3
>>>> +#define INTEL_SUBPLATFORM_G11	4
>>>> +#define INTEL_SUBPLATFORM_G12	5
>>>
>>> Ugh I feel this "breaks" the subplatform idea.. feels like it is just
>>> too many bits when two separate sets of information get tracked (Gxx
>>> plus MBD).
>> 
>> I think they could be specified independent of each other, though. The
>> subplatform if-else ladder would have to be replaced with independent
>> ifs. You'd have the G10/G11/G12 and 1 bit separately for MBD.
>> 
>> Only the macros for PCI IDs need to be separate (MBD vs not). You'll
>> then have:
>> 
>> static const u16 subplatform_g10_ids[] = {
>> 	INTEL_DG2_G10_IDS(0),
>> 	INTEL_DG2_G10_NB_MBD_IDS(0),
>> 	INTEL_ATS_M150_IDS(0),
>> };
>> 
>> Ditto for g11 and g12, and separately:
>> 
>> static const u16 subplatform_mbd_ids[] = {
>> 	INTEL_DG2_G10_NB_MBD_IDS(0),
>> 	INTEL_DG2_G11_NB_MBD_IDS(0),
>> 	INTEL_DG2_G12_NB_MBD_IDS(0),
>> };
>> 
>> The IS_DG2_G10() etc. macros would remain unchanged. IS_DG2_MBD() would
>> only be IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_MBD).
>> 
>> Main point is, a platform could belong to multiple independent
>> subplatforms.
>> 
>> Unless I'm missing something. ;)
>> 
>>> How about a separate "is_mbd" flag in runtime_info? You can split the
>>> PCI IDs split as you have done, but do a search against the MBD ones and
>>> set the flag.
>> 
>> What I dislike about this is that it's really not *runtime* info in any
>> sense, and it adds another way to define platform features. And we
>> already have too many.
>
> I was reluctant to suggest extending usage of subplatform bits in this 
> way but it would be acceptable. My reservation/uncertainty was whether 
> MBP is a "proper" subplatform. I see it's separate PCI IDs and even 
> separate HW features, as seen in this series, but wasn't sure. Anyway, 
> your proposal works for me. Better 4 bits than 6 so as much as possible 
> remain for platform bits.

The alternative is separate struct intel_device_info with a static
is_mbd flag. But the duplication there is also getting out of hands. C
is really crap at this.

BR,
Jani.

>
> Regards,
>
> Tvrtko
>
>> 
>> BR,
>> Jani.
>> 
>> 
>>>
>>> Regards,
>>>
>>> Tvrtko
>>>
>>>>    
>>>>    /* ADL */
>>>>    #define INTEL_SUBPLATFORM_RPL	0
>>>> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>>>> index 4585fed4e41e..198be417bb2d 100644
>>>> --- a/include/drm/i915_pciids.h
>>>> +++ b/include/drm/i915_pciids.h
>>>> @@ -693,32 +693,41 @@
>>>>    	INTEL_VGA_DEVICE(0xA7A9, info)
>>>>    
>>>>    /* DG2 */
>>>> -#define INTEL_DG2_G10_IDS(info) \
>>>> +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
>>>>    	INTEL_VGA_DEVICE(0x5690, info), \
>>>>    	INTEL_VGA_DEVICE(0x5691, info), \
>>>> -	INTEL_VGA_DEVICE(0x5692, info), \
>>>> +	INTEL_VGA_DEVICE(0x5692, info)
>>>> +
>>>> +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
>>>> +	INTEL_VGA_DEVICE(0x5693, info), \
>>>> +	INTEL_VGA_DEVICE(0x5694, info), \
>>>> +	INTEL_VGA_DEVICE(0x5695, info)
>>>> +
>>>> +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
>>>> +	INTEL_VGA_DEVICE(0x5696, info), \
>>>> +	INTEL_VGA_DEVICE(0x5697, info)
>>>> +
>>>> +#define INTEL_DG2_G10_IDS(info) \
>>>>    	INTEL_VGA_DEVICE(0x56A0, info), \
>>>>    	INTEL_VGA_DEVICE(0x56A1, info), \
>>>>    	INTEL_VGA_DEVICE(0x56A2, info)
>>>>    
>>>>    #define INTEL_DG2_G11_IDS(info) \
>>>> -	INTEL_VGA_DEVICE(0x5693, info), \
>>>> -	INTEL_VGA_DEVICE(0x5694, info), \
>>>> -	INTEL_VGA_DEVICE(0x5695, info), \
>>>>    	INTEL_VGA_DEVICE(0x56A5, info), \
>>>>    	INTEL_VGA_DEVICE(0x56A6, info), \
>>>>    	INTEL_VGA_DEVICE(0x56B0, info), \
>>>>    	INTEL_VGA_DEVICE(0x56B1, info)
>>>>    
>>>>    #define INTEL_DG2_G12_IDS(info) \
>>>> -	INTEL_VGA_DEVICE(0x5696, info), \
>>>> -	INTEL_VGA_DEVICE(0x5697, info), \
>>>>    	INTEL_VGA_DEVICE(0x56A3, info), \
>>>>    	INTEL_VGA_DEVICE(0x56A4, info), \
>>>>    	INTEL_VGA_DEVICE(0x56B2, info), \
>>>>    	INTEL_VGA_DEVICE(0x56B3, info)
>>>>    
>>>>    #define INTEL_DG2_IDS(info) \
>>>> +	INTEL_DG2_G10_NB_MBD_IDS(info), \
>>>> +	INTEL_DG2_G11_NB_MBD_IDS(info), \
>>>> +	INTEL_DG2_G12_NB_MBD_IDS(info), \
>>>>    	INTEL_DG2_G10_IDS(info), \
>>>>    	INTEL_DG2_G11_IDS(info), \
>>>>    	INTEL_DG2_G12_IDS(info)
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for DG2 VRAM_SR Support (rev3)

[Patchwork]

== Series Details ==

Series: DG2 VRAM_SR Support (rev3)
URL   : https://patchwork.freedesktop.org/series/104128/
State : warning

== Summary ==

Error: dim checkpatch failed
ee513fcc2693 drm/i915/dgfx: OpRegion VRAM Self Refresh Support
341133e9b9ad drm/i915/dg1: OpRegion PCON DG1 MBD config support
b0e90ba1012b drm/i915/dg2: Add DG2_NB_MBD subplatform
-:108: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#108: FILE: include/drm/i915_pciids.h:696:
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
 	INTEL_VGA_DEVICE(0x5690, info), \
 	INTEL_VGA_DEVICE(0x5691, info), \
+	INTEL_VGA_DEVICE(0x5692, info)

-:108: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#108: FILE: include/drm/i915_pciids.h:696:
+#define INTEL_DG2_G10_NB_MBD_IDS(info) \
 	INTEL_VGA_DEVICE(0x5690, info), \
 	INTEL_VGA_DEVICE(0x5691, info), \
+	INTEL_VGA_DEVICE(0x5692, info)

-:114: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#114: FILE: include/drm/i915_pciids.h:701:
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5693, info), \
+	INTEL_VGA_DEVICE(0x5694, info), \
+	INTEL_VGA_DEVICE(0x5695, info)

-:114: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#114: FILE: include/drm/i915_pciids.h:701:
+#define INTEL_DG2_G11_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5693, info), \
+	INTEL_VGA_DEVICE(0x5694, info), \
+	INTEL_VGA_DEVICE(0x5695, info)

-:119: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#119: FILE: include/drm/i915_pciids.h:706:
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5696, info), \
+	INTEL_VGA_DEVICE(0x5697, info)

-:119: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#119: FILE: include/drm/i915_pciids.h:706:
+#define INTEL_DG2_G12_NB_MBD_IDS(info) \
+	INTEL_VGA_DEVICE(0x5696, info), \
+	INTEL_VGA_DEVICE(0x5697, info)

-:123: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#123: FILE: include/drm/i915_pciids.h:710:
+#define INTEL_DG2_G10_IDS(info) \
 	INTEL_VGA_DEVICE(0x56A0, info), \
 	INTEL_VGA_DEVICE(0x56A1, info), \
 	INTEL_VGA_DEVICE(0x56A2, info)

-:123: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#123: FILE: include/drm/i915_pciids.h:710:
+#define INTEL_DG2_G10_IDS(info) \
 	INTEL_VGA_DEVICE(0x56A0, info), \
 	INTEL_VGA_DEVICE(0x56A1, info), \
 	INTEL_VGA_DEVICE(0x56A2, info)

total: 4 errors, 0 warnings, 4 checks, 117 lines checked
b835f2871301 drm/i915/dg2: DG2 MBD config
-:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#50: FILE: drivers/gpu/drm/i915/i915_drv.h:1025:
+#define IS_DG2_MBD(dev_priv) (IS_DG2_G10_NB_MBD(dev_priv) || IS_DG2_G11_NB_MBD(dev_priv) || \
+			      IS_DG2_G12_NB_MBD(dev_priv))

total: 0 errors, 0 warnings, 1 checks, 29 lines checked
28151cba023d drm/i915/dgfx: Add has_lmem_sr
78ead46ad383 drm/i915/dgfx: Setup VRAM SR with D3COLD
-:101: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#101: FILE: drivers/gpu/drm/i915/intel_pcode.c:271:
+			      REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND,
+			      DG1_PCODE_D3_VRAM_SR) |

-:103: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#103: FILE: drivers/gpu/drm/i915/intel_pcode.c:273:
+			      REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1,
+			      DG1_ENABLE_SR), 0); /* no data needed for this cmd */

total: 0 errors, 0 warnings, 2 checks, 138 lines checked
434f8395d301 drm/i915/rpm: Enable D3Cold VRAM SR Support
3824ea24e1b1 drm/i915/xehpsdv: Store lmem region in gt
993fde5ec166 drm/i915/rpm: d3cold Policy
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/i915_params.c:201:
+i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
+	"Enable Vidoe RAM Self refresh when size of lmem is greater to this threshold. "

total: 0 errors, 0 warnings, 1 checks, 58 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for DG2 VRAM_SR Support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6650 bytes --]

== Series Details ==

Series: DG2 VRAM_SR Support (rev3)
URL   : https://patchwork.freedesktop.org/series/104128/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11768 -> Patchwork_104128v3
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/index.html

Participating hosts (43 -> 41)
------------------------------

  Additional (1): bat-atsm-1 
  Missing    (3): bat-dg2-8 fi-rkl-11600 fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_104128v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@requests:
    - fi-blb-e6850:       [PASS][1] -> [DMESG-FAIL][2] ([i915#4528])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-blb-e6850/igt@i915_selftest@live@requests.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-hsw-g3258:       NOTRUN -> [SKIP][3] ([fdo#109271] / [fdo#111827])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - fi-tgl-u2:          [PASS][4] -> [DMESG-WARN][5] ([i915#402])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
    - bat-adlp-4:         [PASS][6] -> [DMESG-WARN][7] ([i915#3576])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-adlp-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_psr@cursor_plane_move:
    - fi-tgl-u2:          [PASS][8] -> [SKIP][9] ([i915#668]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-tgl-u2/igt@kms_psr@cursor_plane_move.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-tgl-u2/igt@kms_psr@cursor_plane_move.html

  
#### Possible fixes ####

  * igt@gem_mmap@basic:
    - {bat-jsl-2}:        [TIMEOUT][10] -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-jsl-2/igt@gem_mmap@basic.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-jsl-2/igt@gem_mmap@basic.html

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - {bat-jsl-2}:        [INCOMPLETE][12] -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-jsl-2/igt@i915_pm_rpm@basic-pci-d3-state.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-jsl-2/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - bat-adlp-4:         [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-adlp-4/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [INCOMPLETE][16] ([i915#4785]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
    - bat-dg1-5:          [DMESG-FAIL][18] ([i915#4494] / [i915#4957]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-dg1-5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@hugepages:
    - {bat-dg2-9}:        [DMESG-WARN][20] ([i915#5763]) -> [PASS][21] +6 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/bat-dg2-9/igt@i915_selftest@live@hugepages.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/bat-dg2-9/igt@i915_selftest@live@hugepages.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#6244]: https://gitlab.freedesktop.org/drm/intel/issues/6244
  [i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668


Build changes
-------------

  * Linux: CI_DRM_11768 -> Patchwork_104128v3

  CI-20190529: 20190529
  CI_DRM_11768: 6da0a0872a9b44e2be9645c1d7045fe88e035c25 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_104128v3: 6da0a0872a9b44e2be9645c1d7045fe88e035c25 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

24ce73fadadf drm/i915/rpm: d3cold Policy
db7b5682236b drm/i915/xehpsdv: Store lmem region in gt
021917594e67 drm/i915/rpm: Enable D3Cold VRAM SR Support
4def24a74ec4 drm/i915/dgfx: Setup VRAM SR with D3COLD
d2de13a41efa drm/i915/dgfx: Add has_lmem_sr
073141907737 drm/i915/dg2: DG2 MBD config
38861479e73e drm/i915/dg2: Add DG2_NB_MBD subplatform
5a18e5bde1f2 drm/i915/dg1: OpRegion PCON DG1 MBD config support
1d91e586ce36 drm/i915/dgfx: OpRegion VRAM Self Refresh Support

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/index.html

[-- Attachment #2: Type: text/html, Size: 7243 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for DG2 VRAM_SR Support (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 33239 bytes --]

== Series Details ==

Series: DG2 VRAM_SR Support (rev3)
URL   : https://patchwork.freedesktop.org/series/104128/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11768_full -> Patchwork_104128v3_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_104128v3_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_104128v3_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 10)
------------------------------

  Missing    (2): shard-rkl shard-tglu 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_104128v3_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@execlists:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl4/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl6/igt@i915_selftest@live@execlists.html

  
Known issues
------------

  Here are the changes found in Patchwork_104128v3_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@create-ext:
    - shard-skl:          [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl10/igt@gem_eio@create-ext.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl1/igt@gem_eio@create-ext.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][5] -> [FAIL][6] ([i915#5784])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb7/igt@gem_eio@unwedge-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb3/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([i915#4525])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb4/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb6/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-kbl:          [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-glk4/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_params@no-vebox:
    - shard-iclb:         NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@gem_exec_params@no-vebox.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][14] -> [SKIP][15] ([i915#2190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb2/igt@gem_huc_copy@huc-copy.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-skl:          NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +3 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-iclb:         NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-kbl:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#768])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-skl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [PASS][21] -> [DMESG-WARN][22] ([i915#5566] / [i915#716])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk4/igt@gen9_exec_parse@allowed-all.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-glk7/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-apl:          [PASS][23] -> [FAIL][24] ([i915#4275])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl7/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_selftest@live@hangcheck:
    - shard-tglb:         [PASS][25] -> [DMESG-WARN][26] ([i915#5591])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb1/igt@i915_selftest@live@hangcheck.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb3/igt@i915_selftest@live@hangcheck.html

  * igt@kms_addfb_basic@bad-pitch-65536:
    - shard-skl:          NOTRUN -> [DMESG-WARN][27] ([i915#1982])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@kms_addfb_basic@bad-pitch-65536.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#5286])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][29] ([fdo#109271]) +33 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][30] ([i915#3743])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][31] ([fdo#110725] / [fdo#111614])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][32] ([i915#3763])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl9/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#109278]) +3 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_ccs.html

  * igt@kms_color@pipe-d-ctm-blue-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109278] / [i915#1149])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@kms_color@pipe-d-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-25:
    - shard-skl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@kms_color_chamelium@pipe-b-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][39] ([i915#2105])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#109274] / [fdo#109278])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html

  * igt@kms_cursor_legacy@cursor-vs-flip-legacy:
    - shard-iclb:         [PASS][41] -> [DMESG-WARN][42] ([i915#1888])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb1/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [PASS][43] -> [INCOMPLETE][44] ([i915#180] / [i915#1982] / [i915#4939])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-kbl:          [PASS][45] -> [DMESG-WARN][46] ([i915#180]) +4 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip@plain-flip-ts-check@c-edp1:
    - shard-skl:          [PASS][47] -> [FAIL][48] ([i915#2122])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl4/igt@kms_flip@plain-flip-ts-check@c-edp1.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl2/igt@kms_flip@plain-flip-ts-check@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271]) +7 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-iclb:         NOTRUN -> [SKIP][50] ([fdo#109280])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-skl:          [PASS][51] -> [INCOMPLETE][52] ([i915#1982] / [i915#4939])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl7/igt@kms_frontbuffer_tracking@psr-suspend.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl6/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
    - shard-kbl:          [PASS][53] -> [FAIL][54] ([i915#1188]) +1 similar issue
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-apl:          NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_pipe_crc_basic@read-crc-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
    - shard-skl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl4/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
    - shard-apl:          [PASS][58] -> [DMESG-WARN][59] ([i915#180])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-skl:          NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][61] ([i915#265])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
    - shard-iclb:         [PASS][62] -> [SKIP][63] ([i915#5176]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb6/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1:
    - shard-iclb:         [PASS][64] -> [SKIP][65] ([i915#5235]) +2 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb5/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-skl:          NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#658])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][68] -> [SKIP][69] ([fdo#109441]) +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb8/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglb:         [PASS][70] -> [SKIP][71] ([i915#5519])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
    - shard-iclb:         [PASS][72] -> [SKIP][73] ([i915#5519])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-skl:          NOTRUN -> [SKIP][74] ([fdo#109271]) +124 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_sysfs_edid_timing:
    - shard-kbl:          NOTRUN -> [FAIL][75] ([IGT#2])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_sysfs_edid_timing.html

  * igt@nouveau_crc@pipe-c-source-outp-inactive:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([i915#2530])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@nouveau_crc@pipe-c-source-outp-inactive.html

  * igt@sw_sync@sync_multi_timeline_wait:
    - shard-apl:          NOTRUN -> [FAIL][77] ([i915#6140])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl4/igt@sw_sync@sync_multi_timeline_wait.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [FAIL][78] ([i915#2410]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [FAIL][80] ([i915#2842]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
    - shard-apl:          [SKIP][82] ([fdo#109271]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl4/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][84] ([i915#2842]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-kbl:          [FAIL][86] ([i915#2842]) -> [PASS][87] +3 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][88] ([i915#2849]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - shard-apl:          [DMESG-WARN][90] ([i915#180]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-apl7/igt@gem_exec_suspend@basic-s3@smem.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-apl4/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [DMESG-WARN][92] ([i915#118]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk2/igt@gem_exec_whisper@basic-queues-all.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html

  * igt@i915_selftest@live@hangcheck:
    - shard-iclb:         [INCOMPLETE][94] -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb1/igt@i915_selftest@live@hangcheck.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb4/igt@i915_selftest@live@hangcheck.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-skl:          [FAIL][96] ([i915#2521]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][98] ([i915#79]) -> [PASS][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1:
    - shard-glk:          [FAIL][100] ([i915#2122]) -> [PASS][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [INCOMPLETE][102] ([i915#3614]) -> [PASS][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_flip@flip-vs-suspend@c-edp1:
    - shard-skl:          [INCOMPLETE][104] ([i915#4839]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl6/igt@kms_flip@flip-vs-suspend@c-edp1.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl7/igt@kms_flip@flip-vs-suspend@c-edp1.html

  * igt@kms_flip@plain-flip-ts-check@a-edp1:
    - shard-skl:          [FAIL][106] ([i915#2122]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl4/igt@kms_flip@plain-flip-ts-check@a-edp1.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl2/igt@kms_flip@plain-flip-ts-check@a-edp1.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
    - shard-kbl:          [FAIL][108] ([i915#1188]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][110] ([i915#180]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][112] ([fdo#109441]) -> [PASS][113] +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@perf@polling-parameterized:
    - shard-skl:          [FAIL][114] ([i915#5639]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-skl1/igt@perf@polling-parameterized.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-skl10/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [FAIL][116] ([i915#6117]) -> [SKIP][117] ([i915#4525])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][118] ([i915#658]) -> [SKIP][119] ([i915#588])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb6/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
    - shard-iclb:         [SKIP][120] ([i915#2920]) -> [SKIP][121] ([i915#658]) +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb1/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][122] ([i915#658]) -> [SKIP][123] ([i915#2920])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb6/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-iclb:         [FAIL][124] ([i915#5939]) -> [SKIP][125] ([fdo#109642] / [fdo#111068] / [i915#658])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb5/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-iclb:         [SKIP][126] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][127] ([i915#5939])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][128], [FAIL][129], [FAIL][130]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl3/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl4/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11768/shard-kbl6/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl1/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl6/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/shard-kbl4/igt@runner@aborted.html

  

### Piglit changes ###

#### Issues hit ####

  * spec@arb_compute_shader@local-id-explosion:
    - pig-kbl-iris:       NOTRUN -> [INCOMPLETE][137] ([i915#4747])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/pig-kbl-iris/spec@arb_compute_shader@local-id-explosion.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4747]: https://gitlab.freedesktop.org/drm/intel/issues/4747
  [i915#4839]: https://gitlab.freedesktop.org/drm/intel/issues/4839
  [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_11768 -> Patchwork_104128v3

  CI-20190529: 20190529
  CI_DRM_11768: 6da0a0872a9b44e2be9645c1d7045fe88e035c25 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6533: 6b5107d91827962808441db6b98e478aa9e67bdb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_104128v3: 6da0a0872a9b44e2be9645c1d7045fe88e035c25 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104128v3/index.html

[-- Attachment #2: Type: text/html, Size: 40066 bytes --]

Re: [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Matt Roper]

On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>  drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
>  include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
>  4 files changed, 47 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5bc6a774c5a..f1f8699eedfd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>  
>  #define IS_DG2_G10(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>  #define IS_DG2_G11(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>  #define IS_DG2_G12(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>  #define IS_ADLS_RPLS(dev_priv) \
>  	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..93da555adc4e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>  	INTEL_RPLP_IDS(0),
>  };
>  
> +static const u16 subplatform_g10_mb_mbd_ids[] = {
> +	INTEL_DG2_G10_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g11_mb_mbd_ids[] = {
> +	INTEL_DG2_G11_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g12_mb_mbd_ids[] = {
> +	INTEL_DG2_G12_NB_MBD_IDS(0),
> +};

We only need a single MBD subplatform, not three new subplatforms.
Unless I'm forgetting something, a single device ID can be assigned two
two independent subplatforms at the same time.  So the decision about
whether to set the G10, G11, or G12 bit is one decision.  The decision
about whether to set the MBD bit is a completely separate decision that
doesn't care about the G10/G11/G12 stuff.

> +
>  static const u16 subplatform_g10_ids[] = {
>  	INTEL_DG2_G10_IDS(0),
>  	INTEL_ATS_M150_IDS(0),
> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>  	} else if (find_devid(devid, subplatform_rpl_ids,
>  			      ARRAY_SIZE(subplatform_rpl_ids))) {
>  		mask = BIT(INTEL_SUBPLATFORM_RPL);
> +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);

Assuming you consolidate MBD back down to just a single extra
subplatform, the lookup and bit setting should happen in a separate 'if'
statement (not an 'else' block).

        if (find_devid(devid, subplatform_mbd_ids,
                       ARRAY_SIZE(subplatform_mbd_ids)))
                mask |= BIT(INTEL_SUBPLATFORM_MBD);


Matt

>  	} else if (find_devid(devid, subplatform_g10_ids,
>  			      ARRAY_SIZE(subplatform_g10_ids))) {
>  		mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 08341174ee0a..c929e2d7e59c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -97,7 +97,7 @@ enum intel_platform {
>   * it is fine for the same bit to be used on multiple parent platforms.
>   */
>  
> -#define INTEL_SUBPLATFORM_BITS (3)
> +#define INTEL_SUBPLATFORM_BITS (6)
>  #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>  
>  /* HSW/BDW/SKL/KBL/CFL */
> @@ -111,9 +111,12 @@ enum intel_platform {
>  #define INTEL_SUBPLATFORM_UY	(0)
>  
>  /* DG2 */
> -#define INTEL_SUBPLATFORM_G10	0
> -#define INTEL_SUBPLATFORM_G11	1
> -#define INTEL_SUBPLATFORM_G12	2
> +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
> +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
> +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
> +#define INTEL_SUBPLATFORM_G10	3
> +#define INTEL_SUBPLATFORM_G11	4
> +#define INTEL_SUBPLATFORM_G12	5
>  
>  /* ADL */
>  #define INTEL_SUBPLATFORM_RPL	0
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 4585fed4e41e..198be417bb2d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -693,32 +693,41 @@
>  	INTEL_VGA_DEVICE(0xA7A9, info)
>  
>  /* DG2 */
> -#define INTEL_DG2_G10_IDS(info) \
> +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
>  	INTEL_VGA_DEVICE(0x5690, info), \
>  	INTEL_VGA_DEVICE(0x5691, info), \
> -	INTEL_VGA_DEVICE(0x5692, info), \
> +	INTEL_VGA_DEVICE(0x5692, info)
> +
> +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5693, info), \
> +	INTEL_VGA_DEVICE(0x5694, info), \
> +	INTEL_VGA_DEVICE(0x5695, info)
> +
> +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5696, info), \
> +	INTEL_VGA_DEVICE(0x5697, info)
> +
> +#define INTEL_DG2_G10_IDS(info) \
>  	INTEL_VGA_DEVICE(0x56A0, info), \
>  	INTEL_VGA_DEVICE(0x56A1, info), \
>  	INTEL_VGA_DEVICE(0x56A2, info)
>  
>  #define INTEL_DG2_G11_IDS(info) \
> -	INTEL_VGA_DEVICE(0x5693, info), \
> -	INTEL_VGA_DEVICE(0x5694, info), \
> -	INTEL_VGA_DEVICE(0x5695, info), \
>  	INTEL_VGA_DEVICE(0x56A5, info), \
>  	INTEL_VGA_DEVICE(0x56A6, info), \
>  	INTEL_VGA_DEVICE(0x56B0, info), \
>  	INTEL_VGA_DEVICE(0x56B1, info)
>  
>  #define INTEL_DG2_G12_IDS(info) \
> -	INTEL_VGA_DEVICE(0x5696, info), \
> -	INTEL_VGA_DEVICE(0x5697, info), \
>  	INTEL_VGA_DEVICE(0x56A3, info), \
>  	INTEL_VGA_DEVICE(0x56A4, info), \
>  	INTEL_VGA_DEVICE(0x56B2, info), \
>  	INTEL_VGA_DEVICE(0x56B3, info)
>  
>  #define INTEL_DG2_IDS(info) \
> +	INTEL_DG2_G10_NB_MBD_IDS(info), \
> +	INTEL_DG2_G11_NB_MBD_IDS(info), \
> +	INTEL_DG2_G12_NB_MBD_IDS(info), \
>  	INTEL_DG2_G10_IDS(info), \
>  	INTEL_DG2_G11_IDS(info), \
>  	INTEL_DG2_G12_IDS(info)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Matt Roper]

On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> DG2 NB SKU need to distinguish between MBD and AIC to probe
> the VRAM Self Refresh feature support. Adding those sub platform
> accordingly.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h          |  3 +++
>  drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
>  include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
>  4 files changed, 47 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a5bc6a774c5a..f1f8699eedfd 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
>  
>  #define IS_DG2_G10(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10_NB_MBD) || \
>  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
>  #define IS_DG2_G11(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11_NB_MBD) || \
>  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
>  #define IS_DG2_G12(dev_priv) \
> +	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12_NB_MBD) || \
>  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
>  #define IS_ADLS_RPLS(dev_priv) \
>  	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index f0bf23726ed8..93da555adc4e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
>  	INTEL_RPLP_IDS(0),
>  };
>  
> +static const u16 subplatform_g10_mb_mbd_ids[] = {
> +	INTEL_DG2_G10_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g11_mb_mbd_ids[] = {
> +	INTEL_DG2_G11_NB_MBD_IDS(0),
> +};
> +
> +static const u16 subplatform_g12_mb_mbd_ids[] = {
> +	INTEL_DG2_G12_NB_MBD_IDS(0),
> +};

We only need a single MBD subplatform, not three new subplatforms.
Unless I'm forgetting something, a single device ID can be assigned two
two independent subplatforms at the same time.  So the decision about
whether to set the G10, G11, or G12 bit is one decision.  The decision
about whether to set the MBD bit is a completely separate decision that
doesn't care about the G10/G11/G12 stuff.

> +
>  static const u16 subplatform_g10_ids[] = {
>  	INTEL_DG2_G10_IDS(0),
>  	INTEL_ATS_M150_IDS(0),
> @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>  	} else if (find_devid(devid, subplatform_rpl_ids,
>  			      ARRAY_SIZE(subplatform_rpl_ids))) {
>  		mask = BIT(INTEL_SUBPLATFORM_RPL);
> +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);

Assuming you consolidate MBD back down to just a single extra
subplatform, the lookup and bit setting should happen in a separate 'if'
statement (not an 'else' block).

        if (find_devid(devid, subplatform_mbd_ids,
                       ARRAY_SIZE(subplatform_mbd_ids)))
                mask |= BIT(INTEL_SUBPLATFORM_MBD);


Matt

>  	} else if (find_devid(devid, subplatform_g10_ids,
>  			      ARRAY_SIZE(subplatform_g10_ids))) {
>  		mask = BIT(INTEL_SUBPLATFORM_G10);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 08341174ee0a..c929e2d7e59c 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -97,7 +97,7 @@ enum intel_platform {
>   * it is fine for the same bit to be used on multiple parent platforms.
>   */
>  
> -#define INTEL_SUBPLATFORM_BITS (3)
> +#define INTEL_SUBPLATFORM_BITS (6)
>  #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
>  
>  /* HSW/BDW/SKL/KBL/CFL */
> @@ -111,9 +111,12 @@ enum intel_platform {
>  #define INTEL_SUBPLATFORM_UY	(0)
>  
>  /* DG2 */
> -#define INTEL_SUBPLATFORM_G10	0
> -#define INTEL_SUBPLATFORM_G11	1
> -#define INTEL_SUBPLATFORM_G12	2
> +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
> +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
> +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
> +#define INTEL_SUBPLATFORM_G10	3
> +#define INTEL_SUBPLATFORM_G11	4
> +#define INTEL_SUBPLATFORM_G12	5
>  
>  /* ADL */
>  #define INTEL_SUBPLATFORM_RPL	0
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 4585fed4e41e..198be417bb2d 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -693,32 +693,41 @@
>  	INTEL_VGA_DEVICE(0xA7A9, info)
>  
>  /* DG2 */
> -#define INTEL_DG2_G10_IDS(info) \
> +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
>  	INTEL_VGA_DEVICE(0x5690, info), \
>  	INTEL_VGA_DEVICE(0x5691, info), \
> -	INTEL_VGA_DEVICE(0x5692, info), \
> +	INTEL_VGA_DEVICE(0x5692, info)
> +
> +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5693, info), \
> +	INTEL_VGA_DEVICE(0x5694, info), \
> +	INTEL_VGA_DEVICE(0x5695, info)
> +
> +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
> +	INTEL_VGA_DEVICE(0x5696, info), \
> +	INTEL_VGA_DEVICE(0x5697, info)
> +
> +#define INTEL_DG2_G10_IDS(info) \
>  	INTEL_VGA_DEVICE(0x56A0, info), \
>  	INTEL_VGA_DEVICE(0x56A1, info), \
>  	INTEL_VGA_DEVICE(0x56A2, info)
>  
>  #define INTEL_DG2_G11_IDS(info) \
> -	INTEL_VGA_DEVICE(0x5693, info), \
> -	INTEL_VGA_DEVICE(0x5694, info), \
> -	INTEL_VGA_DEVICE(0x5695, info), \
>  	INTEL_VGA_DEVICE(0x56A5, info), \
>  	INTEL_VGA_DEVICE(0x56A6, info), \
>  	INTEL_VGA_DEVICE(0x56B0, info), \
>  	INTEL_VGA_DEVICE(0x56B1, info)
>  
>  #define INTEL_DG2_G12_IDS(info) \
> -	INTEL_VGA_DEVICE(0x5696, info), \
> -	INTEL_VGA_DEVICE(0x5697, info), \
>  	INTEL_VGA_DEVICE(0x56A3, info), \
>  	INTEL_VGA_DEVICE(0x56A4, info), \
>  	INTEL_VGA_DEVICE(0x56B2, info), \
>  	INTEL_VGA_DEVICE(0x56B3, info)
>  
>  #define INTEL_DG2_IDS(info) \
> +	INTEL_DG2_G10_NB_MBD_IDS(info), \
> +	INTEL_DG2_G11_NB_MBD_IDS(info), \
> +	INTEL_DG2_G12_NB_MBD_IDS(info), \
>  	INTEL_DG2_G10_IDS(info), \
>  	INTEL_DG2_G11_IDS(info), \
>  	INTEL_DG2_G12_IDS(info)
> -- 
> 2.26.2
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation

RE: [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Gupta, Anshuman]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, June 17, 2022 5:43 AM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Nilawar,
> Badal <badal.nilawar@intel.com>; Ewins, Jon <jon.ewins@intel.com>; Vivi,
> Rodrigo <rodrigo.vivi@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> Tangudu, Tilak <tilak.tangudu@intel.com>
> Subject: Re: [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform
> 
> On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> > DG2 NB SKU need to distinguish between MBD and AIC to probe the VRAM
> > Self Refresh feature support. Adding those sub platform accordingly.
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h          |  3 +++
> >  drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
> >  include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
> >  4 files changed, 47 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index a5bc6a774c5a..f1f8699eedfd
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_PONTEVECCHIO)
> >
> >  #define IS_DG2_G10(dev_priv) \
> > +	IS_SUBPLATFORM(dev_priv, INTEL_DG2,
> INTEL_SUBPLATFORM_G10_NB_MBD) ||
> > +\
> >  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define
> > IS_DG2_G11(dev_priv) \
> > +	IS_SUBPLATFORM(dev_priv, INTEL_DG2,
> INTEL_SUBPLATFORM_G11_NB_MBD) ||
> > +\
> >  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> #define
> > IS_DG2_G12(dev_priv) \
> > +	IS_SUBPLATFORM(dev_priv, INTEL_DG2,
> INTEL_SUBPLATFORM_G12_NB_MBD) ||
> > +\
> >  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
> #define
> > IS_ADLS_RPLS(dev_priv) \
> >  	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S,
> INTEL_SUBPLATFORM_RPL)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index f0bf23726ed8..93da555adc4e 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
> >  	INTEL_RPLP_IDS(0),
> >  };
> >
> > +static const u16 subplatform_g10_mb_mbd_ids[] = {
> > +	INTEL_DG2_G10_NB_MBD_IDS(0),
> > +};
> > +
> > +static const u16 subplatform_g11_mb_mbd_ids[] = {
> > +	INTEL_DG2_G11_NB_MBD_IDS(0),
> > +};
> > +
> > +static const u16 subplatform_g12_mb_mbd_ids[] = {
> > +	INTEL_DG2_G12_NB_MBD_IDS(0),
> > +};
> 
> We only need a single MBD subplatform, not three new subplatforms.
> Unless I'm forgetting something, a single device ID can be assigned two two
> independent subplatforms at the same time.  So the decision about whether to
> set the G10, G11, or G12 bit is one decision.  The decision about whether to set
> the MBD bit is a completely separate decision that doesn't care about the
> G10/G11/G12 stuff.
> 
> > +
> >  static const u16 subplatform_g10_ids[] = {
> >  	INTEL_DG2_G10_IDS(0),
> >  	INTEL_ATS_M150_IDS(0),
> > @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> >  	} else if (find_devid(devid, subplatform_rpl_ids,
> >  			      ARRAY_SIZE(subplatform_rpl_ids))) {
> >  		mask = BIT(INTEL_SUBPLATFORM_RPL);
> > +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> > +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> > +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> > +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> > +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> > +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> > +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> > +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> > +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
> 
> Assuming you consolidate MBD back down to just a single extra subplatform,
> the lookup and bit setting should happen in a separate 'if'
> statement (not an 'else' block).
> 
>         if (find_devid(devid, subplatform_mbd_ids,
>                        ARRAY_SIZE(subplatform_mbd_ids)))
>                 mask |= BIT(INTEL_SUBPLATFORM_MBD);
Thanks Matt , Jani and Tvrtko for review comment,
I will create only INTEL_SUBPLATFORM_MBD and address it.
Regards,
Anshuman Gupta.
> 
> 
> Matt
> 
> >  	} else if (find_devid(devid, subplatform_g10_ids,
> >  			      ARRAY_SIZE(subplatform_g10_ids))) {
> >  		mask = BIT(INTEL_SUBPLATFORM_G10);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 08341174ee0a..c929e2d7e59c 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -97,7 +97,7 @@ enum intel_platform {
> >   * it is fine for the same bit to be used on multiple parent platforms.
> >   */
> >
> > -#define INTEL_SUBPLATFORM_BITS (3)
> > +#define INTEL_SUBPLATFORM_BITS (6)
> >  #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
> >
> >  /* HSW/BDW/SKL/KBL/CFL */
> > @@ -111,9 +111,12 @@ enum intel_platform {
> >  #define INTEL_SUBPLATFORM_UY	(0)
> >
> >  /* DG2 */
> > -#define INTEL_SUBPLATFORM_G10	0
> > -#define INTEL_SUBPLATFORM_G11	1
> > -#define INTEL_SUBPLATFORM_G12	2
> > +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
> > +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
> > +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
> > +#define INTEL_SUBPLATFORM_G10	3
> > +#define INTEL_SUBPLATFORM_G11	4
> > +#define INTEL_SUBPLATFORM_G12	5
> >
> >  /* ADL */
> >  #define INTEL_SUBPLATFORM_RPL	0
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 4585fed4e41e..198be417bb2d 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -693,32 +693,41 @@
> >  	INTEL_VGA_DEVICE(0xA7A9, info)
> >
> >  /* DG2 */
> > -#define INTEL_DG2_G10_IDS(info) \
> > +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x5690, info), \
> >  	INTEL_VGA_DEVICE(0x5691, info), \
> > -	INTEL_VGA_DEVICE(0x5692, info), \
> > +	INTEL_VGA_DEVICE(0x5692, info)
> > +
> > +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x5693, info), \
> > +	INTEL_VGA_DEVICE(0x5694, info), \
> > +	INTEL_VGA_DEVICE(0x5695, info)
> > +
> > +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x5696, info), \
> > +	INTEL_VGA_DEVICE(0x5697, info)
> > +
> > +#define INTEL_DG2_G10_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x56A0, info), \
> >  	INTEL_VGA_DEVICE(0x56A1, info), \
> >  	INTEL_VGA_DEVICE(0x56A2, info)
> >
> >  #define INTEL_DG2_G11_IDS(info) \
> > -	INTEL_VGA_DEVICE(0x5693, info), \
> > -	INTEL_VGA_DEVICE(0x5694, info), \
> > -	INTEL_VGA_DEVICE(0x5695, info), \
> >  	INTEL_VGA_DEVICE(0x56A5, info), \
> >  	INTEL_VGA_DEVICE(0x56A6, info), \
> >  	INTEL_VGA_DEVICE(0x56B0, info), \
> >  	INTEL_VGA_DEVICE(0x56B1, info)
> >
> >  #define INTEL_DG2_G12_IDS(info) \
> > -	INTEL_VGA_DEVICE(0x5696, info), \
> > -	INTEL_VGA_DEVICE(0x5697, info), \
> >  	INTEL_VGA_DEVICE(0x56A3, info), \
> >  	INTEL_VGA_DEVICE(0x56A4, info), \
> >  	INTEL_VGA_DEVICE(0x56B2, info), \
> >  	INTEL_VGA_DEVICE(0x56B3, info)
> >
> >  #define INTEL_DG2_IDS(info) \
> > +	INTEL_DG2_G10_NB_MBD_IDS(info), \
> > +	INTEL_DG2_G11_NB_MBD_IDS(info), \
> > +	INTEL_DG2_G12_NB_MBD_IDS(info), \
> >  	INTEL_DG2_G10_IDS(info), \
> >  	INTEL_DG2_G11_IDS(info), \
> >  	INTEL_DG2_G12_IDS(info)
> > --
> > 2.26.2
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation

Re: [Intel-gfx] [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform

[Gupta, Anshuman]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Friday, June 17, 2022 5:43 AM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Nilawar,
> Badal <badal.nilawar@intel.com>; Ewins, Jon <jon.ewins@intel.com>; Vivi,
> Rodrigo <rodrigo.vivi@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>;
> Tangudu, Tilak <tilak.tangudu@intel.com>
> Subject: Re: [PATCH v2 3/9] drm/i915/dg2: Add DG2_NB_MBD subplatform
> 
> On Thu, Jun 16, 2022 at 05:31:00PM +0530, Anshuman Gupta wrote:
> > DG2 NB SKU need to distinguish between MBD and AIC to probe the VRAM
> > Self Refresh feature support. Adding those sub platform accordingly.
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h          |  3 +++
> >  drivers/gpu/drm/i915/intel_device_info.c | 21 +++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_device_info.h | 11 +++++++----
> >  include/drm/i915_pciids.h                | 23 ++++++++++++++++-------
> >  4 files changed, 47 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index a5bc6a774c5a..f1f8699eedfd
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1007,10 +1007,13 @@ IS_SUBPLATFORM(const struct drm_i915_private
> > *i915,  #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv,
> > INTEL_PONTEVECCHIO)
> >
> >  #define IS_DG2_G10(dev_priv) \
> > +	IS_SUBPLATFORM(dev_priv, INTEL_DG2,
> INTEL_SUBPLATFORM_G10_NB_MBD) ||
> > +\
> >  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define
> > IS_DG2_G11(dev_priv) \
> > +	IS_SUBPLATFORM(dev_priv, INTEL_DG2,
> INTEL_SUBPLATFORM_G11_NB_MBD) ||
> > +\
> >  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> #define
> > IS_DG2_G12(dev_priv) \
> > +	IS_SUBPLATFORM(dev_priv, INTEL_DG2,
> INTEL_SUBPLATFORM_G12_NB_MBD) ||
> > +\
> >  	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
> #define
> > IS_ADLS_RPLS(dev_priv) \
> >  	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S,
> INTEL_SUBPLATFORM_RPL)
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> > b/drivers/gpu/drm/i915/intel_device_info.c
> > index f0bf23726ed8..93da555adc4e 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.c
> > +++ b/drivers/gpu/drm/i915/intel_device_info.c
> > @@ -187,6 +187,18 @@ static const u16 subplatform_rpl_ids[] = {
> >  	INTEL_RPLP_IDS(0),
> >  };
> >
> > +static const u16 subplatform_g10_mb_mbd_ids[] = {
> > +	INTEL_DG2_G10_NB_MBD_IDS(0),
> > +};
> > +
> > +static const u16 subplatform_g11_mb_mbd_ids[] = {
> > +	INTEL_DG2_G11_NB_MBD_IDS(0),
> > +};
> > +
> > +static const u16 subplatform_g12_mb_mbd_ids[] = {
> > +	INTEL_DG2_G12_NB_MBD_IDS(0),
> > +};
> 
> We only need a single MBD subplatform, not three new subplatforms.
> Unless I'm forgetting something, a single device ID can be assigned two two
> independent subplatforms at the same time.  So the decision about whether to
> set the G10, G11, or G12 bit is one decision.  The decision about whether to set
> the MBD bit is a completely separate decision that doesn't care about the
> G10/G11/G12 stuff.
> 
> > +
> >  static const u16 subplatform_g10_ids[] = {
> >  	INTEL_DG2_G10_IDS(0),
> >  	INTEL_ATS_M150_IDS(0),
> > @@ -246,6 +258,15 @@ void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> >  	} else if (find_devid(devid, subplatform_rpl_ids,
> >  			      ARRAY_SIZE(subplatform_rpl_ids))) {
> >  		mask = BIT(INTEL_SUBPLATFORM_RPL);
> > +	} else if (find_devid(devid, subplatform_g10_mb_mbd_ids,
> > +			      ARRAY_SIZE(subplatform_g10_mb_mbd_ids))) {
> > +		mask = BIT(INTEL_SUBPLATFORM_G10_NB_MBD);
> > +	} else if (find_devid(devid, subplatform_g11_mb_mbd_ids,
> > +			      ARRAY_SIZE(subplatform_g11_mb_mbd_ids))) {
> > +		mask = BIT(INTEL_SUBPLATFORM_G11_NB_MBD);
> > +	} else if (find_devid(devid, subplatform_g12_mb_mbd_ids,
> > +			      ARRAY_SIZE(subplatform_g12_mb_mbd_ids))) {
> > +		mask = BIT(INTEL_SUBPLATFORM_G12_NB_MBD);
> 
> Assuming you consolidate MBD back down to just a single extra subplatform,
> the lookup and bit setting should happen in a separate 'if'
> statement (not an 'else' block).
> 
>         if (find_devid(devid, subplatform_mbd_ids,
>                        ARRAY_SIZE(subplatform_mbd_ids)))
>                 mask |= BIT(INTEL_SUBPLATFORM_MBD);
Thanks Matt , Jani and Tvrtko for review comment,
I will create only INTEL_SUBPLATFORM_MBD and address it.
Regards,
Anshuman Gupta.
> 
> 
> Matt
> 
> >  	} else if (find_devid(devid, subplatform_g10_ids,
> >  			      ARRAY_SIZE(subplatform_g10_ids))) {
> >  		mask = BIT(INTEL_SUBPLATFORM_G10);
> > diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> > b/drivers/gpu/drm/i915/intel_device_info.h
> > index 08341174ee0a..c929e2d7e59c 100644
> > --- a/drivers/gpu/drm/i915/intel_device_info.h
> > +++ b/drivers/gpu/drm/i915/intel_device_info.h
> > @@ -97,7 +97,7 @@ enum intel_platform {
> >   * it is fine for the same bit to be used on multiple parent platforms.
> >   */
> >
> > -#define INTEL_SUBPLATFORM_BITS (3)
> > +#define INTEL_SUBPLATFORM_BITS (6)
> >  #define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
> >
> >  /* HSW/BDW/SKL/KBL/CFL */
> > @@ -111,9 +111,12 @@ enum intel_platform {
> >  #define INTEL_SUBPLATFORM_UY	(0)
> >
> >  /* DG2 */
> > -#define INTEL_SUBPLATFORM_G10	0
> > -#define INTEL_SUBPLATFORM_G11	1
> > -#define INTEL_SUBPLATFORM_G12	2
> > +#define INTEL_SUBPLATFORM_G10_NB_MBD	0
> > +#define INTEL_SUBPLATFORM_G11_NB_MBD	1
> > +#define INTEL_SUBPLATFORM_G12_NB_MBD	2
> > +#define INTEL_SUBPLATFORM_G10	3
> > +#define INTEL_SUBPLATFORM_G11	4
> > +#define INTEL_SUBPLATFORM_G12	5
> >
> >  /* ADL */
> >  #define INTEL_SUBPLATFORM_RPL	0
> > diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> > index 4585fed4e41e..198be417bb2d 100644
> > --- a/include/drm/i915_pciids.h
> > +++ b/include/drm/i915_pciids.h
> > @@ -693,32 +693,41 @@
> >  	INTEL_VGA_DEVICE(0xA7A9, info)
> >
> >  /* DG2 */
> > -#define INTEL_DG2_G10_IDS(info) \
> > +#define INTEL_DG2_G10_NB_MBD_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x5690, info), \
> >  	INTEL_VGA_DEVICE(0x5691, info), \
> > -	INTEL_VGA_DEVICE(0x5692, info), \
> > +	INTEL_VGA_DEVICE(0x5692, info)
> > +
> > +#define INTEL_DG2_G11_NB_MBD_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x5693, info), \
> > +	INTEL_VGA_DEVICE(0x5694, info), \
> > +	INTEL_VGA_DEVICE(0x5695, info)
> > +
> > +#define INTEL_DG2_G12_NB_MBD_IDS(info) \
> > +	INTEL_VGA_DEVICE(0x5696, info), \
> > +	INTEL_VGA_DEVICE(0x5697, info)
> > +
> > +#define INTEL_DG2_G10_IDS(info) \
> >  	INTEL_VGA_DEVICE(0x56A0, info), \
> >  	INTEL_VGA_DEVICE(0x56A1, info), \
> >  	INTEL_VGA_DEVICE(0x56A2, info)
> >
> >  #define INTEL_DG2_G11_IDS(info) \
> > -	INTEL_VGA_DEVICE(0x5693, info), \
> > -	INTEL_VGA_DEVICE(0x5694, info), \
> > -	INTEL_VGA_DEVICE(0x5695, info), \
> >  	INTEL_VGA_DEVICE(0x56A5, info), \
> >  	INTEL_VGA_DEVICE(0x56A6, info), \
> >  	INTEL_VGA_DEVICE(0x56B0, info), \
> >  	INTEL_VGA_DEVICE(0x56B1, info)
> >
> >  #define INTEL_DG2_G12_IDS(info) \
> > -	INTEL_VGA_DEVICE(0x5696, info), \
> > -	INTEL_VGA_DEVICE(0x5697, info), \
> >  	INTEL_VGA_DEVICE(0x56A3, info), \
> >  	INTEL_VGA_DEVICE(0x56A4, info), \
> >  	INTEL_VGA_DEVICE(0x56B2, info), \
> >  	INTEL_VGA_DEVICE(0x56B3, info)
> >
> >  #define INTEL_DG2_IDS(info) \
> > +	INTEL_DG2_G10_NB_MBD_IDS(info), \
> > +	INTEL_DG2_G11_NB_MBD_IDS(info), \
> > +	INTEL_DG2_G12_NB_MBD_IDS(info), \
> >  	INTEL_DG2_G10_IDS(info), \
> >  	INTEL_DG2_G11_IDS(info), \
> >  	INTEL_DG2_G12_IDS(info)
> > --
> > 2.26.2
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> VTT-OSGC Platform Enablement
> Intel Corporation

RE: [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Gupta, Anshuman]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 16, 2022 8:02 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Wilson, Chris P <chris.p.wilson@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR
> Support
> 
> On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Intel Client DGFX card supports D3Cold with two option.
> > D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
> >
> > i915 requires to evict the lmem objects to smem in order to support
> > D3Cold-Off, which increases i915 the suspend/resume latency. Enabling
> > VRAM Self Refresh feature optimize the latency with additional power
> > cost which required to retain the lmem.
> >
> > Adding intel_runtime_idle (runtime_idle callback) to enable VRAM_SR,
> > it will be used for policy to choose between D3Cold-off vs
> > D3Cold-VRAM_SR.
> >
> > Since we have introduced i915 runtime_idle callback.
> > It need to be warranted that Runtime PM Core invokes runtime_idle
> > callback when runtime usages count becomes zero. That requires to use
> > pm_runtime_put instead of pm_runtime_put_autosuspend.
> >
> > TODO: GuC interface state save/restore.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Chris Wilson <chris.p.wilson@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_driver.c      | 26 +++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
> >  2 files changed, 27 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index aa1fb15b1f11..fcff5f3fe05e 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
> >  	return i915_pm_resume(kdev);
> >  }
> >
> > +static int intel_runtime_idle(struct device *kdev) {
> > +	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > +	int ret = 1;
> > +
> > +	if (!HAS_LMEM_SR(dev_priv)) {
> > +		/*TODO: Prepare for D3Cold-Off */
> > +		goto out;
> > +	}
> > +
> > +	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +
> > +	ret = intel_pm_vram_sr(dev_priv, true);
> > +	if (!ret)
> > +		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
> 
> Please add the debug in the intel_pm_vram_sr() function instead.
Thanks for review comment, will fix this.
Regards,
Anshuman Gupta.
> 
> BR,
> Jani.
> 
> > +
> > +	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +
> > +out:
> > +	pm_runtime_mark_last_busy(kdev);
> > +	pm_runtime_autosuspend(kdev);
> > +
> > +	return ret;
> > +}
> > +
> >  static int intel_runtime_suspend(struct device *kdev)  {
> >  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev); @@ -1742,6
> > +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
> >  	.restore = i915_pm_restore,
> >
> >  	/* S0ix (via runtime suspend) event handlers */
> > +	.runtime_idle = intel_runtime_idle,
> >  	.runtime_suspend = intel_runtime_suspend,
> >  	.runtime_resume = intel_runtime_resume,  }; diff --git
> > a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 6ed5786bcd29..4dade7e8a795 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct
> > intel_runtime_pm *rpm,
> >
> >  	intel_runtime_pm_release(rpm, wakelock);
> >
> > -	pm_runtime_mark_last_busy(kdev);
> > -	pm_runtime_put_autosuspend(kdev);
> > +	pm_runtime_put(kdev);
> >  }
> >
> >  /**
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR Support

[Gupta, Anshuman]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 16, 2022 8:02 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Wilson, Chris P <chris.p.wilson@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/rpm: Enable D3Cold VRAM SR
> Support
> 
> On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Intel Client DGFX card supports D3Cold with two option.
> > D3Cold-off zero watt, D3Cold-VRAM Self Refresh.
> >
> > i915 requires to evict the lmem objects to smem in order to support
> > D3Cold-Off, which increases i915 the suspend/resume latency. Enabling
> > VRAM Self Refresh feature optimize the latency with additional power
> > cost which required to retain the lmem.
> >
> > Adding intel_runtime_idle (runtime_idle callback) to enable VRAM_SR,
> > it will be used for policy to choose between D3Cold-off vs
> > D3Cold-VRAM_SR.
> >
> > Since we have introduced i915 runtime_idle callback.
> > It need to be warranted that Runtime PM Core invokes runtime_idle
> > callback when runtime usages count becomes zero. That requires to use
> > pm_runtime_put instead of pm_runtime_put_autosuspend.
> >
> > TODO: GuC interface state save/restore.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Chris Wilson <chris.p.wilson@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_driver.c      | 26 +++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |  3 +--
> >  2 files changed, 27 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index aa1fb15b1f11..fcff5f3fe05e 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -1557,6 +1557,31 @@ static int i915_pm_restore(struct device *kdev)
> >  	return i915_pm_resume(kdev);
> >  }
> >
> > +static int intel_runtime_idle(struct device *kdev) {
> > +	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > +	int ret = 1;
> > +
> > +	if (!HAS_LMEM_SR(dev_priv)) {
> > +		/*TODO: Prepare for D3Cold-Off */
> > +		goto out;
> > +	}
> > +
> > +	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +
> > +	ret = intel_pm_vram_sr(dev_priv, true);
> > +	if (!ret)
> > +		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n");
> 
> Please add the debug in the intel_pm_vram_sr() function instead.
Thanks for review comment, will fix this.
Regards,
Anshuman Gupta.
> 
> BR,
> Jani.
> 
> > +
> > +	enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +
> > +out:
> > +	pm_runtime_mark_last_busy(kdev);
> > +	pm_runtime_autosuspend(kdev);
> > +
> > +	return ret;
> > +}
> > +
> >  static int intel_runtime_suspend(struct device *kdev)  {
> >  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev); @@ -1742,6
> > +1767,7 @@ const struct dev_pm_ops i915_pm_ops = {
> >  	.restore = i915_pm_restore,
> >
> >  	/* S0ix (via runtime suspend) event handlers */
> > +	.runtime_idle = intel_runtime_idle,
> >  	.runtime_suspend = intel_runtime_suspend,
> >  	.runtime_resume = intel_runtime_resume,  }; diff --git
> > a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 6ed5786bcd29..4dade7e8a795 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -492,8 +492,7 @@ static void __intel_runtime_pm_put(struct
> > intel_runtime_pm *rpm,
> >
> >  	intel_runtime_pm_release(rpm, wakelock);
> >
> > -	pm_runtime_mark_last_busy(kdev);
> > -	pm_runtime_put_autosuspend(kdev);
> > +	pm_runtime_put(kdev);
> >  }
> >
> >  /**
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

RE: [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Gupta, Anshuman]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, June 16, 2022 6:26 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Nilawar, Badal
> <badal.nilawar@intel.com>; Ewins, Jon <jon.ewins@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; Tangudu,
> Tilak <tilak.tangudu@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: Re: [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh
> Support
> 
> On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> > DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> > opportunistic S0ix system wide suspend flow as well.
> >
> > Without VRSR enablement i915 has to evict the lmem objects to system
> > memory. Depending on some heuristics driver will evict lmem objects
> > without VRSR.
> >
> > VRSR feature requires Host BIOS support, VRSR will be enable/disable
> > by HOST BIOS using ACPI OpRegion.
> >
> > Adding OpRegion VRSR support in order to enable/disable VRSR on
> > discrete cards.
> >
> > BSpec: 53440
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_opregion.c | 62
> > ++++++++++++++++++-  drivers/gpu/drm/i915/display/intel_opregion.h |
> > 11 ++++
> >  2 files changed, 72 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > index 6876ba30d5a9..11d8c5bb23ac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > @@ -53,6 +53,8 @@
> >  #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
> >  #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x)
> */
> >
> > +#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
> > +#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
> >  #define PCON_HEADLESS_SKU	BIT(13)
> >
> >  struct opregion_header {
> > @@ -130,7 +132,8 @@ struct opregion_asle {
> >  	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
> >  			 * address of raw VBT data. */
> >  	u32 rvds;	/* Size of raw vbt data */
> > -	u8 rsvd[58];
> > +	u8 vrsr;	/* DGFX Video Ram Self Refresh */
> > +	u8 rsvd[57];
> >  } __packed;
> >
> >  /* OpRegion mailbox #5: ASLE ext */
> > @@ -201,6 +204,9 @@ struct opregion_asle_ext {
> >
> >  #define ASLE_PHED_EDID_VALID_MASK	0x3
> >
> > +/* VRAM SR */
> > +#define ASLE_VRSR_ENABLE		BIT(0)
> > +
> >  /* Software System Control Interrupt (SWSCI) */
> >  #define SWSCI_SCIC_INDICATOR		(1 << 0)
> >  #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
> > @@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private
> *dev_priv)
> >  		opregion->header->over.minor,
> >  		opregion->header->over.revision);
> >
> > +	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n",
> > +opregion->header->pcon);
> > +
> >  	mboxes = opregion->header->mboxes;
> >  	if (mboxes & MBOX_ACPI) {
> >  		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
> @@
> > -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private
> *i915)
> >  	opregion->vbt = NULL;
> >  	opregion->lid_state = NULL;
> >  }
> > +
> > +/**
> > + * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
> > + * Refresh capability support.
> > + * @i915: pointer to i915 device.
> > + *
> > + * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
> > + * capability support. It is only applocable to DGFX.
> > + *
> > + * Returns:
> > + * true when bios supports vram_sr, or false if bios doesn't support.
> > + */
> > +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private
> > +*i915) {
> > +	struct intel_opregion *opregion = &i915->opregion;
> > +
> > +	if (!IS_DGFX(i915))
> > +		return false;
> > +
> > +	if (!opregion)
> 
> This is always true. You should check for !opregion->header.
> 
> > +		return false;
> > +
> > +	if (opregion->header->pcon &
> PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
> > +		return opregion->header->pcon &
> PCON_DGFX_BIOS_SUPPORTS_VRSR;
> > +	else
> > +		return false;
> > +}
> > +
> > +/**
> > + * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
> > + * @i915: pointer to i915 device.
> > + * @enable: Argument to enable/disable VRSR.
> > + *
> > + * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
> > + * HOST BIOS will enables and disbales VRAM_SR during
> > + * ACPI _PS3/_OFF and _PS/_ON glue method.
> > + */
> > +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool
> > +enable) {
> > +	struct intel_opregion *opregion = &i915->opregion;
> > +
> > +	if (!opregion)
> 
> Same as above.
> 
> > +		return;
> > +
> > +	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not
> available\n"))
> > +		return;
> 
> I'd just bundle !opregion->asle into the early return.
> 
> > +
> > +	if (enable)
> > +		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
> > +	else
> > +		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE; }
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h
> > b/drivers/gpu/drm/i915/display/intel_opregion.h
> > index 2f261f985400..73c9d81d5ee6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> > @@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct
> drm_i915_private *dev_priv,
> >  				  pci_power_t state);
> >  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
> > struct edid *intel_opregion_get_edid(struct intel_connector
> > *connector);
> > +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private
> > +*i915); void intel_opregion_vram_sr(struct drm_i915_private *i915,
> > +bool enable);
> >
> >  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
> >
> > @@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct
> drm_i915_private *i915)
> >  	return false;
> >  }
> >
> > +static bool intel_opregion_bios_supports_vram_sr(struct
> > +drm_i915_private *i915) {
> > +	return false;
> > +}
> > +
> > +static void intel_opregion_vram_sr(struct drm_i915_private *i915,
> > +bool enable) { }
> > +
> 
> Both of these stubs need to be static inline.
Thanks for I will fix all of above comment.
Regards,
Anshuman Gupta.
> 
> BR,
> Jani.
> 
> >  #endif /* CONFIG_ACPI */
> >
> >  #endif
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh Support

[Gupta, Anshuman]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, June 16, 2022 6:26 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>; Nilawar, Badal
> <badal.nilawar@intel.com>; Ewins, Jon <jon.ewins@intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; Ursulin, Tvrtko <tvrtko.ursulin@intel.com>; Tangudu,
> Tilak <tilak.tangudu@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: Re: [PATCH v2 1/9] drm/i915/dgfx: OpRegion VRAM Self Refresh
> Support
> 
> On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Intel DGFX cards provides a feature Video Ram Self Refrsh(VRSR).
> > DGFX VRSR can be enabled with runtime suspend D3Cold flow and with
> > opportunistic S0ix system wide suspend flow as well.
> >
> > Without VRSR enablement i915 has to evict the lmem objects to system
> > memory. Depending on some heuristics driver will evict lmem objects
> > without VRSR.
> >
> > VRSR feature requires Host BIOS support, VRSR will be enable/disable
> > by HOST BIOS using ACPI OpRegion.
> >
> > Adding OpRegion VRSR support in order to enable/disable VRSR on
> > discrete cards.
> >
> > BSpec: 53440
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_opregion.c | 62
> > ++++++++++++++++++-  drivers/gpu/drm/i915/display/intel_opregion.h |
> > 11 ++++
> >  2 files changed, 72 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
> > b/drivers/gpu/drm/i915/display/intel_opregion.c
> > index 6876ba30d5a9..11d8c5bb23ac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.c
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.c
> > @@ -53,6 +53,8 @@
> >  #define MBOX_ASLE_EXT		BIT(4)	/* Mailbox #5 */
> >  #define MBOX_BACKLIGHT		BIT(5)	/* Mailbox #2 (valid from v3.x)
> */
> >
> > +#define PCON_DGFX_BIOS_SUPPORTS_VRSR			BIT(11)
> > +#define PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID	BIT(12)
> >  #define PCON_HEADLESS_SKU	BIT(13)
> >
> >  struct opregion_header {
> > @@ -130,7 +132,8 @@ struct opregion_asle {
> >  	u64 rvda;	/* Physical (2.0) or relative from opregion (2.1+)
> >  			 * address of raw VBT data. */
> >  	u32 rvds;	/* Size of raw vbt data */
> > -	u8 rsvd[58];
> > +	u8 vrsr;	/* DGFX Video Ram Self Refresh */
> > +	u8 rsvd[57];
> >  } __packed;
> >
> >  /* OpRegion mailbox #5: ASLE ext */
> > @@ -201,6 +204,9 @@ struct opregion_asle_ext {
> >
> >  #define ASLE_PHED_EDID_VALID_MASK	0x3
> >
> > +/* VRAM SR */
> > +#define ASLE_VRSR_ENABLE		BIT(0)
> > +
> >  /* Software System Control Interrupt (SWSCI) */
> >  #define SWSCI_SCIC_INDICATOR		(1 << 0)
> >  #define SWSCI_SCIC_MAIN_FUNCTION_SHIFT	1
> > @@ -921,6 +927,8 @@ int intel_opregion_setup(struct drm_i915_private
> *dev_priv)
> >  		opregion->header->over.minor,
> >  		opregion->header->over.revision);
> >
> > +	drm_dbg(&dev_priv->drm, "OpRegion PCON values 0x%x\n",
> > +opregion->header->pcon);
> > +
> >  	mboxes = opregion->header->mboxes;
> >  	if (mboxes & MBOX_ACPI) {
> >  		drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n");
> @@
> > -1246,3 +1254,55 @@ void intel_opregion_unregister(struct drm_i915_private
> *i915)
> >  	opregion->vbt = NULL;
> >  	opregion->lid_state = NULL;
> >  }
> > +
> > +/**
> > + * intel_opregion_bios_supports_vram_sr() get HOST BIOS VRAM Self
> > + * Refresh capability support.
> > + * @i915: pointer to i915 device.
> > + *
> > + * It checks opregion pcon vram_sr fields to get HOST BIOS vram_sr
> > + * capability support. It is only applocable to DGFX.
> > + *
> > + * Returns:
> > + * true when bios supports vram_sr, or false if bios doesn't support.
> > + */
> > +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private
> > +*i915) {
> > +	struct intel_opregion *opregion = &i915->opregion;
> > +
> > +	if (!IS_DGFX(i915))
> > +		return false;
> > +
> > +	if (!opregion)
> 
> This is always true. You should check for !opregion->header.
> 
> > +		return false;
> > +
> > +	if (opregion->header->pcon &
> PCON_DGFX_BIOS_SUPPORTS_VRSR_FIELD_VALID)
> > +		return opregion->header->pcon &
> PCON_DGFX_BIOS_SUPPORTS_VRSR;
> > +	else
> > +		return false;
> > +}
> > +
> > +/**
> > + * intel_opregion_vram_sr() - enable/disable VRAM Self Refresh.
> > + * @i915: pointer to i915 device.
> > + * @enable: Argument to enable/disable VRSR.
> > + *
> > + * It enables/disables vram_sr in opregion ASLE MBOX, based upon that
> > + * HOST BIOS will enables and disbales VRAM_SR during
> > + * ACPI _PS3/_OFF and _PS/_ON glue method.
> > + */
> > +void intel_opregion_vram_sr(struct drm_i915_private *i915, bool
> > +enable) {
> > +	struct intel_opregion *opregion = &i915->opregion;
> > +
> > +	if (!opregion)
> 
> Same as above.
> 
> > +		return;
> > +
> > +	if (drm_WARN(&i915->drm, !opregion->asle, "ASLE MAILBOX3 is not
> available\n"))
> > +		return;
> 
> I'd just bundle !opregion->asle into the early return.
> 
> > +
> > +	if (enable)
> > +		opregion->asle->vrsr |= ASLE_VRSR_ENABLE;
> > +	else
> > +		opregion->asle->vrsr &= ~ASLE_VRSR_ENABLE; }
> > diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h
> > b/drivers/gpu/drm/i915/display/intel_opregion.h
> > index 2f261f985400..73c9d81d5ee6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_opregion.h
> > +++ b/drivers/gpu/drm/i915/display/intel_opregion.h
> > @@ -75,6 +75,8 @@ int intel_opregion_notify_adapter(struct
> drm_i915_private *dev_priv,
> >  				  pci_power_t state);
> >  int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
> > struct edid *intel_opregion_get_edid(struct intel_connector
> > *connector);
> > +bool intel_opregion_bios_supports_vram_sr(struct drm_i915_private
> > +*i915); void intel_opregion_vram_sr(struct drm_i915_private *i915,
> > +bool enable);
> >
> >  bool intel_opregion_headless_sku(struct drm_i915_private *i915);
> >
> > @@ -134,6 +136,15 @@ static inline bool intel_opregion_headless_sku(struct
> drm_i915_private *i915)
> >  	return false;
> >  }
> >
> > +static bool intel_opregion_bios_supports_vram_sr(struct
> > +drm_i915_private *i915) {
> > +	return false;
> > +}
> > +
> > +static void intel_opregion_vram_sr(struct drm_i915_private *i915,
> > +bool enable) { }
> > +
> 
> Both of these stubs need to be static inline.
Thanks for I will fix all of above comment.
Regards,
Anshuman Gupta.
> 
> BR,
> Jani.
> 
> >  #endif /* CONFIG_ACPI */
> >
> >  #endif
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Andi Shyti]

Hi,

On Thu, Jun 16, 2022 at 05:31:05PM +0530, Anshuman Gupta wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
> 
> Cc: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c       | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f33290358c51..7a535f670ae1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
>  	GEM_BUG_ON(!HAS_REGION(i915, id));
>  	GEM_BUG_ON(i915->mm.regions[id]);
>  	i915->mm.regions[id] = mem;
> +	gt->lmem = mem;
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index df708802889d..cd7744eaaeaa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
>  #include "intel_gt_buffer_pool_types.h"
>  #include "intel_hwconfig.h"
>  #include "intel_llc_types.h"
> +#include "intel_memory_region.h"
>  #include "intel_reset_types.h"
>  #include "intel_rc6_types.h"
>  #include "intel_rps_types.h"
> @@ -202,6 +203,8 @@ struct intel_gt {
>  	 */
>  	phys_addr_t phys_addr;
>  
> +	struct intel_memory_region *lmem;
> +

this was somewhere in my next patch that is getting very
delayed... anyway, with Jani's include note:

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

>  	struct intel_gt_info {
>  		unsigned int id;
>  
> -- 
> 2.26.2

Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/xehpsdv: Store lmem region in gt

[Andi Shyti]

Hi,

On Thu, Jun 16, 2022 at 05:31:05PM +0530, Anshuman Gupta wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Store a pointer to respective local memory region in intel_gt so it can be
> used when memory local to a GT needs to be allocated.
> 
> Cc: Andi Shyti <andi.shyti@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c       | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f33290358c51..7a535f670ae1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -91,6 +91,7 @@ static int intel_gt_probe_lmem(struct intel_gt *gt)
>  	GEM_BUG_ON(!HAS_REGION(i915, id));
>  	GEM_BUG_ON(i915->mm.regions[id]);
>  	i915->mm.regions[id] = mem;
> +	gt->lmem = mem;
>  
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index df708802889d..cd7744eaaeaa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -23,6 +23,7 @@
>  #include "intel_gt_buffer_pool_types.h"
>  #include "intel_hwconfig.h"
>  #include "intel_llc_types.h"
> +#include "intel_memory_region.h"
>  #include "intel_reset_types.h"
>  #include "intel_rc6_types.h"
>  #include "intel_rps_types.h"
> @@ -202,6 +203,8 @@ struct intel_gt {
>  	 */
>  	phys_addr_t phys_addr;
>  
> +	struct intel_memory_region *lmem;
> +

this was somewhere in my next patch that is getting very
delayed... anyway, with Jani's include note:

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

>  	struct intel_gt_info {
>  		unsigned int id;
>  
> -- 
> 2.26.2

RE: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Gupta, Anshuman]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 16, 2022 7:58 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy
> 
> On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Add d3cold_sr_lmem_threshold modparam to choose between d3cold-off
> > zero watt and d3cold-VRAM Self Refresh.
> > i915 requires to evict the lmem objects to smem in order to support
> > d3cold-Off.
> >
> > If gfx root port is not capable of sending PME from d3cold then i915
> > don't need to program d3cold-off/d3cold-vram_sr sequence.
> >
> > FIXME: Eviction of lmem objects in case of D3Cold off is wip.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++---
> > drivers/gpu/drm/i915/i915_params.c |  4 ++++
> > drivers/gpu/drm/i915/i915_params.h |  3 ++-
> >  3 files changed, 30 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index fcff5f3fe05e..aef4b17efdbe 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device
> > *kdev)  static int intel_runtime_idle(struct device *kdev)  {
> >  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > +	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > +	u64 lmem_total = to_gt(dev_priv)->lmem->total;
> > +	u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
> > +	u64 lmem_used = lmem_total - lmem_avail;
> > +	struct pci_dev *root_pdev;
> >  	int ret = 1;
> >
> > -	if (!HAS_LMEM_SR(dev_priv)) {
> > -		/*TODO: Prepare for D3Cold-Off */
> > +	root_pdev = pcie_find_root_port(pdev);
> > +	if (!root_pdev)
> > +		goto out;
> > +
> > +	if (!pci_pme_capable(root_pdev, PCI_D3cold))
> >  		goto out;
> > -	}
> >
> >  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> >
> > +	if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 *
> 1024) {
> > +		drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n");
> > +		pci_d3cold_enable(root_pdev);
> > +		/* FIXME: Eviction of lmem objects and guc reset is wip */
> > +		intel_pm_vram_sr(dev_priv, false);
> > +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +		goto out;
> > +	} else if (!HAS_LMEM_SR(dev_priv)) {
> > +		/* Disable D3Cold to reduce the eviction latency */
> > +		pci_d3cold_disable(root_pdev);
> > +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +		goto out;
> > +	}
> 
> This is *way* too low level code for such high level function. This needs to be
> abstracted better.
> 
> > +
> >  	ret = intel_pm_vram_sr(dev_priv, true);
> >  	if (!ret)
> >  		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n"); diff
> --git
> > a/drivers/gpu/drm/i915/i915_params.c
> > b/drivers/gpu/drm/i915/i915_params.c
> > index 701fbc98afa0..6c6b3c372d4d 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
> >  	"Enable support for Intel GVT-g graphics virtualization host
> > support(default:false)");  #endif
> >
> > +i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
> > +	"Enable Vidoe RAM Self refresh when size of lmem is greater to this
> threshold. "
> > +	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
> > +
> >  #if CONFIG_DRM_I915_REQUEST_TIMEOUT
> >  i915_param_named_unsafe(request_timeout_ms, uint, 0600,
> >  			"Default request/fence/batch buffer expiration
> timeout."); diff
> > --git a/drivers/gpu/drm/i915/i915_params.h
> > b/drivers/gpu/drm/i915/i915_params.h
> > index b5e7ea45d191..28f20ebaf41f 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -83,7 +83,8 @@ struct drm_printer;
> >  	param(bool, verbose_state_checks, true, 0) \
> >  	param(bool, nuclear_pageflip, false, 0400) \
> >  	param(bool, enable_dp_mst, true, 0600) \
> > -	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ?
> 0400 : 0)
> > +	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ?
> 0400 : 0) \
> > +	param(int, d3cold_sr_lmem_threshold, 300, 0600) \
> 
> What's the point of the parameter?
We want a configurable option to choose an optimum lmem usages threshold on which, i915
can choose lmem self-refresh. This threshold value would require some profiling as well. 
That is the reason this threshold kept as module param.  
> 
> Also, please read the comment /* leave bools at the end to not create holes */
> above.
Thanks for review comment , I will re order the module param.
Regards ,
Anshuman Gupta.
> 
> 
> BR,
> Jani.
> 
> 
> >
> >  #define MEMBER(T, member, ...) T member;  struct i915_params {
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy

[Gupta, Anshuman]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Thursday, June 16, 2022 7:58 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>; intel-
> gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/rpm: d3cold Policy
> 
> On Thu, 16 Jun 2022, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Add d3cold_sr_lmem_threshold modparam to choose between d3cold-off
> > zero watt and d3cold-VRAM Self Refresh.
> > i915 requires to evict the lmem objects to smem in order to support
> > d3cold-Off.
> >
> > If gfx root port is not capable of sending PME from d3cold then i915
> > don't need to program d3cold-off/d3cold-vram_sr sequence.
> >
> > FIXME: Eviction of lmem objects in case of D3Cold off is wip.
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_driver.c | 27 ++++++++++++++++++++++++---
> > drivers/gpu/drm/i915/i915_params.c |  4 ++++
> > drivers/gpu/drm/i915/i915_params.h |  3 ++-
> >  3 files changed, 30 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> > b/drivers/gpu/drm/i915/i915_driver.c
> > index fcff5f3fe05e..aef4b17efdbe 100644
> > --- a/drivers/gpu/drm/i915/i915_driver.c
> > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > @@ -1560,15 +1560,36 @@ static int i915_pm_restore(struct device
> > *kdev)  static int intel_runtime_idle(struct device *kdev)  {
> >  	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> > +	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
> > +	u64 lmem_total = to_gt(dev_priv)->lmem->total;
> > +	u64 lmem_avail = to_gt(dev_priv)->lmem->avail;
> > +	u64 lmem_used = lmem_total - lmem_avail;
> > +	struct pci_dev *root_pdev;
> >  	int ret = 1;
> >
> > -	if (!HAS_LMEM_SR(dev_priv)) {
> > -		/*TODO: Prepare for D3Cold-Off */
> > +	root_pdev = pcie_find_root_port(pdev);
> > +	if (!root_pdev)
> > +		goto out;
> > +
> > +	if (!pci_pme_capable(root_pdev, PCI_D3cold))
> >  		goto out;
> > -	}
> >
> >  	disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> >
> > +	if (lmem_used < dev_priv->params.d3cold_sr_lmem_threshold  * 1024 *
> 1024) {
> > +		drm_dbg(&dev_priv->drm, "Prepare for D3Cold off\n");
> > +		pci_d3cold_enable(root_pdev);
> > +		/* FIXME: Eviction of lmem objects and guc reset is wip */
> > +		intel_pm_vram_sr(dev_priv, false);
> > +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +		goto out;
> > +	} else if (!HAS_LMEM_SR(dev_priv)) {
> > +		/* Disable D3Cold to reduce the eviction latency */
> > +		pci_d3cold_disable(root_pdev);
> > +		enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
> > +		goto out;
> > +	}
> 
> This is *way* too low level code for such high level function. This needs to be
> abstracted better.
> 
> > +
> >  	ret = intel_pm_vram_sr(dev_priv, true);
> >  	if (!ret)
> >  		drm_dbg(&dev_priv->drm, "VRAM Self Refresh enabled\n"); diff
> --git
> > a/drivers/gpu/drm/i915/i915_params.c
> > b/drivers/gpu/drm/i915/i915_params.c
> > index 701fbc98afa0..6c6b3c372d4d 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -197,6 +197,10 @@ i915_param_named(enable_gvt, bool, 0400,
> >  	"Enable support for Intel GVT-g graphics virtualization host
> > support(default:false)");  #endif
> >
> > +i915_param_named_unsafe(d3cold_sr_lmem_threshold, int, 0400,
> > +	"Enable Vidoe RAM Self refresh when size of lmem is greater to this
> threshold. "
> > +	"It helps to optimize the suspend/resume latecy. (default: 300mb)");
> > +
> >  #if CONFIG_DRM_I915_REQUEST_TIMEOUT
> >  i915_param_named_unsafe(request_timeout_ms, uint, 0600,
> >  			"Default request/fence/batch buffer expiration
> timeout."); diff
> > --git a/drivers/gpu/drm/i915/i915_params.h
> > b/drivers/gpu/drm/i915/i915_params.h
> > index b5e7ea45d191..28f20ebaf41f 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -83,7 +83,8 @@ struct drm_printer;
> >  	param(bool, verbose_state_checks, true, 0) \
> >  	param(bool, nuclear_pageflip, false, 0400) \
> >  	param(bool, enable_dp_mst, true, 0600) \
> > -	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ?
> 0400 : 0)
> > +	param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ?
> 0400 : 0) \
> > +	param(int, d3cold_sr_lmem_threshold, 300, 0600) \
> 
> What's the point of the parameter?
We want a configurable option to choose an optimum lmem usages threshold on which, i915
can choose lmem self-refresh. This threshold value would require some profiling as well. 
That is the reason this threshold kept as module param.  
> 
> Also, please read the comment /* leave bools at the end to not create holes */
> above.
Thanks for review comment , I will re order the module param.
Regards ,
Anshuman Gupta.
> 
> 
> BR,
> Jani.
> 
> 
> >
> >  #define MEMBER(T, member, ...) T member;  struct i915_params {
> 
> --
> Jani Nikula, Intel Open Source Graphics Center