* [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize
@ 2022-06-17 9:48 Jani Nikula
2022-06-17 9:48 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: convert modeset setup to struct drm_i915_private *i915 Jani Nikula
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Jani Nikula @ 2022-06-17 9:48 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Split out the modeset hardware state readout and sanitize, or state
setup, to a separate file.
Do some drive-by checkpatch fixes while at it.
v2: Rebase
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 739 +-----------------
drivers/gpu/drm/i915/display/intel_display.h | 12 +
.../drm/i915/display/intel_modeset_setup.c | 736 +++++++++++++++++
.../drm/i915/display/intel_modeset_setup.h | 15 +
5 files changed, 778 insertions(+), 725 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.c
create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 37a8ea56f7d6..c84a9cd8440d 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -244,6 +244,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
display/intel_modeset_verify.o \
+ display/intel_modeset_setup.o \
display/intel_overlay.o \
display/intel_pch_display.o \
display/intel_pch_refclk.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 90bd26431e31..710a51f14649 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -101,6 +101,7 @@
#include "intel_hdcp.h"
#include "intel_hotplug.h"
#include "intel_modeset_verify.h"
+#include "intel_modeset_setup.h"
#include "intel_overlay.h"
#include "intel_panel.h"
#include "intel_pch_display.h"
@@ -130,8 +131,6 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
-static void intel_modeset_setup_hw_state(struct drm_device *dev,
- struct drm_modeset_acquire_ctx *ctx);
/**
* intel_update_watermarks - update FIFO watermark values based on current modes
@@ -166,7 +165,7 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
* We don't use the sprite, so we can ignore that. And on Crestline we have
* to set the non-SR watermarks to 8.
*/
-static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
if (dev_priv->wm_disp->update_wm)
dev_priv->wm_disp->update_wm(dev_priv);
@@ -733,10 +732,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
DRM_MODE_ROTATE_0);
}
-static void
-intel_set_plane_visible(struct intel_crtc_state *crtc_state,
- struct intel_plane_state *plane_state,
- bool visible)
+void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state,
+ bool visible)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
@@ -748,7 +746,7 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
}
-static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
+void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct drm_plane *plane;
@@ -783,7 +781,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
crtc->base.base.id, crtc->base.name);
intel_set_plane_visible(crtc_state, plane_state, false);
- fixup_plane_bitmasks(crtc_state);
+ intel_plane_fixup_bitmasks(crtc_state);
crtc_state->data_rate[plane->id] = 0;
crtc_state->data_rate_y[plane->id] = 0;
crtc_state->rel_data_rate[plane->id] = 0;
@@ -2209,9 +2207,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
}
-static void
-modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
- struct intel_power_domain_mask *old_domains)
+void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+ struct intel_power_domain_mask *old_domains)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2235,8 +2232,8 @@ modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
domain);
}
-static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
- struct intel_power_domain_mask *domains)
+void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
+ struct intel_power_domain_mask *domains)
{
intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
&crtc->enabled_power_domains,
@@ -2416,89 +2413,6 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
i830_enable_pipe(dev_priv, pipe);
}
-static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
- struct drm_modeset_acquire_ctx *ctx)
-{
- struct intel_encoder *encoder;
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct intel_bw_state *bw_state =
- to_intel_bw_state(dev_priv->bw_obj.state);
- struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
- struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(dev_priv->dbuf.obj.state);
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
- struct intel_plane *plane;
- struct drm_atomic_state *state;
- struct intel_crtc_state *temp_crtc_state;
- enum pipe pipe = crtc->pipe;
- int ret;
-
- if (!crtc_state->hw.active)
- return;
-
- for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(plane->base.state);
-
- if (plane_state->uapi.visible)
- intel_plane_disable_noatomic(crtc, plane);
- }
-
- state = drm_atomic_state_alloc(&dev_priv->drm);
- if (!state) {
- drm_dbg_kms(&dev_priv->drm,
- "failed to disable [CRTC:%d:%s], out of memory",
- crtc->base.base.id, crtc->base.name);
- return;
- }
-
- state->acquire_ctx = ctx;
-
- /* Everything's already locked, -EDEADLK can't happen. */
- temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
- ret = drm_atomic_add_affected_connectors(state, &crtc->base);
-
- drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
-
- dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
-
- drm_atomic_state_put(state);
-
- drm_dbg_kms(&dev_priv->drm,
- "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
- crtc->base.base.id, crtc->base.name);
-
- crtc->active = false;
- crtc->base.enabled = false;
-
- drm_WARN_ON(&dev_priv->drm,
- drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
- crtc_state->uapi.active = false;
- crtc_state->uapi.connector_mask = 0;
- crtc_state->uapi.encoder_mask = 0;
- intel_crtc_free_hw_state(crtc_state);
- memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
-
- for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
- encoder->base.crtc = NULL;
-
- intel_fbc_disable(crtc);
- intel_update_watermarks(dev_priv);
- intel_disable_shared_dpll(crtc_state);
-
- intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
-
- cdclk_state->min_cdclk[pipe] = 0;
- cdclk_state->min_voltage_level[pipe] = 0;
- cdclk_state->active_pipes &= ~BIT(pipe);
-
- dbuf_state->active_pipes &= ~BIT(pipe);
-
- bw_state->data_rate[pipe] = 0;
- bw_state->num_active_planes[pipe] = 0;
-}
/*
* turn all crtc's off, but do not adjust state
@@ -4948,39 +4862,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
return 0;
}
-static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
-{
- struct intel_connector *connector;
- struct drm_connector_list_iter conn_iter;
-
- drm_connector_list_iter_begin(dev, &conn_iter);
- for_each_intel_connector_iter(connector, &conn_iter) {
- struct drm_connector_state *conn_state = connector->base.state;
- struct intel_encoder *encoder =
- to_intel_encoder(connector->base.encoder);
-
- if (conn_state->crtc)
- drm_connector_put(&connector->base);
-
- if (encoder) {
- struct intel_crtc *crtc =
- to_intel_crtc(encoder->base.crtc);
- const struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
-
- conn_state->best_encoder = &encoder->base;
- conn_state->crtc = &crtc->base;
- conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
-
- drm_connector_get(&connector->base);
- } else {
- conn_state->best_encoder = NULL;
- conn_state->crtc = NULL;
- }
- }
- drm_connector_list_iter_end(&conn_iter);
-}
-
static int
compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
struct intel_crtc_state *crtc_state)
@@ -5165,27 +5046,6 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
}
-static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
-{
- if (intel_crtc_is_bigjoiner_slave(crtc_state))
- return;
-
- crtc_state->uapi.enable = crtc_state->hw.enable;
- crtc_state->uapi.active = crtc_state->hw.active;
- drm_WARN_ON(crtc_state->uapi.crtc->dev,
- drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
-
- crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
- crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
-
- drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
- crtc_state->hw.degamma_lut);
- drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
- crtc_state->hw.gamma_lut);
- drm_property_replace_blob(&crtc_state->uapi.ctm,
- crtc_state->hw.ctm);
-}
-
static void
copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
struct intel_crtc *slave_crtc)
@@ -6115,8 +5975,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state)
return 0;
}
-static void
-intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
+void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -7670,7 +7529,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->update_pipe) {
- modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
+ intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
}
}
@@ -7770,7 +7629,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
- modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
+ intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
@@ -9060,576 +8919,6 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
intel_de_posting_read(dev_priv, DPLL(pipe));
}
-static void
-intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
-{
- struct intel_crtc *crtc;
-
- if (DISPLAY_VER(dev_priv) >= 4)
- return;
-
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_plane *plane =
- to_intel_plane(crtc->base.primary);
- struct intel_crtc *plane_crtc;
- enum pipe pipe;
-
- if (!plane->get_hw_state(plane, &pipe))
- continue;
-
- if (pipe == crtc->pipe)
- continue;
-
- drm_dbg_kms(&dev_priv->drm,
- "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
- plane->base.base.id, plane->base.name);
-
- plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
- intel_plane_disable_noatomic(plane_crtc, plane);
- }
-}
-
-static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
-{
- struct drm_device *dev = crtc->base.dev;
- struct intel_encoder *encoder;
-
- for_each_encoder_on_crtc(dev, &crtc->base, encoder)
- return true;
-
- return false;
-}
-
-static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
-{
- struct drm_device *dev = encoder->base.dev;
- struct intel_connector *connector;
-
- for_each_connector_on_encoder(dev, &encoder->base, connector)
- return connector;
-
- return NULL;
-}
-
-static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
-{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-
- if (!crtc_state->hw.active && !HAS_GMCH(i915))
- return;
-
- /*
- * We start out with underrun reporting disabled to avoid races.
- * For correct bookkeeping mark this on active crtcs.
- *
- * Also on gmch platforms we dont have any hardware bits to
- * disable the underrun reporting. Which means we need to start
- * out with underrun reporting disabled also on inactive pipes,
- * since otherwise we'll complain about the garbage we read when
- * e.g. coming up after runtime pm.
- *
- * No protection against concurrent access is required - at
- * worst a fifo underrun happens which also sets this to false.
- */
- crtc->cpu_fifo_underrun_disabled = true;
-
- /*
- * We track the PCH trancoder underrun reporting state
- * within the crtc. With crtc for pipe A housing the underrun
- * reporting state for PCH transcoder A, crtc for pipe B housing
- * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
- * and marking underrun reporting as disabled for the non-existing
- * PCH transcoders B and C would prevent enabling the south
- * error interrupt (see cpt_can_enable_serr_int()).
- */
- if (intel_has_pch_trancoder(i915, crtc->pipe))
- crtc->pch_fifo_underrun_disabled = true;
-}
-
-static void intel_sanitize_crtc(struct intel_crtc *crtc,
- struct drm_modeset_acquire_ctx *ctx)
-{
- struct drm_device *dev = crtc->base.dev;
- struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
-
- if (crtc_state->hw.active) {
- struct intel_plane *plane;
-
- /* Disable everything but the primary plane */
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(plane->base.state);
-
- if (plane_state->uapi.visible &&
- plane->base.type != DRM_PLANE_TYPE_PRIMARY)
- intel_plane_disable_noatomic(crtc, plane);
- }
-
- /* Disable any background color/etc. set by the BIOS */
- intel_color_commit_noarm(crtc_state);
- intel_color_commit_arm(crtc_state);
- }
-
- /* Adjust the state of the output pipe according to whether we
- * have active connectors/encoders. */
- if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
- !intel_crtc_is_bigjoiner_slave(crtc_state))
- intel_crtc_disable_noatomic(crtc, ctx);
-}
-
-static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
-{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-
- /*
- * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
- * the hardware when a high res displays plugged in. DPLL P
- * divider is zero, and the pipe timings are bonkers. We'll
- * try to disable everything in that case.
- *
- * FIXME would be nice to be able to sanitize this state
- * without several WARNs, but for now let's take the easy
- * road.
- */
- return IS_SANDYBRIDGE(dev_priv) &&
- crtc_state->hw.active &&
- crtc_state->shared_dpll &&
- crtc_state->port_clock == 0;
-}
-
-static void intel_sanitize_encoder(struct intel_encoder *encoder)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_connector *connector;
- struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
- struct intel_crtc_state *crtc_state = crtc ?
- to_intel_crtc_state(crtc->base.state) : NULL;
-
- /* We need to check both for a crtc link (meaning that the
- * encoder is active and trying to read from a pipe) and the
- * pipe itself being active. */
- bool has_active_crtc = crtc_state &&
- crtc_state->hw.active;
-
- if (crtc_state && has_bogus_dpll_config(crtc_state)) {
- drm_dbg_kms(&dev_priv->drm,
- "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
- pipe_name(crtc->pipe));
- has_active_crtc = false;
- }
-
- connector = intel_encoder_find_connector(encoder);
- if (connector && !has_active_crtc) {
- drm_dbg_kms(&dev_priv->drm,
- "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
- encoder->base.base.id,
- encoder->base.name);
-
- /* Connector is active, but has no active pipe. This is
- * fallout from our resume register restoring. Disable
- * the encoder manually again. */
- if (crtc_state) {
- struct drm_encoder *best_encoder;
-
- drm_dbg_kms(&dev_priv->drm,
- "[ENCODER:%d:%s] manually disabled\n",
- encoder->base.base.id,
- encoder->base.name);
-
- /* avoid oopsing in case the hooks consult best_encoder */
- best_encoder = connector->base.state->best_encoder;
- connector->base.state->best_encoder = &encoder->base;
-
- /* FIXME NULL atomic state passed! */
- if (encoder->disable)
- encoder->disable(NULL, encoder, crtc_state,
- connector->base.state);
- if (encoder->post_disable)
- encoder->post_disable(NULL, encoder, crtc_state,
- connector->base.state);
-
- connector->base.state->best_encoder = best_encoder;
- }
- encoder->base.crtc = NULL;
-
- /* Inconsistent output/port/pipe state happens presumably due to
- * a bug in one of the get_hw_state functions. Or someplace else
- * in our code, like the register restore mess on resume. Clamp
- * things to off as a safer default. */
-
- connector->base.dpms = DRM_MODE_DPMS_OFF;
- connector->base.encoder = NULL;
- }
-
- /* notify opregion of the sanitized encoder state */
- intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
-
- if (HAS_DDI(dev_priv))
- intel_ddi_sanitize_encoder_pll_mapping(encoder);
-}
-
-/* FIXME read out full plane state for all planes */
-static void readout_plane_state(struct drm_i915_private *dev_priv)
-{
- struct intel_plane *plane;
- struct intel_crtc *crtc;
-
- for_each_intel_plane(&dev_priv->drm, plane) {
- struct intel_plane_state *plane_state =
- to_intel_plane_state(plane->base.state);
- struct intel_crtc_state *crtc_state;
- enum pipe pipe = PIPE_A;
- bool visible;
-
- visible = plane->get_hw_state(plane, &pipe);
-
- crtc = intel_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
- intel_set_plane_visible(crtc_state, plane_state, visible);
-
- drm_dbg_kms(&dev_priv->drm,
- "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
- plane->base.base.id, plane->base.name,
- str_enabled_disabled(visible), pipe_name(pipe));
- }
-
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
-
- fixup_plane_bitmasks(crtc_state);
- }
-}
-
-static void intel_modeset_readout_hw_state(struct drm_device *dev)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
- struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(dev_priv->dbuf.obj.state);
- enum pipe pipe;
- struct intel_crtc *crtc;
- struct intel_encoder *encoder;
- struct intel_connector *connector;
- struct drm_connector_list_iter conn_iter;
- u8 active_pipes = 0;
-
- for_each_intel_crtc(dev, crtc) {
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
-
- __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
- intel_crtc_free_hw_state(crtc_state);
- intel_crtc_state_reset(crtc_state, crtc);
-
- intel_crtc_get_pipe_config(crtc_state);
-
- crtc_state->hw.enable = crtc_state->hw.active;
-
- crtc->base.enabled = crtc_state->hw.enable;
- crtc->active = crtc_state->hw.active;
-
- if (crtc_state->hw.active)
- active_pipes |= BIT(crtc->pipe);
-
- drm_dbg_kms(&dev_priv->drm,
- "[CRTC:%d:%s] hw state readout: %s\n",
- crtc->base.base.id, crtc->base.name,
- str_enabled_disabled(crtc_state->hw.active));
- }
-
- cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes;
-
- readout_plane_state(dev_priv);
-
- for_each_intel_encoder(dev, encoder) {
- struct intel_crtc_state *crtc_state = NULL;
-
- pipe = 0;
-
- if (encoder->get_hw_state(encoder, &pipe)) {
- crtc = intel_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
-
- encoder->base.crtc = &crtc->base;
- intel_encoder_get_config(encoder, crtc_state);
-
- /* read out to slave crtc as well for bigjoiner */
- if (crtc_state->bigjoiner_pipes) {
- struct intel_crtc *slave_crtc;
-
- /* encoder should read be linked to bigjoiner master */
- WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
-
- for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
- intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
- struct intel_crtc_state *slave_crtc_state;
-
- slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
- intel_encoder_get_config(encoder, slave_crtc_state);
- }
- }
- } else {
- encoder->base.crtc = NULL;
- }
-
- if (encoder->sync_state)
- encoder->sync_state(encoder, crtc_state);
-
- drm_dbg_kms(&dev_priv->drm,
- "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
- encoder->base.base.id, encoder->base.name,
- str_enabled_disabled(encoder->base.crtc),
- pipe_name(pipe));
- }
-
- intel_dpll_readout_hw_state(dev_priv);
-
- drm_connector_list_iter_begin(dev, &conn_iter);
- for_each_intel_connector_iter(connector, &conn_iter) {
- if (connector->get_hw_state(connector)) {
- struct intel_crtc_state *crtc_state;
- struct intel_crtc *crtc;
-
- connector->base.dpms = DRM_MODE_DPMS_ON;
-
- encoder = intel_attached_encoder(connector);
- connector->base.encoder = &encoder->base;
-
- crtc = to_intel_crtc(encoder->base.crtc);
- crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
-
- if (crtc_state && crtc_state->hw.active) {
- /*
- * This has to be done during hardware readout
- * because anything calling .crtc_disable may
- * rely on the connector_mask being accurate.
- */
- crtc_state->uapi.connector_mask |=
- drm_connector_mask(&connector->base);
- crtc_state->uapi.encoder_mask |=
- drm_encoder_mask(&encoder->base);
- }
- } else {
- connector->base.dpms = DRM_MODE_DPMS_OFF;
- connector->base.encoder = NULL;
- }
- drm_dbg_kms(&dev_priv->drm,
- "[CONNECTOR:%d:%s] hw state readout: %s\n",
- connector->base.base.id, connector->base.name,
- str_enabled_disabled(connector->base.encoder));
- }
- drm_connector_list_iter_end(&conn_iter);
-
- for_each_intel_crtc(dev, crtc) {
- struct intel_bw_state *bw_state =
- to_intel_bw_state(dev_priv->bw_obj.state);
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
- struct intel_plane *plane;
- int min_cdclk = 0;
-
- if (crtc_state->hw.active) {
- /*
- * The initial mode needs to be set in order to keep
- * the atomic core happy. It wants a valid mode if the
- * crtc's enabled, so we do the above call.
- *
- * But we don't set all the derived state fully, hence
- * set a flag to indicate that a full recalculation is
- * needed on the next commit.
- */
- crtc_state->inherited = true;
-
- intel_crtc_update_active_timings(crtc_state);
-
- intel_crtc_copy_hw_to_uapi_state(crtc_state);
- }
-
- for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
- const struct intel_plane_state *plane_state =
- to_intel_plane_state(plane->base.state);
-
- /*
- * FIXME don't have the fb yet, so can't
- * use intel_plane_data_rate() :(
- */
- if (plane_state->uapi.visible)
- crtc_state->data_rate[plane->id] =
- 4 * crtc_state->pixel_rate;
- /*
- * FIXME don't have the fb yet, so can't
- * use plane->min_cdclk() :(
- */
- if (plane_state->uapi.visible && plane->min_cdclk) {
- if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
- crtc_state->min_cdclk[plane->id] =
- DIV_ROUND_UP(crtc_state->pixel_rate, 2);
- else
- crtc_state->min_cdclk[plane->id] =
- crtc_state->pixel_rate;
- }
- drm_dbg_kms(&dev_priv->drm,
- "[PLANE:%d:%s] min_cdclk %d kHz\n",
- plane->base.base.id, plane->base.name,
- crtc_state->min_cdclk[plane->id]);
- }
-
- if (crtc_state->hw.active) {
- min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
- if (drm_WARN_ON(dev, min_cdclk < 0))
- min_cdclk = 0;
- }
-
- cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
- cdclk_state->min_voltage_level[crtc->pipe] =
- crtc_state->min_voltage_level;
-
- intel_bw_crtc_update(bw_state, crtc_state);
- }
-}
-
-static void
-get_encoder_power_domains(struct drm_i915_private *dev_priv)
-{
- struct intel_encoder *encoder;
-
- for_each_intel_encoder(&dev_priv->drm, encoder) {
- struct intel_crtc_state *crtc_state;
-
- if (!encoder->get_power_domains)
- continue;
-
- /*
- * MST-primary and inactive encoders don't have a crtc state
- * and neither of these require any power domain references.
- */
- if (!encoder->base.crtc)
- continue;
-
- crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
- encoder->get_power_domains(encoder, crtc_state);
- }
-}
-
-static void intel_early_display_was(struct drm_i915_private *dev_priv)
-{
- /*
- * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
- * Also known as Wa_14010480278.
- */
- if (IS_DISPLAY_VER(dev_priv, 10, 12))
- intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
- intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
-
- if (IS_HASWELL(dev_priv)) {
- /*
- * WaRsPkgCStateDisplayPMReq:hsw
- * System hang if this isn't done before disabling all planes!
- */
- intel_de_write(dev_priv, CHICKEN_PAR1_1,
- intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
- }
-
- if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
- /* Display WA #1142:kbl,cfl,cml */
- intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
- KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
- intel_de_rmw(dev_priv, CHICKEN_MISC_2,
- KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
- KBL_ARB_FILL_SPARE_14);
- }
-}
-
-
-/* Scan out the current hw modeset state,
- * and sanitizes it to the current state
- */
-static void
-intel_modeset_setup_hw_state(struct drm_device *dev,
- struct drm_modeset_acquire_ctx *ctx)
-{
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_encoder *encoder;
- struct intel_crtc *crtc;
- intel_wakeref_t wakeref;
-
- wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
-
- intel_early_display_was(dev_priv);
- intel_modeset_readout_hw_state(dev);
-
- /* HW state is read out, now we need to sanitize this mess. */
- get_encoder_power_domains(dev_priv);
-
- intel_pch_sanitize(dev_priv);
-
- /*
- * intel_sanitize_plane_mapping() may need to do vblank
- * waits, so we need vblank interrupts restored beforehand.
- */
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
-
- intel_sanitize_fifo_underrun_reporting(crtc_state);
-
- drm_crtc_vblank_reset(&crtc->base);
-
- if (crtc_state->hw.active)
- intel_crtc_vblank_on(crtc_state);
- }
-
- intel_fbc_sanitize(dev_priv);
-
- intel_sanitize_plane_mapping(dev_priv);
-
- for_each_intel_encoder(dev, encoder)
- intel_sanitize_encoder(encoder);
-
- for_each_intel_crtc(&dev_priv->drm, crtc) {
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
-
- intel_sanitize_crtc(crtc, ctx);
- intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
- }
-
- intel_modeset_update_connector_atomic_state(dev);
-
- intel_dpll_sanitize_state(dev_priv);
-
- if (IS_G4X(dev_priv)) {
- g4x_wm_get_hw_state(dev_priv);
- g4x_wm_sanitize(dev_priv);
- } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_wm_get_hw_state(dev_priv);
- vlv_wm_sanitize(dev_priv);
- } else if (DISPLAY_VER(dev_priv) >= 9) {
- skl_wm_get_hw_state(dev_priv);
- skl_wm_sanitize(dev_priv);
- } else if (HAS_PCH_SPLIT(dev_priv)) {
- ilk_wm_get_hw_state(dev_priv);
- }
-
- for_each_intel_crtc(dev, crtc) {
- struct intel_crtc_state *crtc_state =
- to_intel_crtc_state(crtc->base.state);
- struct intel_power_domain_mask put_domains;
-
- modeset_get_crtc_power_domains(crtc_state, &put_domains);
- if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
- modeset_put_crtc_power_domains(crtc, &put_domains);
- }
-
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
-
- intel_power_domains_sanitize_state(dev_priv);
-}
-
void intel_display_resume(struct drm_device *dev)
{
struct drm_i915_private *i915 = to_i915(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 2feb8ae5d5d4..8610e17cc593 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -56,6 +56,7 @@ struct intel_initial_plane_config;
struct intel_load_detect_pipe;
struct intel_plane;
struct intel_plane_state;
+struct intel_power_domain_mask;
struct intel_remapped_info;
struct intel_rotation_info;
struct pci_dev;
@@ -563,6 +564,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
const struct intel_crtc_state *pipe_config,
bool fastset);
+void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
void intel_plane_destroy(struct drm_plane *plane);
void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
@@ -659,10 +661,16 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state);
void intel_plane_disable_noatomic(struct intel_crtc *crtc,
struct intel_plane *plane);
+void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state,
+ bool visible);
+void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
void intel_display_driver_register(struct drm_i915_private *i915);
void intel_display_driver_unregister(struct drm_i915_private *i915);
+void intel_update_watermarks(struct drm_i915_private *i915);
+
/* modesetting */
bool intel_modeset_probe_defer(struct pci_dev *pdev);
void intel_modeset_init_hw(struct drm_i915_private *i915);
@@ -674,6 +682,10 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
void intel_display_resume(struct drm_device *dev);
int intel_modeset_all_pipes(struct intel_atomic_state *state);
+void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+ struct intel_power_domain_mask *old_domains);
+void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
+ struct intel_power_domain_mask *domains);
/* modesetting asserts */
void assert_transcoder(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
new file mode 100644
index 000000000000..c340f3393246
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * Read out the current hardware modeset state, and sanitize it to the current
+ * state.
+ */
+
+#include <drm/drm_atomic_uapi.h>
+#include <drm/drm_atomic_state_helper.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_bw.h"
+#include "intel_color.h"
+#include "intel_crtc.h"
+#include "intel_crtc_state_dump.h"
+#include "intel_ddi.h"
+#include "intel_de.h"
+#include "intel_display.h"
+#include "intel_display_power.h"
+#include "intel_display_types.h"
+#include "intel_modeset_setup.h"
+#include "intel_pch_display.h"
+#include "intel_pm.h"
+
+static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
+ struct drm_modeset_acquire_ctx *ctx)
+{
+ struct intel_encoder *encoder;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_bw_state *bw_state =
+ to_intel_bw_state(dev_priv->bw_obj.state);
+ struct intel_cdclk_state *cdclk_state =
+ to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ struct intel_dbuf_state *dbuf_state =
+ to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+ struct intel_plane *plane;
+ struct drm_atomic_state *state;
+ struct intel_crtc_state *temp_crtc_state;
+ enum pipe pipe = crtc->pipe;
+ int ret;
+
+ if (!crtc_state->hw.active)
+ return;
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ if (plane_state->uapi.visible)
+ intel_plane_disable_noatomic(crtc, plane);
+ }
+
+ state = drm_atomic_state_alloc(&dev_priv->drm);
+ if (!state) {
+ drm_dbg_kms(&dev_priv->drm,
+ "failed to disable [CRTC:%d:%s], out of memory",
+ crtc->base.base.id, crtc->base.name);
+ return;
+ }
+
+ state->acquire_ctx = ctx;
+
+ /* Everything's already locked, -EDEADLK can't happen. */
+ temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
+ ret = drm_atomic_add_affected_connectors(state, &crtc->base);
+
+ drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
+
+ dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
+
+ drm_atomic_state_put(state);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
+ crtc->base.base.id, crtc->base.name);
+
+ crtc->active = false;
+ crtc->base.enabled = false;
+
+ drm_WARN_ON(&dev_priv->drm,
+ drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
+ crtc_state->uapi.active = false;
+ crtc_state->uapi.connector_mask = 0;
+ crtc_state->uapi.encoder_mask = 0;
+ intel_crtc_free_hw_state(crtc_state);
+ memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
+
+ for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
+ encoder->base.crtc = NULL;
+
+ intel_fbc_disable(crtc);
+ intel_update_watermarks(dev_priv);
+ intel_disable_shared_dpll(crtc_state);
+
+ intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
+
+ cdclk_state->min_cdclk[pipe] = 0;
+ cdclk_state->min_voltage_level[pipe] = 0;
+ cdclk_state->active_pipes &= ~BIT(pipe);
+
+ dbuf_state->active_pipes &= ~BIT(pipe);
+
+ bw_state->data_rate[pipe] = 0;
+ bw_state->num_active_planes[pipe] = 0;
+}
+
+static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
+{
+ struct intel_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ struct drm_connector_state *conn_state = connector->base.state;
+ struct intel_encoder *encoder =
+ to_intel_encoder(connector->base.encoder);
+
+ if (conn_state->crtc)
+ drm_connector_put(&connector->base);
+
+ if (encoder) {
+ struct intel_crtc *crtc =
+ to_intel_crtc(encoder->base.crtc);
+ const struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ conn_state->best_encoder = &encoder->base;
+ conn_state->crtc = &crtc->base;
+ conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
+
+ drm_connector_get(&connector->base);
+ } else {
+ conn_state->best_encoder = NULL;
+ conn_state->crtc = NULL;
+ }
+ }
+ drm_connector_list_iter_end(&conn_iter);
+}
+
+static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
+{
+ if (intel_crtc_is_bigjoiner_slave(crtc_state))
+ return;
+
+ crtc_state->uapi.enable = crtc_state->hw.enable;
+ crtc_state->uapi.active = crtc_state->hw.active;
+ drm_WARN_ON(crtc_state->uapi.crtc->dev,
+ drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
+
+ crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
+ crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
+
+ drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
+ crtc_state->hw.degamma_lut);
+ drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
+ crtc_state->hw.gamma_lut);
+ drm_property_replace_blob(&crtc_state->uapi.ctm,
+ crtc_state->hw.ctm);
+}
+
+static void
+intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+{
+ struct intel_crtc *crtc;
+
+ if (DISPLAY_VER(dev_priv) >= 4)
+ return;
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_plane *plane =
+ to_intel_plane(crtc->base.primary);
+ struct intel_crtc *plane_crtc;
+ enum pipe pipe;
+
+ if (!plane->get_hw_state(plane, &pipe))
+ continue;
+
+ if (pipe == crtc->pipe)
+ continue;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
+ plane->base.base.id, plane->base.name);
+
+ plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ intel_plane_disable_noatomic(plane_crtc, plane);
+ }
+}
+
+static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct intel_encoder *encoder;
+
+ for_each_encoder_on_crtc(dev, &crtc->base, encoder)
+ return true;
+
+ return false;
+}
+
+static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder->base.dev;
+ struct intel_connector *connector;
+
+ for_each_connector_on_encoder(dev, &encoder->base, connector)
+ return connector;
+
+ return NULL;
+}
+
+static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+
+ if (!crtc_state->hw.active && !HAS_GMCH(i915))
+ return;
+
+ /*
+ * We start out with underrun reporting disabled to avoid races.
+ * For correct bookkeeping mark this on active crtcs.
+ *
+ * Also on gmch platforms we dont have any hardware bits to
+ * disable the underrun reporting. Which means we need to start
+ * out with underrun reporting disabled also on inactive pipes,
+ * since otherwise we'll complain about the garbage we read when
+ * e.g. coming up after runtime pm.
+ *
+ * No protection against concurrent access is required - at
+ * worst a fifo underrun happens which also sets this to false.
+ */
+ crtc->cpu_fifo_underrun_disabled = true;
+
+ /*
+ * We track the PCH trancoder underrun reporting state
+ * within the crtc. With crtc for pipe A housing the underrun
+ * reporting state for PCH transcoder A, crtc for pipe B housing
+ * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
+ * and marking underrun reporting as disabled for the non-existing
+ * PCH transcoders B and C would prevent enabling the south
+ * error interrupt (see cpt_can_enable_serr_int()).
+ */
+ if (intel_has_pch_trancoder(i915, crtc->pipe))
+ crtc->pch_fifo_underrun_disabled = true;
+}
+
+static void intel_sanitize_crtc(struct intel_crtc *crtc,
+ struct drm_modeset_acquire_ctx *ctx)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+
+ if (crtc_state->hw.active) {
+ struct intel_plane *plane;
+
+ /* Disable everything but the primary plane */
+ for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ if (plane_state->uapi.visible &&
+ plane->base.type != DRM_PLANE_TYPE_PRIMARY)
+ intel_plane_disable_noatomic(crtc, plane);
+ }
+
+ /* Disable any background color/etc. set by the BIOS */
+ intel_color_commit_noarm(crtc_state);
+ intel_color_commit_arm(crtc_state);
+ }
+
+ /*
+ * Adjust the state of the output pipe according to whether we have
+ * active connectors/encoders.
+ */
+ if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
+ !intel_crtc_is_bigjoiner_slave(crtc_state))
+ intel_crtc_disable_noatomic(crtc, ctx);
+}
+
+static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+
+ /*
+ * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
+ * the hardware when a high res displays plugged in. DPLL P
+ * divider is zero, and the pipe timings are bonkers. We'll
+ * try to disable everything in that case.
+ *
+ * FIXME would be nice to be able to sanitize this state
+ * without several WARNs, but for now let's take the easy
+ * road.
+ */
+ return IS_SANDYBRIDGE(dev_priv) &&
+ crtc_state->hw.active &&
+ crtc_state->shared_dpll &&
+ crtc_state->port_clock == 0;
+}
+
+static void intel_sanitize_encoder(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_connector *connector;
+ struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_crtc_state *crtc_state = crtc ?
+ to_intel_crtc_state(crtc->base.state) : NULL;
+
+ /*
+ * We need to check both for a crtc link (meaning that the encoder is
+ * active and trying to read from a pipe) and the pipe itself being
+ * active.
+ */
+ bool has_active_crtc = crtc_state &&
+ crtc_state->hw.active;
+
+ if (crtc_state && has_bogus_dpll_config(crtc_state)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
+ pipe_name(crtc->pipe));
+ has_active_crtc = false;
+ }
+
+ connector = intel_encoder_find_connector(encoder);
+ if (connector && !has_active_crtc) {
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
+ encoder->base.base.id,
+ encoder->base.name);
+
+ /*
+ * Connector is active, but has no active pipe. This is fallout
+ * from our resume register restoring. Disable the encoder
+ * manually again.
+ */
+ if (crtc_state) {
+ struct drm_encoder *best_encoder;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] manually disabled\n",
+ encoder->base.base.id,
+ encoder->base.name);
+
+ /* avoid oopsing in case the hooks consult best_encoder */
+ best_encoder = connector->base.state->best_encoder;
+ connector->base.state->best_encoder = &encoder->base;
+
+ /* FIXME NULL atomic state passed! */
+ if (encoder->disable)
+ encoder->disable(NULL, encoder, crtc_state,
+ connector->base.state);
+ if (encoder->post_disable)
+ encoder->post_disable(NULL, encoder, crtc_state,
+ connector->base.state);
+
+ connector->base.state->best_encoder = best_encoder;
+ }
+ encoder->base.crtc = NULL;
+
+ /*
+ * Inconsistent output/port/pipe state happens presumably due to
+ * a bug in one of the get_hw_state functions. Or someplace else
+ * in our code, like the register restore mess on resume. Clamp
+ * things to off as a safer default.
+ */
+ connector->base.dpms = DRM_MODE_DPMS_OFF;
+ connector->base.encoder = NULL;
+ }
+
+ /* notify opregion of the sanitized encoder state */
+ intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
+
+ if (HAS_DDI(dev_priv))
+ intel_ddi_sanitize_encoder_pll_mapping(encoder);
+}
+
+/* FIXME read out full plane state for all planes */
+static void readout_plane_state(struct drm_i915_private *dev_priv)
+{
+ struct intel_plane *plane;
+ struct intel_crtc *crtc;
+
+ for_each_intel_plane(&dev_priv->drm, plane) {
+ struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+ struct intel_crtc_state *crtc_state;
+ enum pipe pipe = PIPE_A;
+ bool visible;
+
+ visible = plane->get_hw_state(plane, &pipe);
+
+ crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
+ intel_set_plane_visible(crtc_state, plane_state, visible);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
+ plane->base.base.id, plane->base.name,
+ str_enabled_disabled(visible), pipe_name(pipe));
+ }
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ intel_plane_fixup_bitmasks(crtc_state);
+ }
+}
+
+static void intel_modeset_readout_hw_state(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_cdclk_state *cdclk_state =
+ to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ struct intel_dbuf_state *dbuf_state =
+ to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+ enum pipe pipe;
+ struct intel_crtc *crtc;
+ struct intel_encoder *encoder;
+ struct intel_connector *connector;
+ struct drm_connector_list_iter conn_iter;
+ u8 active_pipes = 0;
+
+ for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
+ intel_crtc_free_hw_state(crtc_state);
+ intel_crtc_state_reset(crtc_state, crtc);
+
+ intel_crtc_get_pipe_config(crtc_state);
+
+ crtc_state->hw.enable = crtc_state->hw.active;
+
+ crtc->base.enabled = crtc_state->hw.enable;
+ crtc->active = crtc_state->hw.active;
+
+ if (crtc_state->hw.active)
+ active_pipes |= BIT(crtc->pipe);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[CRTC:%d:%s] hw state readout: %s\n",
+ crtc->base.base.id, crtc->base.name,
+ str_enabled_disabled(crtc_state->hw.active));
+ }
+
+ cdclk_state->active_pipes = active_pipes;
+ dbuf_state->active_pipes = active_pipes;
+
+ readout_plane_state(dev_priv);
+
+ for_each_intel_encoder(dev, encoder) {
+ struct intel_crtc_state *crtc_state = NULL;
+
+ pipe = 0;
+
+ if (encoder->get_hw_state(encoder, &pipe)) {
+ crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
+ encoder->base.crtc = &crtc->base;
+ intel_encoder_get_config(encoder, crtc_state);
+
+ /* read out to slave crtc as well for bigjoiner */
+ if (crtc_state->bigjoiner_pipes) {
+ struct intel_crtc *slave_crtc;
+
+ /* encoder should read be linked to bigjoiner master */
+ WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
+
+ for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
+ intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
+ struct intel_crtc_state *slave_crtc_state;
+
+ slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
+ intel_encoder_get_config(encoder, slave_crtc_state);
+ }
+ }
+ } else {
+ encoder->base.crtc = NULL;
+ }
+
+ if (encoder->sync_state)
+ encoder->sync_state(encoder, crtc_state);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
+ encoder->base.base.id, encoder->base.name,
+ str_enabled_disabled(encoder->base.crtc),
+ pipe_name(pipe));
+ }
+
+ intel_dpll_readout_hw_state(dev_priv);
+
+ drm_connector_list_iter_begin(dev, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (connector->get_hw_state(connector)) {
+ struct intel_crtc_state *crtc_state;
+ struct intel_crtc *crtc;
+
+ connector->base.dpms = DRM_MODE_DPMS_ON;
+
+ encoder = intel_attached_encoder(connector);
+ connector->base.encoder = &encoder->base;
+
+ crtc = to_intel_crtc(encoder->base.crtc);
+ crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
+
+ if (crtc_state && crtc_state->hw.active) {
+ /*
+ * This has to be done during hardware readout
+ * because anything calling .crtc_disable may
+ * rely on the connector_mask being accurate.
+ */
+ crtc_state->uapi.connector_mask |=
+ drm_connector_mask(&connector->base);
+ crtc_state->uapi.encoder_mask |=
+ drm_encoder_mask(&encoder->base);
+ }
+ } else {
+ connector->base.dpms = DRM_MODE_DPMS_OFF;
+ connector->base.encoder = NULL;
+ }
+ drm_dbg_kms(&dev_priv->drm,
+ "[CONNECTOR:%d:%s] hw state readout: %s\n",
+ connector->base.base.id, connector->base.name,
+ str_enabled_disabled(connector->base.encoder));
+ }
+ drm_connector_list_iter_end(&conn_iter);
+
+ for_each_intel_crtc(dev, crtc) {
+ struct intel_bw_state *bw_state =
+ to_intel_bw_state(dev_priv->bw_obj.state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+ struct intel_plane *plane;
+ int min_cdclk = 0;
+
+ if (crtc_state->hw.active) {
+ /*
+ * The initial mode needs to be set in order to keep
+ * the atomic core happy. It wants a valid mode if the
+ * crtc's enabled, so we do the above call.
+ *
+ * But we don't set all the derived state fully, hence
+ * set a flag to indicate that a full recalculation is
+ * needed on the next commit.
+ */
+ crtc_state->inherited = true;
+
+ intel_crtc_update_active_timings(crtc_state);
+
+ intel_crtc_copy_hw_to_uapi_state(crtc_state);
+ }
+
+ for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ const struct intel_plane_state *plane_state =
+ to_intel_plane_state(plane->base.state);
+
+ /*
+ * FIXME don't have the fb yet, so can't
+ * use intel_plane_data_rate() :(
+ */
+ if (plane_state->uapi.visible)
+ crtc_state->data_rate[plane->id] =
+ 4 * crtc_state->pixel_rate;
+ /*
+ * FIXME don't have the fb yet, so can't
+ * use plane->min_cdclk() :(
+ */
+ if (plane_state->uapi.visible && plane->min_cdclk) {
+ if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
+ crtc_state->min_cdclk[plane->id] =
+ DIV_ROUND_UP(crtc_state->pixel_rate, 2);
+ else
+ crtc_state->min_cdclk[plane->id] =
+ crtc_state->pixel_rate;
+ }
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] min_cdclk %d kHz\n",
+ plane->base.base.id, plane->base.name,
+ crtc_state->min_cdclk[plane->id]);
+ }
+
+ if (crtc_state->hw.active) {
+ min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
+ if (drm_WARN_ON(dev, min_cdclk < 0))
+ min_cdclk = 0;
+ }
+
+ cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
+ cdclk_state->min_voltage_level[crtc->pipe] =
+ crtc_state->min_voltage_level;
+
+ intel_bw_crtc_update(bw_state, crtc_state);
+ }
+}
+
+static void
+get_encoder_power_domains(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
+ struct intel_crtc_state *crtc_state;
+
+ if (!encoder->get_power_domains)
+ continue;
+
+ /*
+ * MST-primary and inactive encoders don't have a crtc state
+ * and neither of these require any power domain references.
+ */
+ if (!encoder->base.crtc)
+ continue;
+
+ crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
+ encoder->get_power_domains(encoder, crtc_state);
+ }
+}
+
+static void intel_early_display_was(struct drm_i915_private *dev_priv)
+{
+ /*
+ * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
+ * Also known as Wa_14010480278.
+ */
+ if (IS_DISPLAY_VER(dev_priv, 10, 12))
+ intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
+ intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
+
+ if (IS_HASWELL(dev_priv)) {
+ /*
+ * WaRsPkgCStateDisplayPMReq:hsw
+ * System hang if this isn't done before disabling all planes!
+ */
+ intel_de_write(dev_priv, CHICKEN_PAR1_1,
+ intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+ }
+
+ if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
+ /* Display WA #1142:kbl,cfl,cml */
+ intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+ KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
+ intel_de_rmw(dev_priv, CHICKEN_MISC_2,
+ KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
+ KBL_ARB_FILL_SPARE_14);
+ }
+}
+
+void intel_modeset_setup_hw_state(struct drm_device *dev,
+ struct drm_modeset_acquire_ctx *ctx)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_encoder *encoder;
+ struct intel_crtc *crtc;
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+
+ intel_early_display_was(dev_priv);
+ intel_modeset_readout_hw_state(dev);
+
+ /* HW state is read out, now we need to sanitize this mess. */
+ get_encoder_power_domains(dev_priv);
+
+ intel_pch_sanitize(dev_priv);
+
+ /*
+ * intel_sanitize_plane_mapping() may need to do vblank
+ * waits, so we need vblank interrupts restored beforehand.
+ */
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ intel_sanitize_fifo_underrun_reporting(crtc_state);
+
+ drm_crtc_vblank_reset(&crtc->base);
+
+ if (crtc_state->hw.active)
+ intel_crtc_vblank_on(crtc_state);
+ }
+
+ intel_fbc_sanitize(dev_priv);
+
+ intel_sanitize_plane_mapping(dev_priv);
+
+ for_each_intel_encoder(dev, encoder)
+ intel_sanitize_encoder(encoder);
+
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+
+ intel_sanitize_crtc(crtc, ctx);
+ intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
+ }
+
+ intel_modeset_update_connector_atomic_state(dev);
+
+ intel_dpll_sanitize_state(dev_priv);
+
+ if (IS_G4X(dev_priv)) {
+ g4x_wm_get_hw_state(dev_priv);
+ g4x_wm_sanitize(dev_priv);
+ } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ vlv_wm_get_hw_state(dev_priv);
+ vlv_wm_sanitize(dev_priv);
+ } else if (DISPLAY_VER(dev_priv) >= 9) {
+ skl_wm_get_hw_state(dev_priv);
+ skl_wm_sanitize(dev_priv);
+ } else if (HAS_PCH_SPLIT(dev_priv)) {
+ ilk_wm_get_hw_state(dev_priv);
+ }
+
+ for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
+ struct intel_power_domain_mask put_domains;
+
+ intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
+ if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
+ intel_modeset_put_crtc_power_domains(crtc, &put_domains);
+ }
+
+ intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
+
+ intel_power_domains_sanitize_state(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.h b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
new file mode 100644
index 000000000000..c29b34c6a7b0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_MODESET_SETUP_H__
+#define __INTEL_MODESET_SETUP_H__
+
+struct drm_device;
+struct drm_modeset_acquire_ctx;
+
+void intel_modeset_setup_hw_state(struct drm_device *dev,
+ struct drm_modeset_acquire_ctx *ctx);
+
+#endif /* __INTEL_MODESET_SETUP_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/display: convert modeset setup to struct drm_i915_private *i915
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
@ 2022-06-17 9:48 ` Jani Nikula
2022-06-17 13:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize Patchwork
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2022-06-17 9:48 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Pass struct drm_i915_private * instead of struct drm_device *, and
rename dev_priv to i915.
v2: Rebase
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 194 +++++++++---------
.../drm/i915/display/intel_modeset_setup.h | 4 +-
3 files changed, 100 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 710a51f14649..903226e2a626 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -838,7 +838,7 @@ __intel_display_resume(struct drm_i915_private *i915,
struct drm_crtc *crtc;
int i, ret;
- intel_modeset_setup_hw_state(&i915->drm, ctx);
+ intel_modeset_setup_hw_state(i915, ctx);
intel_vga_redisable(i915);
if (!state)
@@ -8766,7 +8766,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_setup_outputs(i915);
drm_modeset_lock_all(dev);
- intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx);
+ intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
intel_acpi_assign_connector_fwnodes(i915);
drm_modeset_unlock_all(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index c340f3393246..f0e04d3904c6 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -28,13 +28,13 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct drm_modeset_acquire_ctx *ctx)
{
struct intel_encoder *encoder;
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_bw_state *bw_state =
- to_intel_bw_state(dev_priv->bw_obj.state);
+ to_intel_bw_state(i915->bw_obj.state);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ to_intel_cdclk_state(i915->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+ to_intel_dbuf_state(i915->dbuf.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -46,7 +46,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
if (!crtc_state->hw.active)
return;
- for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
const struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
@@ -54,9 +54,9 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
intel_plane_disable_noatomic(crtc, plane);
}
- state = drm_atomic_state_alloc(&dev_priv->drm);
+ state = drm_atomic_state_alloc(&i915->drm);
if (!state) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"failed to disable [CRTC:%d:%s], out of memory",
crtc->base.base.id, crtc->base.name);
return;
@@ -68,20 +68,20 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
ret = drm_atomic_add_affected_connectors(state, &crtc->base);
- drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
+ drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
+ i915->display->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
crtc->base.base.id, crtc->base.name);
crtc->active = false;
crtc->base.enabled = false;
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(&i915->drm,
drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
crtc_state->uapi.active = false;
crtc_state->uapi.connector_mask = 0;
@@ -89,14 +89,14 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
intel_crtc_free_hw_state(crtc_state);
memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
- for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
+ for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder)
encoder->base.crtc = NULL;
intel_fbc_disable(crtc);
- intel_update_watermarks(dev_priv);
+ intel_update_watermarks(i915);
intel_disable_shared_dpll(crtc_state);
- intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
+ intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
cdclk_state->min_cdclk[pipe] = 0;
cdclk_state->min_voltage_level[pipe] = 0;
@@ -108,12 +108,12 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
bw_state->num_active_planes[pipe] = 0;
}
-static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
+static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
{
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
- drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
struct drm_connector_state *conn_state = connector->base.state;
struct intel_encoder *encoder =
@@ -163,14 +163,14 @@ static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state
}
static void
-intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
+intel_sanitize_plane_mapping(struct drm_i915_private *i915)
{
struct intel_crtc *crtc;
- if (DISPLAY_VER(dev_priv) >= 4)
+ if (DISPLAY_VER(i915) >= 4)
return;
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_plane *plane =
to_intel_plane(crtc->base.primary);
struct intel_crtc *plane_crtc;
@@ -182,11 +182,11 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
if (pipe == crtc->pipe)
continue;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
plane->base.base.id, plane->base.name);
- plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ plane_crtc = intel_crtc_for_pipe(i915, pipe);
intel_plane_disable_noatomic(plane_crtc, plane);
}
}
@@ -252,14 +252,14 @@ static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state
static void intel_sanitize_crtc(struct intel_crtc *crtc,
struct drm_modeset_acquire_ctx *ctx)
{
- struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
if (crtc_state->hw.active) {
struct intel_plane *plane;
/* Disable everything but the primary plane */
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
const struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
@@ -284,7 +284,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc,
static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
/*
* Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
@@ -296,7 +296,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
* without several WARNs, but for now let's take the easy
* road.
*/
- return IS_SANDYBRIDGE(dev_priv) &&
+ return IS_SANDYBRIDGE(i915) &&
crtc_state->hw.active &&
crtc_state->shared_dpll &&
crtc_state->port_clock == 0;
@@ -304,7 +304,7 @@ static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
static void intel_sanitize_encoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_connector *connector;
struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
struct intel_crtc_state *crtc_state = crtc ?
@@ -319,7 +319,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
crtc_state->hw.active;
if (crtc_state && has_bogus_dpll_config(crtc_state)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"BIOS has misprogrammed the hardware. Disabling pipe %c\n",
pipe_name(crtc->pipe));
has_active_crtc = false;
@@ -327,7 +327,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
connector = intel_encoder_find_connector(encoder);
if (connector && !has_active_crtc) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] has active connectors but no active pipe!\n",
encoder->base.base.id,
encoder->base.name);
@@ -340,7 +340,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
if (crtc_state) {
struct drm_encoder *best_encoder;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] manually disabled\n",
encoder->base.base.id,
encoder->base.name);
@@ -374,17 +374,17 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
/* notify opregion of the sanitized encoder state */
intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
- if (HAS_DDI(dev_priv))
+ if (HAS_DDI(i915))
intel_ddi_sanitize_encoder_pll_mapping(encoder);
}
/* FIXME read out full plane state for all planes */
-static void readout_plane_state(struct drm_i915_private *dev_priv)
+static void readout_plane_state(struct drm_i915_private *i915)
{
struct intel_plane *plane;
struct intel_crtc *crtc;
- for_each_intel_plane(&dev_priv->drm, plane) {
+ for_each_intel_plane(&i915->drm, plane) {
struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
struct intel_crtc_state *crtc_state;
@@ -393,18 +393,18 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
visible = plane->get_hw_state(plane, &pipe);
- crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ crtc = intel_crtc_for_pipe(i915, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
intel_set_plane_visible(crtc_state, plane_state, visible);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
plane->base.base.id, plane->base.name,
str_enabled_disabled(visible), pipe_name(pipe));
}
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -412,13 +412,12 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
}
}
-static void intel_modeset_readout_hw_state(struct drm_device *dev)
+static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+ to_intel_cdclk_state(i915->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+ to_intel_dbuf_state(i915->dbuf.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@@ -426,7 +425,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
struct drm_connector_list_iter conn_iter;
u8 active_pipes = 0;
- for_each_intel_crtc(dev, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -444,7 +443,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->hw.active)
active_pipes |= BIT(crtc->pipe);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[CRTC:%d:%s] hw state readout: %s\n",
crtc->base.base.id, crtc->base.name,
str_enabled_disabled(crtc_state->hw.active));
@@ -453,15 +452,15 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
cdclk_state->active_pipes = active_pipes;
dbuf_state->active_pipes = active_pipes;
- readout_plane_state(dev_priv);
+ readout_plane_state(i915);
- for_each_intel_encoder(dev, encoder) {
+ for_each_intel_encoder(&i915->drm, encoder) {
struct intel_crtc_state *crtc_state = NULL;
pipe = 0;
if (encoder->get_hw_state(encoder, &pipe)) {
- crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ crtc = intel_crtc_for_pipe(i915, pipe);
crtc_state = to_intel_crtc_state(crtc->base.state);
encoder->base.crtc = &crtc->base;
@@ -474,7 +473,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
/* encoder should read be linked to bigjoiner master */
WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
- for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
struct intel_crtc_state *slave_crtc_state;
@@ -489,16 +488,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (encoder->sync_state)
encoder->sync_state(encoder, crtc_state);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
encoder->base.base.id, encoder->base.name,
str_enabled_disabled(encoder->base.crtc),
pipe_name(pipe));
}
- intel_dpll_readout_hw_state(dev_priv);
+ intel_dpll_readout_hw_state(i915);
- drm_connector_list_iter_begin(dev, &conn_iter);
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
if (connector->get_hw_state(connector)) {
struct intel_crtc_state *crtc_state;
@@ -527,16 +526,16 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
connector->base.dpms = DRM_MODE_DPMS_OFF;
connector->base.encoder = NULL;
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[CONNECTOR:%d:%s] hw state readout: %s\n",
connector->base.base.id, connector->base.name,
str_enabled_disabled(connector->base.encoder));
}
drm_connector_list_iter_end(&conn_iter);
- for_each_intel_crtc(dev, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_bw_state *bw_state =
- to_intel_bw_state(dev_priv->bw_obj.state);
+ to_intel_bw_state(i915->bw_obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -559,7 +558,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
intel_crtc_copy_hw_to_uapi_state(crtc_state);
}
- for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+ for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
const struct intel_plane_state *plane_state =
to_intel_plane_state(plane->base.state);
@@ -575,14 +574,14 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
* use plane->min_cdclk() :(
*/
if (plane_state->uapi.visible && plane->min_cdclk) {
- if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
+ if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
crtc_state->min_cdclk[plane->id] =
DIV_ROUND_UP(crtc_state->pixel_rate, 2);
else
crtc_state->min_cdclk[plane->id] =
crtc_state->pixel_rate;
}
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"[PLANE:%d:%s] min_cdclk %d kHz\n",
plane->base.base.id, plane->base.name,
crtc_state->min_cdclk[plane->id]);
@@ -590,7 +589,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
if (crtc_state->hw.active) {
min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
- if (drm_WARN_ON(dev, min_cdclk < 0))
+ if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
min_cdclk = 0;
}
@@ -603,11 +602,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
}
static void
-get_encoder_power_domains(struct drm_i915_private *dev_priv)
+get_encoder_power_domains(struct drm_i915_private *i915)
{
struct intel_encoder *encoder;
- for_each_intel_encoder(&dev_priv->drm, encoder) {
+ for_each_intel_encoder(&i915->drm, encoder) {
struct intel_crtc_state *crtc_state;
if (!encoder->get_power_domains)
@@ -625,58 +624,57 @@ get_encoder_power_domains(struct drm_i915_private *dev_priv)
}
}
-static void intel_early_display_was(struct drm_i915_private *dev_priv)
+static void intel_early_display_was(struct drm_i915_private *i915)
{
/*
* Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
* Also known as Wa_14010480278.
*/
- if (IS_DISPLAY_VER(dev_priv, 10, 12))
- intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
- intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
+ if (IS_DISPLAY_VER(i915, 10, 12))
+ intel_de_write(i915, GEN9_CLKGATE_DIS_0,
+ intel_de_read(i915, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
- if (IS_HASWELL(dev_priv)) {
+ if (IS_HASWELL(i915)) {
/*
* WaRsPkgCStateDisplayPMReq:hsw
* System hang if this isn't done before disabling all planes!
*/
- intel_de_write(dev_priv, CHICKEN_PAR1_1,
- intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
+ intel_de_write(i915, CHICKEN_PAR1_1,
+ intel_de_read(i915, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
}
- if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
+ if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
/* Display WA #1142:kbl,cfl,cml */
- intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+ intel_de_rmw(i915, CHICKEN_PAR1_1,
KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
- intel_de_rmw(dev_priv, CHICKEN_MISC_2,
+ intel_de_rmw(i915, CHICKEN_MISC_2,
KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
KBL_ARB_FILL_SPARE_14);
}
}
-void intel_modeset_setup_hw_state(struct drm_device *dev,
+void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
struct drm_modeset_acquire_ctx *ctx)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
- wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
+ wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
- intel_early_display_was(dev_priv);
- intel_modeset_readout_hw_state(dev);
+ intel_early_display_was(i915);
+ intel_modeset_readout_hw_state(i915);
/* HW state is read out, now we need to sanitize this mess. */
- get_encoder_power_domains(dev_priv);
+ get_encoder_power_domains(i915);
- intel_pch_sanitize(dev_priv);
+ intel_pch_sanitize(i915);
/*
* intel_sanitize_plane_mapping() may need to do vblank
* waits, so we need vblank interrupts restored beforehand.
*/
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -688,14 +686,14 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
intel_crtc_vblank_on(crtc_state);
}
- intel_fbc_sanitize(dev_priv);
+ intel_fbc_sanitize(i915);
- intel_sanitize_plane_mapping(dev_priv);
+ intel_sanitize_plane_mapping(i915);
- for_each_intel_encoder(dev, encoder)
+ for_each_intel_encoder(&i915->drm, encoder)
intel_sanitize_encoder(encoder);
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
@@ -703,34 +701,34 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
}
- intel_modeset_update_connector_atomic_state(dev);
-
- intel_dpll_sanitize_state(dev_priv);
-
- if (IS_G4X(dev_priv)) {
- g4x_wm_get_hw_state(dev_priv);
- g4x_wm_sanitize(dev_priv);
- } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_wm_get_hw_state(dev_priv);
- vlv_wm_sanitize(dev_priv);
- } else if (DISPLAY_VER(dev_priv) >= 9) {
- skl_wm_get_hw_state(dev_priv);
- skl_wm_sanitize(dev_priv);
- } else if (HAS_PCH_SPLIT(dev_priv)) {
- ilk_wm_get_hw_state(dev_priv);
+ intel_modeset_update_connector_atomic_state(i915);
+
+ intel_dpll_sanitize_state(i915);
+
+ if (IS_G4X(i915)) {
+ g4x_wm_get_hw_state(i915);
+ g4x_wm_sanitize(i915);
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ vlv_wm_get_hw_state(i915);
+ vlv_wm_sanitize(i915);
+ } else if (DISPLAY_VER(i915) >= 9) {
+ skl_wm_get_hw_state(i915);
+ skl_wm_sanitize(i915);
+ } else if (HAS_PCH_SPLIT(i915)) {
+ ilk_wm_get_hw_state(i915);
}
- for_each_intel_crtc(dev, crtc) {
+ for_each_intel_crtc(&i915->drm, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_power_domain_mask put_domains;
intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
- if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
+ if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
intel_modeset_put_crtc_power_domains(crtc, &put_domains);
}
- intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
+ intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
- intel_power_domains_sanitize_state(dev_priv);
+ intel_power_domains_sanitize_state(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.h b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
index c29b34c6a7b0..3beff67b33d0 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.h
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
@@ -6,10 +6,10 @@
#ifndef __INTEL_MODESET_SETUP_H__
#define __INTEL_MODESET_SETUP_H__
-struct drm_device;
+struct drm_i915_private;
struct drm_modeset_acquire_ctx;
-void intel_modeset_setup_hw_state(struct drm_device *dev,
+void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
struct drm_modeset_acquire_ctx *ctx);
#endif /* __INTEL_MODESET_SETUP_H__ */
--
2.30.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
2022-06-17 9:48 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: convert modeset setup to struct drm_i915_private *i915 Jani Nikula
@ 2022-06-17 13:58 ` Patchwork
2022-06-17 13:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-06-17 13:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
URL : https://patchwork.freedesktop.org/series/105281/
State : warning
== Summary ==
Error: dim checkpatch failed
4bf73e0fb102 drm/i915/display: split out hw state readout and sanitize
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in <module>
import git
ModuleNotFoundError: No module named 'git'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in <module>
import git
ModuleNotFoundError: No module named 'git'
-:289: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#289: FILE: drivers/gpu/drm/i915/display/intel_display.c:7532:
+ intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
-:928: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#928:
new file mode 100644
-:1410: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#1410: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:478:
+ intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
-:1413: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#1413: FILE: drivers/gpu/drm/i915/display/intel_modeset_setup.c:481:
+ slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
total: 0 errors, 4 warnings, 0 checks, 1627 lines checked
918eac730201 drm/i915/display: convert modeset setup to struct drm_i915_private *i915
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
2022-06-17 9:48 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: convert modeset setup to struct drm_i915_private *i915 Jani Nikula
2022-06-17 13:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize Patchwork
@ 2022-06-17 13:58 ` Patchwork
2022-06-17 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-06-17 13:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
URL : https://patchwork.freedesktop.org/series/105281/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
` (2 preceding siblings ...)
2022-06-17 13:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-06-17 14:17 ` Patchwork
2022-06-17 22:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-06-20 16:37 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-06-17 14:17 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6162 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
URL : https://patchwork.freedesktop.org/series/105281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11775 -> Patchwork_105281v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/index.html
Participating hosts (32 -> 34)
------------------------------
Additional (3): fi-kbl-soraka fi-tgl-dsi fi-pnv-d510
Missing (1): fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_105281v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gem:
- fi-blb-e6850: NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-blb-e6850/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +7 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271]) +9 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][7] ([fdo#109271])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-guc/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#533])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_page_flip:
- fi-pnv-d510: NOTRUN -> [SKIP][9] ([fdo#109271]) +40 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-bsw-n3050: [FAIL][10] ([i915#6042]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][12] ([i915#4528]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-blb-e6850/igt@i915_selftest@live@requests.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_flip@basic-plain-flip@a-edp1:
- fi-tgl-u2: [DMESG-WARN][14] ([i915#402]) -> [PASS][15] +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#6042]: https://gitlab.freedesktop.org/drm/intel/issues/6042
Build changes
-------------
* Linux: CI_DRM_11775 -> Patchwork_105281v1
CI-20190529: 20190529
CI_DRM_11775: 93bea5a783b94aa5336606ddee482f659ccd9804 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6534: 6137099c021e26b8593ddd832d6e3b3d3bc3b1d0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105281v1: 93bea5a783b94aa5336606ddee482f659ccd9804 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
14246cdc70c7 drm/i915/display: convert modeset setup to struct drm_i915_private *i915
c5dd08cef570 drm/i915/display: split out hw state readout and sanitize
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/index.html
[-- Attachment #2: Type: text/html, Size: 6870 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
` (3 preceding siblings ...)
2022-06-17 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-06-17 22:11 ` Patchwork
2022-06-20 16:37 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
5 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-06-17 22:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27998 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915/display: split out hw state readout and sanitize
URL : https://patchwork.freedesktop.org/series/105281/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11775_full -> Patchwork_105281v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 10)
------------------------------
Missing (3): shard-rkl shard-dg1 shard-tglu
Known issues
------------
Here are the changes found in Patchwork_105281v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +7 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][3] -> [SKIP][4] ([i915#4525])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb8/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: NOTRUN -> [FAIL][5] ([i915#2842]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][10] -> [FAIL][11] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2849])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@gem_lmem_swapping@heavy-verify-random.html
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@random:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-apl6/igt@gem_lmem_swapping@random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][17] ([i915#2658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@vma-merge:
- shard-kbl: NOTRUN -> [FAIL][18] ([i915#3318])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@gem_userptr_blits@vma-merge.html
* igt@i915_module_load@load:
- shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#6227])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@i915_module_load@load.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][20] -> [FAIL][21] ([i915#454]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][22] -> [INCOMPLETE][23] ([i915#4939])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl1/igt@i915_pm_rpm@system-suspend-execbuf.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl1/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-apl6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-a-gamma:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +7 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@kms_color_chamelium@pipe-a-gamma.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][29] ([i915#2105])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@kms_content_protection@uevent.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#2122])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-glk2/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-glk3/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#2122])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl1/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl3/igt@kms_flip@flip-vs-blocking-wf-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][34] -> [DMESG-WARN][35] ([i915#180]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][36] -> [SKIP][37] ([i915#3701])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271]) +89 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271]) +57 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_hdr@bpc-switch@pipe-a-dp-1:
- shard-kbl: [PASS][40] -> [FAIL][41] ([i915#1188])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl3/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl3/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#533])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145] / [i915#265])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][45] ([i915#265])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1:
- shard-iclb: [PASS][46] -> [SKIP][47] ([i915#5176]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb7/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b-edp-1.html
* igt@kms_psr@cursor_mmap_cpu:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271]) +8 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-apl6/igt@kms_psr@cursor_mmap_cpu.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109441]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][51] ([IGT#2])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@kms_sysfs_edid_timing.html
* igt@sw_sync@sync_merge_same:
- shard-skl: NOTRUN -> [FAIL][52] ([i915#6140])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@sw_sync@sync_merge_same.html
- shard-kbl: NOTRUN -> [FAIL][53] ([i915#6140])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@sw_sync@sync_merge_same.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2994]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@sysfs_clients@pidname.html
- shard-kbl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl4/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][56] ([i915#658]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb3/igt@feature_discovery@psr2.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [FAIL][58] -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb5/igt@gem_ctx_exec@basic-nohangcheck.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-tglb6/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][60] ([i915#3070]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb1/igt@gem_eio@unwedge-stress.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb8/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [SKIP][62] ([i915#4525]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb2/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][64] ([i915#2842]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [FAIL][66] ([i915#2842]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl3/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-iclb: [FAIL][68] ([i915#2842]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb8/igt@gem_exec_fair@basic-pace@rcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_softpin@reverse:
- shard-skl: [DMESG-WARN][70] ([i915#1982]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl1/igt@gem_softpin@reverse.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl3/igt@gem_softpin@reverse.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][72] ([i915#180]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1:
- shard-glk: [SKIP][74] ([fdo#109271]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-glk8/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-glk6/igt@kms_dither@fb-8bpc-vs-panel-8bpc@pipe-a-hdmi-a-1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2:
- shard-glk: [FAIL][76] ([i915#79]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][78] ([i915#79]) -> [PASS][79] +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [FAIL][80] ([i915#2122]) -> [PASS][81] +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl1/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_hdmi_inject@inject-audio:
- shard-skl: [SKIP][82] ([fdo#109271]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl7/igt@kms_hdmi_inject@inject-audio.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl10/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1:
- shard-iclb: [SKIP][84] ([i915#5235]) -> [PASS][85] +5 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-c-edp-1.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][86] ([fdo#109441]) -> [PASS][87] +2 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-skl: [FAIL][88] ([i915#43]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl3/igt@kms_vblank@pipe-b-accuracy-idle.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl6/igt@kms_vblank@pipe-b-accuracy-idle.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][90] ([i915#180]) -> [PASS][91] +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][92] ([i915#4525]) -> [FAIL][93] ([i915#6117])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][94] ([fdo#109271]) -> [FAIL][95] ([i915#2842])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@kms_chamelium@hdmi-audio:
- shard-skl: [SKIP][96] ([fdo#109271] / [fdo#111827] / [i915#1888]) -> [SKIP][97] ([fdo#109271] / [fdo#111827])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl4/igt@kms_chamelium@hdmi-audio.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl7/igt@kms_chamelium@hdmi-audio.html
* igt@kms_cursor_crc@pipe-d-cursor-128x42-random:
- shard-skl: [SKIP][98] ([fdo#109271] / [i915#1888]) -> [SKIP][99] ([fdo#109271]) +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl3/igt@kms_cursor_crc@pipe-d-cursor-128x42-random.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl6/igt@kms_cursor_crc@pipe-d-cursor-128x42-random.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: [FAIL][100] ([i915#1188]) -> [DMESG-FAIL][101] ([i915#180])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl7/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][102] ([i915#658]) -> [SKIP][103] ([i915#2920])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][104] ([fdo#111068] / [i915#658]) -> [SKIP][105] ([i915#2920])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][106] ([i915#2920]) -> [SKIP][107] ([i915#658]) +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@runner@aborted:
- shard-skl: ([FAIL][108], [FAIL][109]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][110], [FAIL][111], [FAIL][112]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl7/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-skl3/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl3/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl1/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-skl6/igt@runner@aborted.html
- shard-kbl: ([FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92]) -> ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl7/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl4/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl7/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl1/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11775/shard-kbl6/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl6/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl6/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl6/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl7/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/shard-kbl7/igt@runner@aborted.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* Linux: CI_DRM_11775 -> Patchwork_105281v1
CI-20190529: 20190529
CI_DRM_11775: 93bea5a783b94aa5336606ddee482f659ccd9804 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6534: 6137099c021e26b8593ddd832d6e3b3d3bc3b1d0 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105281v1: 93bea5a783b94aa5336606ddee482f659ccd9804 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105281v1/index.html
[-- Attachment #2: Type: text/html, Size: 34983 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
` (4 preceding siblings ...)
2022-06-17 22:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-06-20 16:37 ` Jani Nikula
5 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2022-06-20 16:37 UTC (permalink / raw)
To: intel-gfx
On Fri, 17 Jun 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> Split out the modeset hardware state readout and sanitize, or state
> setup, to a separate file.
>
> Do some drive-by checkpatch fixes while at it.
>
> v2: Rebase
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> # v1
Both patches pushed to drm-intel-next, thanks for the review.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 739 +-----------------
> drivers/gpu/drm/i915/display/intel_display.h | 12 +
> .../drm/i915/display/intel_modeset_setup.c | 736 +++++++++++++++++
> .../drm/i915/display/intel_modeset_setup.h | 15 +
> 5 files changed, 778 insertions(+), 725 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.c
> create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_setup.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 37a8ea56f7d6..c84a9cd8440d 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -244,6 +244,7 @@ i915-y += \
> display/intel_hotplug.o \
> display/intel_lpe_audio.o \
> display/intel_modeset_verify.o \
> + display/intel_modeset_setup.o \
> display/intel_overlay.o \
> display/intel_pch_display.o \
> display/intel_pch_refclk.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 90bd26431e31..710a51f14649 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -101,6 +101,7 @@
> #include "intel_hdcp.h"
> #include "intel_hotplug.h"
> #include "intel_modeset_verify.h"
> +#include "intel_modeset_setup.h"
> #include "intel_overlay.h"
> #include "intel_panel.h"
> #include "intel_pch_display.h"
> @@ -130,8 +131,6 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
> static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
> static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
> -static void intel_modeset_setup_hw_state(struct drm_device *dev,
> - struct drm_modeset_acquire_ctx *ctx);
>
> /**
> * intel_update_watermarks - update FIFO watermark values based on current modes
> @@ -166,7 +165,7 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
> * We don't use the sprite, so we can ignore that. And on Crestline we have
> * to set the non-SR watermarks to 8.
> */
> -static void intel_update_watermarks(struct drm_i915_private *dev_priv)
> +void intel_update_watermarks(struct drm_i915_private *dev_priv)
> {
> if (dev_priv->wm_disp->update_wm)
> dev_priv->wm_disp->update_wm(dev_priv);
> @@ -733,10 +732,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> DRM_MODE_ROTATE_0);
> }
>
> -static void
> -intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *plane_state,
> - bool visible)
> +void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state,
> + bool visible)
> {
> struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>
> @@ -748,7 +746,7 @@ intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
> }
>
> -static void fixup_plane_bitmasks(struct intel_crtc_state *crtc_state)
> +void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> struct drm_plane *plane;
> @@ -783,7 +781,7 @@ void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> crtc->base.base.id, crtc->base.name);
>
> intel_set_plane_visible(crtc_state, plane_state, false);
> - fixup_plane_bitmasks(crtc_state);
> + intel_plane_fixup_bitmasks(crtc_state);
> crtc_state->data_rate[plane->id] = 0;
> crtc_state->data_rate_y[plane->id] = 0;
> crtc_state->rel_data_rate[plane->id] = 0;
> @@ -2209,9 +2207,8 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
> }
>
> -static void
> -modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> - struct intel_power_domain_mask *old_domains)
> +void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> + struct intel_power_domain_mask *old_domains)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -2235,8 +2232,8 @@ modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> domain);
> }
>
> -static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> - struct intel_power_domain_mask *domains)
> +void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> + struct intel_power_domain_mask *domains)
> {
> intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
> &crtc->enabled_power_domains,
> @@ -2416,89 +2413,6 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
> i830_enable_pipe(dev_priv, pipe);
> }
>
> -static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> - struct drm_modeset_acquire_ctx *ctx)
> -{
> - struct intel_encoder *encoder;
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_bw_state *bw_state =
> - to_intel_bw_state(dev_priv->bw_obj.state);
> - struct intel_cdclk_state *cdclk_state =
> - to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> - struct intel_dbuf_state *dbuf_state =
> - to_intel_dbuf_state(dev_priv->dbuf.obj.state);
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> - struct intel_plane *plane;
> - struct drm_atomic_state *state;
> - struct intel_crtc_state *temp_crtc_state;
> - enum pipe pipe = crtc->pipe;
> - int ret;
> -
> - if (!crtc_state->hw.active)
> - return;
> -
> - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(plane->base.state);
> -
> - if (plane_state->uapi.visible)
> - intel_plane_disable_noatomic(crtc, plane);
> - }
> -
> - state = drm_atomic_state_alloc(&dev_priv->drm);
> - if (!state) {
> - drm_dbg_kms(&dev_priv->drm,
> - "failed to disable [CRTC:%d:%s], out of memory",
> - crtc->base.base.id, crtc->base.name);
> - return;
> - }
> -
> - state->acquire_ctx = ctx;
> -
> - /* Everything's already locked, -EDEADLK can't happen. */
> - temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
> - ret = drm_atomic_add_affected_connectors(state, &crtc->base);
> -
> - drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
> -
> - dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
> -
> - drm_atomic_state_put(state);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
> - crtc->base.base.id, crtc->base.name);
> -
> - crtc->active = false;
> - crtc->base.enabled = false;
> -
> - drm_WARN_ON(&dev_priv->drm,
> - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
> - crtc_state->uapi.active = false;
> - crtc_state->uapi.connector_mask = 0;
> - crtc_state->uapi.encoder_mask = 0;
> - intel_crtc_free_hw_state(crtc_state);
> - memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
> -
> - for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
> - encoder->base.crtc = NULL;
> -
> - intel_fbc_disable(crtc);
> - intel_update_watermarks(dev_priv);
> - intel_disable_shared_dpll(crtc_state);
> -
> - intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
> -
> - cdclk_state->min_cdclk[pipe] = 0;
> - cdclk_state->min_voltage_level[pipe] = 0;
> - cdclk_state->active_pipes &= ~BIT(pipe);
> -
> - dbuf_state->active_pipes &= ~BIT(pipe);
> -
> - bw_state->data_rate[pipe] = 0;
> - bw_state->num_active_planes[pipe] = 0;
> -}
>
> /*
> * turn all crtc's off, but do not adjust state
> @@ -4948,39 +4862,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> return 0;
> }
>
> -static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> -{
> - struct intel_connector *connector;
> - struct drm_connector_list_iter conn_iter;
> -
> - drm_connector_list_iter_begin(dev, &conn_iter);
> - for_each_intel_connector_iter(connector, &conn_iter) {
> - struct drm_connector_state *conn_state = connector->base.state;
> - struct intel_encoder *encoder =
> - to_intel_encoder(connector->base.encoder);
> -
> - if (conn_state->crtc)
> - drm_connector_put(&connector->base);
> -
> - if (encoder) {
> - struct intel_crtc *crtc =
> - to_intel_crtc(encoder->base.crtc);
> - const struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> -
> - conn_state->best_encoder = &encoder->base;
> - conn_state->crtc = &crtc->base;
> - conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
> -
> - drm_connector_get(&connector->base);
> - } else {
> - conn_state->best_encoder = NULL;
> - conn_state->crtc = NULL;
> - }
> - }
> - drm_connector_list_iter_end(&conn_iter);
> -}
> -
> static int
> compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
> struct intel_crtc_state *crtc_state)
> @@ -5165,27 +5046,6 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
> intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
> }
>
> -static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> -{
> - if (intel_crtc_is_bigjoiner_slave(crtc_state))
> - return;
> -
> - crtc_state->uapi.enable = crtc_state->hw.enable;
> - crtc_state->uapi.active = crtc_state->hw.active;
> - drm_WARN_ON(crtc_state->uapi.crtc->dev,
> - drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> -
> - crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> - crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
> -
> - drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
> - crtc_state->hw.degamma_lut);
> - drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
> - crtc_state->hw.gamma_lut);
> - drm_property_replace_blob(&crtc_state->uapi.ctm,
> - crtc_state->hw.ctm);
> -}
> -
> static void
> copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
> struct intel_crtc *slave_crtc)
> @@ -6115,8 +5975,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state)
> return 0;
> }
>
> -static void
> -intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
> +void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -7670,7 +7529,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> new_crtc_state, i) {
> if (intel_crtc_needs_modeset(new_crtc_state) ||
> new_crtc_state->update_pipe) {
> - modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
> + intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
> }
> }
>
> @@ -7770,7 +7629,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> intel_post_plane_update(state, crtc);
>
> - modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
> + intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
>
> intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
>
> @@ -9060,576 +8919,6 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> intel_de_posting_read(dev_priv, DPLL(pipe));
> }
>
> -static void
> -intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
> -{
> - struct intel_crtc *crtc;
> -
> - if (DISPLAY_VER(dev_priv) >= 4)
> - return;
> -
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> - struct intel_plane *plane =
> - to_intel_plane(crtc->base.primary);
> - struct intel_crtc *plane_crtc;
> - enum pipe pipe;
> -
> - if (!plane->get_hw_state(plane, &pipe))
> - continue;
> -
> - if (pipe == crtc->pipe)
> - continue;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
> - plane->base.base.id, plane->base.name);
> -
> - plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
> - intel_plane_disable_noatomic(plane_crtc, plane);
> - }
> -}
> -
> -static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct intel_encoder *encoder;
> -
> - for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> - return true;
> -
> - return false;
> -}
> -
> -static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
> -{
> - struct drm_device *dev = encoder->base.dev;
> - struct intel_connector *connector;
> -
> - for_each_connector_on_encoder(dev, &encoder->base, connector)
> - return connector;
> -
> - return NULL;
> -}
> -
> -static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
> -{
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> -
> - if (!crtc_state->hw.active && !HAS_GMCH(i915))
> - return;
> -
> - /*
> - * We start out with underrun reporting disabled to avoid races.
> - * For correct bookkeeping mark this on active crtcs.
> - *
> - * Also on gmch platforms we dont have any hardware bits to
> - * disable the underrun reporting. Which means we need to start
> - * out with underrun reporting disabled also on inactive pipes,
> - * since otherwise we'll complain about the garbage we read when
> - * e.g. coming up after runtime pm.
> - *
> - * No protection against concurrent access is required - at
> - * worst a fifo underrun happens which also sets this to false.
> - */
> - crtc->cpu_fifo_underrun_disabled = true;
> -
> - /*
> - * We track the PCH trancoder underrun reporting state
> - * within the crtc. With crtc for pipe A housing the underrun
> - * reporting state for PCH transcoder A, crtc for pipe B housing
> - * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
> - * and marking underrun reporting as disabled for the non-existing
> - * PCH transcoders B and C would prevent enabling the south
> - * error interrupt (see cpt_can_enable_serr_int()).
> - */
> - if (intel_has_pch_trancoder(i915, crtc->pipe))
> - crtc->pch_fifo_underrun_disabled = true;
> -}
> -
> -static void intel_sanitize_crtc(struct intel_crtc *crtc,
> - struct drm_modeset_acquire_ctx *ctx)
> -{
> - struct drm_device *dev = crtc->base.dev;
> - struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> -
> - if (crtc_state->hw.active) {
> - struct intel_plane *plane;
> -
> - /* Disable everything but the primary plane */
> - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(plane->base.state);
> -
> - if (plane_state->uapi.visible &&
> - plane->base.type != DRM_PLANE_TYPE_PRIMARY)
> - intel_plane_disable_noatomic(crtc, plane);
> - }
> -
> - /* Disable any background color/etc. set by the BIOS */
> - intel_color_commit_noarm(crtc_state);
> - intel_color_commit_arm(crtc_state);
> - }
> -
> - /* Adjust the state of the output pipe according to whether we
> - * have active connectors/encoders. */
> - if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
> - !intel_crtc_is_bigjoiner_slave(crtc_state))
> - intel_crtc_disable_noatomic(crtc, ctx);
> -}
> -
> -static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -
> - /*
> - * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
> - * the hardware when a high res displays plugged in. DPLL P
> - * divider is zero, and the pipe timings are bonkers. We'll
> - * try to disable everything in that case.
> - *
> - * FIXME would be nice to be able to sanitize this state
> - * without several WARNs, but for now let's take the easy
> - * road.
> - */
> - return IS_SANDYBRIDGE(dev_priv) &&
> - crtc_state->hw.active &&
> - crtc_state->shared_dpll &&
> - crtc_state->port_clock == 0;
> -}
> -
> -static void intel_sanitize_encoder(struct intel_encoder *encoder)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_connector *connector;
> - struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> - struct intel_crtc_state *crtc_state = crtc ?
> - to_intel_crtc_state(crtc->base.state) : NULL;
> -
> - /* We need to check both for a crtc link (meaning that the
> - * encoder is active and trying to read from a pipe) and the
> - * pipe itself being active. */
> - bool has_active_crtc = crtc_state &&
> - crtc_state->hw.active;
> -
> - if (crtc_state && has_bogus_dpll_config(crtc_state)) {
> - drm_dbg_kms(&dev_priv->drm,
> - "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
> - pipe_name(crtc->pipe));
> - has_active_crtc = false;
> - }
> -
> - connector = intel_encoder_find_connector(encoder);
> - if (connector && !has_active_crtc) {
> - drm_dbg_kms(&dev_priv->drm,
> - "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
> - encoder->base.base.id,
> - encoder->base.name);
> -
> - /* Connector is active, but has no active pipe. This is
> - * fallout from our resume register restoring. Disable
> - * the encoder manually again. */
> - if (crtc_state) {
> - struct drm_encoder *best_encoder;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "[ENCODER:%d:%s] manually disabled\n",
> - encoder->base.base.id,
> - encoder->base.name);
> -
> - /* avoid oopsing in case the hooks consult best_encoder */
> - best_encoder = connector->base.state->best_encoder;
> - connector->base.state->best_encoder = &encoder->base;
> -
> - /* FIXME NULL atomic state passed! */
> - if (encoder->disable)
> - encoder->disable(NULL, encoder, crtc_state,
> - connector->base.state);
> - if (encoder->post_disable)
> - encoder->post_disable(NULL, encoder, crtc_state,
> - connector->base.state);
> -
> - connector->base.state->best_encoder = best_encoder;
> - }
> - encoder->base.crtc = NULL;
> -
> - /* Inconsistent output/port/pipe state happens presumably due to
> - * a bug in one of the get_hw_state functions. Or someplace else
> - * in our code, like the register restore mess on resume. Clamp
> - * things to off as a safer default. */
> -
> - connector->base.dpms = DRM_MODE_DPMS_OFF;
> - connector->base.encoder = NULL;
> - }
> -
> - /* notify opregion of the sanitized encoder state */
> - intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
> -
> - if (HAS_DDI(dev_priv))
> - intel_ddi_sanitize_encoder_pll_mapping(encoder);
> -}
> -
> -/* FIXME read out full plane state for all planes */
> -static void readout_plane_state(struct drm_i915_private *dev_priv)
> -{
> - struct intel_plane *plane;
> - struct intel_crtc *crtc;
> -
> - for_each_intel_plane(&dev_priv->drm, plane) {
> - struct intel_plane_state *plane_state =
> - to_intel_plane_state(plane->base.state);
> - struct intel_crtc_state *crtc_state;
> - enum pipe pipe = PIPE_A;
> - bool visible;
> -
> - visible = plane->get_hw_state(plane, &pipe);
> -
> - crtc = intel_crtc_for_pipe(dev_priv, pipe);
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> -
> - intel_set_plane_visible(crtc_state, plane_state, visible);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
> - plane->base.base.id, plane->base.name,
> - str_enabled_disabled(visible), pipe_name(pipe));
> - }
> -
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> -
> - fixup_plane_bitmasks(crtc_state);
> - }
> -}
> -
> -static void intel_modeset_readout_hw_state(struct drm_device *dev)
> -{
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_cdclk_state *cdclk_state =
> - to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> - struct intel_dbuf_state *dbuf_state =
> - to_intel_dbuf_state(dev_priv->dbuf.obj.state);
> - enum pipe pipe;
> - struct intel_crtc *crtc;
> - struct intel_encoder *encoder;
> - struct intel_connector *connector;
> - struct drm_connector_list_iter conn_iter;
> - u8 active_pipes = 0;
> -
> - for_each_intel_crtc(dev, crtc) {
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> -
> - __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> - intel_crtc_free_hw_state(crtc_state);
> - intel_crtc_state_reset(crtc_state, crtc);
> -
> - intel_crtc_get_pipe_config(crtc_state);
> -
> - crtc_state->hw.enable = crtc_state->hw.active;
> -
> - crtc->base.enabled = crtc_state->hw.enable;
> - crtc->active = crtc_state->hw.active;
> -
> - if (crtc_state->hw.active)
> - active_pipes |= BIT(crtc->pipe);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "[CRTC:%d:%s] hw state readout: %s\n",
> - crtc->base.base.id, crtc->base.name,
> - str_enabled_disabled(crtc_state->hw.active));
> - }
> -
> - cdclk_state->active_pipes = dbuf_state->active_pipes = active_pipes;
> -
> - readout_plane_state(dev_priv);
> -
> - for_each_intel_encoder(dev, encoder) {
> - struct intel_crtc_state *crtc_state = NULL;
> -
> - pipe = 0;
> -
> - if (encoder->get_hw_state(encoder, &pipe)) {
> - crtc = intel_crtc_for_pipe(dev_priv, pipe);
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> -
> - encoder->base.crtc = &crtc->base;
> - intel_encoder_get_config(encoder, crtc_state);
> -
> - /* read out to slave crtc as well for bigjoiner */
> - if (crtc_state->bigjoiner_pipes) {
> - struct intel_crtc *slave_crtc;
> -
> - /* encoder should read be linked to bigjoiner master */
> - WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
> -
> - for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
> - intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
> - struct intel_crtc_state *slave_crtc_state;
> -
> - slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
> - intel_encoder_get_config(encoder, slave_crtc_state);
> - }
> - }
> - } else {
> - encoder->base.crtc = NULL;
> - }
> -
> - if (encoder->sync_state)
> - encoder->sync_state(encoder, crtc_state);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
> - encoder->base.base.id, encoder->base.name,
> - str_enabled_disabled(encoder->base.crtc),
> - pipe_name(pipe));
> - }
> -
> - intel_dpll_readout_hw_state(dev_priv);
> -
> - drm_connector_list_iter_begin(dev, &conn_iter);
> - for_each_intel_connector_iter(connector, &conn_iter) {
> - if (connector->get_hw_state(connector)) {
> - struct intel_crtc_state *crtc_state;
> - struct intel_crtc *crtc;
> -
> - connector->base.dpms = DRM_MODE_DPMS_ON;
> -
> - encoder = intel_attached_encoder(connector);
> - connector->base.encoder = &encoder->base;
> -
> - crtc = to_intel_crtc(encoder->base.crtc);
> - crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
> -
> - if (crtc_state && crtc_state->hw.active) {
> - /*
> - * This has to be done during hardware readout
> - * because anything calling .crtc_disable may
> - * rely on the connector_mask being accurate.
> - */
> - crtc_state->uapi.connector_mask |=
> - drm_connector_mask(&connector->base);
> - crtc_state->uapi.encoder_mask |=
> - drm_encoder_mask(&encoder->base);
> - }
> - } else {
> - connector->base.dpms = DRM_MODE_DPMS_OFF;
> - connector->base.encoder = NULL;
> - }
> - drm_dbg_kms(&dev_priv->drm,
> - "[CONNECTOR:%d:%s] hw state readout: %s\n",
> - connector->base.base.id, connector->base.name,
> - str_enabled_disabled(connector->base.encoder));
> - }
> - drm_connector_list_iter_end(&conn_iter);
> -
> - for_each_intel_crtc(dev, crtc) {
> - struct intel_bw_state *bw_state =
> - to_intel_bw_state(dev_priv->bw_obj.state);
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> - struct intel_plane *plane;
> - int min_cdclk = 0;
> -
> - if (crtc_state->hw.active) {
> - /*
> - * The initial mode needs to be set in order to keep
> - * the atomic core happy. It wants a valid mode if the
> - * crtc's enabled, so we do the above call.
> - *
> - * But we don't set all the derived state fully, hence
> - * set a flag to indicate that a full recalculation is
> - * needed on the next commit.
> - */
> - crtc_state->inherited = true;
> -
> - intel_crtc_update_active_timings(crtc_state);
> -
> - intel_crtc_copy_hw_to_uapi_state(crtc_state);
> - }
> -
> - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> - const struct intel_plane_state *plane_state =
> - to_intel_plane_state(plane->base.state);
> -
> - /*
> - * FIXME don't have the fb yet, so can't
> - * use intel_plane_data_rate() :(
> - */
> - if (plane_state->uapi.visible)
> - crtc_state->data_rate[plane->id] =
> - 4 * crtc_state->pixel_rate;
> - /*
> - * FIXME don't have the fb yet, so can't
> - * use plane->min_cdclk() :(
> - */
> - if (plane_state->uapi.visible && plane->min_cdclk) {
> - if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
> - crtc_state->min_cdclk[plane->id] =
> - DIV_ROUND_UP(crtc_state->pixel_rate, 2);
> - else
> - crtc_state->min_cdclk[plane->id] =
> - crtc_state->pixel_rate;
> - }
> - drm_dbg_kms(&dev_priv->drm,
> - "[PLANE:%d:%s] min_cdclk %d kHz\n",
> - plane->base.base.id, plane->base.name,
> - crtc_state->min_cdclk[plane->id]);
> - }
> -
> - if (crtc_state->hw.active) {
> - min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
> - if (drm_WARN_ON(dev, min_cdclk < 0))
> - min_cdclk = 0;
> - }
> -
> - cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
> - cdclk_state->min_voltage_level[crtc->pipe] =
> - crtc_state->min_voltage_level;
> -
> - intel_bw_crtc_update(bw_state, crtc_state);
> - }
> -}
> -
> -static void
> -get_encoder_power_domains(struct drm_i915_private *dev_priv)
> -{
> - struct intel_encoder *encoder;
> -
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> - struct intel_crtc_state *crtc_state;
> -
> - if (!encoder->get_power_domains)
> - continue;
> -
> - /*
> - * MST-primary and inactive encoders don't have a crtc state
> - * and neither of these require any power domain references.
> - */
> - if (!encoder->base.crtc)
> - continue;
> -
> - crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
> - encoder->get_power_domains(encoder, crtc_state);
> - }
> -}
> -
> -static void intel_early_display_was(struct drm_i915_private *dev_priv)
> -{
> - /*
> - * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
> - * Also known as Wa_14010480278.
> - */
> - if (IS_DISPLAY_VER(dev_priv, 10, 12))
> - intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
> - intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
> -
> - if (IS_HASWELL(dev_priv)) {
> - /*
> - * WaRsPkgCStateDisplayPMReq:hsw
> - * System hang if this isn't done before disabling all planes!
> - */
> - intel_de_write(dev_priv, CHICKEN_PAR1_1,
> - intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
> - }
> -
> - if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
> - /* Display WA #1142:kbl,cfl,cml */
> - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> - KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
> - intel_de_rmw(dev_priv, CHICKEN_MISC_2,
> - KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
> - KBL_ARB_FILL_SPARE_14);
> - }
> -}
> -
> -
> -/* Scan out the current hw modeset state,
> - * and sanitizes it to the current state
> - */
> -static void
> -intel_modeset_setup_hw_state(struct drm_device *dev,
> - struct drm_modeset_acquire_ctx *ctx)
> -{
> - struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_encoder *encoder;
> - struct intel_crtc *crtc;
> - intel_wakeref_t wakeref;
> -
> - wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> -
> - intel_early_display_was(dev_priv);
> - intel_modeset_readout_hw_state(dev);
> -
> - /* HW state is read out, now we need to sanitize this mess. */
> - get_encoder_power_domains(dev_priv);
> -
> - intel_pch_sanitize(dev_priv);
> -
> - /*
> - * intel_sanitize_plane_mapping() may need to do vblank
> - * waits, so we need vblank interrupts restored beforehand.
> - */
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> -
> - intel_sanitize_fifo_underrun_reporting(crtc_state);
> -
> - drm_crtc_vblank_reset(&crtc->base);
> -
> - if (crtc_state->hw.active)
> - intel_crtc_vblank_on(crtc_state);
> - }
> -
> - intel_fbc_sanitize(dev_priv);
> -
> - intel_sanitize_plane_mapping(dev_priv);
> -
> - for_each_intel_encoder(dev, encoder)
> - intel_sanitize_encoder(encoder);
> -
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> -
> - intel_sanitize_crtc(crtc, ctx);
> - intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
> - }
> -
> - intel_modeset_update_connector_atomic_state(dev);
> -
> - intel_dpll_sanitize_state(dev_priv);
> -
> - if (IS_G4X(dev_priv)) {
> - g4x_wm_get_hw_state(dev_priv);
> - g4x_wm_sanitize(dev_priv);
> - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - vlv_wm_get_hw_state(dev_priv);
> - vlv_wm_sanitize(dev_priv);
> - } else if (DISPLAY_VER(dev_priv) >= 9) {
> - skl_wm_get_hw_state(dev_priv);
> - skl_wm_sanitize(dev_priv);
> - } else if (HAS_PCH_SPLIT(dev_priv)) {
> - ilk_wm_get_hw_state(dev_priv);
> - }
> -
> - for_each_intel_crtc(dev, crtc) {
> - struct intel_crtc_state *crtc_state =
> - to_intel_crtc_state(crtc->base.state);
> - struct intel_power_domain_mask put_domains;
> -
> - modeset_get_crtc_power_domains(crtc_state, &put_domains);
> - if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
> - modeset_put_crtc_power_domains(crtc, &put_domains);
> - }
> -
> - intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
> -
> - intel_power_domains_sanitize_state(dev_priv);
> -}
> -
> void intel_display_resume(struct drm_device *dev)
> {
> struct drm_i915_private *i915 = to_i915(dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 2feb8ae5d5d4..8610e17cc593 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -56,6 +56,7 @@ struct intel_initial_plane_config;
> struct intel_load_detect_pipe;
> struct intel_plane;
> struct intel_plane_state;
> +struct intel_power_domain_mask;
> struct intel_remapped_info;
> struct intel_rotation_info;
> struct pci_dev;
> @@ -563,6 +564,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
> bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> const struct intel_crtc_state *pipe_config,
> bool fastset);
> +void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
>
> void intel_plane_destroy(struct drm_plane *plane);
> void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
> @@ -659,10 +661,16 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state);
> void intel_plane_disable_noatomic(struct intel_crtc *crtc,
> struct intel_plane *plane);
> +void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state,
> + bool visible);
> +void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state);
>
> void intel_display_driver_register(struct drm_i915_private *i915);
> void intel_display_driver_unregister(struct drm_i915_private *i915);
>
> +void intel_update_watermarks(struct drm_i915_private *i915);
> +
> /* modesetting */
> bool intel_modeset_probe_defer(struct pci_dev *pdev);
> void intel_modeset_init_hw(struct drm_i915_private *i915);
> @@ -674,6 +682,10 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915);
> void intel_modeset_driver_remove_nogem(struct drm_i915_private *i915);
> void intel_display_resume(struct drm_device *dev);
> int intel_modeset_all_pipes(struct intel_atomic_state *state);
> +void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> + struct intel_power_domain_mask *old_domains);
> +void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> + struct intel_power_domain_mask *domains);
>
> /* modesetting asserts */
> void assert_transcoder(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> new file mode 100644
> index 000000000000..c340f3393246
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -0,0 +1,736 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + *
> + * Read out the current hardware modeset state, and sanitize it to the current
> + * state.
> + */
> +
> +#include <drm/drm_atomic_uapi.h>
> +#include <drm/drm_atomic_state_helper.h>
> +
> +#include "i915_drv.h"
> +#include "intel_atomic.h"
> +#include "intel_bw.h"
> +#include "intel_color.h"
> +#include "intel_crtc.h"
> +#include "intel_crtc_state_dump.h"
> +#include "intel_ddi.h"
> +#include "intel_de.h"
> +#include "intel_display.h"
> +#include "intel_display_power.h"
> +#include "intel_display_types.h"
> +#include "intel_modeset_setup.h"
> +#include "intel_pch_display.h"
> +#include "intel_pm.h"
> +
> +static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
> + struct drm_modeset_acquire_ctx *ctx)
> +{
> + struct intel_encoder *encoder;
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_bw_state *bw_state =
> + to_intel_bw_state(dev_priv->bw_obj.state);
> + struct intel_cdclk_state *cdclk_state =
> + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> + struct intel_dbuf_state *dbuf_state =
> + to_intel_dbuf_state(dev_priv->dbuf.obj.state);
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_plane *plane;
> + struct drm_atomic_state *state;
> + struct intel_crtc_state *temp_crtc_state;
> + enum pipe pipe = crtc->pipe;
> + int ret;
> +
> + if (!crtc_state->hw.active)
> + return;
> +
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> +
> + if (plane_state->uapi.visible)
> + intel_plane_disable_noatomic(crtc, plane);
> + }
> +
> + state = drm_atomic_state_alloc(&dev_priv->drm);
> + if (!state) {
> + drm_dbg_kms(&dev_priv->drm,
> + "failed to disable [CRTC:%d:%s], out of memory",
> + crtc->base.base.id, crtc->base.name);
> + return;
> + }
> +
> + state->acquire_ctx = ctx;
> +
> + /* Everything's already locked, -EDEADLK can't happen. */
> + temp_crtc_state = intel_atomic_get_crtc_state(state, crtc);
> + ret = drm_atomic_add_affected_connectors(state, &crtc->base);
> +
> + drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
> +
> + dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
> +
> + drm_atomic_state_put(state);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
> + crtc->base.base.id, crtc->base.name);
> +
> + crtc->active = false;
> + crtc->base.enabled = false;
> +
> + drm_WARN_ON(&dev_priv->drm,
> + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0);
> + crtc_state->uapi.active = false;
> + crtc_state->uapi.connector_mask = 0;
> + crtc_state->uapi.encoder_mask = 0;
> + intel_crtc_free_hw_state(crtc_state);
> + memset(&crtc_state->hw, 0, sizeof(crtc_state->hw));
> +
> + for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)
> + encoder->base.crtc = NULL;
> +
> + intel_fbc_disable(crtc);
> + intel_update_watermarks(dev_priv);
> + intel_disable_shared_dpll(crtc_state);
> +
> + intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
> +
> + cdclk_state->min_cdclk[pipe] = 0;
> + cdclk_state->min_voltage_level[pipe] = 0;
> + cdclk_state->active_pipes &= ~BIT(pipe);
> +
> + dbuf_state->active_pipes &= ~BIT(pipe);
> +
> + bw_state->data_rate[pipe] = 0;
> + bw_state->num_active_planes[pipe] = 0;
> +}
> +
> +static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
> +{
> + struct intel_connector *connector;
> + struct drm_connector_list_iter conn_iter;
> +
> + drm_connector_list_iter_begin(dev, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + struct drm_connector_state *conn_state = connector->base.state;
> + struct intel_encoder *encoder =
> + to_intel_encoder(connector->base.encoder);
> +
> + if (conn_state->crtc)
> + drm_connector_put(&connector->base);
> +
> + if (encoder) {
> + struct intel_crtc *crtc =
> + to_intel_crtc(encoder->base.crtc);
> + const struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> +
> + conn_state->best_encoder = &encoder->base;
> + conn_state->crtc = &crtc->base;
> + conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
> +
> + drm_connector_get(&connector->base);
> + } else {
> + conn_state->best_encoder = NULL;
> + conn_state->crtc = NULL;
> + }
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +}
> +
> +static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
> +{
> + if (intel_crtc_is_bigjoiner_slave(crtc_state))
> + return;
> +
> + crtc_state->uapi.enable = crtc_state->hw.enable;
> + crtc_state->uapi.active = crtc_state->hw.active;
> + drm_WARN_ON(crtc_state->uapi.crtc->dev,
> + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
> +
> + crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
> + crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
> +
> + drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
> + crtc_state->hw.degamma_lut);
> + drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
> + crtc_state->hw.gamma_lut);
> + drm_property_replace_blob(&crtc_state->uapi.ctm,
> + crtc_state->hw.ctm);
> +}
> +
> +static void
> +intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv)
> +{
> + struct intel_crtc *crtc;
> +
> + if (DISPLAY_VER(dev_priv) >= 4)
> + return;
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_plane *plane =
> + to_intel_plane(crtc->base.primary);
> + struct intel_crtc *plane_crtc;
> + enum pipe pipe;
> +
> + if (!plane->get_hw_state(plane, &pipe))
> + continue;
> +
> + if (pipe == crtc->pipe)
> + continue;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
> + plane->base.base.id, plane->base.name);
> +
> + plane_crtc = intel_crtc_for_pipe(dev_priv, pipe);
> + intel_plane_disable_noatomic(plane_crtc, plane);
> + }
> +}
> +
> +static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct intel_encoder *encoder;
> +
> + for_each_encoder_on_crtc(dev, &crtc->base, encoder)
> + return true;
> +
> + return false;
> +}
> +
> +static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
> +{
> + struct drm_device *dev = encoder->base.dev;
> + struct intel_connector *connector;
> +
> + for_each_connector_on_encoder(dev, &encoder->base, connector)
> + return connector;
> +
> + return NULL;
> +}
> +
> +static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +
> + if (!crtc_state->hw.active && !HAS_GMCH(i915))
> + return;
> +
> + /*
> + * We start out with underrun reporting disabled to avoid races.
> + * For correct bookkeeping mark this on active crtcs.
> + *
> + * Also on gmch platforms we dont have any hardware bits to
> + * disable the underrun reporting. Which means we need to start
> + * out with underrun reporting disabled also on inactive pipes,
> + * since otherwise we'll complain about the garbage we read when
> + * e.g. coming up after runtime pm.
> + *
> + * No protection against concurrent access is required - at
> + * worst a fifo underrun happens which also sets this to false.
> + */
> + crtc->cpu_fifo_underrun_disabled = true;
> +
> + /*
> + * We track the PCH trancoder underrun reporting state
> + * within the crtc. With crtc for pipe A housing the underrun
> + * reporting state for PCH transcoder A, crtc for pipe B housing
> + * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
> + * and marking underrun reporting as disabled for the non-existing
> + * PCH transcoders B and C would prevent enabling the south
> + * error interrupt (see cpt_can_enable_serr_int()).
> + */
> + if (intel_has_pch_trancoder(i915, crtc->pipe))
> + crtc->pch_fifo_underrun_disabled = true;
> +}
> +
> +static void intel_sanitize_crtc(struct intel_crtc *crtc,
> + struct drm_modeset_acquire_ctx *ctx)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> + if (crtc_state->hw.active) {
> + struct intel_plane *plane;
> +
> + /* Disable everything but the primary plane */
> + for_each_intel_plane_on_crtc(dev, crtc, plane) {
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> +
> + if (plane_state->uapi.visible &&
> + plane->base.type != DRM_PLANE_TYPE_PRIMARY)
> + intel_plane_disable_noatomic(crtc, plane);
> + }
> +
> + /* Disable any background color/etc. set by the BIOS */
> + intel_color_commit_noarm(crtc_state);
> + intel_color_commit_arm(crtc_state);
> + }
> +
> + /*
> + * Adjust the state of the output pipe according to whether we have
> + * active connectors/encoders.
> + */
> + if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc) &&
> + !intel_crtc_is_bigjoiner_slave(crtc_state))
> + intel_crtc_disable_noatomic(crtc, ctx);
> +}
> +
> +static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> +
> + /*
> + * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
> + * the hardware when a high res displays plugged in. DPLL P
> + * divider is zero, and the pipe timings are bonkers. We'll
> + * try to disable everything in that case.
> + *
> + * FIXME would be nice to be able to sanitize this state
> + * without several WARNs, but for now let's take the easy
> + * road.
> + */
> + return IS_SANDYBRIDGE(dev_priv) &&
> + crtc_state->hw.active &&
> + crtc_state->shared_dpll &&
> + crtc_state->port_clock == 0;
> +}
> +
> +static void intel_sanitize_encoder(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_connector *connector;
> + struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> + struct intel_crtc_state *crtc_state = crtc ?
> + to_intel_crtc_state(crtc->base.state) : NULL;
> +
> + /*
> + * We need to check both for a crtc link (meaning that the encoder is
> + * active and trying to read from a pipe) and the pipe itself being
> + * active.
> + */
> + bool has_active_crtc = crtc_state &&
> + crtc_state->hw.active;
> +
> + if (crtc_state && has_bogus_dpll_config(crtc_state)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
> + pipe_name(crtc->pipe));
> + has_active_crtc = false;
> + }
> +
> + connector = intel_encoder_find_connector(encoder);
> + if (connector && !has_active_crtc) {
> + drm_dbg_kms(&dev_priv->drm,
> + "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
> + encoder->base.base.id,
> + encoder->base.name);
> +
> + /*
> + * Connector is active, but has no active pipe. This is fallout
> + * from our resume register restoring. Disable the encoder
> + * manually again.
> + */
> + if (crtc_state) {
> + struct drm_encoder *best_encoder;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[ENCODER:%d:%s] manually disabled\n",
> + encoder->base.base.id,
> + encoder->base.name);
> +
> + /* avoid oopsing in case the hooks consult best_encoder */
> + best_encoder = connector->base.state->best_encoder;
> + connector->base.state->best_encoder = &encoder->base;
> +
> + /* FIXME NULL atomic state passed! */
> + if (encoder->disable)
> + encoder->disable(NULL, encoder, crtc_state,
> + connector->base.state);
> + if (encoder->post_disable)
> + encoder->post_disable(NULL, encoder, crtc_state,
> + connector->base.state);
> +
> + connector->base.state->best_encoder = best_encoder;
> + }
> + encoder->base.crtc = NULL;
> +
> + /*
> + * Inconsistent output/port/pipe state happens presumably due to
> + * a bug in one of the get_hw_state functions. Or someplace else
> + * in our code, like the register restore mess on resume. Clamp
> + * things to off as a safer default.
> + */
> + connector->base.dpms = DRM_MODE_DPMS_OFF;
> + connector->base.encoder = NULL;
> + }
> +
> + /* notify opregion of the sanitized encoder state */
> + intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
> +
> + if (HAS_DDI(dev_priv))
> + intel_ddi_sanitize_encoder_pll_mapping(encoder);
> +}
> +
> +/* FIXME read out full plane state for all planes */
> +static void readout_plane_state(struct drm_i915_private *dev_priv)
> +{
> + struct intel_plane *plane;
> + struct intel_crtc *crtc;
> +
> + for_each_intel_plane(&dev_priv->drm, plane) {
> + struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> + struct intel_crtc_state *crtc_state;
> + enum pipe pipe = PIPE_A;
> + bool visible;
> +
> + visible = plane->get_hw_state(plane, &pipe);
> +
> + crtc = intel_crtc_for_pipe(dev_priv, pipe);
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> + intel_set_plane_visible(crtc_state, plane_state, visible);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
> + plane->base.base.id, plane->base.name,
> + str_enabled_disabled(visible), pipe_name(pipe));
> + }
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> +
> + intel_plane_fixup_bitmasks(crtc_state);
> + }
> +}
> +
> +static void intel_modeset_readout_hw_state(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_cdclk_state *cdclk_state =
> + to_intel_cdclk_state(dev_priv->cdclk.obj.state);
> + struct intel_dbuf_state *dbuf_state =
> + to_intel_dbuf_state(dev_priv->dbuf.obj.state);
> + enum pipe pipe;
> + struct intel_crtc *crtc;
> + struct intel_encoder *encoder;
> + struct intel_connector *connector;
> + struct drm_connector_list_iter conn_iter;
> + u8 active_pipes = 0;
> +
> + for_each_intel_crtc(dev, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> +
> + __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
> + intel_crtc_free_hw_state(crtc_state);
> + intel_crtc_state_reset(crtc_state, crtc);
> +
> + intel_crtc_get_pipe_config(crtc_state);
> +
> + crtc_state->hw.enable = crtc_state->hw.active;
> +
> + crtc->base.enabled = crtc_state->hw.enable;
> + crtc->active = crtc_state->hw.active;
> +
> + if (crtc_state->hw.active)
> + active_pipes |= BIT(crtc->pipe);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[CRTC:%d:%s] hw state readout: %s\n",
> + crtc->base.base.id, crtc->base.name,
> + str_enabled_disabled(crtc_state->hw.active));
> + }
> +
> + cdclk_state->active_pipes = active_pipes;
> + dbuf_state->active_pipes = active_pipes;
> +
> + readout_plane_state(dev_priv);
> +
> + for_each_intel_encoder(dev, encoder) {
> + struct intel_crtc_state *crtc_state = NULL;
> +
> + pipe = 0;
> +
> + if (encoder->get_hw_state(encoder, &pipe)) {
> + crtc = intel_crtc_for_pipe(dev_priv, pipe);
> + crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> + encoder->base.crtc = &crtc->base;
> + intel_encoder_get_config(encoder, crtc_state);
> +
> + /* read out to slave crtc as well for bigjoiner */
> + if (crtc_state->bigjoiner_pipes) {
> + struct intel_crtc *slave_crtc;
> +
> + /* encoder should read be linked to bigjoiner master */
> + WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
> +
> + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
> + intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
> + struct intel_crtc_state *slave_crtc_state;
> +
> + slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
> + intel_encoder_get_config(encoder, slave_crtc_state);
> + }
> + }
> + } else {
> + encoder->base.crtc = NULL;
> + }
> +
> + if (encoder->sync_state)
> + encoder->sync_state(encoder, crtc_state);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
> + encoder->base.base.id, encoder->base.name,
> + str_enabled_disabled(encoder->base.crtc),
> + pipe_name(pipe));
> + }
> +
> + intel_dpll_readout_hw_state(dev_priv);
> +
> + drm_connector_list_iter_begin(dev, &conn_iter);
> + for_each_intel_connector_iter(connector, &conn_iter) {
> + if (connector->get_hw_state(connector)) {
> + struct intel_crtc_state *crtc_state;
> + struct intel_crtc *crtc;
> +
> + connector->base.dpms = DRM_MODE_DPMS_ON;
> +
> + encoder = intel_attached_encoder(connector);
> + connector->base.encoder = &encoder->base;
> +
> + crtc = to_intel_crtc(encoder->base.crtc);
> + crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
> +
> + if (crtc_state && crtc_state->hw.active) {
> + /*
> + * This has to be done during hardware readout
> + * because anything calling .crtc_disable may
> + * rely on the connector_mask being accurate.
> + */
> + crtc_state->uapi.connector_mask |=
> + drm_connector_mask(&connector->base);
> + crtc_state->uapi.encoder_mask |=
> + drm_encoder_mask(&encoder->base);
> + }
> + } else {
> + connector->base.dpms = DRM_MODE_DPMS_OFF;
> + connector->base.encoder = NULL;
> + }
> + drm_dbg_kms(&dev_priv->drm,
> + "[CONNECTOR:%d:%s] hw state readout: %s\n",
> + connector->base.base.id, connector->base.name,
> + str_enabled_disabled(connector->base.encoder));
> + }
> + drm_connector_list_iter_end(&conn_iter);
> +
> + for_each_intel_crtc(dev, crtc) {
> + struct intel_bw_state *bw_state =
> + to_intel_bw_state(dev_priv->bw_obj.state);
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_plane *plane;
> + int min_cdclk = 0;
> +
> + if (crtc_state->hw.active) {
> + /*
> + * The initial mode needs to be set in order to keep
> + * the atomic core happy. It wants a valid mode if the
> + * crtc's enabled, so we do the above call.
> + *
> + * But we don't set all the derived state fully, hence
> + * set a flag to indicate that a full recalculation is
> + * needed on the next commit.
> + */
> + crtc_state->inherited = true;
> +
> + intel_crtc_update_active_timings(crtc_state);
> +
> + intel_crtc_copy_hw_to_uapi_state(crtc_state);
> + }
> +
> + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> + const struct intel_plane_state *plane_state =
> + to_intel_plane_state(plane->base.state);
> +
> + /*
> + * FIXME don't have the fb yet, so can't
> + * use intel_plane_data_rate() :(
> + */
> + if (plane_state->uapi.visible)
> + crtc_state->data_rate[plane->id] =
> + 4 * crtc_state->pixel_rate;
> + /*
> + * FIXME don't have the fb yet, so can't
> + * use plane->min_cdclk() :(
> + */
> + if (plane_state->uapi.visible && plane->min_cdclk) {
> + if (crtc_state->double_wide || DISPLAY_VER(dev_priv) >= 10)
> + crtc_state->min_cdclk[plane->id] =
> + DIV_ROUND_UP(crtc_state->pixel_rate, 2);
> + else
> + crtc_state->min_cdclk[plane->id] =
> + crtc_state->pixel_rate;
> + }
> + drm_dbg_kms(&dev_priv->drm,
> + "[PLANE:%d:%s] min_cdclk %d kHz\n",
> + plane->base.base.id, plane->base.name,
> + crtc_state->min_cdclk[plane->id]);
> + }
> +
> + if (crtc_state->hw.active) {
> + min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
> + if (drm_WARN_ON(dev, min_cdclk < 0))
> + min_cdclk = 0;
> + }
> +
> + cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
> + cdclk_state->min_voltage_level[crtc->pipe] =
> + crtc_state->min_voltage_level;
> +
> + intel_bw_crtc_update(bw_state, crtc_state);
> + }
> +}
> +
> +static void
> +get_encoder_power_domains(struct drm_i915_private *dev_priv)
> +{
> + struct intel_encoder *encoder;
> +
> + for_each_intel_encoder(&dev_priv->drm, encoder) {
> + struct intel_crtc_state *crtc_state;
> +
> + if (!encoder->get_power_domains)
> + continue;
> +
> + /*
> + * MST-primary and inactive encoders don't have a crtc state
> + * and neither of these require any power domain references.
> + */
> + if (!encoder->base.crtc)
> + continue;
> +
> + crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
> + encoder->get_power_domains(encoder, crtc_state);
> + }
> +}
> +
> +static void intel_early_display_was(struct drm_i915_private *dev_priv)
> +{
> + /*
> + * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
> + * Also known as Wa_14010480278.
> + */
> + if (IS_DISPLAY_VER(dev_priv, 10, 12))
> + intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0,
> + intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS);
> +
> + if (IS_HASWELL(dev_priv)) {
> + /*
> + * WaRsPkgCStateDisplayPMReq:hsw
> + * System hang if this isn't done before disabling all planes!
> + */
> + intel_de_write(dev_priv, CHICKEN_PAR1_1,
> + intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
> + }
> +
> + if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv)) {
> + /* Display WA #1142:kbl,cfl,cml */
> + intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> + KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
> + intel_de_rmw(dev_priv, CHICKEN_MISC_2,
> + KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
> + KBL_ARB_FILL_SPARE_14);
> + }
> +}
> +
> +void intel_modeset_setup_hw_state(struct drm_device *dev,
> + struct drm_modeset_acquire_ctx *ctx)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_encoder *encoder;
> + struct intel_crtc *crtc;
> + intel_wakeref_t wakeref;
> +
> + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> +
> + intel_early_display_was(dev_priv);
> + intel_modeset_readout_hw_state(dev);
> +
> + /* HW state is read out, now we need to sanitize this mess. */
> + get_encoder_power_domains(dev_priv);
> +
> + intel_pch_sanitize(dev_priv);
> +
> + /*
> + * intel_sanitize_plane_mapping() may need to do vblank
> + * waits, so we need vblank interrupts restored beforehand.
> + */
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> +
> + intel_sanitize_fifo_underrun_reporting(crtc_state);
> +
> + drm_crtc_vblank_reset(&crtc->base);
> +
> + if (crtc_state->hw.active)
> + intel_crtc_vblank_on(crtc_state);
> + }
> +
> + intel_fbc_sanitize(dev_priv);
> +
> + intel_sanitize_plane_mapping(dev_priv);
> +
> + for_each_intel_encoder(dev, encoder)
> + intel_sanitize_encoder(encoder);
> +
> + for_each_intel_crtc(&dev_priv->drm, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> +
> + intel_sanitize_crtc(crtc, ctx);
> + intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
> + }
> +
> + intel_modeset_update_connector_atomic_state(dev);
> +
> + intel_dpll_sanitize_state(dev_priv);
> +
> + if (IS_G4X(dev_priv)) {
> + g4x_wm_get_hw_state(dev_priv);
> + g4x_wm_sanitize(dev_priv);
> + } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> + vlv_wm_get_hw_state(dev_priv);
> + vlv_wm_sanitize(dev_priv);
> + } else if (DISPLAY_VER(dev_priv) >= 9) {
> + skl_wm_get_hw_state(dev_priv);
> + skl_wm_sanitize(dev_priv);
> + } else if (HAS_PCH_SPLIT(dev_priv)) {
> + ilk_wm_get_hw_state(dev_priv);
> + }
> +
> + for_each_intel_crtc(dev, crtc) {
> + struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> + struct intel_power_domain_mask put_domains;
> +
> + intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
> + if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
> + intel_modeset_put_crtc_power_domains(crtc, &put_domains);
> + }
> +
> + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
> +
> + intel_power_domains_sanitize_state(dev_priv);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.h b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
> new file mode 100644
> index 000000000000..c29b34c6a7b0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_MODESET_SETUP_H__
> +#define __INTEL_MODESET_SETUP_H__
> +
> +struct drm_device;
> +struct drm_modeset_acquire_ctx;
> +
> +void intel_modeset_setup_hw_state(struct drm_device *dev,
> + struct drm_modeset_acquire_ctx *ctx);
> +
> +#endif /* __INTEL_MODESET_SETUP_H__ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-06-20 16:38 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-17 9:48 [Intel-gfx] [PATCH 1/2] drm/i915/display: split out hw state readout and sanitize Jani Nikula
2022-06-17 9:48 ` [Intel-gfx] [PATCH 2/2] drm/i915/display: convert modeset setup to struct drm_i915_private *i915 Jani Nikula
2022-06-17 13:58 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/display: split out hw state readout and sanitize Patchwork
2022-06-17 13:58 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-17 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-17 22:11 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-06-20 16:37 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
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