[PATCH] riscv: config: enable SOC_STARFIVE in defconfig

[PATCH] riscv: config: enable SOC_STARFIVE in defconfig

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options
as it is not enabled in the default defconfig. Add it to make catching
dt regressions etc easier.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---

git send-email gave me an error that was unclear as to whether anything
got sent. Checked lore (and my inbox) but didn't see it come through so
hopefully this isn't a resend.

 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 0cc17db8aaba..f8d7d9527c6e 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -18,6 +18,7 @@ CONFIG_EXPERT=y
 CONFIG_PROFILING=y
 CONFIG_SOC_MICROCHIP_POLARFIRE=y
 CONFIG_SOC_SIFIVE=y
+CONFIG_SOC_STARFIVE=y
 CONFIG_SOC_VIRT=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
-- 
2.36.1


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Re: [PATCH] riscv: config: enable SOC_STARFIVE in defconfig

[Emil Renner Berthing]

On Fri, 17 Jun 2022 at 19:26, Conor Dooley <mail@conchuod.ie> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options
> as it is not enabled in the default defconfig. Add it to make catching
> dt regressions etc easier.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Thanks, this would be great.
Acked-by: Emil Renner Berthing <kernel@esmil.dk>

>
> git send-email gave me an error that was unclear as to whether anything
> got sent. Checked lore (and my inbox) but didn't see it come through so
> hopefully this isn't a resend.
>
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 0cc17db8aaba..f8d7d9527c6e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -18,6 +18,7 @@ CONFIG_EXPERT=y
>  CONFIG_PROFILING=y
>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>  CONFIG_SOC_SIFIVE=y
> +CONFIG_SOC_STARFIVE=y
>  CONFIG_SOC_VIRT=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y
> --
> 2.36.1
>

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Re: [PATCH] riscv: config: enable SOC_STARFIVE in defconfig

[Conor.Dooley]

Hey Palmer,
This should be good to take for 5.20.
Thanks,
Conor

On 20/06/2022 22:08, Emil Renner Berthing wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Fri, 17 Jun 2022 at 19:26, Conor Dooley <mail@conchuod.ie> wrote:
>> From: Conor Dooley <conor.dooley@microchip.com>
>>
>> SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options
>> as it is not enabled in the default defconfig. Add it to make catching
>> dt regressions etc easier.
>>
>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Thanks, this would be great.
> Acked-by: Emil Renner Berthing <kernel@esmil.dk>
> 
>>
>> git send-email gave me an error that was unclear as to whether anything
>> got sent. Checked lore (and my inbox) but didn't see it come through so
>> hopefully this isn't a resend.
>>
>>  arch/riscv/configs/defconfig | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
>> index 0cc17db8aaba..f8d7d9527c6e 100644
>> --- a/arch/riscv/configs/defconfig
>> +++ b/arch/riscv/configs/defconfig
>> @@ -18,6 +18,7 @@ CONFIG_EXPERT=y
>>  CONFIG_PROFILING=y
>>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>>  CONFIG_SOC_SIFIVE=y
>> +CONFIG_SOC_STARFIVE=y
>>  CONFIG_SOC_VIRT=y
>>  CONFIG_SMP=y
>>  CONFIG_HOTPLUG_CPU=y
>> --
>> 2.36.1
>>

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Re: [PATCH] riscv: config: enable SOC_STARFIVE in defconfig

[Palmer Dabbelt]

On Fri, 17 Jun 2022 11:24:25 PDT (-0700), mail@conchuod.ie wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options
> as it is not enabled in the default defconfig. Add it to make catching
> dt regressions etc easier.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>
> git send-email gave me an error that was unclear as to whether anything
> got sent. Checked lore (and my inbox) but didn't see it come through so
> hopefully this isn't a resend.
>
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 0cc17db8aaba..f8d7d9527c6e 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -18,6 +18,7 @@ CONFIG_EXPERT=y
>  CONFIG_PROFILING=y
>  CONFIG_SOC_MICROCHIP_POLARFIRE=y
>  CONFIG_SOC_SIFIVE=y
> +CONFIG_SOC_STARFIVE=y
>  CONFIG_SOC_VIRT=y
>  CONFIG_SMP=y
>  CONFIG_HOTPLUG_CPU=y

Thanks, this is on for-next.

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