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From: Serge Semin <fancer.lancer@gmail.com>
To: Conor Dooley <mail@conchuod.ie>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Sam Ravnborg <sam@ravnborg.org>,
	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
	Vinod Koul <vkoul@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Damien Le Moal <damien.lemoal@opensource.wdc.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Niklas Cassel <niklas.cassel@wdc.com>,
	Dillon Min <dillon.minfei@gmail.com>,
	Heng Sia <jee.heng.sia@intel.com>,
	Jose Abreu <joabreu@synopsys.com>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
	alsa-devel@alsa-project.org, linux-spi@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
Date: Mon, 20 Jun 2022 23:56:54 +0300	[thread overview]
Message-ID: <20220620205654.g7fyipwytbww5757@mobilestation> (raw)
In-Reply-To: <20220618123035.563070-7-mail@conchuod.ie>

On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/spi/snps,dw-apb-ssi.yaml         | 48 ++++++++++++++-----
>  1 file changed, 35 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
>        of the designware controller, and the upper limit is also subject to
>        controller configuration.
>  
> -patternProperties:
> -  "^.*@[0-9a-f]+$":
> -    type: object
> -    properties:
> -      reg:
> -        minimum: 0
> -        maximum: 3
> -
> -      spi-rx-bus-width:
> -        const: 1
> -
> -      spi-tx-bus-width:
> -        const: 1
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: snps,dwc-ssi-1.01a
> +
> +then:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 4
> +
> +        spi-tx-bus-width:
> +          const: 4
> +
> +else:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 1
> +
> +        spi-tx-bus-width:
> +          const: 1

You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.

Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.

-Sergey

>  
>  unevaluatedProperties: false
>  
> -- 
> 2.36.1
> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Serge Semin <fancer.lancer@gmail.com>
To: Conor Dooley <mail@conchuod.ie>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Sam Ravnborg <sam@ravnborg.org>,
	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
	Vinod Koul <vkoul@kernel.org>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Mark Brown <broonie@kernel.org>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Masahiro Yamada <masahiroy@kernel.org>,
	Damien Le Moal <damien.lemoal@opensource.wdc.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Niklas Cassel <niklas.cassel@wdc.com>,
	Dillon Min <dillon.minfei@gmail.com>,
	Heng Sia <jee.heng.sia@intel.com>,
	Jose Abreu <joabreu@synopsys.com>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
	alsa-devel@alsa-project.org, linux-spi@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
Date: Mon, 20 Jun 2022 23:56:54 +0300	[thread overview]
Message-ID: <20220620205654.g7fyipwytbww5757@mobilestation> (raw)
In-Reply-To: <20220618123035.563070-7-mail@conchuod.ie>

On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/spi/snps,dw-apb-ssi.yaml         | 48 ++++++++++++++-----
>  1 file changed, 35 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
>        of the designware controller, and the upper limit is also subject to
>        controller configuration.
>  
> -patternProperties:
> -  "^.*@[0-9a-f]+$":
> -    type: object
> -    properties:
> -      reg:
> -        minimum: 0
> -        maximum: 3
> -
> -      spi-rx-bus-width:
> -        const: 1
> -
> -      spi-tx-bus-width:
> -        const: 1
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: snps,dwc-ssi-1.01a
> +
> +then:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 4
> +
> +        spi-tx-bus-width:
> +          const: 4
> +
> +else:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 1
> +
> +        spi-tx-bus-width:
> +          const: 1

You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.

Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.

-Sergey

>  
>  unevaluatedProperties: false
>  
> -- 
> 2.36.1
> 

WARNING: multiple messages have this Message-ID (diff)
From: Serge Semin <fancer.lancer@gmail.com>
To: Conor Dooley <mail@conchuod.ie>
Cc: Niklas Cassel <niklas.cassel@wdc.com>,
	alsa-devel@alsa-project.org, David Airlie <airlied@linux.ie>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-riscv@lists.infradead.org, Sam Ravnborg <sam@ravnborg.org>,
	Damien Le Moal <damien.lemoal@opensource.wdc.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jose Abreu <joabreu@synopsys.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
	devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	Mark Brown <broonie@kernel.org>,
	dri-devel@lists.freedesktop.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Dillon Min <dillon.minfei@gmail.com>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Heng Sia <jee.heng.sia@intel.com>,
	linux-spi@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	dmaengine@vger.kernel.org, Masahiro Yamada <masahiroy@kernel.org>
Subject: Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
Date: Mon, 20 Jun 2022 23:56:54 +0300	[thread overview]
Message-ID: <20220620205654.g7fyipwytbww5757@mobilestation> (raw)
In-Reply-To: <20220618123035.563070-7-mail@conchuod.ie>

On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/spi/snps,dw-apb-ssi.yaml         | 48 ++++++++++++++-----
>  1 file changed, 35 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
>        of the designware controller, and the upper limit is also subject to
>        controller configuration.
>  
> -patternProperties:
> -  "^.*@[0-9a-f]+$":
> -    type: object
> -    properties:
> -      reg:
> -        minimum: 0
> -        maximum: 3
> -
> -      spi-rx-bus-width:
> -        const: 1
> -
> -      spi-tx-bus-width:
> -        const: 1
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: snps,dwc-ssi-1.01a
> +
> +then:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 4
> +
> +        spi-tx-bus-width:
> +          const: 4
> +
> +else:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 1
> +
> +        spi-tx-bus-width:
> +          const: 1

You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.

Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.

-Sergey

>  
>  unevaluatedProperties: false
>  
> -- 
> 2.36.1
> 

WARNING: multiple messages have this Message-ID (diff)
From: Serge Semin <fancer.lancer@gmail.com>
To: Conor Dooley <mail@conchuod.ie>
Cc: Niklas Cassel <niklas.cassel@wdc.com>,
	alsa-devel@alsa-project.org, David Airlie <airlied@linux.ie>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	linux-kernel@vger.kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	linux-riscv@lists.infradead.org, Sam Ravnborg <sam@ravnborg.org>,
	Damien Le Moal <damien.lemoal@opensource.wdc.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Jose Abreu <joabreu@synopsys.com>,
	Geert Uytterhoeven <geert@linux-m68k.org>,
	Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
	devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>,
	Mark Brown <broonie@kernel.org>,
	dri-devel@lists.freedesktop.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Dillon Min <dillon.minfei@gmail.com>,
	Liam Girdwood <lgirdwood@gmail.com>,
	Heng Sia <jee.heng.sia@intel.com>,
	linux-spi@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	dmaengine@vger.kernel.org, Masahiro Yamada <masahiroy@kernel.org>
Subject: Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi
Date: Mon, 20 Jun 2022 23:56:54 +0300	[thread overview]
Message-ID: <20220620205654.g7fyipwytbww5757@mobilestation> (raw)
In-Reply-To: <20220618123035.563070-7-mail@conchuod.ie>

On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a
> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect
> this.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../bindings/spi/snps,dw-apb-ssi.yaml         | 48 ++++++++++++++-----
>  1 file changed, 35 insertions(+), 13 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index e25d44c218f2..f2b9e3f062cd 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -135,19 +135,41 @@ properties:
>        of the designware controller, and the upper limit is also subject to
>        controller configuration.
>  
> -patternProperties:
> -  "^.*@[0-9a-f]+$":
> -    type: object
> -    properties:
> -      reg:
> -        minimum: 0
> -        maximum: 3
> -
> -      spi-rx-bus-width:
> -        const: 1
> -
> -      spi-tx-bus-width:
> -        const: 1
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: snps,dwc-ssi-1.01a
> +
> +then:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 4
> +
> +        spi-tx-bus-width:
> +          const: 4
> +
> +else:
> +  patternProperties:
> +    "^.*@[0-9a-f]+$":
> +      type: object
> +      properties:
> +        reg:
> +          minimum: 0
> +          maximum: 3
> +
> +        spi-rx-bus-width:
> +          const: 1
> +
> +        spi-tx-bus-width:
> +          const: 1

You can just use a more relaxed constraint "enum: [1 2 4 8]" here
irrespective from the compatible string. The modern DW APB SSI
controllers of v.4.* and newer also support the enhanced SPI Modes too
(Dual, Quad and Octal). Since the IP-core version is auto-detected at
run-time there is no way to create a DT-schema correctly constraining
the Rx/Tx SPI bus widths. So let's keep the
compatible-string-independent "patternProperties" here but just extend
the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width"
properties values.

Note the DW APB SSI/AHB SSI driver currently doesn't support the
enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI
bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the
DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly
activated by means of the corresponding CSR. So most likely the DW AHB
SSI controllers need some specific setups too.

-Sergey

>  
>  unevaluatedProperties: false
>  
> -- 
> 2.36.1
> 

  parent reply	other threads:[~2022-06-20 20:57 UTC|newest]

Thread overview: 159+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-18 12:30 [PATCH 00/14] Canaan devicetree fixes Conor Dooley
2022-06-18 12:30 ` Conor Dooley
2022-06-18 12:30 ` Conor Dooley
2022-06-18 12:30 ` [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt to dt-schema Conor Dooley
2022-06-18 12:30   ` [PATCH 01/14] dt-bindings: display: convert ilitek, ili9341.txt " Conor Dooley
2022-06-18 12:30   ` [PATCH 01/14] dt-bindings: display: convert ilitek,ili9341.txt " Conor Dooley
2022-06-27 23:20   ` Rob Herring
2022-06-27 23:20     ` Rob Herring
2022-06-27 23:20     ` Rob Herring
2022-06-18 12:30 ` [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 in isolation Conor Dooley
2022-06-18 12:30   ` [PATCH 02/14] dt-bindings: display: panel: allow ilitek, ili9341 " Conor Dooley
2022-06-18 12:30   ` [PATCH 02/14] dt-bindings: display: panel: allow ilitek,ili9341 " Conor Dooley
2022-06-27 23:17   ` Rob Herring
2022-06-27 23:17     ` Rob Herring
2022-06-27 23:17     ` Rob Herring
2022-06-28  6:26     ` Conor.Dooley
2022-06-28  6:26       ` Conor.Dooley
2022-06-28  6:26       ` Conor.Dooley
2022-06-18 12:30 ` [PATCH 03/14] ASoC: dt-bindings: convert designware-i2s to dt-schema Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-27 23:22   ` Rob Herring
2022-06-27 23:22     ` Rob Herring
2022-06-27 23:22     ` Rob Herring
2022-06-18 12:30 ` [PATCH 04/14] dt-bindings: dma: add Canaan k210 to Synopsys DesignWare DMA Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-27 23:29   ` Rob Herring
2022-06-27 23:29     ` Rob Herring
2022-06-27 23:29     ` Rob Herring
2022-06-28  6:30     ` Conor.Dooley
2022-06-28  6:30       ` Conor.Dooley
2022-06-28  6:30       ` Conor.Dooley
2022-06-28  7:08       ` Geert Uytterhoeven
2022-06-28  7:08         ` Geert Uytterhoeven
2022-06-28  7:08         ` Geert Uytterhoeven
2022-06-28  7:13         ` Conor.Dooley
2022-06-28  7:13           ` Conor.Dooley
2022-06-28  7:13           ` Conor.Dooley
2022-06-28 11:04         ` Serge Semin
2022-06-28 11:04           ` Serge Semin
2022-06-28 11:04           ` Serge Semin
2022-06-18 12:30 ` [PATCH 05/14] dt-bindings: timer: add Canaan k210 to Synopsys DesignWare timer Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-27 23:30   ` Rob Herring
2022-06-27 23:30     ` Rob Herring
2022-06-27 23:30     ` Rob Herring
2022-06-28 11:06     ` Serge Semin
2022-06-28 11:06       ` Serge Semin
2022-06-28 11:06       ` Serge Semin
2022-06-18 12:30 ` [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi Conor Dooley
2022-06-18 12:30   ` [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r, t}x-bus-width " Conor Dooley
2022-06-18 12:30   ` [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width " Conor Dooley
2022-06-20  8:02   ` Geert Uytterhoeven
2022-06-20  8:02     ` Geert Uytterhoeven
2022-06-20  8:02     ` Geert Uytterhoeven
2022-06-20  8:02     ` Geert Uytterhoeven
2022-06-20  8:47     ` Conor.Dooley
2022-06-20  8:47       ` Conor.Dooley
2022-06-20  8:47       ` Conor.Dooley
2022-06-20  8:47       ` Conor.Dooley
2022-06-20 20:56   ` Serge Semin [this message]
2022-06-20 20:56     ` Serge Semin
2022-06-20 20:56     ` Serge Semin
2022-06-20 20:56     ` Serge Semin
2022-06-20 21:06     ` Conor.Dooley
2022-06-20 21:06       ` Conor.Dooley
2022-06-20 21:06       ` Conor.Dooley
2022-06-20 21:06       ` Conor.Dooley
2022-06-20 22:46       ` Damien Le Moal
2022-06-20 22:46         ` Damien Le Moal
2022-06-20 22:46         ` Damien Le Moal
2022-06-20 22:46         ` Damien Le Moal
2022-06-20 22:49         ` Conor Dooley
2022-06-20 22:49           ` Conor Dooley
2022-06-20 22:49           ` Conor Dooley
2022-06-20 22:49           ` Conor Dooley
2022-06-20 23:17           ` Damien Le Moal
2022-06-20 23:17             ` Damien Le Moal
2022-06-20 23:17             ` Damien Le Moal
2022-06-20 23:17             ` Damien Le Moal
2022-06-21 16:06             ` Conor.Dooley
2022-06-21 16:06               ` Conor.Dooley
2022-06-21 16:06               ` Conor.Dooley
2022-06-21 16:06               ` Conor.Dooley
2022-06-23 10:25               ` Serge Semin
2022-06-23 10:25                 ` Serge Semin
2022-06-23 10:25                 ` Serge Semin
2022-06-23 10:25                 ` Serge Semin
2022-06-23 12:41                 ` Conor Dooley
2022-06-23 12:41                   ` Conor Dooley
2022-06-23 12:41                   ` Conor Dooley
2022-06-27 17:15       ` Rob Herring
2022-06-27 17:15         ` Rob Herring
2022-06-27 17:15         ` Rob Herring
2022-06-27 18:05         ` Conor.Dooley
2022-06-27 18:05           ` Conor.Dooley
2022-06-27 18:05           ` Conor.Dooley
2022-06-21  7:03     ` Geert Uytterhoeven
2022-06-21  7:03       ` Geert Uytterhoeven
2022-06-21  7:03       ` Geert Uytterhoeven
2022-06-21  7:03       ` Geert Uytterhoeven
2022-06-21  9:32       ` Serge Semin
2022-06-21  9:32         ` Serge Semin
2022-06-21  9:32         ` Serge Semin
2022-06-21  9:32         ` Serge Semin
2022-06-18 12:30 ` [PATCH 07/14] riscv: dts: canaan: fix the k210's memory node Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:35   ` Conor.Dooley
2022-06-18 12:35     ` Conor.Dooley
2022-06-18 12:35     ` Conor.Dooley
2022-06-19 23:38   ` Damien Le Moal
2022-06-19 23:38     ` Damien Le Moal
2022-06-19 23:38     ` Damien Le Moal
2022-06-19 23:54     ` Conor.Dooley
2022-06-19 23:54       ` Conor.Dooley
2022-06-19 23:54       ` Conor.Dooley
2022-06-20  0:25       ` Damien Le Moal
2022-06-20  0:25         ` Damien Le Moal
2022-06-20  0:25         ` Damien Le Moal
2022-06-21  9:49         ` Conor.Dooley
2022-06-21  9:49           ` Conor.Dooley
2022-06-21  9:49           ` Conor.Dooley
2022-06-21  9:49           ` Conor.Dooley
2022-06-27  6:55           ` Krzysztof Kozlowski
2022-06-27  6:55             ` Krzysztof Kozlowski
2022-06-27  6:55             ` Krzysztof Kozlowski
2022-06-27  7:06             ` Conor.Dooley
2022-06-27  7:06               ` Conor.Dooley
2022-06-27  7:06               ` Conor.Dooley
2022-06-27  9:24               ` Krzysztof Kozlowski
2022-06-27  9:24                 ` Krzysztof Kozlowski
2022-06-27  9:24                 ` Krzysztof Kozlowski
2022-06-27 11:03                 ` Conor.Dooley
2022-06-27 11:03                   ` Conor.Dooley
2022-06-27 11:03                   ` Conor.Dooley
2022-06-18 12:30 ` [PATCH 08/14] riscv: dts: canaan: add a specific compatible for k210's dma Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30 ` [PATCH 09/14] riscv: dts: canaan: add a specific compatible for k210's timers Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30 ` [PATCH 10/14] riscv: dts: canaan: fix mmc node names Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30 ` [PATCH 11/14] riscv: dts: canaan: fix kd233 display spi frequency Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30 ` [PATCH 12/14] riscv: dts: canaan: use custom compatible for k210 i2s Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30 ` [PATCH 13/14] riscv: dts: canaan: remove spi-max-frequency from controllers Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30 ` [PATCH 14/14] riscv: dts: canaan: build all devicetress if SOC_CANAAN Conor Dooley
2022-06-18 12:30   ` Conor Dooley
2022-06-18 12:30   ` Conor Dooley

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