* [PATCH v3 1/8] ppc/pnv: move root port attach to pnv_phb4_realize()
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 2/8] ppc/pnv: attach phb3/phb4 root ports in QOM tree Daniel Henrique Barboza
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
Creating a root port is something related to the PHB, not the PEC. It
also makes the logic more in line with what pnv-phb3 does.
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb4.c | 4 ++++
hw/pci-host/pnv_phb4_pec.c | 3 ---
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 6594016121..23ad8de7ee 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1547,6 +1547,7 @@ static void pnv_phb4_instance_init(Object *obj)
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(phb->pec);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XiveSource *xsrc = &phb->xsrc;
int nr_irqs;
@@ -1583,6 +1584,9 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb);
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
+ /* Add a single Root port if running with defaults */
+ pnv_phb_attach_root_port(pci, pecc->rp_model);
+
/* Setup XIVE Source */
if (phb->big_phb) {
nr_irqs = PNV_PHB4_MAX_INTs;
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 8b7e823fa5..c9aaf1c28e 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -130,9 +130,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
return;
}
-
- /* Add a single Root port if running with defaults */
- pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model);
}
static void pnv_pec_realize(DeviceState *dev, Error **errp)
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/8] ppc/pnv: attach phb3/phb4 root ports in QOM tree
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 1/8] ppc/pnv: move root port attach to pnv_phb4_realize() Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier Daniel Henrique Barboza
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
At this moment we leave the pnv-phb3(4)-root-port unattached in QOM:
/unattached (container)
(...)
/device[2] (pnv-phb3-root-port)
/bus master container[0] (memory-region)
/bus master[0] (memory-region)
/pci_bridge_io[0] (memory-region)
/pci_bridge_io[1] (memory-region)
/pci_bridge_mem[0] (memory-region)
/pci_bridge_pci[0] (memory-region)
/pci_bridge_pref_mem[0] (memory-region)
/pci_bridge_vga_io_hi[0] (memory-region)
/pci_bridge_vga_io_lo[0] (memory-region)
/pci_bridge_vga_mem[0] (memory-region)
/pcie.0 (PCIE)
Let's make changes in pnv_phb_attach_root_port() to attach the created
root ports to its corresponding PHB.
This is the result afterwards:
/pnv-phb3[0] (pnv-phb3)
/lsi (ics)
/msi (phb3-msi)
/msi32[0] (memory-region)
/msi64[0] (memory-region)
/pbcq (pnv-pbcq)
(...)
/phb3_iommu[0] (pnv-phb3-iommu-memory-region)
/pnv-phb3-root.0 (pnv-phb3-root)
/pnv-phb3-root-port[0] (pnv-phb3-root-port)
/bus master container[0] (memory-region)
/bus master[0] (memory-region)
/pci_bridge_io[0] (memory-region)
/pci_bridge_io[1] (memory-region)
/pci_bridge_mem[0] (memory-region)
/pci_bridge_pci[0] (memory-region)
/pci_bridge_pref_mem[0] (memory-region)
/pci_bridge_vga_io_hi[0] (memory-region)
/pci_bridge_vga_io_lo[0] (memory-region)
/pci_bridge_vga_mem[0] (memory-region)
/pcie.0 (PCIE)
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb3.c | 2 +-
hw/pci-host/pnv_phb4.c | 2 +-
hw/ppc/pnv.c | 7 ++++++-
include/hw/ppc/pnv.h | 2 +-
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 26ac9b7123..4ba660f8b9 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1052,7 +1052,7 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
- pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB3_ROOT_PORT);
+ pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT, phb->phb_id);
}
void pnv_phb3_update_regions(PnvPHB3 *phb)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 23ad8de7ee..ffd9d8a947 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1585,7 +1585,7 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
/* Add a single Root port if running with defaults */
- pnv_phb_attach_root_port(pci, pecc->rp_model);
+ pnv_phb_attach_root_port(pci, pecc->rp_model, phb->phb_id);
/* Setup XIVE Source */
if (phb->big_phb) {
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 7c08a78d6c..40e0cbd84d 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1190,9 +1190,14 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
}
/* Attach a root port device */
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name)
+void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
{
PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
+ g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
+ const char *dev_id = DEVICE(root)->id;
+
+ object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
+ OBJECT(root));
pci_realize_and_unref(root, pci->bus, &error_fatal);
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 86cb7d7f97..033890a23f 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -189,7 +189,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name);
+void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 1/8] ppc/pnv: move root port attach to pnv_phb4_realize() Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 2/8] ppc/pnv: attach phb3/phb4 root ports in QOM tree Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-22 6:20 ` Cédric Le Goater
2022-06-22 10:06 ` Frederic Barrat
2022-06-21 17:34 ` [PATCH v3 4/8] ppc/pnv: make pnv_ics_get() use the chip8->phbs[] array Daniel Henrique Barboza
` (5 subsequent siblings)
8 siblings, 2 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
It is not advisable to execute an object_dynamic_cast() to poke into
bus->qbus.parent and follow it up with a C cast into the PnvPHB type we
think we got.
In fact this is not needed. There is nothing sophisticated being done
with the PHB object retrieved during root_port_realize() for both
PHB3 and PHB4. We're retrieving a PHB reference PHB just to access
phb->chip_id and phb->phb_id and use them to define the chassis/slot
of the root port.
phb->phb_id is already being passed to pnv_phb_attach_root_port() via
the 'index' parameter. Let's also add a 'chip_id' parameter to this
function and assign chassis and slot right there. This will spare us
from the hassle of accessing the PHB object inside realize().
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb3.c | 18 ++----------------
hw/pci-host/pnv_phb4.c | 18 ++----------------
hw/ppc/pnv.c | 15 +++++++++++++--
include/hw/ppc/pnv.h | 3 ++-
4 files changed, 19 insertions(+), 35 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 4ba660f8b9..afe5698167 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1052,7 +1052,8 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
- pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT, phb->phb_id);
+ pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
+ phb->phb_id, phb->chip_id);
}
void pnv_phb3_update_regions(PnvPHB3 *phb)
@@ -1139,23 +1140,8 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
PCIDevice *pci = PCI_DEVICE(dev);
- PCIBus *bus = pci_get_bus(pci);
- PnvPHB3 *phb = NULL;
Error *local_err = NULL;
- phb = (PnvPHB3 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
- TYPE_PNV_PHB3);
-
- if (!phb) {
- error_setg(errp,
-"pnv_phb3_root_port devices must be connected to pnv-phb3 buses");
- return;
- }
-
- /* Set unique chassis/slot values for the root port */
- qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
- qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
-
rpc->parent_realize(dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index ffd9d8a947..725b3d740b 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1585,7 +1585,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
/* Add a single Root port if running with defaults */
- pnv_phb_attach_root_port(pci, pecc->rp_model, phb->phb_id);
+ pnv_phb_attach_root_port(pci, pecc->rp_model,
+ phb->phb_id, phb->chip_id);
/* Setup XIVE Source */
if (phb->big_phb) {
@@ -1781,23 +1782,8 @@ static void pnv_phb4_root_port_reset(DeviceState *dev)
static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
{
PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
- PCIDevice *pci = PCI_DEVICE(dev);
- PCIBus *bus = pci_get_bus(pci);
- PnvPHB4 *phb = NULL;
Error *local_err = NULL;
- phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
- TYPE_PNV_PHB4);
-
- if (!phb) {
- error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id);
- return;
- }
-
- /* Set unique chassis/slot values for the root port */
- qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
- qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
-
rpc->parent_realize(dev, &local_err);
if (local_err) {
error_propagate(errp, local_err);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 40e0cbd84d..c5e63bede7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1189,8 +1189,15 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
}
}
-/* Attach a root port device */
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
+/*
+ * Attach a root port device.
+ *
+ * 'index' will be used both as a PCIE slot value and to calculate
+ * QOM id. 'chip_id' is going to be used as PCIE chassis for the
+ * root port.
+ */
+void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
+ int index, int chip_id)
{
PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
@@ -1199,6 +1206,10 @@ void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
OBJECT(root));
+ /* Set unique chassis/slot values for the root port */
+ qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
+ qdev_prop_set_uint16(DEVICE(root), "slot", index);
+
pci_realize_and_unref(root, pci->bus, &error_fatal);
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 033890a23f..b991194223 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -189,7 +189,8 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
TYPE_PNV_CHIP_POWER10)
PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
-void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index);
+void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
+ int index, int chip_id);
#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
typedef struct PnvMachineClass PnvMachineClass;
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier
2022-06-21 17:34 ` [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier Daniel Henrique Barboza
@ 2022-06-22 6:20 ` Cédric Le Goater
2022-06-22 10:06 ` Frederic Barrat
1 sibling, 0 replies; 12+ messages in thread
From: Cédric Le Goater @ 2022-06-22 6:20 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, fbarrat
On 6/21/22 19:34, Daniel Henrique Barboza wrote:
> It is not advisable to execute an object_dynamic_cast() to poke into
> bus->qbus.parent and follow it up with a C cast into the PnvPHB type we
> think we got.
>
> In fact this is not needed. There is nothing sophisticated being done
> with the PHB object retrieved during root_port_realize() for both
> PHB3 and PHB4. We're retrieving a PHB reference PHB just to access
> phb->chip_id and phb->phb_id and use them to define the chassis/slot
> of the root port.
>
> phb->phb_id is already being passed to pnv_phb_attach_root_port() via
> the 'index' parameter. Let's also add a 'chip_id' parameter to this
> function and assign chassis and slot right there. This will spare us
> from the hassle of accessing the PHB object inside realize().
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/pci-host/pnv_phb3.c | 18 ++----------------
> hw/pci-host/pnv_phb4.c | 18 ++----------------
> hw/ppc/pnv.c | 15 +++++++++++++--
> include/hw/ppc/pnv.h | 3 ++-
> 4 files changed, 19 insertions(+), 35 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index 4ba660f8b9..afe5698167 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -1052,7 +1052,8 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
>
> pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
>
> - pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT, phb->phb_id);
> + pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
> + phb->phb_id, phb->chip_id);
> }
>
> void pnv_phb3_update_regions(PnvPHB3 *phb)
> @@ -1139,23 +1140,8 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
> {
> PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> PCIDevice *pci = PCI_DEVICE(dev);
> - PCIBus *bus = pci_get_bus(pci);
> - PnvPHB3 *phb = NULL;
> Error *local_err = NULL;
>
> - phb = (PnvPHB3 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
> - TYPE_PNV_PHB3);
> -
> - if (!phb) {
> - error_setg(errp,
> -"pnv_phb3_root_port devices must be connected to pnv-phb3 buses");
> - return;
> - }
> -
> - /* Set unique chassis/slot values for the root port */
> - qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
> - qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
> -
> rpc->parent_realize(dev, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index ffd9d8a947..725b3d740b 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1585,7 +1585,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
> pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
>
> /* Add a single Root port if running with defaults */
> - pnv_phb_attach_root_port(pci, pecc->rp_model, phb->phb_id);
> + pnv_phb_attach_root_port(pci, pecc->rp_model,
> + phb->phb_id, phb->chip_id);
>
> /* Setup XIVE Source */
> if (phb->big_phb) {
> @@ -1781,23 +1782,8 @@ static void pnv_phb4_root_port_reset(DeviceState *dev)
> static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
> {
> PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> - PCIDevice *pci = PCI_DEVICE(dev);
> - PCIBus *bus = pci_get_bus(pci);
> - PnvPHB4 *phb = NULL;
> Error *local_err = NULL;
>
> - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
> - TYPE_PNV_PHB4);
> -
> - if (!phb) {
> - error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id);
> - return;
> - }
> -
> - /* Set unique chassis/slot values for the root port */
> - qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
> - qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
> -
> rpc->parent_realize(dev, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 40e0cbd84d..c5e63bede7 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1189,8 +1189,15 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
> }
> }
>
> -/* Attach a root port device */
> -void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
> +/*
> + * Attach a root port device.
> + *
> + * 'index' will be used both as a PCIE slot value and to calculate
> + * QOM id. 'chip_id' is going to be used as PCIE chassis for the
> + * root port.
> + */
> +void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
> + int index, int chip_id)
> {
> PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
> g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
> @@ -1199,6 +1206,10 @@ void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
> object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
> OBJECT(root));
>
> + /* Set unique chassis/slot values for the root port */
> + qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
> + qdev_prop_set_uint16(DEVICE(root), "slot", index);
> +
> pci_realize_and_unref(root, pci->bus, &error_fatal);
> }
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 033890a23f..b991194223 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -189,7 +189,8 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
> TYPE_PNV_CHIP_POWER10)
>
> PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
> -void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index);
> +void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
> + int index, int chip_id);
>
> #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
> typedef struct PnvMachineClass PnvMachineClass;
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier
2022-06-21 17:34 ` [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier Daniel Henrique Barboza
2022-06-22 6:20 ` Cédric Le Goater
@ 2022-06-22 10:06 ` Frederic Barrat
1 sibling, 0 replies; 12+ messages in thread
From: Frederic Barrat @ 2022-06-22 10:06 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel; +Cc: qemu-ppc, clg
On 21/06/2022 19:34, Daniel Henrique Barboza wrote:
> It is not advisable to execute an object_dynamic_cast() to poke into
> bus->qbus.parent and follow it up with a C cast into the PnvPHB type we
> think we got.
>
> In fact this is not needed. There is nothing sophisticated being done
> with the PHB object retrieved during root_port_realize() for both
> PHB3 and PHB4. We're retrieving a PHB reference PHB just to access
> phb->chip_id and phb->phb_id and use them to define the chassis/slot
> of the root port.
>
> phb->phb_id is already being passed to pnv_phb_attach_root_port() via
> the 'index' parameter. Let's also add a 'chip_id' parameter to this
> function and assign chassis and slot right there. This will spare us
> from the hassle of accessing the PHB object inside realize().
>
> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> hw/pci-host/pnv_phb3.c | 18 ++----------------
> hw/pci-host/pnv_phb4.c | 18 ++----------------
> hw/ppc/pnv.c | 15 +++++++++++++--
> include/hw/ppc/pnv.h | 3 ++-
> 4 files changed, 19 insertions(+), 35 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
> index 4ba660f8b9..afe5698167 100644
> --- a/hw/pci-host/pnv_phb3.c
> +++ b/hw/pci-host/pnv_phb3.c
> @@ -1052,7 +1052,8 @@ static void pnv_phb3_realize(DeviceState *dev, Error **errp)
>
> pci_setup_iommu(pci->bus, pnv_phb3_dma_iommu, phb);
>
> - pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT, phb->phb_id);
> + pnv_phb_attach_root_port(pci, TYPE_PNV_PHB3_ROOT_PORT,
> + phb->phb_id, phb->chip_id);
> }
>
> void pnv_phb3_update_regions(PnvPHB3 *phb)
> @@ -1139,23 +1140,8 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
> {
> PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> PCIDevice *pci = PCI_DEVICE(dev);
> - PCIBus *bus = pci_get_bus(pci);
> - PnvPHB3 *phb = NULL;
> Error *local_err = NULL;
>
> - phb = (PnvPHB3 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
> - TYPE_PNV_PHB3);
> -
> - if (!phb) {
> - error_setg(errp,
> -"pnv_phb3_root_port devices must be connected to pnv-phb3 buses");
> - return;
> - }
> -
> - /* Set unique chassis/slot values for the root port */
> - qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
> - qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
> -
> rpc->parent_realize(dev, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index ffd9d8a947..725b3d740b 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -1585,7 +1585,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp)
> pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE;
>
> /* Add a single Root port if running with defaults */
> - pnv_phb_attach_root_port(pci, pecc->rp_model, phb->phb_id);
> + pnv_phb_attach_root_port(pci, pecc->rp_model,
> + phb->phb_id, phb->chip_id);
>
> /* Setup XIVE Source */
> if (phb->big_phb) {
> @@ -1781,23 +1782,8 @@ static void pnv_phb4_root_port_reset(DeviceState *dev)
> static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
> {
> PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
> - PCIDevice *pci = PCI_DEVICE(dev);
> - PCIBus *bus = pci_get_bus(pci);
> - PnvPHB4 *phb = NULL;
> Error *local_err = NULL;
>
> - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent),
> - TYPE_PNV_PHB4);
> -
> - if (!phb) {
> - error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id);
> - return;
> - }
> -
> - /* Set unique chassis/slot values for the root port */
> - qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id);
> - qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id);
> -
> rpc->parent_realize(dev, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 40e0cbd84d..c5e63bede7 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1189,8 +1189,15 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
> }
> }
>
> -/* Attach a root port device */
> -void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
> +/*
> + * Attach a root port device.
> + *
> + * 'index' will be used both as a PCIE slot value and to calculate
> + * QOM id. 'chip_id' is going to be used as PCIE chassis for the
> + * root port.
> + */
> +void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
> + int index, int chip_id)
> {
> PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
> g_autofree char *default_id = g_strdup_printf("%s[%d]", name, index);
> @@ -1199,6 +1206,10 @@ void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index)
> object_property_add_child(OBJECT(pci->bus), dev_id ? dev_id : default_id,
> OBJECT(root));
>
> + /* Set unique chassis/slot values for the root port */
> + qdev_prop_set_uint8(DEVICE(root), "chassis", chip_id);
> + qdev_prop_set_uint16(DEVICE(root), "slot", index);
> +
> pci_realize_and_unref(root, pci->bus, &error_fatal);
> }
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 033890a23f..b991194223 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -189,7 +189,8 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
> TYPE_PNV_CHIP_POWER10)
>
> PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
> -void pnv_phb_attach_root_port(PCIHostState *pci, const char *name, int index);
> +void pnv_phb_attach_root_port(PCIHostState *pci, const char *name,
> + int index, int chip_id);
>
> #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
> typedef struct PnvMachineClass PnvMachineClass;
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 4/8] ppc/pnv: make pnv_ics_get() use the chip8->phbs[] array
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
` (2 preceding siblings ...)
2022-06-21 17:34 ` [PATCH v3 3/8] ppc/pnv: assign pnv-phb-root-port chassis/slot earlier Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 5/8] ppc/pnv: make pnv_ics_resend() use chip8->phbs[] Daniel Henrique Barboza
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
The function is working today by getting all the child objects of the
chip, interacting with each of them to check whether the child is a PHB,
and then doing what needs to be done.
We have all the chip PHBs in the phbs[] array so interacting with all
child objects is unneeded. Open code pnv_ics_get_phb_ics() into
pnv_ics_get() and remove both pnv_ics_get_phb_ics() and the
ForeachPhb3Args struct.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv.c | 38 +++++++++++---------------------------
1 file changed, 11 insertions(+), 27 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index c5e63bede7..e6cea789f8 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1950,44 +1950,28 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
return NULL;
}
-typedef struct ForeachPhb3Args {
- int irq;
- ICSState *ics;
-} ForeachPhb3Args;
-
-static int pnv_ics_get_child(Object *child, void *opaque)
-{
- ForeachPhb3Args *args = opaque;
- PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
-
- if (phb3) {
- if (ics_valid_irq(&phb3->lsis, args->irq)) {
- args->ics = &phb3->lsis;
- }
- if (ics_valid_irq(ICS(&phb3->msis), args->irq)) {
- args->ics = ICS(&phb3->msis);
- }
- }
- return args->ics ? 1 : 0;
-}
-
static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
- ForeachPhb3Args args = { irq, NULL };
- int i;
+ int i, j;
for (i = 0; i < pnv->num_chips; i++) {
- PnvChip *chip = pnv->chips[i];
Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
if (ics_valid_irq(&chip8->psi.ics, irq)) {
return &chip8->psi.ics;
}
- object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args);
- if (args.ics) {
- return args.ics;
+ for (j = 0; j < chip8->num_phbs; j++) {
+ PnvPHB3 *phb3 = &chip8->phbs[j];
+
+ if (ics_valid_irq(&phb3->lsis, irq)) {
+ return &phb3->lsis;
+ }
+
+ if (ics_valid_irq(ICS(&phb3->msis), irq)) {
+ return ICS(&phb3->msis);
+ }
}
}
return NULL;
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 5/8] ppc/pnv: make pnv_ics_resend() use chip8->phbs[]
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
` (3 preceding siblings ...)
2022-06-21 17:34 ` [PATCH v3 4/8] ppc/pnv: make pnv_ics_get() use the chip8->phbs[] array Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 6/8] ppc/pnv: make pnv_chip_power8_pic_print_info() " Daniel Henrique Barboza
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
pnv_ics_resend() is scrolling through all the child objects of the chip
to search for the PHBs. It's faster and simpler to just use the phbs[]
array.
pnv_ics_resend_child() was folded into pnv_ics_resend() since it's too
simple to justify its own function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index e6cea789f8..74a6c88dd2 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1990,28 +1990,22 @@ PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
return NULL;
}
-static int pnv_ics_resend_child(Object *child, void *opaque)
-{
- PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
-
- if (phb3) {
- ics_resend(&phb3->lsis);
- ics_resend(ICS(&phb3->msis));
- }
- return 0;
-}
-
static void pnv_ics_resend(XICSFabric *xi)
{
PnvMachineState *pnv = PNV_MACHINE(xi);
- int i;
+ int i, j;
for (i = 0; i < pnv->num_chips; i++) {
- PnvChip *chip = pnv->chips[i];
Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
ics_resend(&chip8->psi.ics);
- object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL);
+
+ for (j = 0; j < chip8->num_phbs; j++) {
+ PnvPHB3 *phb3 = &chip8->phbs[j];
+
+ ics_resend(&phb3->lsis);
+ ics_resend(ICS(&phb3->msis));
+ }
}
}
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 6/8] ppc/pnv: make pnv_chip_power8_pic_print_info() use chip8->phbs[]
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
` (4 preceding siblings ...)
2022-06-21 17:34 ` [PATCH v3 5/8] ppc/pnv: make pnv_ics_resend() use chip8->phbs[] Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 7/8] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb3 root bus Daniel Henrique Barboza
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
It's inneficient to scroll all child objects when we have all PHBs
available in chip8->phbs[].
pnv_chip_power8_pic_print_info_child() ended up folded into
pic_print_info() for simplicity.
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv.c | 22 ++++++++--------------
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 74a6c88dd2..d3f77c8367 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -652,25 +652,19 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
}
-static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque)
-{
- Monitor *mon = opaque;
- PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
-
- if (phb3) {
- pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
- ics_pic_print_info(&phb3->lsis, mon);
- }
- return 0;
-}
-
static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ int i;
ics_pic_print_info(&chip8->psi.ics, mon);
- object_child_foreach(OBJECT(chip),
- pnv_chip_power8_pic_print_info_child, mon);
+
+ for (i = 0; i < chip8->num_phbs; i++) {
+ PnvPHB3 *phb3 = &chip8->phbs[i];
+
+ pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
+ ics_pic_print_info(&phb3->lsis, mon);
+ }
}
static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 7/8] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb3 root bus
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
` (5 preceding siblings ...)
2022-06-21 17:34 ` [PATCH v3 6/8] ppc/pnv: make pnv_chip_power8_pic_print_info() " Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-21 17:34 ` [PATCH v3 8/8] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 " Daniel Henrique Barboza
2022-06-27 21:38 ` [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
It's unneeded. No other PCIE_BUS implements this interface.
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fixes: 9ae1329ee2fe ("ppc/pnv: Add models for POWER8 PHB3 PCIe Host bridge")
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb3.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index afe5698167..d58d3c1701 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -1130,10 +1130,6 @@ static const TypeInfo pnv_phb3_root_bus_info = {
.name = TYPE_PNV_PHB3_ROOT_BUS,
.parent = TYPE_PCIE_BUS,
.class_init = pnv_phb3_root_bus_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_PCIE_DEVICE },
- { }
- },
};
static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp)
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 8/8] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 root bus
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
` (6 preceding siblings ...)
2022-06-21 17:34 ` [PATCH v3 7/8] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb3 root bus Daniel Henrique Barboza
@ 2022-06-21 17:34 ` Daniel Henrique Barboza
2022-06-27 21:38 ` [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-21 17:34 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat, Daniel Henrique Barboza
It's unneeded. No other PCIE_BUS implements this interface.
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/pci-host/pnv_phb4.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 725b3d740b..d225ab5b0f 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1752,10 +1752,6 @@ static const TypeInfo pnv_phb4_root_bus_info = {
.name = TYPE_PNV_PHB4_ROOT_BUS,
.parent = TYPE_PCIE_BUS,
.class_init = pnv_phb4_root_bus_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_PCIE_DEVICE },
- { }
- },
};
static void pnv_phb4_root_port_reset(DeviceState *dev)
--
2.36.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v3 0/8] pnv-phb related cleanups
2022-06-21 17:34 [PATCH v3 0/8] pnv-phb related cleanups Daniel Henrique Barboza
` (7 preceding siblings ...)
2022-06-21 17:34 ` [PATCH v3 8/8] ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 " Daniel Henrique Barboza
@ 2022-06-27 21:38 ` Daniel Henrique Barboza
8 siblings, 0 replies; 12+ messages in thread
From: Daniel Henrique Barboza @ 2022-06-27 21:38 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-ppc, clg, fbarrat
Queued in gitlab.com/danielhb/qemu/tree/ppc-next after fixing
the
"We're retrieving a PHB reference PHB just to access"
in the commit msg of patch 03.
Thanks,
Daniel
On 6/21/22 14:34, Daniel Henrique Barboza wrote:
> This version present changes in patch 03. We're now setting chassis and
> slot in pnv_phb_attach_root_port(), avoiding all the hassle of having to
> access the PHB object via bus->qbus.parent inside root_port_realize().
>
> changes from v2:
> - patch 03:
> - set chassis and slot outside of root_port_realize()
> - former patch 04 ("use dev instead of pci->qdev in root_port_realize()"):
> - dropped due to changes in patch 03
> - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2022-06/msg03177.html
>
> Daniel Henrique Barboza (8):
> ppc/pnv: move root port attach to pnv_phb4_realize()
> ppc/pnv: attach phb3/phb4 root ports in QOM tree
> ppc/pnv: assign pnv-phb-root-port chassis/slot earlier
> ppc/pnv: make pnv_ics_get() use the chip8->phbs[] array
> ppc/pnv: make pnv_ics_resend() use chip8->phbs[]
> ppc/pnv: make pnv_chip_power8_pic_print_info() use chip8->phbs[]
> ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb3 root bus
> ppc/pnv: remove 'INTERFACE_PCIE_DEVICE' from phb4 root bus
>
> hw/pci-host/pnv_phb3.c | 22 +-------
> hw/pci-host/pnv_phb4.c | 24 ++-------
> hw/pci-host/pnv_phb4_pec.c | 3 --
> hw/ppc/pnv.c | 102 ++++++++++++++++---------------------
> include/hw/ppc/pnv.h | 3 +-
> 5 files changed, 54 insertions(+), 100 deletions(-)
>
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