[PATCH v2 0/9] Introduce HPE GXP Architecture

[PATCH v2 0/9] Introduce HPE GXP Architecture

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Changes since v2:
 *Added SPI Controller Support
 *Removed hpe,gxp.yaml and hpe,gxp-timer.yaml as those bindings are
  already in linux
 *Added hpe,gxp-spi.yaml as it is necessary to boot the OS and is not
  present in linux.
 *Ported hpe-gxp.dtsi and hpe-bmc-dl360gen10.dts from Linux discarding
  all changes from previous patch.
 *Created hpe-gxp-u-boot.dtsi
 *Added hpe,gxp-spi.yaml and gxp_spi.c to MAINTAINERS
 *Removed hpe,gxp.yaml and hpe,gxp-timer.yaml from MAINTAINERS
 *Removed CONFIG_SYS_SDRAM_SIZE usage from gxp.h and moved SRAM
  calculation to gxp_board.c
 *Removed n for GXP_ECC as n is default in board Kconfig
 *Fixed indentation in board Kconfig
 *Removed use of common.h headers from files
 
The GXP is the HPE BMC SoC that is used in the majority of HPE current
generation servers. Traditionally the asic will last multiple
generations of server before being replaced.

Info about SoC:

 HPE GXP is the name of the HPE SoC. This SoC is used to implement many
 BMC features at HPE. It supports ARMv7 architecture based on the Cortex
 A9 core. It is capable of using an AXI bus to which a memory controller
 is attached. It has multiple SPI interfaces to connect boot flash and
 BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has
 multiple i2c engines to drive connectivity with a host infrastructure.
 The initial patches enable the timer and spi driver enabling U-Boot
 prompt to work and boot to the OS.

Nick Hawkins (9):
  ARM: hpe: gxp: add core support
  timer: gxp: Add HPE GXP timer support
  spi: gxp_spi: Add GXP SPI controller driver
  board: hpe: gxp: add HPE GXP soc support
  dt-bindings: spi: Add hpe gxp spi
  ARM: dts: Add device tree files for hpe gxp soc
  configs: gxp: add core support
  configs: gxp: add gxp_defconfig
  MAINTAINERS: Introduce HPE GXP Architecture

 MAINTAINERS                                   |  12 +
 arch/arm/Kconfig                              |   8 +
 arch/arm/Makefile                             |   1 +
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/hpe-bmc-dl360gen10.dts           |  26 ++
 arch/arm/dts/hpe-gxp-u-boot.dtsi              |  25 ++
 arch/arm/dts/hpe-gxp.dtsi                     | 127 ++++++++
 arch/arm/mach-hpe/Makefile                    |   1 +
 arch/arm/mach-hpe/gxp/Kconfig                 |   9 +
 arch/arm/mach-hpe/gxp/Makefile                |   1 +
 arch/arm/mach-hpe/gxp/reset.c                 |  25 ++
 board/hpe/gxp/Kconfig                         |  46 +++
 board/hpe/gxp/Makefile                        |   1 +
 board/hpe/gxp/gxp_board.c                     |  75 +++++
 configs/gxp_defconfig                         |  59 ++++
 doc/device-tree-bindings/spi/hpe,gxp-spi.yaml |  37 +++
 drivers/spi/Kconfig                           |   6 +
 drivers/spi/Makefile                          |   1 +
 drivers/spi/gxp_spi.c                         | 304 ++++++++++++++++++
 drivers/timer/Kconfig                         |   7 +
 drivers/timer/Makefile                        |   1 +
 drivers/timer/gxp-timer.c                     |  64 ++++
 include/configs/gxp.h                         |  55 ++++
 23 files changed, 893 insertions(+)
 create mode 100644 arch/arm/dts/hpe-bmc-dl360gen10.dts
 create mode 100644 arch/arm/dts/hpe-gxp-u-boot.dtsi
 create mode 100644 arch/arm/dts/hpe-gxp.dtsi
 create mode 100644 arch/arm/mach-hpe/Makefile
 create mode 100644 arch/arm/mach-hpe/gxp/Kconfig
 create mode 100644 arch/arm/mach-hpe/gxp/Makefile
 create mode 100644 arch/arm/mach-hpe/gxp/reset.c
 create mode 100644 board/hpe/gxp/Kconfig
 create mode 100644 board/hpe/gxp/Makefile
 create mode 100644 board/hpe/gxp/gxp_board.c
 create mode 100644 configs/gxp_defconfig
 create mode 100644 doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
 create mode 100644 drivers/spi/gxp_spi.c
 create mode 100644 drivers/timer/gxp-timer.c
 create mode 100644 include/configs/gxp.h

-- 
2.17.1

[PATCH v2 1/9] ARM: hpe: gxp: add core support

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

The GXP is the HPE BMC SoC that is used in the majority
of current generation HPE servers. Traditionally the asic will
last multiple generations of server before being replaced.

Info about SoC:

HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
features at HPE. It supports ARMv7 architecture based on the Cortex A9
core. It is capable of using an AXI bus to whicha memory controller is
attached. It has multiple SPI interfaces to connect boot flash and BIOS
flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
i2c engines to drive connectivity with a host infrastructure. There
currently are no public specifications but this process is being worked.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Removed unused header common.h
---
 arch/arm/Kconfig               |  8 ++++++++
 arch/arm/Makefile              |  1 +
 arch/arm/mach-hpe/Makefile     |  1 +
 arch/arm/mach-hpe/gxp/Kconfig  |  9 +++++++++
 arch/arm/mach-hpe/gxp/Makefile |  1 +
 arch/arm/mach-hpe/gxp/reset.c  | 25 +++++++++++++++++++++++++
 6 files changed, 45 insertions(+)
 create mode 100644 arch/arm/mach-hpe/Makefile
 create mode 100644 arch/arm/mach-hpe/gxp/Kconfig
 create mode 100644 arch/arm/mach-hpe/gxp/Makefile
 create mode 100644 arch/arm/mach-hpe/gxp/reset.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9898c7d68e..1f9fc1bb8e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2085,6 +2085,12 @@ config TARGET_XENGUEST_ARM64
 	select SSCANF
 	imply OF_HAS_PRIOR_STAGE
 
+config ARCH_GXP
+	bool "Support HPE GXP SoCs"
+	select DM
+	select OF_CONTROL
+	imply CMD_DM
+
 endchoice
 
 config SUPPORT_PASSING_ATAGS
@@ -2193,6 +2199,8 @@ source "arch/arm/mach-davinci/Kconfig"
 
 source "arch/arm/mach-exynos/Kconfig"
 
+source "arch/arm/mach-hpe/gxp/Kconfig"
+
 source "arch/arm/mach-highbank/Kconfig"
 
 source "arch/arm/mach-integrator/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 85c23bcf77..cfaa38594c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_BCM283X)		+= bcm283x
 machine-$(CONFIG_ARCH_BCMSTB)		+= bcmstb
 machine-$(CONFIG_ARCH_DAVINCI)		+= davinci
 machine-$(CONFIG_ARCH_EXYNOS)		+= exynos
+machine-$(CONFIG_ARCH_GXP)		+= hpe
 machine-$(CONFIG_ARCH_HIGHBANK)		+= highbank
 machine-$(CONFIG_ARCH_IPQ40XX)		+= ipq40xx
 machine-$(CONFIG_ARCH_K3)		+= k3
diff --git a/arch/arm/mach-hpe/Makefile b/arch/arm/mach-hpe/Makefile
new file mode 100644
index 0000000000..afe5f7a29e
--- /dev/null
+++ b/arch/arm/mach-hpe/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SOC_GXP) += gxp/
diff --git a/arch/arm/mach-hpe/gxp/Kconfig b/arch/arm/mach-hpe/gxp/Kconfig
new file mode 100644
index 0000000000..2d43133ab0
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_GXP
+
+config SOC_GXP
+	bool
+	select CPU_V7A
+
+source "board/hpe/gxp/Kconfig"
+
+endif
diff --git a/arch/arm/mach-hpe/gxp/Makefile b/arch/arm/mach-hpe/gxp/Makefile
new file mode 100644
index 0000000000..f3cc6684b8
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp/Makefile
@@ -0,0 +1 @@
+obj-y += reset.o
diff --git a/arch/arm/mach-hpe/gxp/reset.c b/arch/arm/mach-hpe/gxp/reset.c
new file mode 100644
index 0000000000..ce018a35d9
--- /dev/null
+++ b/arch/arm/mach-hpe/gxp/reset.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GXP driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <asm/io.h>
+
+#define GXP_CCR	0xc0000000
+
+/* empty to satisfy current lowlevel_init, can be removed any time */
+void lowlevel_init(void)
+{
+}
+
+void reset_cpu(ulong ignored)
+{
+	writel(1, GXP_CCR);
+
+	while (1)
+		;	/* loop forever till reset */
+}
-- 
2.17.1

[PATCH v2 2/9] timer: gxp: Add HPE GXP timer support

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add support for the HPE GXP SOC timer. The GXP supports several different
kinds of timers but for the purpose of this driver there is only support
for the General Timer. The timer has a 1us resolution and is 56 bits.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Removed unused header common.h
---
 drivers/timer/Kconfig     |  7 +++++
 drivers/timer/Makefile    |  1 +
 drivers/timer/gxp-timer.c | 64 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 72 insertions(+)
 create mode 100644 drivers/timer/gxp-timer.c

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 7b8ab56ed3..d592dba285 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER
 	  Enables support for the Designware APB Timer driver. This timer is
 	  present on Altera SoCFPGA SoCs.
 
+config GXP_TIMER
+	bool "HPE GXP Timer"
+	depends on TIMER
+	help
+	  Enables support for the GXP Timer driver. This timer is
+	  present on HPE GXP SoCs.
+
 config MPC83XX_TIMER
 	bool "MPC83xx timer support"
 	depends on TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index b2f002d597..cc2b8516b5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o
 obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o
 obj-$(CONFIG_CADENCE_TTC_TIMER)	+= cadence-ttc.o
 obj-$(CONFIG_DESIGNWARE_APB_TIMER)	+= dw-apb-timer.o
+obj-$(CONFIG_GXP_TIMER)		+= gxp-timer.o
 obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
 obj-$(CONFIG_NOMADIK_MTU_TIMER)	+= nomadik-mtu-timer.o
 obj-$(CONFIG_NPCM_TIMER)        += npcm-timer.o
diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c
new file mode 100644
index 0000000000..6f316bc8c5
--- /dev/null
+++ b/drivers/timer/gxp-timer.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define USTIMELO	0x18
+#define USTIMEHI	0x1C
+
+struct gxp_timer_priv {
+	void __iomem *base;
+};
+
+static u64 gxp_timer_get_count(struct udevice *dev)
+{
+	struct gxp_timer_priv *priv = dev_get_priv(dev);
+	u64 val;
+
+	val = readl(priv->base + USTIMEHI);
+	val = (val << 32) | readl(priv->base + USTIMELO);
+
+	return val;
+}
+
+static int gxp_timer_probe(struct udevice *dev)
+{
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct gxp_timer_priv *priv = dev_get_priv(dev);
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base)
+		return -ENOENT;
+
+	uc_priv->clock_rate = 1000000;
+
+	return 0;
+}
+
+static const struct timer_ops gxp_timer_ops = {
+	.get_count = gxp_timer_get_count,
+};
+
+static const struct udevice_id gxp_timer_ids[] = {
+	{ .compatible = "hpe,gxp-timer" },
+	{}
+};
+
+U_BOOT_DRIVER(gxp_timer) = {
+	.name = "gxp-timer",
+	.id = UCLASS_TIMER,
+	.of_match = gxp_timer_ids,
+	.priv_auto = sizeof(struct gxp_timer_priv),
+	.probe = gxp_timer_probe,
+	.ops = &gxp_timer_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.17.1

[PATCH v2 3/9] spi: gxp_spi: Add GXP SPI controller driver

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Added support for SPI, files were not present in v1
---
 drivers/spi/Kconfig   |   6 +
 drivers/spi/Makefile  |   1 +
 drivers/spi/gxp_spi.c | 304 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 311 insertions(+)
 create mode 100644 drivers/spi/gxp_spi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1e515cb2b..e48d72d744 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -186,6 +186,12 @@ config FSL_QSPI_AHB_FULL_MAP
 	  Enable the Freescale QSPI driver to use full AHB memory map space for
 	  flash access.
 
+config GXP_SPI
+	bool "SPI driver for GXP"
+	imply SPI_FLASH_BAR
+	help
+	  Enable support for SPI on GXP.
+
 config ICH_SPI
 	bool "Intel ICH SPI driver"
 	help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06e81b465b..8755408e62 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
 obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
+obj-$(CONFIG_GXP_SPI) += gxp_spi.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
 obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/gxp_spi.c b/drivers/spi/gxp_spi.c
new file mode 100644
index 0000000000..70d76ac66a
--- /dev/null
+++ b/drivers/spi/gxp_spi.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * GXP SPI driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <spi.h>
+#include <asm/io.h>
+#include <dm.h>
+
+#define GXP_SPI0_MAX_CHIPSELECT		2
+
+#define MANUAL_MODE	0
+#define AUTO_MODE		1
+#define OFFSET_SPIMCFG	0x00
+#define OFFSET_SPIMCTRL	0x04
+#define OFFSET_SPICMD		0x05
+#define OFFSET_SPIDCNT	0x06
+#define OFFSET_SPIADDR	0x08
+#define OFFSET_SPILDAT	0x40
+#define GXP_SPILDAT_SIZE 64
+
+#define SPIMCTRL_START	0x01
+#define SPIMCTRL_BUSY		0x02
+
+#define CMD_READ_ARRAY_FAST		0x0b
+
+struct gxp_spi_priv {
+	struct spi_slave	slave;
+	void __iomem *base;
+	unsigned int mode;
+
+};
+
+static void spi_set_mode(struct gxp_spi_priv *priv, int mode)
+{
+	unsigned char value;
+
+	value = readb(priv->base + OFFSET_SPIMCTRL);
+	if (mode == MANUAL_MODE) {
+		writeb(0x55, priv->base + OFFSET_SPICMD);
+		writeb(0xaa, priv->base + OFFSET_SPICMD);
+		/* clear bit5 and bit4, auto_start and start_mask */
+		value &= ~(0x03 << 4);
+	} else {
+		value |= (0x03 << 4);
+	}
+	writeb(value, priv->base + OFFSET_SPIMCTRL);
+}
+
+static int gxp_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din,
+			unsigned long flags)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+
+	unsigned int len = bitlen / 8;
+	unsigned int value;
+	unsigned int addr = 0;
+	unsigned char uchar_out[len];
+	unsigned char *uchar_in = (unsigned char *)din;
+	int read_len;
+	int read_ptr;
+
+	if (dout && din) {
+		/*
+		 * error: gxp spi engin cannot send data to dout and read data from din at the same
+		 * time
+		 */
+		return -1;
+	}
+
+	memset(uchar_out, 0, sizeof(uchar_out));
+	if (dout)
+		memcpy(uchar_out, dout, len);
+
+	if (flags & SPI_XFER_BEGIN) {
+		/* the dout is cmd + addr, cmd=dout[0], add1~3=dout[1~3]. */
+		/* cmd reg */
+		writeb(uchar_out[0], priv->base + OFFSET_SPICMD);
+
+		/* config reg */
+		value = readl(priv->base + OFFSET_SPIMCFG);
+		value &= ~(1 << 24);
+		/* set chipselect */
+		value |= (slave_plat->cs << 24);
+
+		/* addr reg and addr size */
+		if (len >= 4) {
+			addr = uchar_out[1] << 16 | uchar_out[2] << 8 | uchar_out[3];
+			writel(addr, priv->base + OFFSET_SPIADDR);
+			value &= ~(0x07 << 16);
+			/* set the address size to 3 byte */
+			value |= (3 << 16);
+		} else {
+			writel(0, priv->base + OFFSET_SPIADDR);
+			/* set the address size to 0 byte */
+			value &= ~(0x07 << 16);
+		}
+
+		/* dummy */
+		/* clear dummy_cnt to */
+		value &= ~(0x1f << 19);
+		if (uchar_out[0] == CMD_READ_ARRAY_FAST) {
+			/* fast read needs 8 dummy clocks */
+			value |= (8 << 19);
+		}
+
+		writel(value, priv->base + OFFSET_SPIMCFG);
+
+		if (flags & SPI_XFER_END) {
+			/* no data cmd just start it */
+			/* set the data direction bit to 1 */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value |= (1 << 3);
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* set the data byte count */
+			writeb(0, priv->base + OFFSET_SPIDCNT);
+
+			/* set the start bit */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value |= SPIMCTRL_START;
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* wait busy bit is cleared */
+			do {
+				value = readb(priv->base + OFFSET_SPIMCTRL);
+			} while (value & SPIMCTRL_BUSY);
+			return 0;
+		}
+	}
+
+	if (!(flags & SPI_XFER_END) && (flags & SPI_XFER_BEGIN)) {
+		/* first of spi_xfer calls */
+		return 0;
+	}
+
+	/* if dout != null, write data to buf and start transaction */
+	if (dout) {
+		if (len > slave->max_write_size) {
+			printf("SF: write length is too big(>%d)\n", slave->max_write_size);
+			return -1;
+		}
+
+		/* load the data bytes */
+		memcpy((u8 *)priv->base + OFFSET_SPILDAT, dout, len);
+
+		/* write: set the data direction bit to 1 */
+		value = readb(priv->base + OFFSET_SPIMCTRL);
+		value |= (1 << 3);
+		writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+		/* set the data byte count */
+		writeb(len, priv->base + OFFSET_SPIDCNT);
+
+		/* set the start bit */
+		value = readb(priv->base + OFFSET_SPIMCTRL);
+		value |= SPIMCTRL_START;
+		writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+		/* wait busy bit is cleared */
+		do {
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+		} while (value & SPIMCTRL_BUSY);
+
+		return 0;
+	}
+
+	/* if din !=null, start and read data */
+	if (uchar_in) {
+		read_ptr = 0;
+
+		while (read_ptr < len) {
+			read_len = len - read_ptr;
+			if (read_len > GXP_SPILDAT_SIZE)
+				read_len = GXP_SPILDAT_SIZE;
+
+			/* read: set the data direction bit to 0 */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value &= ~(1 << 3);
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* set the data byte count */
+			writeb(read_len, priv->base + OFFSET_SPIDCNT);
+
+			/* set the start bit */
+			value = readb(priv->base + OFFSET_SPIMCTRL);
+			value |= SPIMCTRL_START;
+			writeb(value, priv->base + OFFSET_SPIMCTRL);
+
+			/* wait busy bit is cleared */
+			do {
+				value = readb(priv->base + OFFSET_SPIMCTRL);
+			} while (value & SPIMCTRL_BUSY);
+
+			/* store the data bytes */
+			memcpy(uchar_in + read_ptr, (u8 *)priv->base + OFFSET_SPILDAT, read_len);
+			/* update read_ptr and addr reg */
+			read_ptr += read_len;
+
+			addr = readl(priv->base + OFFSET_SPIADDR);
+			addr += read_len;
+			writel(addr, priv->base + OFFSET_SPIADDR);
+		}
+
+		return 0;
+	}
+	return -2;
+}
+
+static int gxp_spi_set_speed(struct udevice *dev, unsigned int speed)
+{
+	/* Accept any speed */
+	return 0;
+}
+
+static int gxp_spi_set_mode(struct udevice *dev, unsigned int mode)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+
+	priv->mode = mode;
+
+	return 0;
+}
+
+static int gxp_spi_claim_bus(struct udevice *dev)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+	unsigned char cmd;
+
+	spi_set_mode(priv, MANUAL_MODE);
+
+	/* exit 4 bytes addr mode, uboot spi_flash only supports 3 byets address mode */
+	cmd = 0xe9;
+	gxp_spi_xfer(dev, 1 * 8, &cmd, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+	return 0;
+}
+
+static int gxp_spi_release_bus(struct udevice *dev)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(dev->parent);
+
+	spi_set_mode(priv, AUTO_MODE);
+
+	return 0;
+}
+
+int gxp_spi_cs_info(struct udevice *bus, unsigned int cs, struct spi_cs_info *info)
+{
+	if (cs < GXP_SPI0_MAX_CHIPSELECT)
+		return 0;
+	else
+		return -ENODEV;
+}
+
+static int gxp_spi_probe(struct udevice *bus)
+{
+	struct gxp_spi_priv *priv = dev_get_priv(bus);
+
+	priv->base = dev_read_addr_ptr(bus);
+	if (!priv->base)
+		return -ENOENT;
+
+	return 0;
+}
+
+static int gxp_spi_child_pre_probe(struct udevice *dev)
+{
+	struct spi_slave *slave = dev_get_parent_priv(dev);
+
+	slave->max_write_size = GXP_SPILDAT_SIZE;
+
+	return 0;
+}
+
+static const struct dm_spi_ops gxp_spi_ops = {
+	.claim_bus = gxp_spi_claim_bus,
+	.release_bus = gxp_spi_release_bus,
+	.xfer = gxp_spi_xfer,
+	.set_speed = gxp_spi_set_speed,
+	.set_mode = gxp_spi_set_mode,
+	.cs_info = gxp_spi_cs_info,
+};
+
+static const struct udevice_id gxp_spi_ids[] = {
+	{ .compatible = "hpe,gxp-spi" },
+	{ }
+};
+
+U_BOOT_DRIVER(gxp_spi) = {
+	.name	= "gxp_spi",
+	.id	= UCLASS_SPI,
+	.of_match = gxp_spi_ids,
+	.ops	= &gxp_spi_ops,
+	.priv_auto = sizeof(struct gxp_spi_priv),
+	.probe	= gxp_spi_probe,
+	.child_pre_probe = gxp_spi_child_pre_probe,
+};
+
-- 
2.17.1

[PATCH v2 4/9] board: hpe: gxp: add HPE GXP soc support

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add basic support for the HPE GXP SoC. Reset the EHCI controller at
boot.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Removed n for GXP_ECC as n is default.
 *Fix indentation in Kconfig file
 *Removed common.h and used necessary headers only.
 *Removed use of CONFIG_SYS_SDRAM_SIZE and used SZ_ constants instead
 *Moved ifdef's from gxp.h commit to this file.
---
 board/hpe/gxp/Kconfig     | 46 ++++++++++++++++++++++++
 board/hpe/gxp/Makefile    |  1 +
 board/hpe/gxp/gxp_board.c | 75 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 122 insertions(+)
 create mode 100644 board/hpe/gxp/Kconfig
 create mode 100644 board/hpe/gxp/Makefile
 create mode 100644 board/hpe/gxp/gxp_board.c

diff --git a/board/hpe/gxp/Kconfig b/board/hpe/gxp/Kconfig
new file mode 100644
index 0000000000..5b154a3f6e
--- /dev/null
+++ b/board/hpe/gxp/Kconfig
@@ -0,0 +1,46 @@
+choice
+	prompt "SoC select"
+
+config TARGET_GXP
+	bool "GXP"
+	select DM
+	select SOC_GXP
+	imply CMD_DM
+
+config TARGET_GXP2
+	bool "GXP2"
+	select DM
+	select SOC_GXP
+	select GXP_ECC
+	imply CMD_DM
+
+endchoice
+
+choice
+	prompt "GXP VROM size"
+	default GXP_VROM_64MB
+	optional
+
+config GXP_VROM_64MB
+	bool "64MB"
+
+config GXP_VROM_32MB
+	bool "32MB"
+endchoice
+
+config GXP_ECC
+	bool "Enable memory ECC protected"
+	help
+	  Use half of memory to enable ECC protected
+
+config SYS_BOARD
+	default "gxp"
+
+config SYS_VENDOR
+	default "hpe"
+
+config SYS_CONFIG_NAME
+	default "gxp"
+
+config SYS_TEXT_BASE
+	default 0x50000000
diff --git a/board/hpe/gxp/Makefile b/board/hpe/gxp/Makefile
new file mode 100644
index 0000000000..775d6bf849
--- /dev/null
+++ b/board/hpe/gxp/Makefile
@@ -0,0 +1 @@
+obj-y += gxp_board.o
diff --git a/board/hpe/gxp/gxp_board.c b/board/hpe/gxp/gxp_board.c
new file mode 100644
index 0000000000..d94d9b8a19
--- /dev/null
+++ b/board/hpe/gxp/gxp_board.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GXP timer driver
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/uclass.h>
+#include <ram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ECHI_CMD 0xcefe0010
+
+int board_init(void)
+{
+	writel(0x00080002, ECHI_CMD);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (IS_ENABLED(CONFIG_TARGET_GXP)) {
+		if (IS_ENABLED(CONFIG_GXP_ECC)) {
+			/* 0x0f800000 */
+			gd->ram_size = SZ_128M + SZ_64M + SZ_32M + SZ_16M + SZ_8M;
+		} else {
+			/* 0x1f000000 */
+			gd->ram_size = SZ_256M + SZ_128M + SZ_64M + SZ_32M + SZ_16M;
+		}
+
+		if (IS_ENABLED(CONFIG_GXP_VROM_64MB)) {
+			if (IS_ENABLED(CONFIG_GXP_ECC)) {
+				/* 0x0c000000 */
+				gd->ram_size = SZ_128M + SZ_64M;
+			} else {
+				/* 0x18000000 */
+				gd->ram_size = SZ_256M + SZ_128M;
+			}
+		}
+
+		if (IS_ENABLED(CONFIG_GXP_VROM_32MB)) {
+			if (IS_ENABLED(CONFIG_GXP_ECC)) {
+				/* 0x0e000000 */
+				gd->ram_size = SZ_128M + SZ_64M + SZ_32M;
+			} else {
+				/* 0x1c000000 */
+				gd->ram_size = SZ_256M + SZ_128M + SZ_64M;
+			}
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_TARGET_GXP2)) {
+		/* 0x1b200000 */
+		gd->ram_size = SZ_256M + SZ_128M + SZ_32M + SZ_16M + SZ_2M;
+		if (IS_ENABLED(CONFIG_GXP_VROM_64MB)) {
+			/* 0x14000000 */
+			gd->ram_size = SZ_256M + SZ_64M;
+		}
+
+		if (IS_ENABLED(CONFIG_GXP_VROM_32MB)) {
+			/* 0x18000000 */
+			gd->ram_size = SZ_256M + SZ_128M;
+		}
+	}
+
+	return 0;
+}
+
-- 
2.17.1

[PATCH v2 5/9] dt-bindings: spi: Add hpe gxp spi

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add support for the HPE GXP SPI Controller.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Created binding documentation as it does not exist for linux.
---
 doc/device-tree-bindings/spi/hpe,gxp-spi.yaml | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 doc/device-tree-bindings/spi/hpe,gxp-spi.yaml

diff --git a/doc/device-tree-bindings/spi/hpe,gxp-spi.yaml b/doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
new file mode 100644
index 0000000000..5e23de1847
--- /dev/null
+++ b/doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/hpe,gxp-spi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: HPE GXP SPI Controller
+
+maintainers:
+  - Nick Hawkins <nick.hawkins@hpe.com>
+  - Jean-Marie Verdun <verdun@hpe.com>
+
+allOf:
+  - $ref: "spi-controller.yaml#"
+
+properties:
+  compatible:
+    const: mikrotik,rb4xx-spi
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    spi@c00000200{
+          compatible = "hpe,gxp-spi";
+          reg = <0xc0000200 0x80>;
+          #address-cells = <1>;
+          #size-cells = <0>;
+    };
+
-- 
2.17.1

[PATCH v2 6/9] ARM: dts: Add device tree files for hpe gxp soc

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

The HPE SoC is new to linux. A basic device tree layout with minimum
required for linux to boot including a timer and watchdog support has
been created.

The dts file is empty at this point but will be updated in subsequent
updates as board specific features are enabled.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 * Created hpe-gxp-u-boot.dtsi file and added spi node to it.
 * Ported hpe-gxp.dtsi and hpe-bmc-dl360gen10.dts from linux.
---
 arch/arm/dts/Makefile               |   2 +
 arch/arm/dts/hpe-bmc-dl360gen10.dts |  26 ++++++
 arch/arm/dts/hpe-gxp-u-boot.dtsi    |  25 ++++++
 arch/arm/dts/hpe-gxp.dtsi           | 127 ++++++++++++++++++++++++++++
 4 files changed, 180 insertions(+)
 create mode 100644 arch/arm/dts/hpe-bmc-dl360gen10.dts
 create mode 100644 arch/arm/dts/hpe-gxp-u-boot.dtsi
 create mode 100644 arch/arm/dts/hpe-gxp.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..6223998eb7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1213,6 +1213,8 @@ dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
 
 dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
 
+dtb-$(CONFIG_TARGET_GXP) += hpe-bmc-dl360gen10.dts
+
 dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
 					imx8mm-cl-iot-gate-ied.dtbo \
 					imx8mm-cl-iot-gate-ied-adc0.dtbo \
diff --git a/arch/arm/dts/hpe-bmc-dl360gen10.dts b/arch/arm/dts/hpe-bmc-dl360gen10.dts
new file mode 100644
index 0000000000..b8030d9d9f
--- /dev/null
+++ b/arch/arm/dts/hpe-bmc-dl360gen10.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE DL360Gen10
+ */
+
+/include/ "hpe-gxp-u-boot.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "hpe,gxp-dl360gen10", "hpe,gxp";
+	model = "Hewlett Packard Enterprise ProLiant dl360 Gen10";
+
+	aliases {
+		serial0 = &uartc;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x20000000>;
+	};
+};
diff --git a/arch/arm/dts/hpe-gxp-u-boot.dtsi b/arch/arm/dts/hpe-gxp-u-boot.dtsi
new file mode 100644
index 0000000000..7a2b488521
--- /dev/null
+++ b/arch/arm/dts/hpe-gxp-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GXP
+ */
+
+/include/ "hpe-gxp.dtsi"
+
+/ {
+
+	axi {
+		u-boot,dm-pre-reloc;
+
+		ahb@c0000000 {
+			u-boot,dm-pre-reloc;
+
+			spi0: spi@200 {
+				compatible = "hpe,gxp-spi";
+				reg = <0x200 0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/dts/hpe-gxp.dtsi b/arch/arm/dts/hpe-gxp.dtsi
new file mode 100644
index 0000000000..cf735b3c4f
--- /dev/null
+++ b/arch/arm/dts/hpe-gxp.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree file for HPE GXP
+ */
+
+/dts-v1/;
+/ {
+	model = "Hewlett Packard Enterprise GXP BMC";
+	compatible = "hpe,gxp";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L2>;
+		};
+	};
+
+	clocks {
+		pll: clock-0 {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1600000000>;
+		};
+
+		iopclk: clock-1 {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <4>;
+			clock-mult = <1>;
+			clocks = <&pll>;
+		};
+	};
+
+	axi {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+		dma-ranges;
+
+		L2: cache-controller@b0040000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xb0040000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+		};
+
+		ahb@c0000000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xc0000000 0x30000000>;
+			dma-ranges;
+
+			vic0: interrupt-controller@eff0000 {
+				compatible = "arm,pl192-vic";
+				reg = <0xeff0000 0x1000>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			vic1: interrupt-controller@80f00000 {
+				compatible = "arm,pl192-vic";
+				reg = <0x80f00000 0x1000>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+
+			uarta: serial@e0 {
+				compatible = "ns16550a";
+				reg = <0xe0 0x8>;
+				interrupts = <17>;
+				interrupt-parent = <&vic0>;
+				clock-frequency = <1846153>;
+				reg-shift = <0>;
+			};
+
+			uartb: serial@e8 {
+				compatible = "ns16550a";
+				reg = <0xe8 0x8>;
+				interrupts = <18>;
+				interrupt-parent = <&vic0>;
+				clock-frequency = <1846153>;
+				reg-shift = <0>;
+			};
+
+			uartc: serial@f0 {
+				compatible = "ns16550a";
+				reg = <0xf0 0x8>;
+				interrupts = <19>;
+				interrupt-parent = <&vic0>;
+				clock-frequency = <1846153>;
+				reg-shift = <0>;
+			};
+
+			usb0: usb@efe0000 {
+				compatible = "hpe,gxp-ehci", "generic-ehci";
+				reg = <0xefe0000 0x100>;
+				interrupts = <7>;
+				interrupt-parent = <&vic0>;
+			};
+
+			st: timer@80 {
+				compatible = "hpe,gxp-timer";
+				reg = <0x80 0x16>;
+				interrupts = <0>;
+				interrupt-parent = <&vic0>;
+				clocks = <&iopclk>;
+				clock-names = "iop";
+			};
+
+			usb1: usb@efe0100 {
+				compatible = "hpe,gxp-ohci", "generic-ohci";
+				reg = <0xefe0100 0x110>;
+				interrupts = <6>;
+				interrupt-parent = <&vic0>;
+			};
+		};
+	};
+};
-- 
2.17.1

[PATCH v2 7/9] configs: gxp: add core support

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Add the include file for the gxp soc.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Removed CONFIG_SYS_SDRAM_SIZE usage and moved SDRAM size calculation
  to the board file.
---
 include/configs/gxp.h | 55 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 include/configs/gxp.h

diff --git a/include/configs/gxp.h b/include/configs/gxp.h
new file mode 100644
index 0000000000..88d295cf91
--- /dev/null
+++ b/include/configs/gxp.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * GXP board
+ *
+ * (C) Copyright 2022 Hewlett Packard Enterprise Development LP.
+ * Author: Nick Hawkins <nick.hawkins@hpe.com>
+ * Author: Jean-Marie Verdun <verdun@hpe.com>
+ */
+
+#ifndef _GXP_H_
+#define _GXP_H_
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_MALLOC_LEN   0x4000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x2000000
+#define CONFIG_SYS_SDRAM_BASE   0x40000000
+#define CONFIG_SYS_LOAD_ADDR    0x40100000
+#define CONFIG_BOOTCOMMAND  "run spiboot"
+//#define CONFIG_SYS_BOOTM_LEN    0xC00000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"recover_file=openbmc-hpe-recovery-image.mtd\0" \
+	"recover_cmd=usb start; " \
+	"mw.b 0xD100000D 0x40; " \
+	"if fatload usb 0 0x50000000 $recover_file 0x4C0000 0x80000; then " \
+		"setenv bootargs console=ttyS0,115200 recovery; " \
+		"setenv force_recovery; " \
+		"saveenv; " \
+		"bootm  0x50000000; " \
+	"else " \
+		"while itest 0 < 1; do " \
+		"mw.b 0xd1000005 0xc0; " \
+		"sleep .1; " \
+		"mw.b 0xd1000005 0x00; " \
+		"sleep .1; " \
+		"done; " \
+	"fi; " \
+	"reset;\0" \
+	"spiboot=if itest.b *0xD10000B2 == 6; then " \
+		"run recover_cmd;" \
+	"fi;" \
+	"if printenv force_recovery; then " \
+		"run recover_cmd; " \
+	"else " \
+		"bootm 0xfc080000; " \
+		"run recover_cmd; " \
+	"fi;\0"
+
+/*--------------------------------------------------------------------------*/
+/*              Network Configuration             */
+/*--------------------------------------------------------------------------*/
+#define CONFIG_PHY_ADDR             0
+
+#endif
-- 
2.17.1

[PATCH v2 8/9] configs: gxp: add gxp_defconfig

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

This is the initial very basic config that enables the U-Boot console on
the hpe gxp soc.

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Added SPI support
---
 configs/gxp_defconfig | 59 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 configs/gxp_defconfig

diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig
new file mode 100644
index 0000000000..ff4734a2fe
--- /dev/null
+++ b/configs/gxp_defconfig
@@ -0,0 +1,59 @@
+CONFIG_ARM=y
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_ARCH_GXP=y
+CONFIG_SYS_MALLOC_LEN=0x4000000
+CONFIG_GXP_VROM_64MB=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x60000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DEFAULT_DEVICE_TREE="hpe-bmc-dl360gen10"
+CONFIG_ENV_OFFSET_REDUND=0x70000
+CONFIG_SYS_LOAD_ADDR=0x40100000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_LEGACY_IMAGE_FORMAT=n
+CONFIG_BOOTDELAY=5
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlyprintk console=ttyS2,115200 user_debug=31"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="gxp# "
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MISC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_FAT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_NETCONSOLE=y
+CONFIG_MISC=y
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=3
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_MMC is not set
+# CONFIG_POWER is not set
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_GXP_SPI=y
+CONFIG_SHA512=y
+CONFIG_TIMER=y
+CONFIG_GXP_TIMER=y
+CONFIG_LMB=y
-- 
2.17.1

[PATCH v2 9/9] MAINTAINERS: Introduce HPE GXP Architecture

[nick.hawkins]

From: Nick Hawkins <nick.hawkins@hpe.com>

Create a section in MAINTAINERS for the GXP HPE architecture

Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

---

v2:
 *Added gxp_spi.c and hpe,gxp-spi.yaml to list
 *Removed hpe,gxp.yaml and hpe,gxp-timer.yaml as they are already in
  linux
---
 MAINTAINERS | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 56be0bfad0..0d4c49307f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -257,6 +257,18 @@ F:	arch/arm/cpu/armv8/hisilicon
 F:	arch/arm/include/asm/arch-hi6220/
 F:	arch/arm/include/asm/arch-hi3660/
 
+ARM HPE GXP ARCHITECTURE
+M:	Jean-Marie Verdun <verdun@hpe.com>
+M:	Nick Hawkins <nick.hawkins@hpe.com>
+S:	Maintained
+F:	arch/arm/dts/hpe-bmc*
+F:	arch/arm/dts/hpe-gxp*
+F:	arch/arm/mach-hpe/
+F:	board/hpe/
+F:	doc/device-tree-bindings/spi/hpe,gxp-spi.yaml
+F:	drivers/timer/gxp-timer.c
+F:	drivers/spi/gxp_spi.c
+
 ARM IPQ40XX
 M:	Robert Marko <robert.marko@sartura.hr>
 M:	Luka Kovacic <luka.kovacic@sartura.hr>
-- 
2.17.1

Re: [PATCH v2 0/9] Introduce HPE GXP Architecture

[Hawkins, Nick]

Greetings All,
I just wanted to make sure I did not make a mistake with how I submitted the second version of this patch as I am still learning the u-boot patch submission process. Thanks ahead of time for any feedback.
Thanks for your time,
-Nick Hawkins

Re: [PATCH v2 0/9] Introduce HPE GXP Architecture

[Tom Rini]

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On Wed, Jun 22, 2022 at 07:41:56PM +0000, Hawkins, Nick wrote:

> Greetings All,
> I just wanted to make sure I did not make a mistake with how I submitted the second version of this patch as I am still learning the u-boot patch submission process. Thanks ahead of time for any feedback.

I'm reviewing it for next currently and aside from some Kconfig
migrations have posted:
https://patchwork.ozlabs.org/project/uboot/patch/20220622192145.3696770-1-trini@konsulko.com/

As a follow-up cleanup.

-- 
Tom

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Re: [PATCH v2 1/9] ARM: hpe: gxp: add core support

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:34PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> The GXP is the HPE BMC SoC that is used in the majority
> of current generation HPE servers. Traditionally the asic will
> last multiple generations of server before being replaced.
> 
> Info about SoC:
> 
> HPE GXP is the name of the HPE Soc. This SoC is used to implement many BMC
> features at HPE. It supports ARMv7 architecture based on the Cortex A9
> core. It is capable of using an AXI bus to whicha memory controller is
> attached. It has multiple SPI interfaces to connect boot flash and BIOS
> flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple
> i2c engines to drive connectivity with a host infrastructure. There
> currently are no public specifications but this process is being worked.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 2/9] timer: gxp: Add HPE GXP timer support

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:35PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Add support for the HPE GXP SOC timer. The GXP supports several different
> kinds of timers but for the purpose of this driver there is only support
> for the General Timer. The timer has a 1us resolution and is 56 bits.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 3/9] spi: gxp_spi: Add GXP SPI controller driver

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:36PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> The GXP supports 3 separate SPI interfaces to accommodate the system
> flash, core flash, and other functions. The SPI engine supports variable
> clock frequency, selectable 3-byte or 4-byte addressing and a
> configurable x1, x2, and x4 command/address/data modes. The memory
> buffer for reading and writing ranges between 256 bytes and 8KB. This
> driver supports access to the core flash.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 4/9] board: hpe: gxp: add HPE GXP soc support

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:37PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Add basic support for the HPE GXP SoC. Reset the EHCI controller at
> boot.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 5/9] dt-bindings: spi: Add hpe gxp spi

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:38PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Add support for the HPE GXP SPI Controller.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 6/9] ARM: dts: Add device tree files for hpe gxp soc

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:39PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> The HPE SoC is new to linux. A basic device tree layout with minimum
> required for linux to boot including a timer and watchdog support has
> been created.
> 
> The dts file is empty at this point but will be updated in subsequent
> updates as board specific features are enabled.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 7/9] configs: gxp: add core support

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:40PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Add the include file for the gxp soc.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 8/9] configs: gxp: add gxp_defconfig

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:41PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> This is the initial very basic config that enables the U-Boot console on
> the hpe gxp soc.
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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Re: [PATCH v2 9/9] MAINTAINERS: Introduce HPE GXP Architecture

[Tom Rini]

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On Wed, Jun 08, 2022 at 04:21:42PM -0500, nick.hawkins@hpe.com wrote:

> From: Nick Hawkins <nick.hawkins@hpe.com>
> 
> Create a section in MAINTAINERS for the GXP HPE architecture
> 
> Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>

Applied to u-boot/next, thanks!

-- 
Tom

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