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From: Sergey Matyukevich <geomatsi@gmail.com>
To: linux-riscv@lists.infradead.org
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	Sergey Matyukevich <geomatsi@gmail.com>,
	Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Subject: [PATCH v2 1/2] perf: RISC-V: fix access beyond allocated array
Date: Fri, 24 Jun 2022 16:59:01 +0300	[thread overview]
Message-ID: <20220624135902.520748-2-geomatsi@gmail.com> (raw)
In-Reply-To: <20220624135902.520748-1-geomatsi@gmail.com>

From: Sergey Matyukevich <sergey.matyukevich@syntacore.com>

The root cause could be related to the interpretation of the number of
counters reported by SBI firmware. For instance, if we assume that unused
timer counter with index 1 is not reported, then the range is correct
and larger array needs to be allocated.

This is not the case though since SBI firmware is supposed to report the
total number of firmware and hardware counters including special or
unused ones like the timer counter. So just fix the range in for-loop.

Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
---
 drivers/perf/riscv_pmu_sbi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
index dca3537a8dcc..a5d25b51beac 100644
--- a/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@ -457,7 +457,7 @@ static int pmu_sbi_get_ctrinfo(int nctr)
 	if (!pmu_ctr_list)
 		return -ENOMEM;
 
-	for (i = 0; i <= nctr; i++) {
+	for (i = 0; i < nctr; i++) {
 		ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
 		if (ret.error)
 			/* The logical counter ids are not expected to be contiguous */
-- 
2.36.1


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  reply	other threads:[~2022-06-24 13:59 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-24 13:59 [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array Sergey Matyukevich
2022-06-24 13:59 ` Sergey Matyukevich [this message]
2022-07-11  6:43   ` [PATCH v2 1/2] " Sergey Matyukevich
2022-07-11  7:22     ` Atish Patra
2022-07-11  7:22   ` Atish Patra
2022-06-24 13:59 ` [PATCH v2 2/2] perf: RISC-V: exclude invalid pmu counters from SBI calls Sergey Matyukevich
2022-08-10  7:06 ` [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array Sergey Matyukevich

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