From: Atish Patra <atishp@atishpatra.org>
To: Sergey Matyukevich <geomatsi@gmail.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v2 1/2] perf: RISC-V: fix access beyond allocated array
Date: Mon, 11 Jul 2022 00:22:58 -0700 [thread overview]
Message-ID: <CAOnJCUL8LUGbTkt5YywMHS07C0M8Dt1E=w5J22vJwisU_WWF9A@mail.gmail.com> (raw)
In-Reply-To: <YsvGk+ybtFZ9wQk1@curiosity>
On Sun, Jul 10, 2022 at 11:43 PM Sergey Matyukevich <geomatsi@gmail.com> wrote:
>
> > The root cause could be related to the interpretation of the number of
> > counters reported by SBI firmware. For instance, if we assume that unused
> > timer counter with index 1 is not reported, then the range is correct
> > and larger array needs to be allocated.
> >
> > This is not the case though since SBI firmware is supposed to report the
> > total number of firmware and hardware counters including special or
> > unused ones like the timer counter. So just fix the range in for-loop.
>
> Hi Atish,
>
> Just a friendly reminder.
>
Sorry. I thought I already sent the RB tag.
> Regards,
> Sergey
--
Regards,
Atish
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next prev parent reply other threads:[~2022-07-11 7:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-24 13:59 [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array Sergey Matyukevich
2022-06-24 13:59 ` [PATCH v2 1/2] " Sergey Matyukevich
2022-07-11 6:43 ` Sergey Matyukevich
2022-07-11 7:22 ` Atish Patra [this message]
2022-07-11 7:22 ` Atish Patra
2022-06-24 13:59 ` [PATCH v2 2/2] perf: RISC-V: exclude invalid pmu counters from SBI calls Sergey Matyukevich
2022-08-10 7:06 ` [PATCH v2 0/2] perf: RISC-V: fix access beyond allocated array Sergey Matyukevich
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