* [xilinx-xlnx:xlnx_rebase_v5.15_LTS 470/1197] drivers/misc/jesd204b/jesd_phy.c:97:13: warning: variable 'pll' set but not used
@ 2022-06-26 3:56 kernel test robot
0 siblings, 0 replies; only message in thread
From: kernel test robot @ 2022-06-26 3:56 UTC (permalink / raw)
To: Shubhrajyoti Datta; +Cc: kbuild-all, linux-arm-kernel, Michal Simek
Hi Shubhrajyoti,
FYI, the error/warning still remains.
tree: https://github.com/Xilinx/linux-xlnx xlnx_rebase_v5.15_LTS
head: 1e67f149fb5eb4f5eb4e0d4f69194eac6d2497d7
commit: 4cf40e565c55a749ca7a7bbc7bc998fd3f3a2486 [470/1197] misc: jesd204b: Add driver for Xilinx jesd204b
config: mips-allmodconfig
compiler: mips-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/Xilinx/linux-xlnx/commit/4cf40e565c55a749ca7a7bbc7bc998fd3f3a2486
git remote add xilinx-xlnx https://github.com/Xilinx/linux-xlnx
git fetch --no-tags xilinx-xlnx xlnx_rebase_v5.15_LTS
git checkout 4cf40e565c55a749ca7a7bbc7bc998fd3f3a2486
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/clk/ drivers/gpu/drm/xlnx/ drivers/media/platform/xilinx/ drivers/misc/jesd204b/ drivers/phy/xilinx/ drivers/ptp/ drivers/staging/ drivers/uio/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/misc/jesd204b/jesd_phy.c: In function 'read_plls':
>> drivers/misc/jesd204b/jesd_phy.c:97:13: warning: variable 'pll' set but not used [-Wunused-but-set-variable]
97 | int pll = st->pll;
| ^~~
drivers/misc/jesd204b/jesd_phy.c: At top level:
>> drivers/misc/jesd204b/jesd_phy.c:172:6: warning: no previous prototype for 'jesd204_phy_set_speed' [-Wmissing-prototypes]
172 | void jesd204_phy_set_speed(struct jesd204b_phy_state *st, u32 band)
| ^~~~~~~~~~~~~~~~~~~~~
vim +/pll +97 drivers/misc/jesd204b/jesd_phy.c
93
94 static void read_plls(struct jesd204b_phy_state *st)
95 {
96 int i;
> 97 int pll = st->pll;
98 u32 no_of_common_drp_interfaces = 1;
99
100 if (st->pll == CPLL)
101 no_of_common_drp_interfaces = jesd204b_phy_read(
102 st, NR_TRANS_DRP_INTERFACES);
103 else
104 no_of_common_drp_interfaces = jesd204b_phy_read(
105 st, NR_COMMON_DRP_INTERFACES);
106
107 for (i = 0; i < no_of_common_drp_interfaces; i++) {
108 jesd204b_phy_write(st, CHANNEL_XCVR_SEL, i);
109 pll = jesd204b_phy_read(st, CHANNEL_XCVR_TXPLL);
110 pll = jesd204b_phy_read(st, CHANNEL_XCVR_RXPLL);
111 }
112 }
113
114 static void configure_plls(struct jesd204b_phy_state *st, u32 pll)
115 {
116 int i;
117 u32 no_of_common_drp_interfaces;
118
119 if (pll == CPLL)
120 no_of_common_drp_interfaces = jesd204b_phy_read(
121 st, NR_TRANS_DRP_INTERFACES);
122 else
123 no_of_common_drp_interfaces = jesd204b_phy_read(
124 st, NR_COMMON_DRP_INTERFACES);
125
126 for (i = 0; i < no_of_common_drp_interfaces; i++) {
127 jesd204b_phy_write(st, CHANNEL_XCVR_SEL, i);
128 jesd204b_phy_write(st, CHANNEL_XCVR_TXPLL, pll);
129 jesd204b_phy_write(st, CHANNEL_XCVR_RXPLL, pll);
130 }
131 }
132
133 static void configure_channel_drp(struct jesd204b_phy_state *st, u32 setting)
134 {
135 u32 i, j, addr, temp, no_of_common_drp_interfaces;
136 u32 no_channel_drp_reg = GTX7S_QPLL_NUM_CHANNEL_DRP_REGS;
137
138 no_of_common_drp_interfaces = jesd204b_phy_read(
139 st, NR_TRANS_DRP_INTERFACES);
140
141 if (st->pll == CPLL)
142 no_channel_drp_reg = GTX7S_CPLL_NUM_CHANNEL_DRP_REGS;
143 for (i = 0; i < no_of_common_drp_interfaces; i++) {
144 jesd204b_phy_write(st, CHANNEL_DRP_BASE, i);
145 for (j = 0; j < no_channel_drp_reg; j++) {
146 /* Get the register address */
147 if (st->pll == QPLL) {
148 addr = get_gtx7s_qpll_address_lut(j);
149
150 /* Read the register */
151 temp = read_channel_drp_reg(st, addr);
152
153 temp &= (0xFFFF ^ (get_gtx7s_qpll_mask_lut(j)));
154 temp |= ((get_gtx7s_qpll_param_lut(j, setting)
155 << get_gtx7s_qpll_offset_lut(j))
156 & get_gtx7s_qpll_mask_lut(j));
157 } else {
158 addr = get_gtx7s_cpll_address_lut(j);
159
160 temp = read_channel_drp_reg(st, addr);
161
162 temp &= (0xFFFF ^ (get_gtx7s_cpll_mask_lut(j)));
163 temp |= ((get_gtx7s_cpll_param_lut(j, setting)
164 << get_gtx7s_cpll_offset_lut(j))
165 & get_gtx7s_cpll_mask_lut(j));
166 }
167 write_channel_drp_reg(st, addr, temp);
168 }
169 }
170 }
171
> 172 void jesd204_phy_set_speed(struct jesd204b_phy_state *st, u32 band)
173 {
174 /* make sure we have the correct PLL's selected. */
175 configure_channel_drp(st, band);
176 }
177
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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2022-06-26 3:56 [xilinx-xlnx:xlnx_rebase_v5.15_LTS 470/1197] drivers/misc/jesd204b/jesd_phy.c:97:13: warning: variable 'pll' set but not used kernel test robot
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