[PATCH v2 0/2] arm64: dts: mt8173: Fix nor flash node

[PATCH v2 0/2] arm64: dts: mt8173: Fix nor flash node

[Xiangsheng Hou]

Add axi clock since the driver change to DMA mode which need to enable
axi clock. And change spi clock to 26MHz as default.
Add assigned clock property and axi clock binding file.

Changes from v1:
- Modify nor binding file

Xiangsheng Hou (2):
  arm64: dts: mt8173: Fix nor_flash node
  dt-bindings: mediatek: Add assigned clock property and axi clock in
    example

 .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10 ++++++++--
 arch/arm64/boot/dts/mediatek/mt8173.dtsi               |  7 +++++--
 2 files changed, 13 insertions(+), 4 deletions(-)

-- 
2.25.1

[PATCH v2 0/2] arm64: dts: mt8173: Fix nor flash node

[Xiangsheng Hou]

Add axi clock since the driver change to DMA mode which need to enable
axi clock. And change spi clock to 26MHz as default.
Add assigned clock property and axi clock binding file.

Changes from v1:
- Modify nor binding file

Xiangsheng Hou (2):
  arm64: dts: mt8173: Fix nor_flash node
  dt-bindings: mediatek: Add assigned clock property and axi clock in
    example

 .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10 ++++++++--
 arch/arm64/boot/dts/mediatek/mt8173.dtsi               |  7 +++++--
 2 files changed, 13 insertions(+), 4 deletions(-)

-- 
2.25.1


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[PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[Xiangsheng Hou]

Add axi clock since the driver change to DMA mode which need
to enable axi clock. And change spi clock to 26MHz as default.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 40d7b47fc52e..e603170100af 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -790,9 +790,12 @@ thermal: thermal@1100b000 {
 		nor_flash: spi@1100d000 {
 			compatible = "mediatek,mt8173-nor";
 			reg = <0 0x1100d000 0 0xe0>;
+			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
+			assigned-clock-parents = <&clk26m>;
 			clocks = <&pericfg CLK_PERI_SPI>,
-				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
-			clock-names = "spi", "sf";
+				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
+				 <&pericfg CLK_PERI_NFI>;
+			clock-names = "spi", "sf", "axi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-- 
2.25.1

[PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[Xiangsheng Hou]

Add axi clock since the driver change to DMA mode which need
to enable axi clock. And change spi clock to 26MHz as default.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 40d7b47fc52e..e603170100af 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -790,9 +790,12 @@ thermal: thermal@1100b000 {
 		nor_flash: spi@1100d000 {
 			compatible = "mediatek,mt8173-nor";
 			reg = <0 0x1100d000 0 0xe0>;
+			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
+			assigned-clock-parents = <&clk26m>;
 			clocks = <&pericfg CLK_PERI_SPI>,
-				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
-			clock-names = "spi", "sf";
+				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
+				 <&pericfg CLK_PERI_NFI>;
+			clock-names = "spi", "sf", "axi";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-- 
2.25.1


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[PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example

[Xiangsheng Hou]

For mt8173, it is needed to add the axi clock for dma mode.
And it is may needed to adjust default spi frequency.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
 .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
index 41e60fe4b09f..7523d992a614 100644
--- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
@@ -61,6 +61,12 @@ properties:
       - const: axi
       - const: axi_s
 
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-parents:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -82,8 +88,8 @@ examples:
         compatible = "mediatek,mt8173-nor";
         reg = <0 0x1100d000 0 0xe0>;
         interrupts = <1>;
-        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
-        clock-names = "spi", "sf";
+        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>, <&pericfg CLK_PERI_NFI>;
+        clock-names = "spi", "sf", "axi";
         #address-cells = <1>;
         #size-cells = <0>;
 
-- 
2.25.1

[PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example

[Xiangsheng Hou]

For mt8173, it is needed to add the axi clock for dma mode.
And it is may needed to adjust default spi frequency.

Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
---
 .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
index 41e60fe4b09f..7523d992a614 100644
--- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
+++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
@@ -61,6 +61,12 @@ properties:
       - const: axi
       - const: axi_s
 
+  assigned-clocks:
+    maxItems: 1
+
+  assigned-clock-parents:
+    maxItems: 1
+
 required:
   - compatible
   - reg
@@ -82,8 +88,8 @@ examples:
         compatible = "mediatek,mt8173-nor";
         reg = <0 0x1100d000 0 0xe0>;
         interrupts = <1>;
-        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
-        clock-names = "spi", "sf";
+        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>, <&pericfg CLK_PERI_NFI>;
+        clock-names = "spi", "sf", "axi";
         #address-cells = <1>;
         #size-cells = <0>;
 
-- 
2.25.1


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Re: [PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example

[Krzysztof Kozlowski]

On 30/06/2022 11:01, Xiangsheng Hou wrote:
> For mt8173, it is needed to add the axi clock for dma mode.
> And it is may needed to adjust default spi frequency.
> 
> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> ---
>  .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
> index 41e60fe4b09f..7523d992a614 100644
> --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
> +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
> @@ -61,6 +61,12 @@ properties:
>        - const: axi
>        - const: axi_s
>  
> +  assigned-clocks:
> +    maxItems: 1
> +
> +  assigned-clock-parents:
> +    maxItems: 1
> +

There is usually no reason to put this in the bindings.

>  required:
>    - compatible
>    - reg
> @@ -82,8 +88,8 @@ examples:
>          compatible = "mediatek,mt8173-nor";
>          reg = <0 0x1100d000 0 0xe0>;
>          interrupts = <1>;
> -        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> -        clock-names = "spi", "sf";
> +        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>, <&pericfg CLK_PERI_NFI>;
> +        clock-names = "spi", "sf", "axi";
>          #address-cells = <1>;
>          #size-cells = <0>;
>  


Best regards,
Krzysztof

Re: [PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example

[Krzysztof Kozlowski]

On 30/06/2022 11:01, Xiangsheng Hou wrote:
> For mt8173, it is needed to add the axi clock for dma mode.
> And it is may needed to adjust default spi frequency.
> 
> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> ---
>  .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
> index 41e60fe4b09f..7523d992a614 100644
> --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
> +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml
> @@ -61,6 +61,12 @@ properties:
>        - const: axi
>        - const: axi_s
>  
> +  assigned-clocks:
> +    maxItems: 1
> +
> +  assigned-clock-parents:
> +    maxItems: 1
> +

There is usually no reason to put this in the bindings.

>  required:
>    - compatible
>    - reg
> @@ -82,8 +88,8 @@ examples:
>          compatible = "mediatek,mt8173-nor";
>          reg = <0 0x1100d000 0 0xe0>;
>          interrupts = <1>;
> -        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> -        clock-names = "spi", "sf";
> +        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>, <&pericfg CLK_PERI_NFI>;
> +        clock-names = "spi", "sf", "axi";
>          #address-cells = <1>;
>          #size-cells = <0>;
>  


Best regards,
Krzysztof

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Re: [PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example

[xiangsheng.hou]

On Thu, 2022-06-30 at 20:41 +0200, Krzysztof Kozlowski wrote:
> On 30/06/2022 11:01, Xiangsheng Hou wrote:
> > For mt8173, it is needed to add the axi clock for dma mode.
> > And it is may needed to adjust default spi frequency.
> > 
> > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> > ---
> >  .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10
> > ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mtk-nor.yaml
> > index 41e60fe4b09f..7523d992a614 100644
> > --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-
> > nor.yaml
> > +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-
> > nor.yaml
> > @@ -61,6 +61,12 @@ properties:
> >        - const: axi
> >        - const: axi_s
> >  
> > +  assigned-clocks:
> > +    maxItems: 1
> > +
> > +  assigned-clock-parents:
> > +    maxItems: 1
> > +
> 
> There is usually no reason to put this in the bindings. 
> 
Will be remove in next patch.

Re: [PATCH v2 2/2] dt-bindings: mediatek: Add assigned clock property and axi clock in example

[xiangsheng.hou]

On Thu, 2022-06-30 at 20:41 +0200, Krzysztof Kozlowski wrote:
> On 30/06/2022 11:01, Xiangsheng Hou wrote:
> > For mt8173, it is needed to add the axi clock for dma mode.
> > And it is may needed to adjust default spi frequency.
> > 
> > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> > ---
> >  .../devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml  | 10
> > ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-
> > mtk-nor.yaml
> > index 41e60fe4b09f..7523d992a614 100644
> > --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-
> > nor.yaml
> > +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-
> > nor.yaml
> > @@ -61,6 +61,12 @@ properties:
> >        - const: axi
> >        - const: axi_s
> >  
> > +  assigned-clocks:
> > +    maxItems: 1
> > +
> > +  assigned-clock-parents:
> > +    maxItems: 1
> > +
> 
> There is usually no reason to put this in the bindings. 
> 
Will be remove in next patch.
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Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[Matthias Brugger]

On 30/06/2022 11:01, Xiangsheng Hou wrote:
> Add axi clock since the driver change to DMA mode which need
> to enable axi clock. And change spi clock to 26MHz as default.
> 
> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 40d7b47fc52e..e603170100af 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -790,9 +790,12 @@ thermal: thermal@1100b000 {
>   		nor_flash: spi@1100d000 {
>   			compatible = "mediatek,mt8173-nor";
>   			reg = <0 0x1100d000 0 0xe0>;
> +			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
> +			assigned-clock-parents = <&clk26m>;
>   			clocks = <&pericfg CLK_PERI_SPI>,
> -				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> -			clock-names = "spi", "sf";
> +				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
> +				 <&pericfg CLK_PERI_NFI>;
> +			clock-names = "spi", "sf", "axi";
>   			#address-cells = <1>;
>   			#size-cells = <0>;
>   			status = "disabled";

Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[Matthias Brugger]

On 30/06/2022 11:01, Xiangsheng Hou wrote:
> Add axi clock since the driver change to DMA mode which need
> to enable axi clock. And change spi clock to 26MHz as default.
> 
> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 7 +++++--
>   1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 40d7b47fc52e..e603170100af 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -790,9 +790,12 @@ thermal: thermal@1100b000 {
>   		nor_flash: spi@1100d000 {
>   			compatible = "mediatek,mt8173-nor";
>   			reg = <0 0x1100d000 0 0xe0>;
> +			assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>;
> +			assigned-clock-parents = <&clk26m>;
>   			clocks = <&pericfg CLK_PERI_SPI>,
> -				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
> -			clock-names = "spi", "sf";
> +				 <&topckgen CLK_TOP_SPINFI_IFR_SEL>,
> +				 <&pericfg CLK_PERI_NFI>;
> +			clock-names = "spi", "sf", "axi";
>   			#address-cells = <1>;
>   			#size-cells = <0>;
>   			status = "disabled";

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Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[xiangsheng.hou]

Hi Matthias,

On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote:
> 
> On 30/06/2022 11:01, Xiangsheng Hou wrote:
> > Add axi clock since the driver change to DMA mode which need
> > to enable axi clock. And change spi clock to 26MHz as default.
> > 
> > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> 
> Applied, thanks!
> 
I will send a new patch v3 since there need a change in [PATCH v2 2/2]
by review.

Thanks
Xiangsheng Hou

Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[xiangsheng.hou]

Hi Matthias,

On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote:
> 
> On 30/06/2022 11:01, Xiangsheng Hou wrote:
> > Add axi clock since the driver change to DMA mode which need
> > to enable axi clock. And change spi clock to 26MHz as default.
> > 
> > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> 
> Applied, thanks!
> 
I will send a new patch v3 since there need a change in [PATCH v2 2/2]
by review.

Thanks
Xiangsheng Hou


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Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[Matthias Brugger]

On 08/07/2022 03:40, xiangsheng.hou wrote:
> Hi Matthias,
> 
> On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote:
>>
>> On 30/06/2022 11:01, Xiangsheng Hou wrote:
>>> Add axi clock since the driver change to DMA mode which need
>>> to enable axi clock. And change spi clock to 26MHz as default.
>>>
>>> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
>>
>> Applied, thanks!
>>
> I will send a new patch v3 since there need a change in [PATCH v2 2/2]
> by review.
> 

Thanks from letting me know. From what I can see, 1/2 in v3 did not change, so 
as I already applied it, you could have dropped it from the series.

Please correct me if I'm wrong.

Best regards,
Matthias

Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[Matthias Brugger]

On 08/07/2022 03:40, xiangsheng.hou wrote:
> Hi Matthias,
> 
> On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote:
>>
>> On 30/06/2022 11:01, Xiangsheng Hou wrote:
>>> Add axi clock since the driver change to DMA mode which need
>>> to enable axi clock. And change spi clock to 26MHz as default.
>>>
>>> Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
>>
>> Applied, thanks!
>>
> I will send a new patch v3 since there need a change in [PATCH v2 2/2]
> by review.
> 

Thanks from letting me know. From what I can see, 1/2 in v3 did not change, so 
as I already applied it, you could have dropped it from the series.

Please correct me if I'm wrong.

Best regards,
Matthias

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Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[xiangsheng.hou]

Hi Matthias,

On Fri, 2022-07-08 at 10:22 +0200, Matthias Brugger wrote:
> 
> On 08/07/2022 03:40, xiangsheng.hou wrote:
> > Hi Matthias,
> > 
> > On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote:
> > > 
> > > On 30/06/2022 11:01, Xiangsheng Hou wrote:
> > > > Add axi clock since the driver change to DMA mode which need
> > > > to enable axi clock. And change spi clock to 26MHz as default.
> > > > 
> > > > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> > > 
> > > Applied, thanks!
> > > 
> > 
> > I will send a new patch v3 since there need a change in [PATCH v2
> > 2/2]
> > by review.
> > 
> 
> Thanks from letting me know. From what I can see, 1/2 in v3 did not
> change, so 
> as I already applied it, you could have dropped it from the series.
> 
> Please correct me if I'm wrong.
> 
Yes, you are right and I will drop it if there will have next series.

Thanks
Xiangsheng Hou

Re: [PATCH v2 1/2] arm64: dts: mt8173: Fix nor_flash node

[xiangsheng.hou]

Hi Matthias,

On Fri, 2022-07-08 at 10:22 +0200, Matthias Brugger wrote:
> 
> On 08/07/2022 03:40, xiangsheng.hou wrote:
> > Hi Matthias,
> > 
> > On Thu, 2022-07-07 at 16:43 +0200, Matthias Brugger wrote:
> > > 
> > > On 30/06/2022 11:01, Xiangsheng Hou wrote:
> > > > Add axi clock since the driver change to DMA mode which need
> > > > to enable axi clock. And change spi clock to 26MHz as default.
> > > > 
> > > > Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
> > > 
> > > Applied, thanks!
> > > 
> > 
> > I will send a new patch v3 since there need a change in [PATCH v2
> > 2/2]
> > by review.
> > 
> 
> Thanks from letting me know. From what I can see, 1/2 in v3 did not
> change, so 
> as I already applied it, you could have dropped it from the series.
> 
> Please correct me if I'm wrong.
> 
Yes, you are right and I will drop it if there will have next series.

Thanks
Xiangsheng Hou
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