* [PATCH v12 0/7] arm64: sunxi: Allwinner H616 SoC DT support
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
Hi,
the usual update round on the H616 support series, this time only about
DT files, as the necessary code bits have been merged already.
For simplicity I dropped the USB patches again - for now.
There are three new binding patches, to fix dtbs_check complaints.
For the actual .dtsi and .dts files, I addressed Jernej's comments (many
thanks for having a look!)
This is on top of 5.19-rc4, and can also be found here:
https://github.com/apritzel/linux/commits/h616-v12
For a complete changelog, see below.
Thanks!
Andre
==================
This series gathers patches to support the Allwinner H616 SoC. This is
a rather uninspired SoC (Quad-A53 with the usual peripherals), but
allows for some cheap development boards and TV boxes, and supports
up to 4GB of DRAM.
Some DT binding patches are sprinkled throughout the series, to add
the new compatible names right before they are used.
Eventually we get the .dtsi for the SoC in patch 3, and the .dts for
the OrangePi Zero2 board[1] later, followed by the .dts for the X96 Mate
TV box[2] afterwards.
U-Boot and Trusted Firmware support is now merged in released versions,
it allows booting via FEL or SD card, also you can TFTP kernels in on
the OrangePi Zero 2 board.
Many thanks to Jernej for his tremendous help on this, also for the
awesome input and help from the #linux-sunxi IRC channel.
The whole series (including the prerequisites) can also be found here:
https://github.com/apritzel/linux/commits/h616-v12
Happy reviewing!
Cheers,
Andre
[1] https://linux-sunxi.org/Orange_Pi_Zero_2
[2] https://linux-sunxi.org/X96_Mate
Changelog v11 .. v12:
- Add EMAC compatible string to DT bindings
- Make pinctrl interrupts optional in the DT bindings
- Allow a vcc-pi-supply in the pinctrl DT bindings
- Fix RTC interrupt number in the .dtsi
- Add vcc-px-supply properties to the OrangePi Zero 2 DT
- Add /omit-if-no-ref/ to rarely used pinctrl subnodes
- Drop fixed pinctrl properties from the SPI nodes in the .dtsi
- Split off CS0 pin from the SPI0 pins
- Remove bogus interrupt properties from the R_PIO DT node
- Make DCDC-E regulator always-on
Changelog v10 .. v11:
- Drop already merged RTC patches
- Drop USB patches
- Also add RTC gate clock to the H6, but mark it as unused
- Add X96 Mate manufacturer to vendor list
Changelog v9 .. v10:
- based on ccu-sun6i-rtc clock driver
- add RTC bus clock and 32k system PLL clock
- drop clock related code from actual RTC driver (just use RTC bits)
- .dtsi: remove redundant status = "okay"; from .dtsi
- .dts: drop #address-cells = <0> from IRQ controller nodes
- .dtsi: fix indentation of IR node
- .dtsi: adjust RTC node to new binding
- re-add USB patches
Changelog v8 .. v9:
- RTC: Rely on the division to split of the H:M:S part from the day part
- Add Jernej's Review tags
Changelog v7 .. v8:
- Rebase on top of 5.14-rc1, which already includes the previous v7 02/19
- Drop USB and Ethernet patches (to keep series small)
- Use "clocks: false" in RTC DT binding (2/11)
- Include fix for RTC overflow check (3/11)
- Use div_64() to avoid linking error on some 32-bit platforms (4+5/11)
- Adjust to changed RTC overflow check (5/11)
- Drop USB nodes from .dtsi file
- Move mmc-ddr-1_8v property from .dtsi file into board .dts
- Fix DTC warnings (underscore in node name, soc@0, #a-c in IRQ controllers)
Changelog v6 .. v7:
- Fix AXP305 binding documentation blunder (01/19)
- Improve new linear day support (use existing conversion functions) (04/19)
- Add support for changed RTC alarm registers (05/19)
- Add support for RTCs without a LOSC clock (06/19)
- Rework USB PHY2 SIDDQ quirk to use PHY clocks directly (14/19)
- Add X96 Mate compatible string to binding doc (17/19)
- Add Rob's ACKs
Changelog v5 .. v6:
- Drop already merged clock, pinctrl and MMC support from this series
- Properly fix AXP support by skipping power key initialisation
- Add patch to support new RTC date storage encoding
- Re-add USB HCI PHY refactoring
- Add patch to allow USB reset line sharing
- Add patch to introduce quirk for PHY2 SIDDQ clearing
- Re-add USB nodes to the .dtsi
- Add USB gadget support
- Add DT for X96 Mate TV box
Changelog v4 .. v5:
- Fix CCU binding to pass dtbs_check
- Add RSB compatible string to binding doc
- Rename IR pin name to pass dtbs_check
- Add EMAC compatible string to binding doc
- Drop USB PHY support and binding doc patches
- Drop USB nodes from .dtsi and .dts
- Drop second EMAC node from .dtsi
Changelog v3 .. v4:
- Drop MMC and pinctrl matches (already in some -next trees)
- Add Maxime's Acks
- Add patch to update the AXP MFD DT bindings
- Add new patch (05/21) to fix axp20x-pek driver
- Change AXP IRQ fix to check for invalid IRQ line number
- Split joint DT bindings patch (v3 18/21) into subsystems
- move dwmac variable to keep christmas tree
- Use enums for USB PHY compatible strings in DT binding
- Enable watchdog (briefly verified to work)
- Add PHY2 to HCI1&3, this fixes USB
- limit r-ccu register frame length to not collide with NMI controller
- add interrupt-controller property to AXP DT node
Changelog v2 .. v3:
- Add Rob's Acks
- Drop redundant maxItems from pinctrl DT binding
- Rename h_i2s* to just i2s* in pinctrl names
- Use more declarative i2s0_d{in,out}{0,1} names
- Add RSB pins to pinctrl
- Include RSB clocks (sharing with newly added H6 versions)
- Fix CEC clock (add 2nd enable bit, also fix predivider flag)
- Rename PMU_UNK1 register in USB PHY
- Add USB and MUSB DT binding patches
- Add MMC/SD speed modes to .dtsi
Changelog v1 .. v2:
- pinctrl: adjust irq bank map to cover undocumented GPIO bank IRQs
- use differing h_i2s0 pin output names
- r-ccu: fix number of used clocks
- ccu: remove PLL-PERIPHy(4X)
- ccu: fix gpu1 divider range
- ccu: fix usb-phy3 parent
- ccu: add missing TV clocks
- ccu: rework to CLK_OF_DECLARE style
- ccu: enable output bit for PLL clocks
- ccu: renumber clocks
- .dtsi: drop sun50i-a64-system-control fallback
- .dtsi: drop unknown SRAM regions
- .dtsi: add more (undocumented) GPIO interrupts
- .dtsi: fix I2C3 pin names
- .dtsi: use a100-emmc fallback for MMC2
- .dtsi: add second EMAC controller
- .dtsi: use H3 MUSB controller fallback
- .dtsi: fix frame size for USB PHY PMU registers
- .dtsi: add USB0 PHY references
- .dtsi: fix IR controller clock source
- .dts: fix LED naming and swap pins
- .dts: use 5V supply parent for USB supply
- .dts: drop dummy IRQ for AXP
- .dts: enable 3V3 header pin power rail
- .dts: add SPI flash node
- .dts: make USB-C port peripheral only
- add IRQ-less AXP support
- add two patches to support more than one EMAC clock
- add patch to rework and extend USB PHY support
- add DT binding documentation patches
Andre Przywara (7):
dt-bindings: arm: sunxi: Add H616 EMAC compatible
dt-bindings: pinctrl: sunxi: Make interrupts optional
arm64: dts: allwinner: Add Allwinner H616 .dtsi file
dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
dt-bindings: arm: sunxi: Add two H616 board compatible strings
arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
arm64: dts: allwinner: h616: Add X96 Mate TV box support
.../devicetree/bindings/arm/sunxi.yaml | 10 +
.../net/allwinner,sun8i-a83t-emac.yaml | 1 +
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 17 +-
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/allwinner/Makefile | 2 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 213 +++++++
.../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
8 files changed, 997 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
--
2.25.1
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v12 0/7] arm64: sunxi: Allwinner H616 SoC DT support
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
Hi,
the usual update round on the H616 support series, this time only about
DT files, as the necessary code bits have been merged already.
For simplicity I dropped the USB patches again - for now.
There are three new binding patches, to fix dtbs_check complaints.
For the actual .dtsi and .dts files, I addressed Jernej's comments (many
thanks for having a look!)
This is on top of 5.19-rc4, and can also be found here:
https://github.com/apritzel/linux/commits/h616-v12
For a complete changelog, see below.
Thanks!
Andre
==================
This series gathers patches to support the Allwinner H616 SoC. This is
a rather uninspired SoC (Quad-A53 with the usual peripherals), but
allows for some cheap development boards and TV boxes, and supports
up to 4GB of DRAM.
Some DT binding patches are sprinkled throughout the series, to add
the new compatible names right before they are used.
Eventually we get the .dtsi for the SoC in patch 3, and the .dts for
the OrangePi Zero2 board[1] later, followed by the .dts for the X96 Mate
TV box[2] afterwards.
U-Boot and Trusted Firmware support is now merged in released versions,
it allows booting via FEL or SD card, also you can TFTP kernels in on
the OrangePi Zero 2 board.
Many thanks to Jernej for his tremendous help on this, also for the
awesome input and help from the #linux-sunxi IRC channel.
The whole series (including the prerequisites) can also be found here:
https://github.com/apritzel/linux/commits/h616-v12
Happy reviewing!
Cheers,
Andre
[1] https://linux-sunxi.org/Orange_Pi_Zero_2
[2] https://linux-sunxi.org/X96_Mate
Changelog v11 .. v12:
- Add EMAC compatible string to DT bindings
- Make pinctrl interrupts optional in the DT bindings
- Allow a vcc-pi-supply in the pinctrl DT bindings
- Fix RTC interrupt number in the .dtsi
- Add vcc-px-supply properties to the OrangePi Zero 2 DT
- Add /omit-if-no-ref/ to rarely used pinctrl subnodes
- Drop fixed pinctrl properties from the SPI nodes in the .dtsi
- Split off CS0 pin from the SPI0 pins
- Remove bogus interrupt properties from the R_PIO DT node
- Make DCDC-E regulator always-on
Changelog v10 .. v11:
- Drop already merged RTC patches
- Drop USB patches
- Also add RTC gate clock to the H6, but mark it as unused
- Add X96 Mate manufacturer to vendor list
Changelog v9 .. v10:
- based on ccu-sun6i-rtc clock driver
- add RTC bus clock and 32k system PLL clock
- drop clock related code from actual RTC driver (just use RTC bits)
- .dtsi: remove redundant status = "okay"; from .dtsi
- .dts: drop #address-cells = <0> from IRQ controller nodes
- .dtsi: fix indentation of IR node
- .dtsi: adjust RTC node to new binding
- re-add USB patches
Changelog v8 .. v9:
- RTC: Rely on the division to split of the H:M:S part from the day part
- Add Jernej's Review tags
Changelog v7 .. v8:
- Rebase on top of 5.14-rc1, which already includes the previous v7 02/19
- Drop USB and Ethernet patches (to keep series small)
- Use "clocks: false" in RTC DT binding (2/11)
- Include fix for RTC overflow check (3/11)
- Use div_64() to avoid linking error on some 32-bit platforms (4+5/11)
- Adjust to changed RTC overflow check (5/11)
- Drop USB nodes from .dtsi file
- Move mmc-ddr-1_8v property from .dtsi file into board .dts
- Fix DTC warnings (underscore in node name, soc@0, #a-c in IRQ controllers)
Changelog v6 .. v7:
- Fix AXP305 binding documentation blunder (01/19)
- Improve new linear day support (use existing conversion functions) (04/19)
- Add support for changed RTC alarm registers (05/19)
- Add support for RTCs without a LOSC clock (06/19)
- Rework USB PHY2 SIDDQ quirk to use PHY clocks directly (14/19)
- Add X96 Mate compatible string to binding doc (17/19)
- Add Rob's ACKs
Changelog v5 .. v6:
- Drop already merged clock, pinctrl and MMC support from this series
- Properly fix AXP support by skipping power key initialisation
- Add patch to support new RTC date storage encoding
- Re-add USB HCI PHY refactoring
- Add patch to allow USB reset line sharing
- Add patch to introduce quirk for PHY2 SIDDQ clearing
- Re-add USB nodes to the .dtsi
- Add USB gadget support
- Add DT for X96 Mate TV box
Changelog v4 .. v5:
- Fix CCU binding to pass dtbs_check
- Add RSB compatible string to binding doc
- Rename IR pin name to pass dtbs_check
- Add EMAC compatible string to binding doc
- Drop USB PHY support and binding doc patches
- Drop USB nodes from .dtsi and .dts
- Drop second EMAC node from .dtsi
Changelog v3 .. v4:
- Drop MMC and pinctrl matches (already in some -next trees)
- Add Maxime's Acks
- Add patch to update the AXP MFD DT bindings
- Add new patch (05/21) to fix axp20x-pek driver
- Change AXP IRQ fix to check for invalid IRQ line number
- Split joint DT bindings patch (v3 18/21) into subsystems
- move dwmac variable to keep christmas tree
- Use enums for USB PHY compatible strings in DT binding
- Enable watchdog (briefly verified to work)
- Add PHY2 to HCI1&3, this fixes USB
- limit r-ccu register frame length to not collide with NMI controller
- add interrupt-controller property to AXP DT node
Changelog v2 .. v3:
- Add Rob's Acks
- Drop redundant maxItems from pinctrl DT binding
- Rename h_i2s* to just i2s* in pinctrl names
- Use more declarative i2s0_d{in,out}{0,1} names
- Add RSB pins to pinctrl
- Include RSB clocks (sharing with newly added H6 versions)
- Fix CEC clock (add 2nd enable bit, also fix predivider flag)
- Rename PMU_UNK1 register in USB PHY
- Add USB and MUSB DT binding patches
- Add MMC/SD speed modes to .dtsi
Changelog v1 .. v2:
- pinctrl: adjust irq bank map to cover undocumented GPIO bank IRQs
- use differing h_i2s0 pin output names
- r-ccu: fix number of used clocks
- ccu: remove PLL-PERIPHy(4X)
- ccu: fix gpu1 divider range
- ccu: fix usb-phy3 parent
- ccu: add missing TV clocks
- ccu: rework to CLK_OF_DECLARE style
- ccu: enable output bit for PLL clocks
- ccu: renumber clocks
- .dtsi: drop sun50i-a64-system-control fallback
- .dtsi: drop unknown SRAM regions
- .dtsi: add more (undocumented) GPIO interrupts
- .dtsi: fix I2C3 pin names
- .dtsi: use a100-emmc fallback for MMC2
- .dtsi: add second EMAC controller
- .dtsi: use H3 MUSB controller fallback
- .dtsi: fix frame size for USB PHY PMU registers
- .dtsi: add USB0 PHY references
- .dtsi: fix IR controller clock source
- .dts: fix LED naming and swap pins
- .dts: use 5V supply parent for USB supply
- .dts: drop dummy IRQ for AXP
- .dts: enable 3V3 header pin power rail
- .dts: add SPI flash node
- .dts: make USB-C port peripheral only
- add IRQ-less AXP support
- add two patches to support more than one EMAC clock
- add patch to rework and extend USB PHY support
- add DT binding documentation patches
Andre Przywara (7):
dt-bindings: arm: sunxi: Add H616 EMAC compatible
dt-bindings: pinctrl: sunxi: Make interrupts optional
arm64: dts: allwinner: Add Allwinner H616 .dtsi file
dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
dt-bindings: arm: sunxi: Add two H616 board compatible strings
arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
arm64: dts: allwinner: h616: Add X96 Mate TV box support
.../devicetree/bindings/arm/sunxi.yaml | 10 +
.../net/allwinner,sun8i-a83t-emac.yaml | 1 +
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 17 +-
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/allwinner/Makefile | 2 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 213 +++++++
.../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
8 files changed, 997 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
version.
Add it to the list of compatible strings.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
index 6a4831fd3616c..87f1306831cc9 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -22,6 +22,7 @@ properties:
- enum:
- allwinner,sun20i-d1-emac
- allwinner,sun50i-h6-emac
+ - allwinner,sun50i-h616-emac
- const: allwinner,sun50i-a64-emac
reg:
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
version.
Add it to the list of compatible strings.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
index 6a4831fd3616c..87f1306831cc9 100644
--- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
@@ -22,6 +22,7 @@ properties:
- enum:
- allwinner,sun20i-d1-emac
- allwinner,sun50i-h6-emac
+ - allwinner,sun50i-h616-emac
- const: allwinner,sun50i-a64-emac
reg:
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
interrupt (it features only two pins).
However the binding requires at least naming one upstream interrupt,
plus the #interrupt-cells and interrupt-controller properties.
Drop the unconditional requirement for the interrupt properties, and
make them dependent on being not this particular pinctrl device.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index bfce850c20351..0bd903954195b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -133,14 +133,11 @@ patternProperties:
required:
- "#gpio-cells"
- - "#interrupt-cells"
- compatible
- reg
- - interrupts
- clocks
- clock-names
- gpio-controller
- - interrupt-controller
allOf:
# FIXME: We should have the pin bank supplies here, but not a lot of
@@ -148,6 +145,18 @@ allOf:
# warnings.
- $ref: "pinctrl.yaml#"
+ - if:
+ not:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun50i-h616-r-pinctrl
+ then:
+ required:
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-controller
+
- if:
properties:
compatible:
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
interrupt (it features only two pins).
However the binding requires at least naming one upstream interrupt,
plus the #interrupt-cells and interrupt-controller properties.
Drop the unconditional requirement for the interrupt properties, and
make them dependent on being not this particular pinctrl device.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index bfce850c20351..0bd903954195b 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -133,14 +133,11 @@ patternProperties:
required:
- "#gpio-cells"
- - "#interrupt-cells"
- compatible
- reg
- - interrupts
- clocks
- clock-names
- gpio-controller
- - interrupt-controller
allOf:
# FIXME: We should have the pin bank supplies here, but not a lot of
@@ -148,6 +145,18 @@ allOf:
# warnings.
- $ref: "pinctrl.yaml#"
+ - if:
+ not:
+ properties:
+ compatible:
+ enum:
+ - allwinner,sun50i-h616-r-pinctrl
+ then:
+ required:
+ - "#interrupt-cells"
+ - interrupts
+ - interrupt-controller
+
- if:
properties:
compatible:
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
And while there is still the extra sunxi interrupt controller, the
package lacks the corresponding NMI pin, so no interrupts for the PMIC.
The reserved memory node is actually handled by Trusted Firmware now,
but U-Boot fails to propagate this to a separately loaded DTB, so we
keep it in here for now, until U-Boot learns to do this properly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
1 file changed, 579 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index 0000000000000..478f0b395ff58
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun50i-h616-ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h616-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@40000000 {
+ reg = <0x0 0x40000000 0x0 0x80000>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x40000000>;
+
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x03000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x30000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x30000>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h616-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x030090a0 0x20>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-h616-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ ext_rgmii_pins: rgmii-pins {
+ pins = "PI0", "PI1", "PI2", "PI3", "PI4",
+ "PI5", "PI7", "PI8", "PI9", "PI10",
+ "PI11", "PI12", "PI13", "PI14", "PI15",
+ "PI16";
+ function = "emac0";
+ drive-strength = <40>;
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins = "PI6", "PI7";
+ function = "i2c0";
+ };
+
+ i2c3_ph_pins: i2c3-ph-pins {
+ pins = "PH4", "PH5";
+ function = "i2c3";
+ };
+
+ ir_rx_pin: ir-rx-pin {
+ pins = "PH10";
+ function = "ir_rx";
+ };
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC0", "PC1", "PC5", "PC6",
+ "PC8", "PC9", "PC10", "PC11",
+ "PC13", "PC14", "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "PC0", "PC2", "PC4";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi0_cs0_pin: spi0-cs0-pin {
+ pins = "PC3";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi1_pins: spi1-pins {
+ pins = "PH6", "PH7", "PH8";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs0_pin: spi1-cs0-pin {
+ pins = "PH5";
+ function = "spi1";
+ };
+
+ uart0_ph_pins: uart0-ph-pins {
+ pins = "PH0", "PH1";
+ function = "uart0";
+ };
+
+ /omit-if-no-ref/
+ uart1_pins: uart1-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ };
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun50i-h616-mmc",
+ "allwinner,sun50i-a100-mmc";
+ reg = <0x04020000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun50i-h616-mmc",
+ "allwinner,sun50i-a100-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "disabled";
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun50i-h616-emmc",
+ "allwinner,sun50i-a100-emmc";
+ reg = <0x04022000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ status = "disabled";
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@5000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@5000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@5000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@5000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@5001000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05001000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
+ uart5: serial@5001400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05001400 0x400>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@5002000 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@5002400 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002400 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@5002800 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002800 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@5002c00 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002c00 0x400>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@5003000 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05003000 0x400>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@5010000 {
+ compatible = "allwinner,sun50i-h616-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x05010000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@5011000 {
+ compatible = "allwinner,sun50i-h616-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x05011000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac0: ethernet@5020000 {
+ compatible = "allwinner,sun50i-h616-emac",
+ "allwinner,sun50i-a64-emac";
+ syscon = <&syscon>;
+ reg = <0x05020000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC0>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC0>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ rtc: rtc@7000000 {
+ compatible = "allwinner,sun50i-h616-rtc";
+ reg = <0x07000000 0x400>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
+ <&ccu CLK_PLL_SYSTEM_32K>;
+ clock-names = "bus", "hosc",
+ "pll-32k";
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
+ #clock-cells = <1>;
+ };
+
+ r_ccu: clock@7010000 {
+ compatible = "allwinner,sun50i-h616-r-ccu";
+ reg = <0x07010000 0x210>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ <&ccu CLK_PLL_PERIPH0>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ r_pio: pinctrl@7022000 {
+ compatible = "allwinner,sun50i-h616-r-pinctrl";
+ reg = <0x07022000 0x400>;
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+
+ r_i2c_pins: r-i2c-pins {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+
+ r_rsb_pins: r-rsb-pins {
+ pins = "PL0", "PL1";
+ function = "s_rsb";
+ };
+ };
+
+ ir: ir@7040000 {
+ compatible = "allwinner,sun50i-h616-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,
+ <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_R_APB1_IR>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx_pin>;
+ status = "disabled";
+ };
+
+ r_i2c: i2c@7081400 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x07081400 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
+ resets = <&r_ccu RST_R_APB2_I2C>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ r_rsb: rsb@7083000 {
+ compatible = "allwinner,sun50i-h616-rsb",
+ "allwinner,sun8i-a23-rsb";
+ reg = <0x07083000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_RSB>;
+ clock-frequency = <3000000>;
+ resets = <&r_ccu RST_R_APB2_RSB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
And while there is still the extra sunxi interrupt controller, the
package lacks the corresponding NMI pin, so no interrupts for the PMIC.
The reserved memory node is actually handled by Trusted Firmware now,
but U-Boot fails to propagate this to a separately loaded DTB, so we
keep it in here for now, until U-Boot learns to do this properly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
1 file changed, 579 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index 0000000000000..478f0b395ff58
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun50i-h616-ccu.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h616-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = <&ccu CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@40000000 {
+ reg = <0x0 0x40000000 0x0 0x80000>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ soc@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x40000000>;
+
+ syscon: syscon@3000000 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x03000000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x30000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x30000>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = <0x03001000 0x1000>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
+ clock-names = "hosc", "losc", "iosc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h616-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x030090a0 0x20>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-h616-pinctrl";
+ reg = <0x0300b000 0x400>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ ext_rgmii_pins: rgmii-pins {
+ pins = "PI0", "PI1", "PI2", "PI3", "PI4",
+ "PI5", "PI7", "PI8", "PI9", "PI10",
+ "PI11", "PI12", "PI13", "PI14", "PI15",
+ "PI16";
+ function = "emac0";
+ drive-strength = <40>;
+ };
+
+ i2c0_pins: i2c0-pins {
+ pins = "PI6", "PI7";
+ function = "i2c0";
+ };
+
+ i2c3_ph_pins: i2c3-ph-pins {
+ pins = "PH4", "PH5";
+ function = "i2c3";
+ };
+
+ ir_rx_pin: ir-rx-pin {
+ pins = "PH10";
+ function = "ir_rx";
+ };
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ mmc2_pins: mmc2-pins {
+ pins = "PC0", "PC1", "PC5", "PC6",
+ "PC8", "PC9", "PC10", "PC11",
+ "PC13", "PC14", "PC15", "PC16";
+ function = "mmc2";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ spi0_pins: spi0-pins {
+ pins = "PC0", "PC2", "PC4";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi0_cs0_pin: spi0-cs0-pin {
+ pins = "PC3";
+ function = "spi0";
+ };
+
+ /omit-if-no-ref/
+ spi1_pins: spi1-pins {
+ pins = "PH6", "PH7", "PH8";
+ function = "spi1";
+ };
+
+ /omit-if-no-ref/
+ spi1_cs0_pin: spi1-cs0-pin {
+ pins = "PH5";
+ function = "spi1";
+ };
+
+ uart0_ph_pins: uart0-ph-pins {
+ pins = "PH0", "PH1";
+ function = "uart0";
+ };
+
+ /omit-if-no-ref/
+ uart1_pins: uart1-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
+ };
+ };
+
+ gic: interrupt-controller@3021000 {
+ compatible = "arm,gic-400";
+ reg = <0x03021000 0x1000>,
+ <0x03022000 0x2000>,
+ <0x03024000 0x2000>,
+ <0x03026000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ mmc0: mmc@4020000 {
+ compatible = "allwinner,sun50i-h616-mmc",
+ "allwinner,sun50i-a100-mmc";
+ reg = <0x04020000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@4021000 {
+ compatible = "allwinner,sun50i-h616-mmc",
+ "allwinner,sun50i-a100-mmc";
+ reg = <0x04021000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "disabled";
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc2: mmc@4022000 {
+ compatible = "allwinner,sun50i-h616-emmc",
+ "allwinner,sun50i-a100-emmc";
+ reg = <0x04022000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ clock-names = "ahb", "mmc";
+ resets = <&ccu RST_BUS_MMC2>;
+ reset-names = "ahb";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ status = "disabled";
+ max-frequency = <150000000>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-3_3v;
+ cap-sdio-irq;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@5000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000000 0x400>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART0>;
+ resets = <&ccu RST_BUS_UART0>;
+ status = "disabled";
+ };
+
+ uart1: serial@5000400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000400 0x400>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART1>;
+ resets = <&ccu RST_BUS_UART1>;
+ status = "disabled";
+ };
+
+ uart2: serial@5000800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@5000c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05000c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@5001000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05001000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
+ uart5: serial@5001400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x05001400 0x400>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART5>;
+ resets = <&ccu RST_BUS_UART5>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@5002000 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C0>;
+ resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@5002400 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002400 0x400>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C1>;
+ resets = <&ccu RST_BUS_I2C1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@5002800 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002800 0x400>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C2>;
+ resets = <&ccu RST_BUS_I2C2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@5002c00 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05002c00 0x400>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C3>;
+ resets = <&ccu RST_BUS_I2C3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@5003000 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x05003000 0x400>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2C4>;
+ resets = <&ccu RST_BUS_I2C4>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@5010000 {
+ compatible = "allwinner,sun50i-h616-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x05010000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@5011000 {
+ compatible = "allwinner,sun50i-h616-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x05011000 0x1000>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac0: ethernet@5020000 {
+ compatible = "allwinner,sun50i-h616-emac",
+ "allwinner,sun50i-a64-emac";
+ syscon = <&syscon>;
+ reg = <0x05020000 0x10000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC0>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC0>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ rtc: rtc@7000000 {
+ compatible = "allwinner,sun50i-h616-rtc";
+ reg = <0x07000000 0x400>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
+ <&ccu CLK_PLL_SYSTEM_32K>;
+ clock-names = "bus", "hosc",
+ "pll-32k";
+ clock-output-names = "osc32k", "osc32k-out", "iosc";
+ #clock-cells = <1>;
+ };
+
+ r_ccu: clock@7010000 {
+ compatible = "allwinner,sun50i-h616-r-ccu";
+ reg = <0x07010000 0x210>;
+ clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
+ <&ccu CLK_PLL_PERIPH0>;
+ clock-names = "hosc", "losc", "iosc", "pll-periph";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ r_pio: pinctrl@7022000 {
+ compatible = "allwinner,sun50i-h616-r-pinctrl";
+ reg = <0x07022000 0x400>;
+ clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
+ clock-names = "apb", "hosc", "losc";
+ gpio-controller;
+ #gpio-cells = <3>;
+
+ r_i2c_pins: r-i2c-pins {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+
+ r_rsb_pins: r-rsb-pins {
+ pins = "PL0", "PL1";
+ function = "s_rsb";
+ };
+ };
+
+ ir: ir@7040000 {
+ compatible = "allwinner,sun50i-h616-ir",
+ "allwinner,sun6i-a31-ir";
+ reg = <0x07040000 0x400>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB1_IR>,
+ <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_R_APB1_IR>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_rx_pin>;
+ status = "disabled";
+ };
+
+ r_i2c: i2c@7081400 {
+ compatible = "allwinner,sun50i-h616-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x07081400 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_I2C>;
+ resets = <&r_ccu RST_R_APB2_I2C>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ r_rsb: rsb@7083000 {
+ compatible = "allwinner,sun50i-h616-rsb",
+ "allwinner,sun8i-a23-rsb";
+ reg = <0x07083000 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_R_APB2_RSB>;
+ clock-frequency = <3000000>;
+ resets = <&r_ccu RST_R_APB2_RSB>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_rsb_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
for GPIO port I.
Extend the range of supply port names to include vcc-pi-supply to cover
that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 0bd903954195b..25d31c8a191a8 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -127,7 +127,7 @@ patternProperties:
additionalProperties: false
- "^vcc-p[a-hlm]-supply$":
+ "^vcc-p[a-ilm]-supply$":
description:
Power supplies for pin banks.
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
for GPIO port I.
Extend the range of supply port names to include vcc-pi-supply to cover
that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
.../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index 0bd903954195b..25d31c8a191a8 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -127,7 +127,7 @@ patternProperties:
additionalProperties: false
- "^vcc-p[a-hlm]-supply$":
+ "^vcc-p[a-ilm]-supply$":
description:
Power supplies for pin banks.
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 5/7] dt-bindings: arm: sunxi: Add two H616 board compatible strings
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, Rob Herring
This adds the two board compatible strings of two boards with the
Allwinner H616 SoC. One is a development board from OrangePi, the other
some TV box from some formerly unused vendor. Add that vendor to the
vendor list on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++++++++++
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 95278a6a9a8ec..0c2356778208a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -863,6 +863,11 @@ properties:
- const: yones-toptech,bs1078-v2
- const: allwinner,sun6i-a31s
+ - description: X96 Mate TV box
+ items:
+ - const: hechuang,x96-mate
+ - const: allwinner,sun50i-h616
+
- description: Xunlong OrangePi
items:
- const: xunlong,orangepi
@@ -963,4 +968,9 @@ properties:
- const: xunlong,orangepi-zero-plus2-h3
- const: allwinner,sun8i-h3
+ - description: Xunlong OrangePi Zero 2
+ items:
+ - const: xunlong,orangepi-zero2
+ - const: allwinner,sun50i-h616
+
additionalProperties: true
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 0496773a3c4d8..f0db732096941 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -510,6 +510,8 @@ patternProperties:
description: Haoyu Microelectronic Co. Ltd.
"^hardkernel,.*":
description: Hardkernel Co., Ltd
+ "^hechuang,.*":
+ description: Shenzhen Hechuang Intelligent Co.
"^hideep,.*":
description: HiDeep Inc.
"^himax,.*":
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 5/7] dt-bindings: arm: sunxi: Add two H616 board compatible strings
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, Rob Herring
This adds the two board compatible strings of two boards with the
Allwinner H616 SoC. One is a development board from OrangePi, the other
some TV box from some formerly unused vendor. Add that vendor to the
vendor list on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 10 ++++++++++
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 95278a6a9a8ec..0c2356778208a 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.yaml
+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
@@ -863,6 +863,11 @@ properties:
- const: yones-toptech,bs1078-v2
- const: allwinner,sun6i-a31s
+ - description: X96 Mate TV box
+ items:
+ - const: hechuang,x96-mate
+ - const: allwinner,sun50i-h616
+
- description: Xunlong OrangePi
items:
- const: xunlong,orangepi
@@ -963,4 +968,9 @@ properties:
- const: xunlong,orangepi-zero-plus2-h3
- const: allwinner,sun8i-h3
+ - description: Xunlong OrangePi Zero 2
+ items:
+ - const: xunlong,orangepi-zero2
+ - const: allwinner,sun50i-h616
+
additionalProperties: true
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 0496773a3c4d8..f0db732096941 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -510,6 +510,8 @@ patternProperties:
description: Haoyu Microelectronic Co. Ltd.
"^hardkernel,.*":
description: Hardkernel Co., Ltd
+ "^hechuang,.*":
+ description: Shenzhen Hechuang Intelligent Co.
"^hideep,.*":
description: HiDeep Inc.
"^himax,.*":
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
The OrangePi Zero 2 is a development board with the new H616 SoC. It
comes with the following features:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 512MiB/1GiB DDR3 DRAM
- AXP305 PMIC
- Raspberry-Pi-1 compatible GPIO header
- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
- 1 USB 2.0 host port
- 1 USB 2.0 type C port (power supply + OTG)
- MicroSD slot
- on-board 2MiB bootable SPI NOR flash
- 1Gbps Ethernet port (via RTL8211F PHY)
- micro-HDMI port
- (yet) unsupported Allwinner WiFi/BT chip
Add the devicetree file describing the currently supported features.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++
2 files changed, 214 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 8fa5c060a4fef..df2214e6d946a 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index 0000000000000..cff199536d3bc
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 = &emac0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&emac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio0 {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdce>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+ "x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <®_vcc5v>;
+ vinb-supply = <®_vcc5v>;
+ vinc-supply = <®_vcc5v>;
+ vind-supply = <®_vcc5v>;
+ vine-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ bldoin-supply = <®_vcc5v>;
+ cldoin-supply = <®_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-sys";
+ };
+
+ reg_aldo2: aldo2 { /* 3.3V on headers */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext";
+ };
+
+ reg_aldo3: aldo3 { /* 3.3V on headers */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext2";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ bldo2 {
+ /* unused */
+ };
+
+ bldo3 {
+ /* unused */
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ cldo1 {
+ /* reserved */
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-eth-mmc";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&pio {
+ vcc-pc-supply = <®_aldo1>;
+ vcc-pf-supply = <®_aldo1>;
+ vcc-pg-supply = <®_bldo1>;
+ vcc-ph-supply = <®_aldo1>;
+ vcc-pi-supply = <®_aldo1>;
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
The OrangePi Zero 2 is a development board with the new H616 SoC. It
comes with the following features:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 512MiB/1GiB DDR3 DRAM
- AXP305 PMIC
- Raspberry-Pi-1 compatible GPIO header
- extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
- 1 USB 2.0 host port
- 1 USB 2.0 type C port (power supply + OTG)
- MicroSD slot
- on-board 2MiB bootable SPI NOR flash
- 1Gbps Ethernet port (via RTL8211F PHY)
- micro-HDMI port
- (yet) unsupported Allwinner WiFi/BT chip
Add the devicetree file describing the currently supported features.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++
2 files changed, 214 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 8fa5c060a4fef..df2214e6d946a 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index 0000000000000..cff199536d3bc
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 = &emac0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&emac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <®_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+&mdio0 {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdce>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+ "x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <®_vcc5v>;
+ vinb-supply = <®_vcc5v>;
+ vinc-supply = <®_vcc5v>;
+ vind-supply = <®_vcc5v>;
+ vine-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ bldoin-supply = <®_vcc5v>;
+ cldoin-supply = <®_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-sys";
+ };
+
+ reg_aldo2: aldo2 { /* 3.3V on headers */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext";
+ };
+
+ reg_aldo3: aldo3 { /* 3.3V on headers */
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext2";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ bldo2 {
+ /* unused */
+ };
+
+ bldo3 {
+ /* unused */
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ cldo1 {
+ /* reserved */
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-eth-mmc";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&pio {
+ vcc-pc-supply = <®_aldo1>;
+ vcc-pf-supply = <®_aldo1>;
+ vcc-pg-supply = <®_bldo1>;
+ vcc-ph-supply = <®_aldo1>;
+ vcc-pi-supply = <®_aldo1>;
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 11:24 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
The X96 Mate is an Allwinner H616 based TV box, featuring:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 2GiB/4GiB RAM (fully usable!)
- 16/32/64GiB eMMC
- 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
- Unsupported Allwinner WiFi chip
- 2 x USB 2.0 host ports
- HDMI port
- IR receiver
- 5V/2A DC power supply via barrel plug
Add a basic devicetree for it, with SD card and eMMC working, as
well as serial and the essential peripherals, like the AXP PMIC.
This DT is somewhat minimal, and should work on many other similar TV
boxes with the Allwinner H616 chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++
2 files changed, 178 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index df2214e6d946a..6a96494a2e0a3 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
new file mode 100644
index 0000000000000..30b76140b9c8a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2021 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "X96 Mate";
+ compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC input */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ir {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdce>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_dcdce>;
+ vqmmc-supply = <®_bldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+ "x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <®_vcc5v>;
+ vinb-supply = <®_vcc5v>;
+ vinc-supply = <®_vcc5v>;
+ vind-supply = <®_vcc5v>;
+ vine-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ bldoin-supply = <®_vcc5v>;
+ cldoin-supply = <®_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-sys";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext";
+ status = "disabled";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_aldo3: aldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext2";
+ status = "disabled";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_bldo2: bldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8-2";
+ status = "disabled";
+ };
+
+ bldo3 {
+ /* unused */
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ cldo1 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc2v5";
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <1360000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-eth-mmc";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support
@ 2022-07-01 11:24 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-01 11:24 UTC (permalink / raw)
To: Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi, linux-kernel
The X96 Mate is an Allwinner H616 based TV box, featuring:
- Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
- 2GiB/4GiB RAM (fully usable!)
- 16/32/64GiB eMMC
- 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
- Unsupported Allwinner WiFi chip
- 2 x USB 2.0 host ports
- HDMI port
- IR receiver
- 5V/2A DC power supply via barrel plug
Add a basic devicetree for it, with SD card and eMMC working, as
well as serial and the essential peripherals, like the AXP PMIC.
This DT is somewhat minimal, and should work on many other similar TV
boxes with the Allwinner H616 chip.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++
2 files changed, 178 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index df2214e6d946a..6a96494a2e0a3 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
new file mode 100644
index 0000000000000..30b76140b9c8a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2021 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "X96 Mate";
+ compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC input */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&ir {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdce>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_dcdce>;
+ vqmmc-supply = <®_bldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+ "x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <®_vcc5v>;
+ vinb-supply = <®_vcc5v>;
+ vinc-supply = <®_vcc5v>;
+ vind-supply = <®_vcc5v>;
+ vine-supply = <®_vcc5v>;
+ aldoin-supply = <®_vcc5v>;
+ bldoin-supply = <®_vcc5v>;
+ cldoin-supply = <®_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-sys";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_aldo2: aldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext";
+ status = "disabled";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_aldo3: aldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3-ext2";
+ status = "disabled";
+ };
+
+ reg_bldo1: bldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8";
+ };
+
+ /* Enabled by the Android BSP */
+ reg_bldo2: bldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8-2";
+ status = "disabled";
+ };
+
+ bldo3 {
+ /* unused */
+ };
+
+ bldo4 {
+ /* unused */
+ };
+
+ cldo1 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc2v5";
+ };
+
+ cldo2 {
+ /* unused */
+ };
+
+ cldo3 {
+ /* unused */
+ };
+
+ reg_dcdca: dcdca {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdcc: dcdcc {
+ regulator-always-on;
+ regulator-min-microvolt = <810000>;
+ regulator-max-microvolt = <1080000>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdcd: dcdcd {
+ regulator-always-on;
+ regulator-min-microvolt = <1360000>;
+ regulator-max-microvolt = <1360000>;
+ regulator-name = "vdd-dram";
+ };
+
+ reg_dcdce: dcdce {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-eth-mmc";
+ };
+
+ sw {
+ /* unused */
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 20:56 ` Rob Herring
-1 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-07-01 20:56 UTC (permalink / raw)
To: Andre Przywara
Cc: Jakub Kicinski, Paolo Abeni, Krzysztof Kozlowski, devicetree,
linux-sunxi, David S. Miller, linux-arm-kernel, linux-kernel,
Jernej Skrabec, netdev, Eric Dumazet, Linus Walleij,
Chen-Yu Tsai, Rob Herring, Samuel Holland
On Fri, 01 Jul 2022 12:24:47 +0100, Andre Przywara wrote:
> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> version.
>
> Add it to the list of compatible strings.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
@ 2022-07-01 20:56 ` Rob Herring
0 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-07-01 20:56 UTC (permalink / raw)
To: Andre Przywara
Cc: Jakub Kicinski, Paolo Abeni, Krzysztof Kozlowski, devicetree,
linux-sunxi, David S. Miller, linux-arm-kernel, linux-kernel,
Jernej Skrabec, netdev, Eric Dumazet, Linus Walleij,
Chen-Yu Tsai, Rob Herring, Samuel Holland
On Fri, 01 Jul 2022 12:24:47 +0100, Andre Przywara wrote:
> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> version.
>
> Add it to the list of compatible strings.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 20:57 ` Rob Herring
-1 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-07-01 20:57 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Rob Herring, linux-arm-kernel, Jernej Skrabec,
Samuel Holland, Linus Walleij, Krzysztof Kozlowski, linux-kernel,
linux-gpio, devicetree, linux-sunxi
On Fri, 01 Jul 2022 12:24:48 +0100, Andre Przywara wrote:
> The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
> interrupt (it features only two pins).
> However the binding requires at least naming one upstream interrupt,
> plus the #interrupt-cells and interrupt-controller properties.
>
> Drop the unconditional requirement for the interrupt properties, and
> make them dependent on being not this particular pinctrl device.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional
@ 2022-07-01 20:57 ` Rob Herring
0 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-07-01 20:57 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Rob Herring, linux-arm-kernel, Jernej Skrabec,
Samuel Holland, Linus Walleij, Krzysztof Kozlowski, linux-kernel,
linux-gpio, devicetree, linux-sunxi
On Fri, 01 Jul 2022 12:24:48 +0100, Andre Przywara wrote:
> The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
> interrupt (it features only two pins).
> However the binding requires at least naming one upstream interrupt,
> plus the #interrupt-cells and interrupt-controller properties.
>
> Drop the unconditional requirement for the interrupt properties, and
> make them dependent on being not this particular pinctrl device.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-01 20:57 ` Rob Herring
-1 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-07-01 20:57 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Linus Walleij, linux-kernel, devicetree,
linux-arm-kernel, Samuel Holland, Krzysztof Kozlowski,
linux-sunxi, Jernej Skrabec, linux-gpio, Rob Herring
On Fri, 01 Jul 2022 12:24:50 +0100, Andre Przywara wrote:
> The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
> for GPIO port I.
> Extend the range of supply port names to include vcc-pi-supply to cover
> that.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
@ 2022-07-01 20:57 ` Rob Herring
0 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-07-01 20:57 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Linus Walleij, linux-kernel, devicetree,
linux-arm-kernel, Samuel Holland, Krzysztof Kozlowski,
linux-sunxi, Jernej Skrabec, linux-gpio, Rob Herring
On Fri, 01 Jul 2022 12:24:50 +0100, Andre Przywara wrote:
> The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
> for GPIO port I.
> Extend the range of supply port names to include vcc-pi-supply to cover
> that.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-04 23:53 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-04 23:53 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> version.
>
> Add it to the list of compatible strings.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> index 6a4831fd3616c..87f1306831cc9 100644
> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> @@ -22,6 +22,7 @@ properties:
> - enum:
> - allwinner,sun20i-d1-emac
> - allwinner,sun50i-h6-emac
> + - allwinner,sun50i-h616-emac
The H616 manual has register fields for an internal PHY, like H3. Are these not
hooked up for either EMAC?
Regards,
Samuel
> - const: allwinner,sun50i-a64-emac
>
> reg:
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
@ 2022-07-04 23:53 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-04 23:53 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec, Rob Herring,
Krzysztof Kozlowski
Cc: Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> version.
>
> Add it to the list of compatible strings.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> index 6a4831fd3616c..87f1306831cc9 100644
> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> @@ -22,6 +22,7 @@ properties:
> - enum:
> - allwinner,sun20i-d1-emac
> - allwinner,sun50i-h6-emac
> + - allwinner,sun50i-h616-emac
The H616 manual has register fields for an internal PHY, like H3. Are these not
hooked up for either EMAC?
Regards,
Samuel
> - const: allwinner,sun50i-a64-emac
>
> reg:
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-04 23:55 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-04 23:55 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-gpio
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
> interrupt (it features only two pins).
> However the binding requires at least naming one upstream interrupt,
> plus the #interrupt-cells and interrupt-controller properties.
>
> Drop the unconditional requirement for the interrupt properties, and
> make them dependent on being not this particular pinctrl device.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> index bfce850c20351..0bd903954195b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> @@ -133,14 +133,11 @@ patternProperties:
>
> required:
> - "#gpio-cells"
> - - "#interrupt-cells"
> - compatible
> - reg
> - - interrupts
> - clocks
> - clock-names
> - gpio-controller
> - - interrupt-controller
>
> allOf:
> # FIXME: We should have the pin bank supplies here, but not a lot of
> @@ -148,6 +145,18 @@ allOf:
> # warnings.
>
> - $ref: "pinctrl.yaml#"
> + - if:
> + not:
> + properties:
> + compatible:
> + enum:
> + - allwinner,sun50i-h616-r-pinctrl
> + then:
Nit: all of the existing ifs and thens have blank lines between them.
> + required:
> + - "#interrupt-cells"
> + - interrupts
> + - interrupt-controller
> +
> - if:
> properties:
> compatible:
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional
@ 2022-07-04 23:55 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-04 23:55 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-gpio
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
> interrupt (it features only two pins).
> However the binding requires at least naming one upstream interrupt,
> plus the #interrupt-cells and interrupt-controller properties.
>
> Drop the unconditional requirement for the interrupt properties, and
> make them dependent on being not this particular pinctrl device.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
> ---
> .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> index bfce850c20351..0bd903954195b 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
> @@ -133,14 +133,11 @@ patternProperties:
>
> required:
> - "#gpio-cells"
> - - "#interrupt-cells"
> - compatible
> - reg
> - - interrupts
> - clocks
> - clock-names
> - gpio-controller
> - - interrupt-controller
>
> allOf:
> # FIXME: We should have the pin bank supplies here, but not a lot of
> @@ -148,6 +145,18 @@ allOf:
> # warnings.
>
> - $ref: "pinctrl.yaml#"
> + - if:
> + not:
> + properties:
> + compatible:
> + enum:
> + - allwinner,sun50i-h616-r-pinctrl
> + then:
Nit: all of the existing ifs and thens have blank lines between them.
> + required:
> + - "#interrupt-cells"
> + - interrupts
> + - interrupt-controller
> +
> - if:
> properties:
> compatible:
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-05 1:16 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:16 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel
Hi Andre,
On 7/1/22 6:24 AM, Andre Przywara wrote:
> This (relatively) new SoC is similar to the H6, but drops the (broken)
> PCIe support and the USB 3.0 controller. It also gets the management
> controller removed, which in turn removes *some*, but not all of the
> devices formerly dedicated to the ARISC (CPUS).
> And while there is still the extra sunxi interrupt controller, the
> package lacks the corresponding NMI pin, so no interrupts for the PMIC.
>
> The reserved memory node is actually handled by Trusted Firmware now,
> but U-Boot fails to propagate this to a separately loaded DTB, so we
> keep it in here for now, until U-Boot learns to do this properly.
Other than the decision about the reserved-memory node, which is being discussed
in the v11 thread, this looks good to me. Just a few minor comments below.
Regards,
Samuel
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
> 1 file changed, 579 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> new file mode 100644
> index 0000000000000..478f0b395ff58
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> @@ -0,0 +1,579 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2020 Arm Ltd.
> +// based on the H6 dtsi, which is:
> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun50i-h616-ccu.h>
> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
> +#include <dt-bindings/reset/sun50i-h616-ccu.h>
> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu2: cpu@2 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu3: cpu@3 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 512KiB reserved for ARM Trusted Firmware (BL31) */
> + secmon_reserved: secmon@40000000 {
> + reg = <0x0 0x40000000 0x0 0x80000>;
> + no-map;
> + };
> + };
> +
> + osc24M: osc24M-clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + arm,no-tick-in-suspend;
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + soc@0 {
No unit address needed here.
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x40000000>;
> +
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun50i-h616-system-control";
> + reg = <0x03000000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_c: sram@28000 {
> + compatible = "mmio-sram";
> + reg = <0x00028000 0x30000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00028000 0x30000>;
> + };
> + };
> +
> + ccu: clock@3001000 {
> + compatible = "allwinner,sun50i-h616-ccu";
> + reg = <0x03001000 0x1000>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
Please use the recently-added symbolic constants for the RTC clocks.
> + clock-names = "hosc", "losc", "iosc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + watchdog: watchdog@30090a0 {
> + compatible = "allwinner,sun50i-h616-wdt",
> + "allwinner,sun6i-a31-wdt";
> + reg = <0x030090a0 0x20>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + pio: pinctrl@300b000 {
> + compatible = "allwinner,sun50i-h616-pinctrl";
> + reg = <0x0300b000 0x400>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
Same for the RTC clock here.
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + ext_rgmii_pins: rgmii-pins {
> + pins = "PI0", "PI1", "PI2", "PI3", "PI4",
> + "PI5", "PI7", "PI8", "PI9", "PI10",
> + "PI11", "PI12", "PI13", "PI14", "PI15",
> + "PI16";
> + function = "emac0";
> + drive-strength = <40>;
> + };
> +
> + i2c0_pins: i2c0-pins {
> + pins = "PI6", "PI7";
> + function = "i2c0";
> + };
> +
> + i2c3_ph_pins: i2c3-ph-pins {
> + pins = "PH4", "PH5";
> + function = "i2c3";
> + };
> +
> + ir_rx_pin: ir-rx-pin {
> + pins = "PH10";
> + function = "ir_rx";
> + };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3",
> + "PF4", "PF5";
> + function = "mmc0";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + /omit-if-no-ref/
> + mmc1_pins: mmc1-pins {
> + pins = "PG0", "PG1", "PG2", "PG3",
> + "PG4", "PG5";
> + function = "mmc1";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + mmc2_pins: mmc2-pins {
> + pins = "PC0", "PC1", "PC5", "PC6",
> + "PC8", "PC9", "PC10", "PC11",
> + "PC13", "PC14", "PC15", "PC16";
> + function = "mmc2";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + /omit-if-no-ref/
> + spi0_pins: spi0-pins {
> + pins = "PC0", "PC2", "PC4";
> + function = "spi0";
> + };
> +
> + /omit-if-no-ref/
> + spi0_cs0_pin: spi0-cs0-pin {
> + pins = "PC3";
> + function = "spi0";
> + };
> +
> + /omit-if-no-ref/
> + spi1_pins: spi1-pins {
> + pins = "PH6", "PH7", "PH8";
> + function = "spi1";
> + };
> +
> + /omit-if-no-ref/
> + spi1_cs0_pin: spi1-cs0-pin {
> + pins = "PH5";
> + function = "spi1";
> + };
> +
> + uart0_ph_pins: uart0-ph-pins {
> + pins = "PH0", "PH1";
> + function = "uart0";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pins: uart1-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart1_rts_cts_pins: uart1-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> + };
> +
> + gic: interrupt-controller@3021000 {
> + compatible = "arm,gic-400";
> + reg = <0x03021000 0x1000>,
> + <0x03022000 0x2000>,
> + <0x03024000 0x2000>,
> + <0x03026000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + mmc0: mmc@4020000 {
> + compatible = "allwinner,sun50i-h616-mmc",
> + "allwinner,sun50i-a100-mmc";
> + reg = <0x04020000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + max-frequency = <150000000>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + mmc-ddr-3_3v;
> + cap-sdio-irq;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@4021000 {
> + compatible = "allwinner,sun50i-h616-mmc",
> + "allwinner,sun50i-a100-mmc";
> + reg = <0x04021000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins>;
> + status = "disabled";
> + max-frequency = <150000000>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + mmc-ddr-3_3v;
> + cap-sdio-irq;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@4022000 {
> + compatible = "allwinner,sun50i-h616-emmc",
> + "allwinner,sun50i-a100-emmc";
> + reg = <0x04022000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_pins>;
> + status = "disabled";
> + max-frequency = <150000000>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + mmc-ddr-3_3v;
> + cap-sdio-irq;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + uart0: serial@5000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + status = "disabled";
> + };
> +
> + uart1: serial@5000400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + status = "disabled";
> + };
> +
> + uart2: serial@5000800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@5000c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + status = "disabled";
> + };
> +
> + uart4: serial@5001000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05001000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@5001400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05001400 0x400>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c@5002000 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
Future note: this will be affected by [1] which adds a fallback compatible for
variants with offload support. That way we don't have to support them all
individually in the driver if/when we implement that.
[1]: https://lore.kernel.org/lkml/20220702052544.31443-1-samuel@sholland.org/
> + reg = <0x05002000 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@5002400 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002400 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@5002800 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002800 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@5002c00 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002c00 0x400>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c@5003000 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05003000 0x400>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C4>;
> + resets = <&ccu RST_BUS_I2C4>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi0: spi@5010000 {
> + compatible = "allwinner,sun50i-h616-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05010000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@5011000 {
> + compatible = "allwinner,sun50i-h616-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05011000 0x1000>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emac0: ethernet@5020000 {
> + compatible = "allwinner,sun50i-h616-emac",
> + "allwinner,sun50i-a64-emac";
> + syscon = <&syscon>;
> + reg = <0x05020000 0x10000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&ccu RST_BUS_EMAC0>;
> + reset-names = "stmmaceth";
> + clocks = <&ccu CLK_BUS_EMAC0>;
> + clock-names = "stmmaceth";
Nit: clocks then resets then syscon, to follow the usual order.
> + status = "disabled";
> +
> + mdio0: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + rtc: rtc@7000000 {
> + compatible = "allwinner,sun50i-h616-rtc";
> + reg = <0x07000000 0x400>;
> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
> + <&ccu CLK_PLL_SYSTEM_32K>;
> + clock-names = "bus", "hosc",
> + "pll-32k";
> + clock-output-names = "osc32k", "osc32k-out", "iosc";
Since the RTC clock indices were formalized in the binding, this is no longer
needed.
> + #clock-cells = <1>;
> + };
> +
> + r_ccu: clock@7010000 {
> + compatible = "allwinner,sun50i-h616-r-ccu";
> + reg = <0x07010000 0x210>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
Symbolic constants here and in r_pio as well, please.
> + <&ccu CLK_PLL_PERIPH0>;
> + clock-names = "hosc", "losc", "iosc", "pll-periph";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + r_pio: pinctrl@7022000 {
> + compatible = "allwinner,sun50i-h616-r-pinctrl";
> + reg = <0x07022000 0x400>;
> + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + #gpio-cells = <3>;
> +
> + r_i2c_pins: r-i2c-pins {
This is unlikely be used (as opposed to RSB), so I suggest omit-if-no-ref.
> + pins = "PL0", "PL1";
> + function = "s_i2c";
> + };
> +
> + r_rsb_pins: r-rsb-pins {
> + pins = "PL0", "PL1";
> + function = "s_rsb";
> + };
> + };
> +
> + ir: ir@7040000 {
> + compatible = "allwinner,sun50i-h616-ir",
> + "allwinner,sun6i-a31-ir";
> + reg = <0x07040000 0x400>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_IR>,
> + <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_R_APB1_IR>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_rx_pin>;
> + status = "disabled";
> + };
> +
> + r_i2c: i2c@7081400 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x07081400 0x400>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB2_I2C>;
> + resets = <&r_ccu RST_R_APB2_I2C>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + r_rsb: rsb@7083000 {
> + compatible = "allwinner,sun50i-h616-rsb",
> + "allwinner,sun8i-a23-rsb";
> + reg = <0x07083000 0x400>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB2_RSB>;
> + clock-frequency = <3000000>;
> + resets = <&r_ccu RST_R_APB2_RSB>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_rsb_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
@ 2022-07-05 1:16 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:16 UTC (permalink / raw)
To: Andre Przywara, Chen-Yu Tsai, Jernej Skrabec
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel
Hi Andre,
On 7/1/22 6:24 AM, Andre Przywara wrote:
> This (relatively) new SoC is similar to the H6, but drops the (broken)
> PCIe support and the USB 3.0 controller. It also gets the management
> controller removed, which in turn removes *some*, but not all of the
> devices formerly dedicated to the ARISC (CPUS).
> And while there is still the extra sunxi interrupt controller, the
> package lacks the corresponding NMI pin, so no interrupts for the PMIC.
>
> The reserved memory node is actually handled by Trusted Firmware now,
> but U-Boot fails to propagate this to a separately loaded DTB, so we
> keep it in here for now, until U-Boot learns to do this properly.
Other than the decision about the reserved-memory node, which is being discussed
in the v11 thread, this looks good to me. Just a few minor comments below.
Regards,
Samuel
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
> 1 file changed, 579 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> new file mode 100644
> index 0000000000000..478f0b395ff58
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> @@ -0,0 +1,579 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2020 Arm Ltd.
> +// based on the H6 dtsi, which is:
> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun50i-h616-ccu.h>
> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
> +#include <dt-bindings/reset/sun50i-h616-ccu.h>
> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu2: cpu@2 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu3: cpu@3 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 512KiB reserved for ARM Trusted Firmware (BL31) */
> + secmon_reserved: secmon@40000000 {
> + reg = <0x0 0x40000000 0x0 0x80000>;
> + no-map;
> + };
> + };
> +
> + osc24M: osc24M-clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + arm,no-tick-in-suspend;
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + soc@0 {
No unit address needed here.
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x40000000>;
> +
> + syscon: syscon@3000000 {
> + compatible = "allwinner,sun50i-h616-system-control";
> + reg = <0x03000000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_c: sram@28000 {
> + compatible = "mmio-sram";
> + reg = <0x00028000 0x30000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00028000 0x30000>;
> + };
> + };
> +
> + ccu: clock@3001000 {
> + compatible = "allwinner,sun50i-h616-ccu";
> + reg = <0x03001000 0x1000>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
Please use the recently-added symbolic constants for the RTC clocks.
> + clock-names = "hosc", "losc", "iosc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + watchdog: watchdog@30090a0 {
> + compatible = "allwinner,sun50i-h616-wdt",
> + "allwinner,sun6i-a31-wdt";
> + reg = <0x030090a0 0x20>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + pio: pinctrl@300b000 {
> + compatible = "allwinner,sun50i-h616-pinctrl";
> + reg = <0x0300b000 0x400>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
Same for the RTC clock here.
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + ext_rgmii_pins: rgmii-pins {
> + pins = "PI0", "PI1", "PI2", "PI3", "PI4",
> + "PI5", "PI7", "PI8", "PI9", "PI10",
> + "PI11", "PI12", "PI13", "PI14", "PI15",
> + "PI16";
> + function = "emac0";
> + drive-strength = <40>;
> + };
> +
> + i2c0_pins: i2c0-pins {
> + pins = "PI6", "PI7";
> + function = "i2c0";
> + };
> +
> + i2c3_ph_pins: i2c3-ph-pins {
> + pins = "PH4", "PH5";
> + function = "i2c3";
> + };
> +
> + ir_rx_pin: ir-rx-pin {
> + pins = "PH10";
> + function = "ir_rx";
> + };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3",
> + "PF4", "PF5";
> + function = "mmc0";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + /omit-if-no-ref/
> + mmc1_pins: mmc1-pins {
> + pins = "PG0", "PG1", "PG2", "PG3",
> + "PG4", "PG5";
> + function = "mmc1";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + mmc2_pins: mmc2-pins {
> + pins = "PC0", "PC1", "PC5", "PC6",
> + "PC8", "PC9", "PC10", "PC11",
> + "PC13", "PC14", "PC15", "PC16";
> + function = "mmc2";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + /omit-if-no-ref/
> + spi0_pins: spi0-pins {
> + pins = "PC0", "PC2", "PC4";
> + function = "spi0";
> + };
> +
> + /omit-if-no-ref/
> + spi0_cs0_pin: spi0-cs0-pin {
> + pins = "PC3";
> + function = "spi0";
> + };
> +
> + /omit-if-no-ref/
> + spi1_pins: spi1-pins {
> + pins = "PH6", "PH7", "PH8";
> + function = "spi1";
> + };
> +
> + /omit-if-no-ref/
> + spi1_cs0_pin: spi1-cs0-pin {
> + pins = "PH5";
> + function = "spi1";
> + };
> +
> + uart0_ph_pins: uart0-ph-pins {
> + pins = "PH0", "PH1";
> + function = "uart0";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pins: uart1-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart1_rts_cts_pins: uart1-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> + };
> +
> + gic: interrupt-controller@3021000 {
> + compatible = "arm,gic-400";
> + reg = <0x03021000 0x1000>,
> + <0x03022000 0x2000>,
> + <0x03024000 0x2000>,
> + <0x03026000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + mmc0: mmc@4020000 {
> + compatible = "allwinner,sun50i-h616-mmc",
> + "allwinner,sun50i-a100-mmc";
> + reg = <0x04020000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + max-frequency = <150000000>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + mmc-ddr-3_3v;
> + cap-sdio-irq;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@4021000 {
> + compatible = "allwinner,sun50i-h616-mmc",
> + "allwinner,sun50i-a100-mmc";
> + reg = <0x04021000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins>;
> + status = "disabled";
> + max-frequency = <150000000>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + mmc-ddr-3_3v;
> + cap-sdio-irq;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc@4022000 {
> + compatible = "allwinner,sun50i-h616-emmc",
> + "allwinner,sun50i-a100-emmc";
> + reg = <0x04022000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_pins>;
> + status = "disabled";
> + max-frequency = <150000000>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + mmc-ddr-3_3v;
> + cap-sdio-irq;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + uart0: serial@5000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + status = "disabled";
> + };
> +
> + uart1: serial@5000400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + status = "disabled";
> + };
> +
> + uart2: serial@5000800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@5000c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + status = "disabled";
> + };
> +
> + uart4: serial@5001000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05001000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@5001400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05001400 0x400>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c@5002000 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
Future note: this will be affected by [1] which adds a fallback compatible for
variants with offload support. That way we don't have to support them all
individually in the driver if/when we implement that.
[1]: https://lore.kernel.org/lkml/20220702052544.31443-1-samuel@sholland.org/
> + reg = <0x05002000 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@5002400 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002400 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@5002800 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002800 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c@5002c00 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002c00 0x400>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c@5003000 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05003000 0x400>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C4>;
> + resets = <&ccu RST_BUS_I2C4>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi0: spi@5010000 {
> + compatible = "allwinner,sun50i-h616-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05010000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@5011000 {
> + compatible = "allwinner,sun50i-h616-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05011000 0x1000>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emac0: ethernet@5020000 {
> + compatible = "allwinner,sun50i-h616-emac",
> + "allwinner,sun50i-a64-emac";
> + syscon = <&syscon>;
> + reg = <0x05020000 0x10000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&ccu RST_BUS_EMAC0>;
> + reset-names = "stmmaceth";
> + clocks = <&ccu CLK_BUS_EMAC0>;
> + clock-names = "stmmaceth";
Nit: clocks then resets then syscon, to follow the usual order.
> + status = "disabled";
> +
> + mdio0: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + rtc: rtc@7000000 {
> + compatible = "allwinner,sun50i-h616-rtc";
> + reg = <0x07000000 0x400>;
> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
> + <&ccu CLK_PLL_SYSTEM_32K>;
> + clock-names = "bus", "hosc",
> + "pll-32k";
> + clock-output-names = "osc32k", "osc32k-out", "iosc";
Since the RTC clock indices were formalized in the binding, this is no longer
needed.
> + #clock-cells = <1>;
> + };
> +
> + r_ccu: clock@7010000 {
> + compatible = "allwinner,sun50i-h616-r-ccu";
> + reg = <0x07010000 0x210>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
Symbolic constants here and in r_pio as well, please.
> + <&ccu CLK_PLL_PERIPH0>;
> + clock-names = "hosc", "losc", "iosc", "pll-periph";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + r_pio: pinctrl@7022000 {
> + compatible = "allwinner,sun50i-h616-r-pinctrl";
> + reg = <0x07022000 0x400>;
> + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + #gpio-cells = <3>;
> +
> + r_i2c_pins: r-i2c-pins {
This is unlikely be used (as opposed to RSB), so I suggest omit-if-no-ref.
> + pins = "PL0", "PL1";
> + function = "s_i2c";
> + };
> +
> + r_rsb_pins: r-rsb-pins {
> + pins = "PL0", "PL1";
> + function = "s_rsb";
> + };
> + };
> +
> + ir: ir@7040000 {
> + compatible = "allwinner,sun50i-h616-ir",
> + "allwinner,sun6i-a31-ir";
> + reg = <0x07040000 0x400>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_IR>,
> + <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_R_APB1_IR>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_rx_pin>;
> + status = "disabled";
> + };
> +
> + r_i2c: i2c@7081400 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x07081400 0x400>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB2_I2C>;
> + resets = <&r_ccu RST_R_APB2_I2C>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + r_rsb: rsb@7083000 {
> + compatible = "allwinner,sun50i-h616-rsb",
> + "allwinner,sun8i-a23-rsb";
> + reg = <0x07083000 0x400>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB2_RSB>;
> + clock-frequency = <3000000>;
> + resets = <&r_ccu RST_R_APB2_RSB>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_rsb_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-05 1:18 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:18 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
> for GPIO port I.
> Extend the range of supply port names to include vcc-pi-supply to cover
> that.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
@ 2022-07-05 1:18 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:18 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-gpio
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
> for GPIO port I.
> Extend the range of supply port names to include vcc-pi-supply to cover
> that.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Samuel Holland <samuel@sholland.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-05 1:29 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:29 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The X96 Mate is an Allwinner H616 based TV box, featuring:
> - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> - 2GiB/4GiB RAM (fully usable!)
> - 16/32/64GiB eMMC
> - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
> - Unsupported Allwinner WiFi chip
> - 2 x USB 2.0 host ports
> - HDMI port
> - IR receiver
> - 5V/2A DC power supply via barrel plug
>
> Add a basic devicetree for it, with SD card and eMMC working, as
> well as serial and the essential peripherals, like the AXP PMIC.
>
> This DT is somewhat minimal, and should work on many other similar TV
> boxes with the Allwinner H616 chip.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Looks good to me, with one question below.
Reviewed-by: Samuel Holland <samuel@sholland.org>
> ---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++
> 2 files changed, 178 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> index df2214e6d946a..6a96494a2e0a3 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> new file mode 100644
> index 0000000000000..30b76140b9c8a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> @@ -0,0 +1,177 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2021 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "sun50i-h616.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + model = "X96 Mate";
> + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_vcc5v: vcc5v {
> + /* board wide 5V supply directly from the DC input */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +};
> +
> +&ir {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdce>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&mmc2 {
> + vmmc-supply = <®_dcdce>;
> + vqmmc-supply = <®_bldo1>;
> + bus-width = <8>;
> + non-removable;
> + cap-mmc-hw-reset;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + status = "okay";
> +};
> +
> +&r_rsb {
> + status = "okay";
> +
> + axp305: pmic@745 {
> + compatible = "x-powers,axp305", "x-powers,axp805",
> + "x-powers,axp806";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0x745>;
> +
> + x-powers,self-working-mode;
> + vina-supply = <®_vcc5v>;
> + vinb-supply = <®_vcc5v>;
> + vinc-supply = <®_vcc5v>;
> + vind-supply = <®_vcc5v>;
> + vine-supply = <®_vcc5v>;
> + aldoin-supply = <®_vcc5v>;
> + bldoin-supply = <®_vcc5v>;
> + cldoin-supply = <®_vcc5v>;
> +
> + regulators {
> + reg_aldo1: aldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-sys";
> + };
> +
> + /* Enabled by the Android BSP */
> + reg_aldo2: aldo2 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext";
> + status = "disabled";
If you disable these nodes, the regulator core will ignore them and not apply
the voltages. Is that what you want?
Regards,
Samuel
> + };
> +
> + /* Enabled by the Android BSP */
> + reg_aldo3: aldo3 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext2";
> + status = "disabled";
> + };
> +
> + reg_bldo1: bldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8";
> + };
> +
> + /* Enabled by the Android BSP */
> + reg_bldo2: bldo2 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8-2";
> + status = "disabled";
> + };
> +
> + bldo3 {
> + /* unused */
> + };
> +
> + bldo4 {
> + /* unused */
> + };
> +
> + cldo1 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-name = "vcc2v5";
> + };
> +
> + cldo2 {
> + /* unused */
> + };
> +
> + cldo3 {
> + /* unused */
> + };
> +
> + reg_dcdca: dcdca {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
> + regulator-name = "vdd-cpu";
> + };
> +
> + reg_dcdcc: dcdcc {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
> + regulator-name = "vdd-gpu-sys";
> + };
> +
> + reg_dcdcd: dcdcd {
> + regulator-always-on;
> + regulator-min-microvolt = <1360000>;
> + regulator-max-microvolt = <1360000>;
> + regulator-name = "vdd-dram";
> + };
> +
> + reg_dcdce: dcdce {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-eth-mmc";
> + };
> +
> + sw {
> + /* unused */
> + };
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_ph_pins>;
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support
@ 2022-07-05 1:29 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:29 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The X96 Mate is an Allwinner H616 based TV box, featuring:
> - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> - 2GiB/4GiB RAM (fully usable!)
> - 16/32/64GiB eMMC
> - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
> - Unsupported Allwinner WiFi chip
> - 2 x USB 2.0 host ports
> - HDMI port
> - IR receiver
> - 5V/2A DC power supply via barrel plug
>
> Add a basic devicetree for it, with SD card and eMMC working, as
> well as serial and the essential peripherals, like the AXP PMIC.
>
> This DT is somewhat minimal, and should work on many other similar TV
> boxes with the Allwinner H616 chip.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Looks good to me, with one question below.
Reviewed-by: Samuel Holland <samuel@sholland.org>
> ---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++
> 2 files changed, 178 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> index df2214e6d946a..6a96494a2e0a3 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> new file mode 100644
> index 0000000000000..30b76140b9c8a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> @@ -0,0 +1,177 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2021 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "sun50i-h616.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + model = "X96 Mate";
> + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_vcc5v: vcc5v {
> + /* board wide 5V supply directly from the DC input */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +};
> +
> +&ir {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdce>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&mmc2 {
> + vmmc-supply = <®_dcdce>;
> + vqmmc-supply = <®_bldo1>;
> + bus-width = <8>;
> + non-removable;
> + cap-mmc-hw-reset;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + status = "okay";
> +};
> +
> +&r_rsb {
> + status = "okay";
> +
> + axp305: pmic@745 {
> + compatible = "x-powers,axp305", "x-powers,axp805",
> + "x-powers,axp806";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0x745>;
> +
> + x-powers,self-working-mode;
> + vina-supply = <®_vcc5v>;
> + vinb-supply = <®_vcc5v>;
> + vinc-supply = <®_vcc5v>;
> + vind-supply = <®_vcc5v>;
> + vine-supply = <®_vcc5v>;
> + aldoin-supply = <®_vcc5v>;
> + bldoin-supply = <®_vcc5v>;
> + cldoin-supply = <®_vcc5v>;
> +
> + regulators {
> + reg_aldo1: aldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-sys";
> + };
> +
> + /* Enabled by the Android BSP */
> + reg_aldo2: aldo2 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext";
> + status = "disabled";
If you disable these nodes, the regulator core will ignore them and not apply
the voltages. Is that what you want?
Regards,
Samuel
> + };
> +
> + /* Enabled by the Android BSP */
> + reg_aldo3: aldo3 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext2";
> + status = "disabled";
> + };
> +
> + reg_bldo1: bldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8";
> + };
> +
> + /* Enabled by the Android BSP */
> + reg_bldo2: bldo2 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8-2";
> + status = "disabled";
> + };
> +
> + bldo3 {
> + /* unused */
> + };
> +
> + bldo4 {
> + /* unused */
> + };
> +
> + cldo1 {
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-name = "vcc2v5";
> + };
> +
> + cldo2 {
> + /* unused */
> + };
> +
> + cldo3 {
> + /* unused */
> + };
> +
> + reg_dcdca: dcdca {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
> + regulator-name = "vdd-cpu";
> + };
> +
> + reg_dcdcc: dcdcc {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
> + regulator-name = "vdd-gpu-sys";
> + };
> +
> + reg_dcdcd: dcdcd {
> + regulator-always-on;
> + regulator-min-microvolt = <1360000>;
> + regulator-max-microvolt = <1360000>;
> + regulator-name = "vdd-dram";
> + };
> +
> + reg_dcdce: dcdce {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-eth-mmc";
> + };
> +
> + sw {
> + /* unused */
> + };
> + };
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_ph_pins>;
> + status = "okay";
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
2022-07-01 11:24 ` Andre Przywara
@ 2022-07-05 1:45 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:45 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Hi Andre,
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The OrangePi Zero 2 is a development board with the new H616 SoC. It
> comes with the following features:
> - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> - 512MiB/1GiB DDR3 DRAM
> - AXP305 PMIC
> - Raspberry-Pi-1 compatible GPIO header
> - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
> - 1 USB 2.0 host port
> - 1 USB 2.0 type C port (power supply + OTG)
> - MicroSD slot
> - on-board 2MiB bootable SPI NOR flash
> - 1Gbps Ethernet port (via RTL8211F PHY)
> - micro-HDMI port
> - (yet) unsupported Allwinner WiFi/BT chip
>
> Add the devicetree file describing the currently supported features.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
One question below.
> ---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++
> 2 files changed, 214 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> index 8fa5c060a4fef..df2214e6d946a 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> new file mode 100644
> index 0000000000000..cff199536d3bc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> @@ -0,0 +1,213 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2020 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "sun50i-h616.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> + model = "OrangePi Zero2";
> + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
> +
> + aliases {
> + ethernet0 = &emac0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + function = LED_FUNCTION_POWER;
> + color = <LED_COLOR_ID_RED>;
> + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
> + default-state = "on";
> + };
> +
> + led-1 {
> + function = LED_FUNCTION_STATUS;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
> + };
> + };
> +
> + reg_vcc5v: vcc5v {
> + /* board wide 5V supply directly from the USB-C socket */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +};
> +
> +&emac0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ext_rgmii_pins>;
> + phy-mode = "rgmii";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-supply = <®_dcdce>;
> + allwinner,rx-delay-ps = <3100>;
> + allwinner,tx-delay-ps = <700>;
> + status = "okay";
> +};
> +
> +&mdio0 {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdce>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&r_rsb {
> + status = "okay";
> +
> + axp305: pmic@745 {
> + compatible = "x-powers,axp305", "x-powers,axp805",
> + "x-powers,axp806";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0x745>;
> +
> + x-powers,self-working-mode;
> + vina-supply = <®_vcc5v>;
> + vinb-supply = <®_vcc5v>;
> + vinc-supply = <®_vcc5v>;
> + vind-supply = <®_vcc5v>;
> + vine-supply = <®_vcc5v>;
> + aldoin-supply = <®_vcc5v>;
> + bldoin-supply = <®_vcc5v>;
> + cldoin-supply = <®_vcc5v>;
> +
> + regulators {
> + reg_aldo1: aldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-sys";
> + };
> +
> + reg_aldo2: aldo2 { /* 3.3V on headers */
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext";
> + };
> +
> + reg_aldo3: aldo3 { /* 3.3V on headers */
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext2";
> + };
> +
> + reg_bldo1: bldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8";
> + };
> +
> + bldo2 {
> + /* unused */
> + };
> +
> + bldo3 {
> + /* unused */
> + };
> +
> + bldo4 {
> + /* unused */
> + };
> +
> + cldo1 {
> + /* reserved */
> + };
> +
> + cldo2 {
> + /* unused */
> + };
> +
> + cldo3 {
> + /* unused */
> + };
> +
> + reg_dcdca: dcdca {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
> + regulator-name = "vdd-cpu";
> + };
> +
> + reg_dcdcc: dcdcc {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
Where does the max voltage here come from? The H616 datasheet lists the limit
for both VDD_GPU and VDD_SYS as 0.99 V. (This applies to both boards.)
Regards,
Samuel
> + regulator-name = "vdd-gpu-sys";
> + };
> +
> + reg_dcdcd: dcdcd {
> + regulator-always-on;
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-name = "vdd-dram";
> + };
> +
> + reg_dcdce: dcdce {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-eth-mmc";
> + };
> +
> + sw {
> + /* unused */
> + };
> + };
> + };
> +};
> +
> +&pio {
> + vcc-pc-supply = <®_aldo1>;
> + vcc-pf-supply = <®_aldo1>;
> + vcc-pg-supply = <®_bldo1>;
> + vcc-ph-supply = <®_aldo1>;
> + vcc-pi-supply = <®_aldo1>;
> +};
> +
> +&spi0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
> +
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_ph_pins>;
> + status = "okay";
> +};
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
@ 2022-07-05 1:45 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-05 1:45 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Hi Andre,
On 7/1/22 6:24 AM, Andre Przywara wrote:
> The OrangePi Zero 2 is a development board with the new H616 SoC. It
> comes with the following features:
> - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> - 512MiB/1GiB DDR3 DRAM
> - AXP305 PMIC
> - Raspberry-Pi-1 compatible GPIO header
> - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
> - 1 USB 2.0 host port
> - 1 USB 2.0 type C port (power supply + OTG)
> - MicroSD slot
> - on-board 2MiB bootable SPI NOR flash
> - 1Gbps Ethernet port (via RTL8211F PHY)
> - micro-HDMI port
> - (yet) unsupported Allwinner WiFi/BT chip
>
> Add the devicetree file describing the currently supported features.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
One question below.
> ---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++
> 2 files changed, 214 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> index 8fa5c060a4fef..df2214e6d946a 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> new file mode 100644
> index 0000000000000..cff199536d3bc
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> @@ -0,0 +1,213 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2020 Arm Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "sun50i-h616.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> + model = "OrangePi Zero2";
> + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
> +
> + aliases {
> + ethernet0 = &emac0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-0 {
> + function = LED_FUNCTION_POWER;
> + color = <LED_COLOR_ID_RED>;
> + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
> + default-state = "on";
> + };
> +
> + led-1 {
> + function = LED_FUNCTION_STATUS;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
> + };
> + };
> +
> + reg_vcc5v: vcc5v {
> + /* board wide 5V supply directly from the USB-C socket */
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + };
> +};
> +
> +&emac0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ext_rgmii_pins>;
> + phy-mode = "rgmii";
> + phy-handle = <&ext_rgmii_phy>;
> + phy-supply = <®_dcdce>;
> + allwinner,rx-delay-ps = <3100>;
> + allwinner,tx-delay-ps = <700>;
> + status = "okay";
> +};
> +
> +&mdio0 {
> + ext_rgmii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdce>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&r_rsb {
> + status = "okay";
> +
> + axp305: pmic@745 {
> + compatible = "x-powers,axp305", "x-powers,axp805",
> + "x-powers,axp806";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + reg = <0x745>;
> +
> + x-powers,self-working-mode;
> + vina-supply = <®_vcc5v>;
> + vinb-supply = <®_vcc5v>;
> + vinc-supply = <®_vcc5v>;
> + vind-supply = <®_vcc5v>;
> + vine-supply = <®_vcc5v>;
> + aldoin-supply = <®_vcc5v>;
> + bldoin-supply = <®_vcc5v>;
> + cldoin-supply = <®_vcc5v>;
> +
> + regulators {
> + reg_aldo1: aldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-sys";
> + };
> +
> + reg_aldo2: aldo2 { /* 3.3V on headers */
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext";
> + };
> +
> + reg_aldo3: aldo3 { /* 3.3V on headers */
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3-ext2";
> + };
> +
> + reg_bldo1: bldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8";
> + };
> +
> + bldo2 {
> + /* unused */
> + };
> +
> + bldo3 {
> + /* unused */
> + };
> +
> + bldo4 {
> + /* unused */
> + };
> +
> + cldo1 {
> + /* reserved */
> + };
> +
> + cldo2 {
> + /* unused */
> + };
> +
> + cldo3 {
> + /* unused */
> + };
> +
> + reg_dcdca: dcdca {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
> + regulator-name = "vdd-cpu";
> + };
> +
> + reg_dcdcc: dcdcc {
> + regulator-always-on;
> + regulator-min-microvolt = <810000>;
> + regulator-max-microvolt = <1080000>;
Where does the max voltage here come from? The H616 datasheet lists the limit
for both VDD_GPU and VDD_SYS as 0.99 V. (This applies to both boards.)
Regards,
Samuel
> + regulator-name = "vdd-gpu-sys";
> + };
> +
> + reg_dcdcd: dcdcd {
> + regulator-always-on;
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-name = "vdd-dram";
> + };
> +
> + reg_dcdce: dcdce {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-eth-mmc";
> + };
> +
> + sw {
> + /* unused */
> + };
> + };
> + };
> +};
> +
> +&pio {
> + vcc-pc-supply = <®_aldo1>;
> + vcc-pf-supply = <®_aldo1>;
> + vcc-pg-supply = <®_bldo1>;
> + vcc-ph-supply = <®_aldo1>;
> + vcc-pi-supply = <®_aldo1>;
> +};
> +
> +&spi0 {
> + status = "okay";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
> +
> + flash@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_ph_pins>;
> + status = "okay";
> +};
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
2022-07-04 23:53 ` Samuel Holland
@ 2022-07-05 10:19 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-05 10:19 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
On Mon, 4 Jul 2022 18:53:14 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> > version.
> >
> > Add it to the list of compatible strings.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> > .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> > index 6a4831fd3616c..87f1306831cc9 100644
> > --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> > +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> > @@ -22,6 +22,7 @@ properties:
> > - enum:
> > - allwinner,sun20i-d1-emac
> > - allwinner,sun50i-h6-emac
> > + - allwinner,sun50i-h616-emac
>
> The H616 manual has register fields for an internal PHY, like H3. Are these not
> hooked up for either EMAC?
Which register fields do you mean, exactly? The H616 uses the same
internal PHY solution as the H6: an AC200 die co-packaged on the carrier
(or whatever integration solution they actually chose). The difference to
the H6 is that EMAC0 is hardwired to the external RGMII pins, whereas EMAC1
is hardwired to the internal AC200 RMII pins.
From all I could see that does not impact the actual MAC IP: both are the
same as in the H6, or A64, for that matter.
There is one twist, though: the second EMAC uses a separate EMAC clock
register in the syscon. I came up with this patch to support that:
https://github.com/apritzel/linux/commit/078f591017794a0ec689345b0eeb7150908cf85a
That extends the syscon to take an optional(!) index. So EMAC0 works
exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
we need the index: "<&syscon 4>;".
But in my opinion this should not affect the MAC binding, at least not for
MAC0. And I think we should get away without a different compatible string
for EMAC1, since the MAC IP is technically the same, it's just the
connection that is different.
In any case I think this does not affect the level of support we promise
today: EMAC0 with an external PHY only.
Cheers,
Andre
>
> > - const: allwinner,sun50i-a64-emac
> >
> > reg:
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
@ 2022-07-05 10:19 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-05 10:19 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
On Mon, 4 Jul 2022 18:53:14 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> > version.
> >
> > Add it to the list of compatible strings.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> > .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> > index 6a4831fd3616c..87f1306831cc9 100644
> > --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> > +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> > @@ -22,6 +22,7 @@ properties:
> > - enum:
> > - allwinner,sun20i-d1-emac
> > - allwinner,sun50i-h6-emac
> > + - allwinner,sun50i-h616-emac
>
> The H616 manual has register fields for an internal PHY, like H3. Are these not
> hooked up for either EMAC?
Which register fields do you mean, exactly? The H616 uses the same
internal PHY solution as the H6: an AC200 die co-packaged on the carrier
(or whatever integration solution they actually chose). The difference to
the H6 is that EMAC0 is hardwired to the external RGMII pins, whereas EMAC1
is hardwired to the internal AC200 RMII pins.
From all I could see that does not impact the actual MAC IP: both are the
same as in the H6, or A64, for that matter.
There is one twist, though: the second EMAC uses a separate EMAC clock
register in the syscon. I came up with this patch to support that:
https://github.com/apritzel/linux/commit/078f591017794a0ec689345b0eeb7150908cf85a
That extends the syscon to take an optional(!) index. So EMAC0 works
exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
we need the index: "<&syscon 4>;".
But in my opinion this should not affect the MAC binding, at least not for
MAC0. And I think we should get away without a different compatible string
for EMAC1, since the MAC IP is technically the same, it's just the
connection that is different.
In any case I think this does not affect the level of support we promise
today: EMAC0 with an external PHY only.
Cheers,
Andre
>
> > - const: allwinner,sun50i-a64-emac
> >
> > reg:
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
2022-07-05 1:16 ` Samuel Holland
@ 2022-07-05 10:42 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-05 10:42 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On Mon, 4 Jul 2022 20:16:50 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Hi Andre,
>
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > This (relatively) new SoC is similar to the H6, but drops the (broken)
> > PCIe support and the USB 3.0 controller. It also gets the management
> > controller removed, which in turn removes *some*, but not all of the
> > devices formerly dedicated to the ARISC (CPUS).
> > And while there is still the extra sunxi interrupt controller, the
> > package lacks the corresponding NMI pin, so no interrupts for the PMIC.
> >
> > The reserved memory node is actually handled by Trusted Firmware now,
> > but U-Boot fails to propagate this to a separately loaded DTB, so we
> > keep it in here for now, until U-Boot learns to do this properly.
>
> Other than the decision about the reserved-memory node, which is being discussed
> in the v11 thread, this looks good to me. Just a few minor comments below.
Many thanks for going through that file! I will fix what you commented on.
Just one comment on the I2C binding below ....
>
> Regards,
> Samuel
>
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> > .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
> > 1 file changed, 579 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > new file mode 100644
> > index 0000000000000..478f0b395ff58
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > @@ -0,0 +1,579 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +// Copyright (C) 2020 Arm Ltd.
> > +// based on the H6 dtsi, which is:
> > +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/sun50i-h616-ccu.h>
> > +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
> > +#include <dt-bindings/reset/sun50i-h616-ccu.h>
> > +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> > +
> > +/ {
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <0>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <1>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <2>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <3>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + /* 512KiB reserved for ARM Trusted Firmware (BL31) */
> > + secmon_reserved: secmon@40000000 {
> > + reg = <0x0 0x40000000 0x0 0x80000>;
> > + no-map;
> > + };
> > + };
> > +
> > + osc24M: osc24M-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <24000000>;
> > + clock-output-names = "osc24M";
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + arm,no-tick-in-suspend;
> > + interrupts = <GIC_PPI 13
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 14
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 11
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 10
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > +
> > + soc@0 {
>
> No unit address needed here.
>
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x0 0x0 0x40000000>;
> > +
> > + syscon: syscon@3000000 {
> > + compatible = "allwinner,sun50i-h616-system-control";
> > + reg = <0x03000000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + sram_c: sram@28000 {
> > + compatible = "mmio-sram";
> > + reg = <0x00028000 0x30000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x00028000 0x30000>;
> > + };
> > + };
> > +
> > + ccu: clock@3001000 {
> > + compatible = "allwinner,sun50i-h616-ccu";
> > + reg = <0x03001000 0x1000>;
> > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
>
> Please use the recently-added symbolic constants for the RTC clocks.
>
> > + clock-names = "hosc", "losc", "iosc";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + watchdog: watchdog@30090a0 {
> > + compatible = "allwinner,sun50i-h616-wdt",
> > + "allwinner,sun6i-a31-wdt";
> > + reg = <0x030090a0 0x20>;
> > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&osc24M>;
> > + };
> > +
> > + pio: pinctrl@300b000 {
> > + compatible = "allwinner,sun50i-h616-pinctrl";
> > + reg = <0x0300b000 0x400>;
> > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
>
> Same for the RTC clock here.
>
> > + clock-names = "apb", "hosc", "losc";
> > + gpio-controller;
> > + #gpio-cells = <3>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > +
> > + ext_rgmii_pins: rgmii-pins {
> > + pins = "PI0", "PI1", "PI2", "PI3", "PI4",
> > + "PI5", "PI7", "PI8", "PI9", "PI10",
> > + "PI11", "PI12", "PI13", "PI14", "PI15",
> > + "PI16";
> > + function = "emac0";
> > + drive-strength = <40>;
> > + };
> > +
> > + i2c0_pins: i2c0-pins {
> > + pins = "PI6", "PI7";
> > + function = "i2c0";
> > + };
> > +
> > + i2c3_ph_pins: i2c3-ph-pins {
> > + pins = "PH4", "PH5";
> > + function = "i2c3";
> > + };
> > +
> > + ir_rx_pin: ir-rx-pin {
> > + pins = "PH10";
> > + function = "ir_rx";
> > + };
> > +
> > + mmc0_pins: mmc0-pins {
> > + pins = "PF0", "PF1", "PF2", "PF3",
> > + "PF4", "PF5";
> > + function = "mmc0";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > + /omit-if-no-ref/
> > + mmc1_pins: mmc1-pins {
> > + pins = "PG0", "PG1", "PG2", "PG3",
> > + "PG4", "PG5";
> > + function = "mmc1";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > + mmc2_pins: mmc2-pins {
> > + pins = "PC0", "PC1", "PC5", "PC6",
> > + "PC8", "PC9", "PC10", "PC11",
> > + "PC13", "PC14", "PC15", "PC16";
> > + function = "mmc2";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi0_pins: spi0-pins {
> > + pins = "PC0", "PC2", "PC4";
> > + function = "spi0";
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi0_cs0_pin: spi0-cs0-pin {
> > + pins = "PC3";
> > + function = "spi0";
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi1_pins: spi1-pins {
> > + pins = "PH6", "PH7", "PH8";
> > + function = "spi1";
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi1_cs0_pin: spi1-cs0-pin {
> > + pins = "PH5";
> > + function = "spi1";
> > + };
> > +
> > + uart0_ph_pins: uart0-ph-pins {
> > + pins = "PH0", "PH1";
> > + function = "uart0";
> > + };
> > +
> > + /omit-if-no-ref/
> > + uart1_pins: uart1-pins {
> > + pins = "PG6", "PG7";
> > + function = "uart1";
> > + };
> > +
> > + /omit-if-no-ref/
> > + uart1_rts_cts_pins: uart1-rts-cts-pins {
> > + pins = "PG8", "PG9";
> > + function = "uart1";
> > + };
> > + };
> > +
> > + gic: interrupt-controller@3021000 {
> > + compatible = "arm,gic-400";
> > + reg = <0x03021000 0x1000>,
> > + <0x03022000 0x2000>,
> > + <0x03024000 0x2000>,
> > + <0x03026000 0x2000>;
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + };
> > +
> > + mmc0: mmc@4020000 {
> > + compatible = "allwinner,sun50i-h616-mmc",
> > + "allwinner,sun50i-a100-mmc";
> > + reg = <0x04020000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC0>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc0_pins>;
> > + status = "disabled";
> > + max-frequency = <150000000>;
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + cap-sdio-irq;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + mmc1: mmc@4021000 {
> > + compatible = "allwinner,sun50i-h616-mmc",
> > + "allwinner,sun50i-a100-mmc";
> > + reg = <0x04021000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC1>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc1_pins>;
> > + status = "disabled";
> > + max-frequency = <150000000>;
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + cap-sdio-irq;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + mmc2: mmc@4022000 {
> > + compatible = "allwinner,sun50i-h616-emmc",
> > + "allwinner,sun50i-a100-emmc";
> > + reg = <0x04022000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC2>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc2_pins>;
> > + status = "disabled";
> > + max-frequency = <150000000>;
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + cap-sdio-irq;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + uart0: serial@5000000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000000 0x400>;
> > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART0>;
> > + resets = <&ccu RST_BUS_UART0>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@5000400 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000400 0x400>;
> > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART1>;
> > + resets = <&ccu RST_BUS_UART1>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@5000800 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000800 0x400>;
> > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART2>;
> > + resets = <&ccu RST_BUS_UART2>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@5000c00 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000c00 0x400>;
> > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART3>;
> > + resets = <&ccu RST_BUS_UART3>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial@5001000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05001000 0x400>;
> > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART4>;
> > + resets = <&ccu RST_BUS_UART4>;
> > + status = "disabled";
> > + };
> > +
> > + uart5: serial@5001400 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05001400 0x400>;
> > + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART5>;
> > + resets = <&ccu RST_BUS_UART5>;
> > + status = "disabled";
> > + };
> > +
> > + i2c0: i2c@5002000 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
>
> Future note: this will be affected by [1] which adds a fallback compatible for
> variants with offload support. That way we don't have to support them all
> individually in the driver if/when we implement that.
>
> [1]: https://lore.kernel.org/lkml/20220702052544.31443-1-samuel@sholland.org/
I saw (and liked) that. Shall I insert the compatible string already? Or
is it too early for that, because dtbs_checks would fail without the
amended binding in the tree?
Cheers,
Andre
>
> > + reg = <0x05002000 0x400>;
> > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C0>;
> > + resets = <&ccu RST_BUS_I2C0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c0_pins>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c1: i2c@5002400 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05002400 0x400>;
> > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C1>;
> > + resets = <&ccu RST_BUS_I2C1>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c2: i2c@5002800 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05002800 0x400>;
> > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C2>;
> > + resets = <&ccu RST_BUS_I2C2>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c3: i2c@5002c00 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05002c00 0x400>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C3>;
> > + resets = <&ccu RST_BUS_I2C3>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c4: i2c@5003000 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05003000 0x400>;
> > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C4>;
> > + resets = <&ccu RST_BUS_I2C4>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + spi0: spi@5010000 {
> > + compatible = "allwinner,sun50i-h616-spi",
> > + "allwinner,sun8i-h3-spi";
> > + reg = <0x05010000 0x1000>;
> > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> > + clock-names = "ahb", "mod";
> > + resets = <&ccu RST_BUS_SPI0>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + spi1: spi@5011000 {
> > + compatible = "allwinner,sun50i-h616-spi",
> > + "allwinner,sun8i-h3-spi";
> > + reg = <0x05011000 0x1000>;
> > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> > + clock-names = "ahb", "mod";
> > + resets = <&ccu RST_BUS_SPI1>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + emac0: ethernet@5020000 {
> > + compatible = "allwinner,sun50i-h616-emac",
> > + "allwinner,sun50i-a64-emac";
> > + syscon = <&syscon>;
> > + reg = <0x05020000 0x10000>;
> > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + resets = <&ccu RST_BUS_EMAC0>;
> > + reset-names = "stmmaceth";
> > + clocks = <&ccu CLK_BUS_EMAC0>;
> > + clock-names = "stmmaceth";
>
> Nit: clocks then resets then syscon, to follow the usual order.
>
> > + status = "disabled";
> > +
> > + mdio0: mdio {
> > + compatible = "snps,dwmac-mdio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > + rtc: rtc@7000000 {
> > + compatible = "allwinner,sun50i-h616-rtc";
> > + reg = <0x07000000 0x400>;
> > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
> > + <&ccu CLK_PLL_SYSTEM_32K>;
> > + clock-names = "bus", "hosc",
> > + "pll-32k";
> > + clock-output-names = "osc32k", "osc32k-out", "iosc";
>
> Since the RTC clock indices were formalized in the binding, this is no longer
> needed.
>
> > + #clock-cells = <1>;
> > + };
> > +
> > + r_ccu: clock@7010000 {
> > + compatible = "allwinner,sun50i-h616-r-ccu";
> > + reg = <0x07010000 0x210>;
> > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
>
> Symbolic constants here and in r_pio as well, please.
>
> > + <&ccu CLK_PLL_PERIPH0>;
> > + clock-names = "hosc", "losc", "iosc", "pll-periph";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + r_pio: pinctrl@7022000 {
> > + compatible = "allwinner,sun50i-h616-r-pinctrl";
> > + reg = <0x07022000 0x400>;
> > + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
> > + clock-names = "apb", "hosc", "losc";
> > + gpio-controller;
> > + #gpio-cells = <3>;
> > +
> > + r_i2c_pins: r-i2c-pins {
>
> This is unlikely be used (as opposed to RSB), so I suggest omit-if-no-ref.
>
> > + pins = "PL0", "PL1";
> > + function = "s_i2c";
> > + };
> > +
> > + r_rsb_pins: r-rsb-pins {
> > + pins = "PL0", "PL1";
> > + function = "s_rsb";
> > + };
> > + };
> > +
> > + ir: ir@7040000 {
> > + compatible = "allwinner,sun50i-h616-ir",
> > + "allwinner,sun6i-a31-ir";
> > + reg = <0x07040000 0x400>;
> > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > + <&r_ccu CLK_IR>;
> > + clock-names = "apb", "ir";
> > + resets = <&r_ccu RST_R_APB1_IR>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&ir_rx_pin>;
> > + status = "disabled";
> > + };
> > +
> > + r_i2c: i2c@7081400 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x07081400 0x400>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB2_I2C>;
> > + resets = <&r_ccu RST_R_APB2_I2C>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + r_rsb: rsb@7083000 {
> > + compatible = "allwinner,sun50i-h616-rsb",
> > + "allwinner,sun8i-a23-rsb";
> > + reg = <0x07083000 0x400>;
> > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB2_RSB>;
> > + clock-frequency = <3000000>;
> > + resets = <&r_ccu RST_R_APB2_RSB>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&r_rsb_pins>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +};
> >
>
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
@ 2022-07-05 10:42 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-05 10:42 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On Mon, 4 Jul 2022 20:16:50 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Hi Andre,
>
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > This (relatively) new SoC is similar to the H6, but drops the (broken)
> > PCIe support and the USB 3.0 controller. It also gets the management
> > controller removed, which in turn removes *some*, but not all of the
> > devices formerly dedicated to the ARISC (CPUS).
> > And while there is still the extra sunxi interrupt controller, the
> > package lacks the corresponding NMI pin, so no interrupts for the PMIC.
> >
> > The reserved memory node is actually handled by Trusted Firmware now,
> > but U-Boot fails to propagate this to a separately loaded DTB, so we
> > keep it in here for now, until U-Boot learns to do this properly.
>
> Other than the decision about the reserved-memory node, which is being discussed
> in the v11 thread, this looks good to me. Just a few minor comments below.
Many thanks for going through that file! I will fix what you commented on.
Just one comment on the I2C binding below ....
>
> Regards,
> Samuel
>
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > ---
> > .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 579 ++++++++++++++++++
> > 1 file changed, 579 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > new file mode 100644
> > index 0000000000000..478f0b395ff58
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> > @@ -0,0 +1,579 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +// Copyright (C) 2020 Arm Ltd.
> > +// based on the H6 dtsi, which is:
> > +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/clock/sun50i-h616-ccu.h>
> > +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
> > +#include <dt-bindings/reset/sun50i-h616-ccu.h>
> > +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> > +
> > +/ {
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <0>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <1>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <2>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + compatible = "arm,cortex-a53";
> > + device_type = "cpu";
> > + reg = <3>;
> > + enable-method = "psci";
> > + clocks = <&ccu CLK_CPUX>;
> > + };
> > + };
> > +
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + /* 512KiB reserved for ARM Trusted Firmware (BL31) */
> > + secmon_reserved: secmon@40000000 {
> > + reg = <0x0 0x40000000 0x0 0x80000>;
> > + no-map;
> > + };
> > + };
> > +
> > + osc24M: osc24M-clk {
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + clock-frequency = <24000000>;
> > + clock-output-names = "osc24M";
> > + };
> > +
> > + pmu {
> > + compatible = "arm,cortex-a53-pmu";
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-0.2";
> > + method = "smc";
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + arm,no-tick-in-suspend;
> > + interrupts = <GIC_PPI 13
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 14
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 11
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 10
> > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > +
> > + soc@0 {
>
> No unit address needed here.
>
> > + compatible = "simple-bus";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0x0 0x0 0x0 0x40000000>;
> > +
> > + syscon: syscon@3000000 {
> > + compatible = "allwinner,sun50i-h616-system-control";
> > + reg = <0x03000000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + sram_c: sram@28000 {
> > + compatible = "mmio-sram";
> > + reg = <0x00028000 0x30000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges = <0 0x00028000 0x30000>;
> > + };
> > + };
> > +
> > + ccu: clock@3001000 {
> > + compatible = "allwinner,sun50i-h616-ccu";
> > + reg = <0x03001000 0x1000>;
> > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
>
> Please use the recently-added symbolic constants for the RTC clocks.
>
> > + clock-names = "hosc", "losc", "iosc";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + watchdog: watchdog@30090a0 {
> > + compatible = "allwinner,sun50i-h616-wdt",
> > + "allwinner,sun6i-a31-wdt";
> > + reg = <0x030090a0 0x20>;
> > + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&osc24M>;
> > + };
> > +
> > + pio: pinctrl@300b000 {
> > + compatible = "allwinner,sun50i-h616-pinctrl";
> > + reg = <0x0300b000 0x400>;
> > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
>
> Same for the RTC clock here.
>
> > + clock-names = "apb", "hosc", "losc";
> > + gpio-controller;
> > + #gpio-cells = <3>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > +
> > + ext_rgmii_pins: rgmii-pins {
> > + pins = "PI0", "PI1", "PI2", "PI3", "PI4",
> > + "PI5", "PI7", "PI8", "PI9", "PI10",
> > + "PI11", "PI12", "PI13", "PI14", "PI15",
> > + "PI16";
> > + function = "emac0";
> > + drive-strength = <40>;
> > + };
> > +
> > + i2c0_pins: i2c0-pins {
> > + pins = "PI6", "PI7";
> > + function = "i2c0";
> > + };
> > +
> > + i2c3_ph_pins: i2c3-ph-pins {
> > + pins = "PH4", "PH5";
> > + function = "i2c3";
> > + };
> > +
> > + ir_rx_pin: ir-rx-pin {
> > + pins = "PH10";
> > + function = "ir_rx";
> > + };
> > +
> > + mmc0_pins: mmc0-pins {
> > + pins = "PF0", "PF1", "PF2", "PF3",
> > + "PF4", "PF5";
> > + function = "mmc0";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > + /omit-if-no-ref/
> > + mmc1_pins: mmc1-pins {
> > + pins = "PG0", "PG1", "PG2", "PG3",
> > + "PG4", "PG5";
> > + function = "mmc1";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > + mmc2_pins: mmc2-pins {
> > + pins = "PC0", "PC1", "PC5", "PC6",
> > + "PC8", "PC9", "PC10", "PC11",
> > + "PC13", "PC14", "PC15", "PC16";
> > + function = "mmc2";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi0_pins: spi0-pins {
> > + pins = "PC0", "PC2", "PC4";
> > + function = "spi0";
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi0_cs0_pin: spi0-cs0-pin {
> > + pins = "PC3";
> > + function = "spi0";
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi1_pins: spi1-pins {
> > + pins = "PH6", "PH7", "PH8";
> > + function = "spi1";
> > + };
> > +
> > + /omit-if-no-ref/
> > + spi1_cs0_pin: spi1-cs0-pin {
> > + pins = "PH5";
> > + function = "spi1";
> > + };
> > +
> > + uart0_ph_pins: uart0-ph-pins {
> > + pins = "PH0", "PH1";
> > + function = "uart0";
> > + };
> > +
> > + /omit-if-no-ref/
> > + uart1_pins: uart1-pins {
> > + pins = "PG6", "PG7";
> > + function = "uart1";
> > + };
> > +
> > + /omit-if-no-ref/
> > + uart1_rts_cts_pins: uart1-rts-cts-pins {
> > + pins = "PG8", "PG9";
> > + function = "uart1";
> > + };
> > + };
> > +
> > + gic: interrupt-controller@3021000 {
> > + compatible = "arm,gic-400";
> > + reg = <0x03021000 0x1000>,
> > + <0x03022000 0x2000>,
> > + <0x03024000 0x2000>,
> > + <0x03026000 0x2000>;
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + };
> > +
> > + mmc0: mmc@4020000 {
> > + compatible = "allwinner,sun50i-h616-mmc",
> > + "allwinner,sun50i-a100-mmc";
> > + reg = <0x04020000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC0>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc0_pins>;
> > + status = "disabled";
> > + max-frequency = <150000000>;
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + cap-sdio-irq;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + mmc1: mmc@4021000 {
> > + compatible = "allwinner,sun50i-h616-mmc",
> > + "allwinner,sun50i-a100-mmc";
> > + reg = <0x04021000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC1>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc1_pins>;
> > + status = "disabled";
> > + max-frequency = <150000000>;
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + cap-sdio-irq;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + mmc2: mmc@4022000 {
> > + compatible = "allwinner,sun50i-h616-emmc",
> > + "allwinner,sun50i-a100-emmc";
> > + reg = <0x04022000 0x1000>;
> > + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> > + clock-names = "ahb", "mmc";
> > + resets = <&ccu RST_BUS_MMC2>;
> > + reset-names = "ahb";
> > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&mmc2_pins>;
> > + status = "disabled";
> > + max-frequency = <150000000>;
> > + cap-sd-highspeed;
> > + cap-mmc-highspeed;
> > + mmc-ddr-3_3v;
> > + cap-sdio-irq;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + uart0: serial@5000000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000000 0x400>;
> > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART0>;
> > + resets = <&ccu RST_BUS_UART0>;
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@5000400 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000400 0x400>;
> > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART1>;
> > + resets = <&ccu RST_BUS_UART1>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@5000800 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000800 0x400>;
> > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART2>;
> > + resets = <&ccu RST_BUS_UART2>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@5000c00 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05000c00 0x400>;
> > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART3>;
> > + resets = <&ccu RST_BUS_UART3>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial@5001000 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05001000 0x400>;
> > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART4>;
> > + resets = <&ccu RST_BUS_UART4>;
> > + status = "disabled";
> > + };
> > +
> > + uart5: serial@5001400 {
> > + compatible = "snps,dw-apb-uart";
> > + reg = <0x05001400 0x400>;
> > + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + clocks = <&ccu CLK_BUS_UART5>;
> > + resets = <&ccu RST_BUS_UART5>;
> > + status = "disabled";
> > + };
> > +
> > + i2c0: i2c@5002000 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
>
> Future note: this will be affected by [1] which adds a fallback compatible for
> variants with offload support. That way we don't have to support them all
> individually in the driver if/when we implement that.
>
> [1]: https://lore.kernel.org/lkml/20220702052544.31443-1-samuel@sholland.org/
I saw (and liked) that. Shall I insert the compatible string already? Or
is it too early for that, because dtbs_checks would fail without the
amended binding in the tree?
Cheers,
Andre
>
> > + reg = <0x05002000 0x400>;
> > + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C0>;
> > + resets = <&ccu RST_BUS_I2C0>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c0_pins>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c1: i2c@5002400 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05002400 0x400>;
> > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C1>;
> > + resets = <&ccu RST_BUS_I2C1>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c2: i2c@5002800 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05002800 0x400>;
> > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C2>;
> > + resets = <&ccu RST_BUS_I2C2>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c3: i2c@5002c00 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05002c00 0x400>;
> > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C3>;
> > + resets = <&ccu RST_BUS_I2C3>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + i2c4: i2c@5003000 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x05003000 0x400>;
> > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_I2C4>;
> > + resets = <&ccu RST_BUS_I2C4>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + spi0: spi@5010000 {
> > + compatible = "allwinner,sun50i-h616-spi",
> > + "allwinner,sun8i-h3-spi";
> > + reg = <0x05010000 0x1000>;
> > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> > + clock-names = "ahb", "mod";
> > + resets = <&ccu RST_BUS_SPI0>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + spi1: spi@5011000 {
> > + compatible = "allwinner,sun50i-h616-spi",
> > + "allwinner,sun8i-h3-spi";
> > + reg = <0x05011000 0x1000>;
> > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> > + clock-names = "ahb", "mod";
> > + resets = <&ccu RST_BUS_SPI1>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + emac0: ethernet@5020000 {
> > + compatible = "allwinner,sun50i-h616-emac",
> > + "allwinner,sun50i-a64-emac";
> > + syscon = <&syscon>;
> > + reg = <0x05020000 0x10000>;
> > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "macirq";
> > + resets = <&ccu RST_BUS_EMAC0>;
> > + reset-names = "stmmaceth";
> > + clocks = <&ccu CLK_BUS_EMAC0>;
> > + clock-names = "stmmaceth";
>
> Nit: clocks then resets then syscon, to follow the usual order.
>
> > + status = "disabled";
> > +
> > + mdio0: mdio {
> > + compatible = "snps,dwmac-mdio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > + rtc: rtc@7000000 {
> > + compatible = "allwinner,sun50i-h616-rtc";
> > + reg = <0x07000000 0x400>;
> > + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
> > + <&ccu CLK_PLL_SYSTEM_32K>;
> > + clock-names = "bus", "hosc",
> > + "pll-32k";
> > + clock-output-names = "osc32k", "osc32k-out", "iosc";
>
> Since the RTC clock indices were formalized in the binding, this is no longer
> needed.
>
> > + #clock-cells = <1>;
> > + };
> > +
> > + r_ccu: clock@7010000 {
> > + compatible = "allwinner,sun50i-h616-r-ccu";
> > + reg = <0x07010000 0x210>;
> > + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
>
> Symbolic constants here and in r_pio as well, please.
>
> > + <&ccu CLK_PLL_PERIPH0>;
> > + clock-names = "hosc", "losc", "iosc", "pll-periph";
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + r_pio: pinctrl@7022000 {
> > + compatible = "allwinner,sun50i-h616-r-pinctrl";
> > + reg = <0x07022000 0x400>;
> > + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
> > + clock-names = "apb", "hosc", "losc";
> > + gpio-controller;
> > + #gpio-cells = <3>;
> > +
> > + r_i2c_pins: r-i2c-pins {
>
> This is unlikely be used (as opposed to RSB), so I suggest omit-if-no-ref.
>
> > + pins = "PL0", "PL1";
> > + function = "s_i2c";
> > + };
> > +
> > + r_rsb_pins: r-rsb-pins {
> > + pins = "PL0", "PL1";
> > + function = "s_rsb";
> > + };
> > + };
> > +
> > + ir: ir@7040000 {
> > + compatible = "allwinner,sun50i-h616-ir",
> > + "allwinner,sun6i-a31-ir";
> > + reg = <0x07040000 0x400>;
> > + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB1_IR>,
> > + <&r_ccu CLK_IR>;
> > + clock-names = "apb", "ir";
> > + resets = <&r_ccu RST_R_APB1_IR>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&ir_rx_pin>;
> > + status = "disabled";
> > + };
> > +
> > + r_i2c: i2c@7081400 {
> > + compatible = "allwinner,sun50i-h616-i2c",
> > + "allwinner,sun6i-a31-i2c";
> > + reg = <0x07081400 0x400>;
> > + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB2_I2C>;
> > + resets = <&r_ccu RST_R_APB2_I2C>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > +
> > + r_rsb: rsb@7083000 {
> > + compatible = "allwinner,sun50i-h616-rsb",
> > + "allwinner,sun8i-a23-rsb";
> > + reg = <0x07083000 0x400>;
> > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&r_ccu CLK_R_APB2_RSB>;
> > + clock-frequency = <3000000>;
> > + resets = <&r_ccu RST_R_APB2_RSB>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&r_rsb_pins>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +};
> >
>
>
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
2022-07-05 10:19 ` Andre Przywara
@ 2022-07-06 3:55 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-06 3:55 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
Hi Andre,
On 7/5/22 5:19 AM, Andre Przywara wrote:
> On Mon, 4 Jul 2022 18:53:14 -0500
> Samuel Holland <samuel@sholland.org> wrote:
>> On 7/1/22 6:24 AM, Andre Przywara wrote:
>>> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
>>> version.
>>>
>>> Add it to the list of compatible strings.
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>> ---
>>> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> index 6a4831fd3616c..87f1306831cc9 100644
>>> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> @@ -22,6 +22,7 @@ properties:
>>> - enum:
>>> - allwinner,sun20i-d1-emac
>>> - allwinner,sun50i-h6-emac
>>> + - allwinner,sun50i-h616-emac
>>
>> The H616 manual has register fields for an internal PHY, like H3. Are these not
>> hooked up for either EMAC?
>
> Which register fields do you mean, exactly?
I mean bits 15-31 of EMAC_EPHY_CLK_REG0.
> The H616 uses the same internal PHY solution as the H6: an AC200 die
> co-packaged on the carrier (or whatever integration solution they actually
> chose). The difference to the H6 is that EMAC0 is hardwired to the external
> RGMII pins, whereas EMAC1 is hardwired to the internal AC200 RMII pins.
> From all I could see that does not impact the actual MAC IP: both are the
> same as in the H6, or A64, for that matter.
If those bits in EMAC_EPHY_CLK_REG0 have no effect, then I agree. But if
switching bit 15 to internal PHY causes Ethernet to stop working, then the mux
really does exist (even if one side is not connected to anything). In that case,
we need to make sure the mux is set to the external PHY, using the code from H3.
> There is one twist, though: the second EMAC uses a separate EMAC clock
> register in the syscon. I came up with this patch to support that:
> https://github.com/apritzel/linux/commit/078f591017794a0ec689345b0eeb7150908cf85a
> That extends the syscon to take an optional(!) index. So EMAC0 works
> exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
> we need the index: "<&syscon 4>;".
> But in my opinion this should not affect the MAC binding, at least not for
> MAC0.
It definitely affects the MAC binding, because we have to change the definition
of the syscon property. We should still get that reviewed before doing anything
that depends on it. (And I think EMAC0 support depends on it.)
> And I think we should get away without a different compatible string
> for EMAC1, since the MAC IP is technically the same, it's just the
> connection that is different.
If you claim that both EMACs are compatible with allwinner,sun50i-a64-emac, then
you are saying that any existing driver for allwinner,sun50i-a64-emac will also
work with both of the H616 EMACs. But this is not true. If I hook up both EMACs
in the DT per the binding, and use the driver in master, at best only EMAC0 will
work, and likely neither will work.
So at minimum you need a new compatible for the second EMAC, so it only binds to
drivers that know about the syscon offset specifier.
> In any case I think this does not affect the level of support we promise
> today: EMAC0 with an external PHY only.
This can work if you introduce a second compatible for EMAC1. But at that point
you don't need the syscon offset specifier; it can be part of the driver data,
like for R40. (And any future EMAC1 could likely fall back to this compatible.)
Regards,
Samuel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
@ 2022-07-06 3:55 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-06 3:55 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
Hi Andre,
On 7/5/22 5:19 AM, Andre Przywara wrote:
> On Mon, 4 Jul 2022 18:53:14 -0500
> Samuel Holland <samuel@sholland.org> wrote:
>> On 7/1/22 6:24 AM, Andre Przywara wrote:
>>> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
>>> version.
>>>
>>> Add it to the list of compatible strings.
>>>
>>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>>> ---
>>> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> index 6a4831fd3616c..87f1306831cc9 100644
>>> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
>>> @@ -22,6 +22,7 @@ properties:
>>> - enum:
>>> - allwinner,sun20i-d1-emac
>>> - allwinner,sun50i-h6-emac
>>> + - allwinner,sun50i-h616-emac
>>
>> The H616 manual has register fields for an internal PHY, like H3. Are these not
>> hooked up for either EMAC?
>
> Which register fields do you mean, exactly?
I mean bits 15-31 of EMAC_EPHY_CLK_REG0.
> The H616 uses the same internal PHY solution as the H6: an AC200 die
> co-packaged on the carrier (or whatever integration solution they actually
> chose). The difference to the H6 is that EMAC0 is hardwired to the external
> RGMII pins, whereas EMAC1 is hardwired to the internal AC200 RMII pins.
> From all I could see that does not impact the actual MAC IP: both are the
> same as in the H6, or A64, for that matter.
If those bits in EMAC_EPHY_CLK_REG0 have no effect, then I agree. But if
switching bit 15 to internal PHY causes Ethernet to stop working, then the mux
really does exist (even if one side is not connected to anything). In that case,
we need to make sure the mux is set to the external PHY, using the code from H3.
> There is one twist, though: the second EMAC uses a separate EMAC clock
> register in the syscon. I came up with this patch to support that:
> https://github.com/apritzel/linux/commit/078f591017794a0ec689345b0eeb7150908cf85a
> That extends the syscon to take an optional(!) index. So EMAC0 works
> exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
> we need the index: "<&syscon 4>;".
> But in my opinion this should not affect the MAC binding, at least not for
> MAC0.
It definitely affects the MAC binding, because we have to change the definition
of the syscon property. We should still get that reviewed before doing anything
that depends on it. (And I think EMAC0 support depends on it.)
> And I think we should get away without a different compatible string
> for EMAC1, since the MAC IP is technically the same, it's just the
> connection that is different.
If you claim that both EMACs are compatible with allwinner,sun50i-a64-emac, then
you are saying that any existing driver for allwinner,sun50i-a64-emac will also
work with both of the H616 EMACs. But this is not true. If I hook up both EMACs
in the DT per the binding, and use the driver in master, at best only EMAC0 will
work, and likely neither will work.
So at minimum you need a new compatible for the second EMAC, so it only binds to
drivers that know about the syscon offset specifier.
> In any case I think this does not affect the level of support we promise
> today: EMAC0 with an external PHY only.
This can work if you introduce a second compatible for EMAC1. But at that point
you don't need the syscon offset specifier; it can be part of the driver data,
like for R40. (And any future EMAC1 could likely fall back to this compatible.)
Regards,
Samuel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
2022-07-05 10:42 ` Andre Przywara
@ 2022-07-07 6:36 ` Samuel Holland
-1 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-07 6:36 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Hi Andre,
On 7/5/22 5:42 AM, Andre Przywara wrote:
> On Mon, 4 Jul 2022 20:16:50 -0500
> Samuel Holland <samuel@sholland.org> wrote:
>>> + i2c0: i2c@5002000 {
>>> + compatible = "allwinner,sun50i-h616-i2c",
>>> + "allwinner,sun6i-a31-i2c";
>>
>> Future note: this will be affected by [1] which adds a fallback compatible for
>> variants with offload support. That way we don't have to support them all
>> individually in the driver if/when we implement that.
>>
>> [1]: https://lore.kernel.org/lkml/20220702052544.31443-1-samuel@sholland.org/
>
> I saw (and liked) that. Shall I insert the compatible string already? Or
> is it too early for that, because dtbs_checks would fail without the
> amended binding in the tree?
The updated binding is in linux-next, so please add the new compatible.
Regards,
Samuel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
@ 2022-07-07 6:36 ` Samuel Holland
0 siblings, 0 replies; 48+ messages in thread
From: Samuel Holland @ 2022-07-07 6:36 UTC (permalink / raw)
To: Andre Przywara
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Hi Andre,
On 7/5/22 5:42 AM, Andre Przywara wrote:
> On Mon, 4 Jul 2022 20:16:50 -0500
> Samuel Holland <samuel@sholland.org> wrote:
>>> + i2c0: i2c@5002000 {
>>> + compatible = "allwinner,sun50i-h616-i2c",
>>> + "allwinner,sun6i-a31-i2c";
>>
>> Future note: this will be affected by [1] which adds a fallback compatible for
>> variants with offload support. That way we don't have to support them all
>> individually in the driver if/when we implement that.
>>
>> [1]: https://lore.kernel.org/lkml/20220702052544.31443-1-samuel@sholland.org/
>
> I saw (and liked) that. Shall I insert the compatible string already? Or
> is it too early for that, because dtbs_checks would fail without the
> amended binding in the tree?
The updated binding is in linux-next, so please add the new compatible.
Regards,
Samuel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support
2022-07-05 1:29 ` Samuel Holland
@ 2022-07-08 9:48 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-08 9:48 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On Mon, 4 Jul 2022 20:29:45 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > The X96 Mate is an Allwinner H616 based TV box, featuring:
> > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> > - 2GiB/4GiB RAM (fully usable!)
> > - 16/32/64GiB eMMC
> > - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
> > - Unsupported Allwinner WiFi chip
> > - 2 x USB 2.0 host ports
> > - HDMI port
> > - IR receiver
> > - 5V/2A DC power supply via barrel plug
> >
> > Add a basic devicetree for it, with SD card and eMMC working, as
> > well as serial and the essential peripherals, like the AXP PMIC.
> >
> > This DT is somewhat minimal, and should work on many other similar TV
> > boxes with the Allwinner H616 chip.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> Looks good to me, with one question below.
>
> Reviewed-by: Samuel Holland <samuel@sholland.org>
Thanks!
> > ---
> > arch/arm64/boot/dts/allwinner/Makefile | 1 +
> > .../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++
> > 2 files changed, 178 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> > index df2214e6d946a..6a96494a2e0a3 100644
> > --- a/arch/arm64/boot/dts/allwinner/Makefile
> > +++ b/arch/arm64/boot/dts/allwinner/Makefile
> > @@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> > new file mode 100644
> > index 0000000000000..30b76140b9c8a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> > @@ -0,0 +1,177 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2021 Arm Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "sun50i-h616.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + model = "X96 Mate";
> > + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + reg_vcc5v: vcc5v {
> > + /* board wide 5V supply directly from the DC input */
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-5v";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&ir {
> > + status = "okay";
> > +};
> > +
> > +&mmc0 {
> > + vmmc-supply = <®_dcdce>;
> > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> > + bus-width = <4>;
> > + status = "okay";
> > +};
> > +
> > +&mmc2 {
> > + vmmc-supply = <®_dcdce>;
> > + vqmmc-supply = <®_bldo1>;
> > + bus-width = <8>;
> > + non-removable;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + status = "okay";
> > +};
> > +
> > +&r_rsb {
> > + status = "okay";
> > +
> > + axp305: pmic@745 {
> > + compatible = "x-powers,axp305", "x-powers,axp805",
> > + "x-powers,axp806";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + reg = <0x745>;
> > +
> > + x-powers,self-working-mode;
> > + vina-supply = <®_vcc5v>;
> > + vinb-supply = <®_vcc5v>;
> > + vinc-supply = <®_vcc5v>;
> > + vind-supply = <®_vcc5v>;
> > + vine-supply = <®_vcc5v>;
> > + aldoin-supply = <®_vcc5v>;
> > + bldoin-supply = <®_vcc5v>;
> > + cldoin-supply = <®_vcc5v>;
> > +
> > + regulators {
> > + reg_aldo1: aldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-sys";
> > + };
> > +
> > + /* Enabled by the Android BSP */
> > + reg_aldo2: aldo2 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext";
> > + status = "disabled";
>
> If you disable these nodes, the regulator core will ignore them and not apply
> the voltages. Is that what you want?
It's what works ;-)
ALDO2 was enabled and set to 3.3V by Android, also set in their DTB.
However I figured it's not needed for our operation, at least not with
the peripherals we support (including USB): turning it on or off didn't
change anything. I just kept this in as documentation and a guide for
future enablement, as this may drive *something*.
Cheers,
Andre
>
> Regards,
> Samuel
>
> > + };
> > +
> > + /* Enabled by the Android BSP */
> > + reg_aldo3: aldo3 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext2";
> > + status = "disabled";
> > + };
> > +
> > + reg_bldo1: bldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vcc1v8";
> > + };
> > +
> > + /* Enabled by the Android BSP */
> > + reg_bldo2: bldo2 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vcc1v8-2";
> > + status = "disabled";
> > + };
> > +
> > + bldo3 {
> > + /* unused */
> > + };
> > +
> > + bldo4 {
> > + /* unused */
> > + };
> > +
> > + cldo1 {
> > + regulator-min-microvolt = <2500000>;
> > + regulator-max-microvolt = <2500000>;
> > + regulator-name = "vcc2v5";
> > + };
> > +
> > + cldo2 {
> > + /* unused */
> > + };
> > +
> > + cldo3 {
> > + /* unused */
> > + };
> > +
> > + reg_dcdca: dcdca {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
> > + regulator-name = "vdd-cpu";
> > + };
> > +
> > + reg_dcdcc: dcdcc {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
> > + regulator-name = "vdd-gpu-sys";
> > + };
> > +
> > + reg_dcdcd: dcdcd {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1360000>;
> > + regulator-max-microvolt = <1360000>;
> > + regulator-name = "vdd-dram";
> > + };
> > +
> > + reg_dcdce: dcdce {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-eth-mmc";
> > + };
> > +
> > + sw {
> > + /* unused */
> > + };
> > + };
> > + };
> > +};
> > +
> > +&uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_ph_pins>;
> > + status = "okay";
> > +};
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support
@ 2022-07-08 9:48 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-08 9:48 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On Mon, 4 Jul 2022 20:29:45 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > The X96 Mate is an Allwinner H616 based TV box, featuring:
> > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> > - 2GiB/4GiB RAM (fully usable!)
> > - 16/32/64GiB eMMC
> > - 100Mbps Ethernet (via embedded AC200 EPHY, not yet supported)
> > - Unsupported Allwinner WiFi chip
> > - 2 x USB 2.0 host ports
> > - HDMI port
> > - IR receiver
> > - 5V/2A DC power supply via barrel plug
> >
> > Add a basic devicetree for it, with SD card and eMMC working, as
> > well as serial and the essential peripherals, like the AXP PMIC.
> >
> > This DT is somewhat minimal, and should work on many other similar TV
> > boxes with the Allwinner H616 chip.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> Looks good to me, with one question below.
>
> Reviewed-by: Samuel Holland <samuel@sholland.org>
Thanks!
> > ---
> > arch/arm64/boot/dts/allwinner/Makefile | 1 +
> > .../dts/allwinner/sun50i-h616-x96-mate.dts | 177 ++++++++++++++++++
> > 2 files changed, 178 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> > index df2214e6d946a..6a96494a2e0a3 100644
> > --- a/arch/arm64/boot/dts/allwinner/Makefile
> > +++ b/arch/arm64/boot/dts/allwinner/Makefile
> > @@ -39,3 +39,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> > new file mode 100644
> > index 0000000000000..30b76140b9c8a
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
> > @@ -0,0 +1,177 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2021 Arm Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "sun50i-h616.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > + model = "X96 Mate";
> > + compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + reg_vcc5v: vcc5v {
> > + /* board wide 5V supply directly from the DC input */
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-5v";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&ir {
> > + status = "okay";
> > +};
> > +
> > +&mmc0 {
> > + vmmc-supply = <®_dcdce>;
> > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> > + bus-width = <4>;
> > + status = "okay";
> > +};
> > +
> > +&mmc2 {
> > + vmmc-supply = <®_dcdce>;
> > + vqmmc-supply = <®_bldo1>;
> > + bus-width = <8>;
> > + non-removable;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + status = "okay";
> > +};
> > +
> > +&r_rsb {
> > + status = "okay";
> > +
> > + axp305: pmic@745 {
> > + compatible = "x-powers,axp305", "x-powers,axp805",
> > + "x-powers,axp806";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + reg = <0x745>;
> > +
> > + x-powers,self-working-mode;
> > + vina-supply = <®_vcc5v>;
> > + vinb-supply = <®_vcc5v>;
> > + vinc-supply = <®_vcc5v>;
> > + vind-supply = <®_vcc5v>;
> > + vine-supply = <®_vcc5v>;
> > + aldoin-supply = <®_vcc5v>;
> > + bldoin-supply = <®_vcc5v>;
> > + cldoin-supply = <®_vcc5v>;
> > +
> > + regulators {
> > + reg_aldo1: aldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-sys";
> > + };
> > +
> > + /* Enabled by the Android BSP */
> > + reg_aldo2: aldo2 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext";
> > + status = "disabled";
>
> If you disable these nodes, the regulator core will ignore them and not apply
> the voltages. Is that what you want?
It's what works ;-)
ALDO2 was enabled and set to 3.3V by Android, also set in their DTB.
However I figured it's not needed for our operation, at least not with
the peripherals we support (including USB): turning it on or off didn't
change anything. I just kept this in as documentation and a guide for
future enablement, as this may drive *something*.
Cheers,
Andre
>
> Regards,
> Samuel
>
> > + };
> > +
> > + /* Enabled by the Android BSP */
> > + reg_aldo3: aldo3 {
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext2";
> > + status = "disabled";
> > + };
> > +
> > + reg_bldo1: bldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vcc1v8";
> > + };
> > +
> > + /* Enabled by the Android BSP */
> > + reg_bldo2: bldo2 {
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vcc1v8-2";
> > + status = "disabled";
> > + };
> > +
> > + bldo3 {
> > + /* unused */
> > + };
> > +
> > + bldo4 {
> > + /* unused */
> > + };
> > +
> > + cldo1 {
> > + regulator-min-microvolt = <2500000>;
> > + regulator-max-microvolt = <2500000>;
> > + regulator-name = "vcc2v5";
> > + };
> > +
> > + cldo2 {
> > + /* unused */
> > + };
> > +
> > + cldo3 {
> > + /* unused */
> > + };
> > +
> > + reg_dcdca: dcdca {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
> > + regulator-name = "vdd-cpu";
> > + };
> > +
> > + reg_dcdcc: dcdcc {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
> > + regulator-name = "vdd-gpu-sys";
> > + };
> > +
> > + reg_dcdcd: dcdcd {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1360000>;
> > + regulator-max-microvolt = <1360000>;
> > + regulator-name = "vdd-dram";
> > + };
> > +
> > + reg_dcdce: dcdce {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-eth-mmc";
> > + };
> > +
> > + sw {
> > + /* unused */
> > + };
> > + };
> > + };
> > +};
> > +
> > +&uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_ph_pins>;
> > + status = "okay";
> > +};
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
2022-07-05 1:45 ` Samuel Holland
@ 2022-07-08 9:49 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-08 9:49 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On Mon, 4 Jul 2022 20:45:18 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > The OrangePi Zero 2 is a development board with the new H616 SoC. It
> > comes with the following features:
> > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> > - 512MiB/1GiB DDR3 DRAM
> > - AXP305 PMIC
> > - Raspberry-Pi-1 compatible GPIO header
> > - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
> > - 1 USB 2.0 host port
> > - 1 USB 2.0 type C port (power supply + OTG)
> > - MicroSD slot
> > - on-board 2MiB bootable SPI NOR flash
> > - 1Gbps Ethernet port (via RTL8211F PHY)
> > - micro-HDMI port
> > - (yet) unsupported Allwinner WiFi/BT chip
> >
> > Add the devicetree file describing the currently supported features.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> One question below.
>
> > ---
> > arch/arm64/boot/dts/allwinner/Makefile | 1 +
> > .../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++
> > 2 files changed, 214 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> > index 8fa5c060a4fef..df2214e6d946a 100644
> > --- a/arch/arm64/boot/dts/allwinner/Makefile
> > +++ b/arch/arm64/boot/dts/allwinner/Makefile
> > @@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> > new file mode 100644
> > index 0000000000000..cff199536d3bc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> > @@ -0,0 +1,213 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2020 Arm Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "sun50i-h616.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/leds/common.h>
> > +
> > +/ {
> > + model = "OrangePi Zero2";
> > + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
> > +
> > + aliases {
> > + ethernet0 = &emac0;
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + leds {
> > + compatible = "gpio-leds";
> > +
> > + led-0 {
> > + function = LED_FUNCTION_POWER;
> > + color = <LED_COLOR_ID_RED>;
> > + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
> > + default-state = "on";
> > + };
> > +
> > + led-1 {
> > + function = LED_FUNCTION_STATUS;
> > + color = <LED_COLOR_ID_GREEN>;
> > + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
> > + };
> > + };
> > +
> > + reg_vcc5v: vcc5v {
> > + /* board wide 5V supply directly from the USB-C socket */
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-5v";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&emac0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&ext_rgmii_pins>;
> > + phy-mode = "rgmii";
> > + phy-handle = <&ext_rgmii_phy>;
> > + phy-supply = <®_dcdce>;
> > + allwinner,rx-delay-ps = <3100>;
> > + allwinner,tx-delay-ps = <700>;
> > + status = "okay";
> > +};
> > +
> > +&mdio0 {
> > + ext_rgmii_phy: ethernet-phy@1 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + };
> > +};
> > +
> > +&mmc0 {
> > + vmmc-supply = <®_dcdce>;
> > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> > + bus-width = <4>;
> > + status = "okay";
> > +};
> > +
> > +&r_rsb {
> > + status = "okay";
> > +
> > + axp305: pmic@745 {
> > + compatible = "x-powers,axp305", "x-powers,axp805",
> > + "x-powers,axp806";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + reg = <0x745>;
> > +
> > + x-powers,self-working-mode;
> > + vina-supply = <®_vcc5v>;
> > + vinb-supply = <®_vcc5v>;
> > + vinc-supply = <®_vcc5v>;
> > + vind-supply = <®_vcc5v>;
> > + vine-supply = <®_vcc5v>;
> > + aldoin-supply = <®_vcc5v>;
> > + bldoin-supply = <®_vcc5v>;
> > + cldoin-supply = <®_vcc5v>;
> > +
> > + regulators {
> > + reg_aldo1: aldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-sys";
> > + };
> > +
> > + reg_aldo2: aldo2 { /* 3.3V on headers */
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext";
> > + };
> > +
> > + reg_aldo3: aldo3 { /* 3.3V on headers */
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext2";
> > + };
> > +
> > + reg_bldo1: bldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vcc1v8";
> > + };
> > +
> > + bldo2 {
> > + /* unused */
> > + };
> > +
> > + bldo3 {
> > + /* unused */
> > + };
> > +
> > + bldo4 {
> > + /* unused */
> > + };
> > +
> > + cldo1 {
> > + /* reserved */
> > + };
> > +
> > + cldo2 {
> > + /* unused */
> > + };
> > +
> > + cldo3 {
> > + /* unused */
> > + };
> > +
> > + reg_dcdca: dcdca {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
> > + regulator-name = "vdd-cpu";
> > + };
> > +
> > + reg_dcdcc: dcdcc {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
>
> Where does the max voltage here come from? The H616 datasheet lists the limit
> for both VDD_GPU and VDD_SYS as 0.99 V. (This applies to both boards.)
Copied from somewhere, not entirely sure where from. The vendor DT
lists the full AXP range, with a surely unhealthy upper limit of 1.52V.
My copy of the datasheet lists max 1.1V for the CPU and 0.99V for
the GPU (recommended operating conditions), so I am using those values
now.
Thanks for spotting.
Cheers,
Andre
>
> Regards,
> Samuel
>
> > + regulator-name = "vdd-gpu-sys";
> > + };
> > +
> > + reg_dcdcd: dcdcd {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1500000>;
> > + regulator-max-microvolt = <1500000>;
> > + regulator-name = "vdd-dram";
> > + };
> > +
> > + reg_dcdce: dcdce {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-eth-mmc";
> > + };
> > +
> > + sw {
> > + /* unused */
> > + };
> > + };
> > + };
> > +};
> > +
> > +&pio {
> > + vcc-pc-supply = <®_aldo1>;
> > + vcc-pf-supply = <®_aldo1>;
> > + vcc-pg-supply = <®_bldo1>;
> > + vcc-ph-supply = <®_aldo1>;
> > + vcc-pi-supply = <®_aldo1>;
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
> > +
> > + flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + reg = <0>;
> > + spi-max-frequency = <40000000>;
> > + };
> > +};
> > +
> > +&uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_ph_pins>;
> > + status = "okay";
> > +};
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
@ 2022-07-08 9:49 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-08 9:49 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
On Mon, 4 Jul 2022 20:45:18 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
> On 7/1/22 6:24 AM, Andre Przywara wrote:
> > The OrangePi Zero 2 is a development board with the new H616 SoC. It
> > comes with the following features:
> > - Four ARM Cortex-A53 cores, Mali-G31 MP2 GPU
> > - 512MiB/1GiB DDR3 DRAM
> > - AXP305 PMIC
> > - Raspberry-Pi-1 compatible GPIO header
> > - extra 13 pin expansion header, exposing pins for 2x USB 2.0 ports
> > - 1 USB 2.0 host port
> > - 1 USB 2.0 type C port (power supply + OTG)
> > - MicroSD slot
> > - on-board 2MiB bootable SPI NOR flash
> > - 1Gbps Ethernet port (via RTL8211F PHY)
> > - micro-HDMI port
> > - (yet) unsupported Allwinner WiFi/BT chip
> >
> > Add the devicetree file describing the currently supported features.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> One question below.
>
> > ---
> > arch/arm64/boot/dts/allwinner/Makefile | 1 +
> > .../allwinner/sun50i-h616-orangepi-zero2.dts | 213 ++++++++++++++++++
> > 2 files changed, 214 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> > index 8fa5c060a4fef..df2214e6d946a 100644
> > --- a/arch/arm64/boot/dts/allwinner/Makefile
> > +++ b/arch/arm64/boot/dts/allwinner/Makefile
> > @@ -38,3 +38,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> > new file mode 100644
> > index 0000000000000..cff199536d3bc
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
> > @@ -0,0 +1,213 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > +/*
> > + * Copyright (C) 2020 Arm Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "sun50i-h616.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/leds/common.h>
> > +
> > +/ {
> > + model = "OrangePi Zero2";
> > + compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
> > +
> > + aliases {
> > + ethernet0 = &emac0;
> > + serial0 = &uart0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + leds {
> > + compatible = "gpio-leds";
> > +
> > + led-0 {
> > + function = LED_FUNCTION_POWER;
> > + color = <LED_COLOR_ID_RED>;
> > + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
> > + default-state = "on";
> > + };
> > +
> > + led-1 {
> > + function = LED_FUNCTION_STATUS;
> > + color = <LED_COLOR_ID_GREEN>;
> > + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
> > + };
> > + };
> > +
> > + reg_vcc5v: vcc5v {
> > + /* board wide 5V supply directly from the USB-C socket */
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-5v";
> > + regulator-min-microvolt = <5000000>;
> > + regulator-max-microvolt = <5000000>;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&emac0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&ext_rgmii_pins>;
> > + phy-mode = "rgmii";
> > + phy-handle = <&ext_rgmii_phy>;
> > + phy-supply = <®_dcdce>;
> > + allwinner,rx-delay-ps = <3100>;
> > + allwinner,tx-delay-ps = <700>;
> > + status = "okay";
> > +};
> > +
> > +&mdio0 {
> > + ext_rgmii_phy: ethernet-phy@1 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + };
> > +};
> > +
> > +&mmc0 {
> > + vmmc-supply = <®_dcdce>;
> > + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> > + bus-width = <4>;
> > + status = "okay";
> > +};
> > +
> > +&r_rsb {
> > + status = "okay";
> > +
> > + axp305: pmic@745 {
> > + compatible = "x-powers,axp305", "x-powers,axp805",
> > + "x-powers,axp806";
> > + interrupt-controller;
> > + #interrupt-cells = <1>;
> > + reg = <0x745>;
> > +
> > + x-powers,self-working-mode;
> > + vina-supply = <®_vcc5v>;
> > + vinb-supply = <®_vcc5v>;
> > + vinc-supply = <®_vcc5v>;
> > + vind-supply = <®_vcc5v>;
> > + vine-supply = <®_vcc5v>;
> > + aldoin-supply = <®_vcc5v>;
> > + bldoin-supply = <®_vcc5v>;
> > + cldoin-supply = <®_vcc5v>;
> > +
> > + regulators {
> > + reg_aldo1: aldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-sys";
> > + };
> > +
> > + reg_aldo2: aldo2 { /* 3.3V on headers */
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext";
> > + };
> > +
> > + reg_aldo3: aldo3 { /* 3.3V on headers */
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc3v3-ext2";
> > + };
> > +
> > + reg_bldo1: bldo1 {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-name = "vcc1v8";
> > + };
> > +
> > + bldo2 {
> > + /* unused */
> > + };
> > +
> > + bldo3 {
> > + /* unused */
> > + };
> > +
> > + bldo4 {
> > + /* unused */
> > + };
> > +
> > + cldo1 {
> > + /* reserved */
> > + };
> > +
> > + cldo2 {
> > + /* unused */
> > + };
> > +
> > + cldo3 {
> > + /* unused */
> > + };
> > +
> > + reg_dcdca: dcdca {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
> > + regulator-name = "vdd-cpu";
> > + };
> > +
> > + reg_dcdcc: dcdcc {
> > + regulator-always-on;
> > + regulator-min-microvolt = <810000>;
> > + regulator-max-microvolt = <1080000>;
>
> Where does the max voltage here come from? The H616 datasheet lists the limit
> for both VDD_GPU and VDD_SYS as 0.99 V. (This applies to both boards.)
Copied from somewhere, not entirely sure where from. The vendor DT
lists the full AXP range, with a surely unhealthy upper limit of 1.52V.
My copy of the datasheet lists max 1.1V for the CPU and 0.99V for
the GPU (recommended operating conditions), so I am using those values
now.
Thanks for spotting.
Cheers,
Andre
>
> Regards,
> Samuel
>
> > + regulator-name = "vdd-gpu-sys";
> > + };
> > +
> > + reg_dcdcd: dcdcd {
> > + regulator-always-on;
> > + regulator-min-microvolt = <1500000>;
> > + regulator-max-microvolt = <1500000>;
> > + regulator-name = "vdd-dram";
> > + };
> > +
> > + reg_dcdce: dcdce {
> > + regulator-always-on;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-name = "vcc-eth-mmc";
> > + };
> > +
> > + sw {
> > + /* unused */
> > + };
> > + };
> > + };
> > +};
> > +
> > +&pio {
> > + vcc-pc-supply = <®_aldo1>;
> > + vcc-pf-supply = <®_aldo1>;
> > + vcc-pg-supply = <®_bldo1>;
> > + vcc-ph-supply = <®_aldo1>;
> > + vcc-pi-supply = <®_aldo1>;
> > +};
> > +
> > +&spi0 {
> > + status = "okay";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>;
> > +
> > + flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "jedec,spi-nor";
> > + reg = <0>;
> > + spi-max-frequency = <40000000>;
> > + };
> > +};
> > +
> > +&uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_ph_pins>;
> > + status = "okay";
> > +};
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
2022-07-06 3:55 ` Samuel Holland
@ 2022-07-11 0:16 ` Andre Przywara
-1 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-11 0:16 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
On Tue, 5 Jul 2022 22:55:54 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
thanks for the answer! I think we settled this particular issue, just
for clarification some comments/questions below.
> On 7/5/22 5:19 AM, Andre Przywara wrote:
> > On Mon, 4 Jul 2022 18:53:14 -0500
> > Samuel Holland <samuel@sholland.org> wrote:
> >> On 7/1/22 6:24 AM, Andre Przywara wrote:
> >>> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> >>> version.
> >>>
> >>> Add it to the list of compatible strings.
> >>>
> >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >>> ---
> >>> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> >>> index 6a4831fd3616c..87f1306831cc9 100644
> >>> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> >>> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> >>> @@ -22,6 +22,7 @@ properties:
> >>> - enum:
> >>> - allwinner,sun20i-d1-emac
> >>> - allwinner,sun50i-h6-emac
> >>> + - allwinner,sun50i-h616-emac
> >>
> >> The H616 manual has register fields for an internal PHY, like H3. Are these not
> >> hooked up for either EMAC?
> >
> > Which register fields do you mean, exactly?
>
> I mean bits 15-31 of EMAC_EPHY_CLK_REG0.
Right, so those bits look the same as in the H6, and probably do the
same "nothing" here as well, except for PHY_SELECT[15]?
> > The H616 uses the same internal PHY solution as the H6: an AC200 die
> > co-packaged on the carrier (or whatever integration solution they actually
> > chose). The difference to the H6 is that EMAC0 is hardwired to the external
> > RGMII pins, whereas EMAC1 is hardwired to the internal AC200 RMII pins.
> > From all I could see that does not impact the actual MAC IP: both are the
> > same as in the H6, or A64, for that matter.
>
> If those bits in EMAC_EPHY_CLK_REG0 have no effect, then I agree. But if
> switching bit 15 to internal PHY causes Ethernet to stop working, then the mux
> really does exist (even if one side is not connected to anything). In that case,
> we need to make sure the mux is set to the external PHY, using the code from H3.
I guess so, but this is what we do for the H6/A64 already, if I read the
code correctly?
if (gmac->variant->soc_has_internal_phy) {
...
} else {
/* For SoCs without internal PHY the PHY selection bit should be
* set to 0 (external PHY).
*/
reg &= ~H3_EPHY_SELECT;
}
And since we set soc_has_internal_phy to false for the A64 (and H6)
compatible, we should be good?
> > There is one twist, though: the second EMAC uses a separate EMAC clock
> > register in the syscon. I came up with this patch to support that:
> > https://github.com/apritzel/linux/commit/078f591017794a0ec689345b0eeb7150908cf85a
> > That extends the syscon to take an optional(!) index. So EMAC0 works
> > exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
> > we need the index: "<&syscon 4>;".
> > But in my opinion this should not affect the MAC binding, at least not for
> > MAC0.
>
> It definitely affects the MAC binding, because we have to change the definition
> of the syscon property. We should still get that reviewed before doing anything
> that depends on it. (And I think EMAC0 support depends on it.)
Technically I agree that it affects the current binding, at least for
EMAC1. Though this looks like some shortcoming of our binding then, as
the actual EMAC IP looks the same for both instances. It just seems
to be the *connection* to the PHYs that differ, so it's a more PHY
*setup* property than an EMAC configuration issue.
But I guess this ship has sailed, and we have to stick with what we
have right now, so would need a different compatible and some code
additions for EMAC1. But since this relies on the AC200 support
anyway (buggy RFC/WIP code here [1], btw), this doesn't look like a big
problem for now.
[1] https://github.com/apritzel/linux/commits/ac200-WIP)
> > And I think we should get away without a different compatible string
> > for EMAC1, since the MAC IP is technically the same, it's just the
> > connection that is different.
>
> If you claim that both EMACs are compatible with allwinner,sun50i-a64-emac, then
> you are saying that any existing driver for allwinner,sun50i-a64-emac will also
> work with both of the H616 EMACs. But this is not true. If I hook up both EMACs
> in the DT per the binding, and use the driver in master, at best only EMAC0 will
> work, and likely neither will work.
>
> So at minimum you need a new compatible for the second EMAC, so it only binds to
> drivers that know about the syscon offset specifier.
>
> > In any case I think this does not affect the level of support we promise
> > today: EMAC0 with an external PHY only.
>
> This can work if you introduce a second compatible for EMAC1. But at that point
> you don't need the syscon offset specifier; it can be part of the driver data,
> like for R40. (And any future EMAC1 could likely fall back to this compatible.)
Yeah, I agree. For robustness I would prefer having a specifier, so any
future twisted EMAC could be covered without yet another compatible
string. But this is a detail.
Or we use the opportunity to design this differently, so that the PHY
driver enables its PHY using this bit, maybe as part of this AC200 EPHY
"control" driver?
Cheers,
Andre
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible
@ 2022-07-11 0:16 ` Andre Przywara
0 siblings, 0 replies; 48+ messages in thread
From: Andre Przywara @ 2022-07-11 0:16 UTC (permalink / raw)
To: Samuel Holland
Cc: Chen-Yu Tsai, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, netdev
On Tue, 5 Jul 2022 22:55:54 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
thanks for the answer! I think we settled this particular issue, just
for clarification some comments/questions below.
> On 7/5/22 5:19 AM, Andre Przywara wrote:
> > On Mon, 4 Jul 2022 18:53:14 -0500
> > Samuel Holland <samuel@sholland.org> wrote:
> >> On 7/1/22 6:24 AM, Andre Przywara wrote:
> >>> The Allwinner H616 contains an "EMAC" Ethernet MAC compatible to the A64
> >>> version.
> >>>
> >>> Add it to the list of compatible strings.
> >>>
> >>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> >>> ---
> >>> .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 1 +
> >>> 1 file changed, 1 insertion(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> >>> index 6a4831fd3616c..87f1306831cc9 100644
> >>> --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> >>> +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
> >>> @@ -22,6 +22,7 @@ properties:
> >>> - enum:
> >>> - allwinner,sun20i-d1-emac
> >>> - allwinner,sun50i-h6-emac
> >>> + - allwinner,sun50i-h616-emac
> >>
> >> The H616 manual has register fields for an internal PHY, like H3. Are these not
> >> hooked up for either EMAC?
> >
> > Which register fields do you mean, exactly?
>
> I mean bits 15-31 of EMAC_EPHY_CLK_REG0.
Right, so those bits look the same as in the H6, and probably do the
same "nothing" here as well, except for PHY_SELECT[15]?
> > The H616 uses the same internal PHY solution as the H6: an AC200 die
> > co-packaged on the carrier (or whatever integration solution they actually
> > chose). The difference to the H6 is that EMAC0 is hardwired to the external
> > RGMII pins, whereas EMAC1 is hardwired to the internal AC200 RMII pins.
> > From all I could see that does not impact the actual MAC IP: both are the
> > same as in the H6, or A64, for that matter.
>
> If those bits in EMAC_EPHY_CLK_REG0 have no effect, then I agree. But if
> switching bit 15 to internal PHY causes Ethernet to stop working, then the mux
> really does exist (even if one side is not connected to anything). In that case,
> we need to make sure the mux is set to the external PHY, using the code from H3.
I guess so, but this is what we do for the H6/A64 already, if I read the
code correctly?
if (gmac->variant->soc_has_internal_phy) {
...
} else {
/* For SoCs without internal PHY the PHY selection bit should be
* set to 0 (external PHY).
*/
reg &= ~H3_EPHY_SELECT;
}
And since we set soc_has_internal_phy to false for the A64 (and H6)
compatible, we should be good?
> > There is one twist, though: the second EMAC uses a separate EMAC clock
> > register in the syscon. I came up with this patch to support that:
> > https://github.com/apritzel/linux/commit/078f591017794a0ec689345b0eeb7150908cf85a
> > That extends the syscon to take an optional(!) index. So EMAC0 works
> > exactly like before (both as "<&syscon>;", or "<&syscon 0>;", but for EMAC1
> > we need the index: "<&syscon 4>;".
> > But in my opinion this should not affect the MAC binding, at least not for
> > MAC0.
>
> It definitely affects the MAC binding, because we have to change the definition
> of the syscon property. We should still get that reviewed before doing anything
> that depends on it. (And I think EMAC0 support depends on it.)
Technically I agree that it affects the current binding, at least for
EMAC1. Though this looks like some shortcoming of our binding then, as
the actual EMAC IP looks the same for both instances. It just seems
to be the *connection* to the PHYs that differ, so it's a more PHY
*setup* property than an EMAC configuration issue.
But I guess this ship has sailed, and we have to stick with what we
have right now, so would need a different compatible and some code
additions for EMAC1. But since this relies on the AC200 support
anyway (buggy RFC/WIP code here [1], btw), this doesn't look like a big
problem for now.
[1] https://github.com/apritzel/linux/commits/ac200-WIP)
> > And I think we should get away without a different compatible string
> > for EMAC1, since the MAC IP is technically the same, it's just the
> > connection that is different.
>
> If you claim that both EMACs are compatible with allwinner,sun50i-a64-emac, then
> you are saying that any existing driver for allwinner,sun50i-a64-emac will also
> work with both of the H616 EMACs. But this is not true. If I hook up both EMACs
> in the DT per the binding, and use the driver in master, at best only EMAC0 will
> work, and likely neither will work.
>
> So at minimum you need a new compatible for the second EMAC, so it only binds to
> drivers that know about the syscon offset specifier.
>
> > In any case I think this does not affect the level of support we promise
> > today: EMAC0 with an external PHY only.
>
> This can work if you introduce a second compatible for EMAC1. But at that point
> you don't need the syscon offset specifier; it can be part of the driver data,
> like for R40. (And any future EMAC1 could likely fall back to this compatible.)
Yeah, I agree. For robustness I would prefer having a specifier, so any
future twisted EMAC could be covered without yet another compatible
string. But this is a detail.
Or we use the opportunity to design this differently, so that the PHY
driver enables its PHY using this bit, maybe as part of this AC200 EPHY
"control" driver?
Cheers,
Andre
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2022-07-11 0:19 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-01 11:24 [PATCH v12 0/7] arm64: sunxi: Allwinner H616 SoC DT support Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-01 11:24 ` [PATCH v12 1/7] dt-bindings: arm: sunxi: Add H616 EMAC compatible Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-01 20:56 ` Rob Herring
2022-07-01 20:56 ` Rob Herring
2022-07-04 23:53 ` Samuel Holland
2022-07-04 23:53 ` Samuel Holland
2022-07-05 10:19 ` Andre Przywara
2022-07-05 10:19 ` Andre Przywara
2022-07-06 3:55 ` Samuel Holland
2022-07-06 3:55 ` Samuel Holland
2022-07-11 0:16 ` Andre Przywara
2022-07-11 0:16 ` Andre Przywara
2022-07-01 11:24 ` [PATCH v12 2/7] dt-bindings: pinctrl: sunxi: Make interrupts optional Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-01 20:57 ` Rob Herring
2022-07-01 20:57 ` Rob Herring
2022-07-04 23:55 ` Samuel Holland
2022-07-04 23:55 ` Samuel Holland
2022-07-01 11:24 ` [PATCH v12 3/7] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-05 1:16 ` Samuel Holland
2022-07-05 1:16 ` Samuel Holland
2022-07-05 10:42 ` Andre Przywara
2022-07-05 10:42 ` Andre Przywara
2022-07-07 6:36 ` Samuel Holland
2022-07-07 6:36 ` Samuel Holland
2022-07-01 11:24 ` [PATCH v12 4/7] dt-bindings: pinctrl: sunxi: allow vcc-pi-supply Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-01 20:57 ` Rob Herring
2022-07-01 20:57 ` Rob Herring
2022-07-05 1:18 ` Samuel Holland
2022-07-05 1:18 ` Samuel Holland
2022-07-01 11:24 ` [PATCH v12 5/7] dt-bindings: arm: sunxi: Add two H616 board compatible strings Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-01 11:24 ` [PATCH v12 6/7] arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-05 1:45 ` Samuel Holland
2022-07-05 1:45 ` Samuel Holland
2022-07-08 9:49 ` Andre Przywara
2022-07-08 9:49 ` Andre Przywara
2022-07-01 11:24 ` [PATCH v12 7/7] arm64: dts: allwinner: h616: Add X96 Mate TV box support Andre Przywara
2022-07-01 11:24 ` Andre Przywara
2022-07-05 1:29 ` Samuel Holland
2022-07-05 1:29 ` Samuel Holland
2022-07-08 9:48 ` Andre Przywara
2022-07-08 9:48 ` Andre Przywara
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