* [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
Hi,
The SERDES in J7200 SR2.0 supports 2 reference clocks.
The second reference clock (core_ref1_clk) is hardwired to
MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).
Add a new compatible "j7200-wiz-10g" for this device.
The external clocks to SERDES PLL refclock mapping is now
controlled by a special register in System Control Module
(SCM) space. Add a property "ti,scm" to reference it and
configure it in the driver.
cheers,
-roger
Roger Quadros (4):
dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g
phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate
Siddharth Vadapalli (1):
phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200
Swapnil Jakhade (1):
dt-bindings: phy: Add PHY_TYPE_USXGMII definition
Tanmay Patil (1):
phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver
.../bindings/phy/ti,phy-j721e-wiz.yaml | 24 +-
drivers/phy/ti/phy-j721e-wiz.c | 230 ++++++++++++++++--
include/dt-bindings/phy/phy.h | 1 +
3 files changed, 239 insertions(+), 16 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
Hi,
The SERDES in J7200 SR2.0 supports 2 reference clocks.
The second reference clock (core_ref1_clk) is hardwired to
MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).
Add a new compatible "j7200-wiz-10g" for this device.
The external clocks to SERDES PLL refclock mapping is now
controlled by a special register in System Control Module
(SCM) space. Add a property "ti,scm" to reference it and
configure it in the driver.
cheers,
-roger
Roger Quadros (4):
dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g
phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate
Siddharth Vadapalli (1):
phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200
Swapnil Jakhade (1):
dt-bindings: phy: Add PHY_TYPE_USXGMII definition
Tanmay Patil (1):
phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver
.../bindings/phy/ti,phy-j721e-wiz.yaml | 24 +-
drivers/phy/ti/phy-j721e-wiz.c | 230 ++++++++++++++++--
include/dt-bindings/phy/phy.h | 1 +
3 files changed, 239 insertions(+), 16 deletions(-)
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 1/7] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
From: Siddharth Vadapalli <s-vadapalli@ti.com>
Select the same mac divider for SGMII too as the one being used for
QSGMII.
Enable full rate divider configuration support for J721E_WIZ_10G for
SGMII.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 70bac931f99a..8c10ee8e2707 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -325,7 +325,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz)
int i;
for (i = 0; i < num_lanes; i++) {
- if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
+ if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
+ wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
if (ret)
return ret;
@@ -1025,12 +1026,18 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
{
- if (wiz->type != AM64_WIZ_10G)
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+ break;
+ case J721E_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
+ break;
+ default:
return 0;
-
- if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
- return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
-
+ }
return 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 1/7] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
From: Siddharth Vadapalli <s-vadapalli@ti.com>
Select the same mac divider for SGMII too as the one being used for
QSGMII.
Enable full rate divider configuration support for J721E_WIZ_10G for
SGMII.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 70bac931f99a..8c10ee8e2707 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -325,7 +325,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz)
int i;
for (i = 0; i < num_lanes; i++) {
- if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
+ if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
+ wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
if (ret)
return ret;
@@ -1025,12 +1026,18 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
{
- if (wiz->type != AM64_WIZ_10G)
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+ break;
+ case J721E_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
+ break;
+ default:
return 0;
-
- if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
- return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
-
+ }
return 0;
}
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/7] dt-bindings: phy: Add PHY_TYPE_USXGMII definition
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Rob Herring, Roger Quadros
From: Swapnil Jakhade <sjakhade@cadence.com>
Add definition for USXGMII phy type.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index f48c9acf251e..6b901b342348 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -22,5 +22,6 @@
#define PHY_TYPE_QSGMII 9
#define PHY_TYPE_DPHY 10
#define PHY_TYPE_CPHY 11
+#define PHY_TYPE_USXGMII 12
#endif /* _DT_BINDINGS_PHY */
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 2/7] dt-bindings: phy: Add PHY_TYPE_USXGMII definition
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Rob Herring, Roger Quadros
From: Swapnil Jakhade <sjakhade@cadence.com>
Add definition for USXGMII phy type.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index f48c9acf251e..6b901b342348 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -22,5 +22,6 @@
#define PHY_TYPE_QSGMII 9
#define PHY_TYPE_DPHY 10
#define PHY_TYPE_CPHY 11
+#define PHY_TYPE_USXGMII 12
#endif /* _DT_BINDINGS_PHY */
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
From: Tanmay Patil <t-patil@ti.com>
Changes the wiz_p_mac_div_sel() and wiz_mode_select() to
configure serdes for USXGMII.
Adds the support to configure mac_src_sel, refclk_sel and
rxfclk_sel in the LANECTL register and configures the serdes for
usxgmii.
[rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code.
Signed-off-by: Tanmay Patil <t-patil@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 51 +++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 8c10ee8e2707..77accea6ec2f 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -129,6 +129,26 @@ static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 22, 23),
};
+static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 20, 21),
+ REG_FIELD(WIZ_LANECTL(1), 20, 21),
+ REG_FIELD(WIZ_LANECTL(2), 20, 21),
+ REG_FIELD(WIZ_LANECTL(3), 20, 21),
+};
+
+static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 6, 7),
+ REG_FIELD(WIZ_LANECTL(1), 6, 7),
+ REG_FIELD(WIZ_LANECTL(2), 6, 7),
+ REG_FIELD(WIZ_LANECTL(3), 6, 7),
+};
+
+static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 18, 19),
+ REG_FIELD(WIZ_LANECTL(1), 18, 19),
+ REG_FIELD(WIZ_LANECTL(2), 18, 19),
+ REG_FIELD(WIZ_LANECTL(3), 18, 19),
+};
static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANEDIV(0), 16, 22),
REG_FIELD(WIZ_LANEDIV(1), 16, 22),
@@ -280,6 +300,9 @@ struct wiz {
struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
+ struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];
+ struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
+ struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
@@ -326,7 +349,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz)
for (i = 0; i < num_lanes; i++) {
if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
- wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
+ wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||
+ wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
if (ret)
return ret;
@@ -355,6 +379,13 @@ static int wiz_mode_select(struct wiz *wiz)
else
continue;
+ if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
+ ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
+ ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
+ ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
+ mode = LANE_MODE_GEN1;
+ }
+
ret = regmap_field_write(wiz->p_standard_mode[i], mode);
if (ret)
return ret;
@@ -524,6 +555,24 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->p0_fullrt_div[i]);
}
+ wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);
+ if (IS_ERR(wiz->p0_mac_src_sel[i])) {
+ dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_mac_src_sel[i]);
+ }
+
+ wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);
+ if (IS_ERR(wiz->p0_rxfclk_sel[i])) {
+ dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_rxfclk_sel[i]);
+ }
+
+ wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);
+ if (IS_ERR(wiz->p0_refclk_sel[i])) {
+ dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_refclk_sel[i]);
+ }
+
wiz->p_mac_div_sel0[i] =
devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
if (IS_ERR(wiz->p_mac_div_sel0[i])) {
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 3/7] phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
From: Tanmay Patil <t-patil@ti.com>
Changes the wiz_p_mac_div_sel() and wiz_mode_select() to
configure serdes for USXGMII.
Adds the support to configure mac_src_sel, refclk_sel and
rxfclk_sel in the LANECTL register and configures the serdes for
usxgmii.
[rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code.
Signed-off-by: Tanmay Patil <t-patil@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 51 +++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 8c10ee8e2707..77accea6ec2f 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -129,6 +129,26 @@ static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 22, 23),
};
+static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 20, 21),
+ REG_FIELD(WIZ_LANECTL(1), 20, 21),
+ REG_FIELD(WIZ_LANECTL(2), 20, 21),
+ REG_FIELD(WIZ_LANECTL(3), 20, 21),
+};
+
+static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 6, 7),
+ REG_FIELD(WIZ_LANECTL(1), 6, 7),
+ REG_FIELD(WIZ_LANECTL(2), 6, 7),
+ REG_FIELD(WIZ_LANECTL(3), 6, 7),
+};
+
+static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
+ REG_FIELD(WIZ_LANECTL(0), 18, 19),
+ REG_FIELD(WIZ_LANECTL(1), 18, 19),
+ REG_FIELD(WIZ_LANECTL(2), 18, 19),
+ REG_FIELD(WIZ_LANECTL(3), 18, 19),
+};
static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANEDIV(0), 16, 22),
REG_FIELD(WIZ_LANEDIV(1), 16, 22),
@@ -280,6 +300,9 @@ struct wiz {
struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
+ struct regmap_field *p0_mac_src_sel[WIZ_MAX_LANES];
+ struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
+ struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
@@ -326,7 +349,8 @@ static int wiz_p_mac_div_sel(struct wiz *wiz)
for (i = 0; i < num_lanes; i++) {
if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
- wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
+ wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||
+ wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
if (ret)
return ret;
@@ -355,6 +379,13 @@ static int wiz_mode_select(struct wiz *wiz)
else
continue;
+ if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
+ ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
+ ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
+ ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x3);
+ mode = LANE_MODE_GEN1;
+ }
+
ret = regmap_field_write(wiz->p_standard_mode[i], mode);
if (ret)
return ret;
@@ -524,6 +555,24 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->p0_fullrt_div[i]);
}
+ wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);
+ if (IS_ERR(wiz->p0_mac_src_sel[i])) {
+ dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_mac_src_sel[i]);
+ }
+
+ wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);
+ if (IS_ERR(wiz->p0_rxfclk_sel[i])) {
+ dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_rxfclk_sel[i]);
+ }
+
+ wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);
+ if (IS_ERR(wiz->p0_refclk_sel[i])) {
+ dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i);
+ return PTR_ERR(wiz->p0_refclk_sel[i]);
+ }
+
wiz->p_mac_div_sel0[i] =
devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
if (IS_ERR(wiz->p_mac_div_sel0[i])) {
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/7] dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros, Rob Herring
Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div"
as deprecated. The clock muxes are provided by the device driver
so not required in device tree.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index dcd63908aeae..3127bb648427 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -83,6 +83,7 @@ properties:
WIZ node should have subnode for refclk_dig to select the reference
clock source for the reference clock used in the PHY and PMA digital
logic.
+ deprecated: true
properties:
clocks:
minItems: 2
@@ -111,6 +112,7 @@ patternProperties:
description: |
WIZ node should have subnodes for each of the PLLs present in
the SERDES.
+ deprecated: true
properties:
clocks:
maxItems: 2
@@ -136,6 +138,7 @@ patternProperties:
description:
WIZ node should have subnodes for each of the PMA common refclock
provided by the SERDES.
+ deprecated: true
properties:
clocks:
maxItems: 1
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 4/7] dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros, Rob Herring
Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div"
as deprecated. The clock muxes are provided by the device driver
so not required in device tree.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index dcd63908aeae..3127bb648427 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -83,6 +83,7 @@ properties:
WIZ node should have subnode for refclk_dig to select the reference
clock source for the reference clock used in the PHY and PMA digital
logic.
+ deprecated: true
properties:
clocks:
minItems: 2
@@ -111,6 +112,7 @@ patternProperties:
description: |
WIZ node should have subnodes for each of the PLLs present in
the SERDES.
+ deprecated: true
properties:
clocks:
maxItems: 2
@@ -136,6 +138,7 @@ patternProperties:
description:
WIZ node should have subnodes for each of the PMA common refclock
provided by the SERDES.
+ deprecated: true
properties:
clocks:
maxItems: 1
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros, Rob Herring
ti,j7200-wiz-10g supports an additional reference clock.
Add compatible and the additional clock.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
.../bindings/phy/ti,phy-j721e-wiz.yaml | 21 ++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 3127bb648427..8305654b66c9 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -16,19 +16,23 @@ properties:
- ti,j721e-wiz-16g
- ti,j721e-wiz-10g
- ti,am64-wiz-10g
+ - ti,j7200-wiz-10g
power-domains:
maxItems: 1
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
description: clock-specifier to represent input to the WIZ
clock-names:
+ minItems: 3
items:
- const: fck
- const: core_ref_clk
- const: ext_ref_clk
+ - const: core_ref1_clk
num-lanes:
minimum: 1
@@ -106,6 +110,11 @@ properties:
- assigned-clocks
- assigned-clock-parents
+ ti,scm:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to System Control Module for syscon regmap access.
+
patternProperties:
"^pll[0|1]-refclk$":
type: object
@@ -173,6 +182,16 @@ required:
- "#reset-cells"
- ranges
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j7200-wiz-10g
+ then:
+ required:
+ - ti,scm
+
additionalProperties: false
examples:
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros, Rob Herring
ti,j7200-wiz-10g supports an additional reference clock.
Add compatible and the additional clock.
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
.../bindings/phy/ti,phy-j721e-wiz.yaml | 21 ++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 3127bb648427..8305654b66c9 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -16,19 +16,23 @@ properties:
- ti,j721e-wiz-16g
- ti,j721e-wiz-10g
- ti,am64-wiz-10g
+ - ti,j7200-wiz-10g
power-domains:
maxItems: 1
clocks:
- maxItems: 3
+ minItems: 3
+ maxItems: 4
description: clock-specifier to represent input to the WIZ
clock-names:
+ minItems: 3
items:
- const: fck
- const: core_ref_clk
- const: ext_ref_clk
+ - const: core_ref1_clk
num-lanes:
minimum: 1
@@ -106,6 +110,11 @@ properties:
- assigned-clocks
- assigned-clock-parents
+ ti,scm:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ phandle to System Control Module for syscon regmap access.
+
patternProperties:
"^pll[0|1]-refclk$":
type: object
@@ -173,6 +182,16 @@ required:
- "#reset-cells"
- ranges
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,j7200-wiz-10g
+ then:
+ required:
+ - ti,scm
+
additionalProperties: false
examples:
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/7] phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
j7200-wiz-10g supports 2 reference clocks. However, the
control bits for these clocks is in a separate register that
sits in the System Control register space. Handle that register.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 138 ++++++++++++++++++++++++++++++---
1 file changed, 129 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 77accea6ec2f..cc2ab5152f07 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -15,6 +15,7 @@
#include <linux/gpio/consumer.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/mfd/syscon.h>
#include <linux/mux/consumer.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
@@ -23,6 +24,10 @@
#include <linux/regmap.h>
#include <linux/reset-controller.h>
+/* SCM offsets */
+#define SERDES_SUP_CTRL 0x4400
+
+/* SERDES offsets */
#define WIZ_SERDES_CTRL 0x404
#define WIZ_SERDES_TOP_CTRL 0x408
#define WIZ_SERDES_RST 0x40c
@@ -85,6 +90,18 @@ static const struct reg_field pma_cmn_refclk_dig_div =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
static const struct reg_field pma_cmn_refclk1_dig_div =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
+
+static const struct reg_field sup_pll0_refclk_mux_sel =
+ REG_FIELD(SERDES_SUP_CTRL, 0, 1);
+static const struct reg_field sup_pll1_refclk_mux_sel =
+ REG_FIELD(SERDES_SUP_CTRL, 2, 3);
+static const struct reg_field sup_pma_cmn_refclk1_int_mode =
+ REG_FIELD(SERDES_SUP_CTRL, 4, 5);
+static const struct reg_field sup_refclk_dig_sel_10g =
+ REG_FIELD(SERDES_SUP_CTRL, 6, 7);
+static const struct reg_field sup_legacy_clk_override =
+ REG_FIELD(SERDES_SUP_CTRL, 8, 8);
+
static const char * const output_clk_names[] = {
[TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
[TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
@@ -248,6 +265,27 @@ static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
},
};
+static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll0-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll1-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "refclk-dig",
+ },
+};
+
static const struct clk_div_table clk_div_table[] = {
{ .val = 0, .div = 1, },
{ .val = 1, .div = 2, },
@@ -269,14 +307,18 @@ static const struct wiz_clk_div_sel clk_div_sel[] = {
enum wiz_type {
J721E_WIZ_16G,
- J721E_WIZ_10G,
+ J721E_WIZ_10G, /* Also for J7200 SR1.0 */
AM64_WIZ_10G,
+ J7200_WIZ_10G, /* J7200 SR2.0 */
};
struct wiz_data {
enum wiz_type type;
+ const struct reg_field *pll0_refclk_mux_sel;
+ const struct reg_field *pll1_refclk_mux_sel;
const struct reg_field *refclk_dig_sel;
const struct reg_field *pma_cmn_refclk1_dig_div;
+ const struct reg_field *pma_cmn_refclk1_int_mode;
const struct wiz_clk_mux_sel *clk_mux_sel;
unsigned int clk_div_sel_num;
};
@@ -286,6 +328,7 @@ struct wiz_data {
struct wiz {
struct regmap *regmap;
+ struct regmap *scm_regmap;
enum wiz_type type;
const struct wiz_clk_mux_sel *clk_mux_sel;
const struct wiz_clk_div_sel *clk_div_sel;
@@ -304,12 +347,14 @@ struct wiz {
struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
+ struct regmap_field *pma_cmn_refclk1_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
struct regmap_field *pma_cmn_refclk1_dig_div;
struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
struct regmap_field *typec_ln10_swap;
+ struct regmap_field *sup_legacy_clk_override;
struct device *dev;
u32 num_lanes;
@@ -448,6 +493,7 @@ static int wiz_init(struct wiz *wiz)
static int wiz_regfield_init(struct wiz *wiz)
{
struct regmap *regmap = wiz->regmap;
+ struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */
int num_lanes = wiz->num_lanes;
struct device *dev = wiz->dev;
const struct wiz_data *data = wiz->data;
@@ -497,27 +543,46 @@ static int wiz_regfield_init(struct wiz *wiz)
}
}
+ if (wiz->scm_regmap) {
+ scm_regmap = wiz->scm_regmap;
+ wiz->sup_legacy_clk_override =
+ devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override);
+ if (IS_ERR(wiz->sup_legacy_clk_override)) {
+ dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n");
+ return PTR_ERR(wiz->sup_legacy_clk_override);
+ }
+ }
+
wiz->mux_sel_field[PLL0_REFCLK] =
- devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
+ devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
}
wiz->mux_sel_field[PLL1_REFCLK] =
- devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
+ devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
}
- wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap,
+ wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,
*data->refclk_dig_sel);
if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
}
+ if (data->pma_cmn_refclk1_int_mode) {
+ wiz->pma_cmn_refclk1_int_mode =
+ devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode);
+ if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
+ dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
+ return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
+ }
+ }
+
for (i = 0; i < num_lanes; i++) {
wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
p_enable[i]);
@@ -906,9 +971,13 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
struct device_node *clk_node;
int i;
- if (wiz->type == AM64_WIZ_10G) {
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ case J7200_WIZ_10G:
of_clk_del_provider(dev->of_node);
return;
+ default:
+ break;
}
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
@@ -935,9 +1004,6 @@ static int wiz_clock_register(struct wiz *wiz)
int ret;
int i;
- if (wiz->type != AM64_WIZ_10G)
- return 0;
-
clk_index = TI_WIZ_PLL0_REFCLK;
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
@@ -987,6 +1053,22 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
+ if (wiz->data->pma_cmn_refclk1_int_mode) {
+ clk = devm_clk_get(dev, "core_ref1_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "core_ref1_clk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+
+ rate = clk_get_rate(clk);
+ if (rate >= 100000000)
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
+ else
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
+ }
+
clk = devm_clk_get(dev, "ext_ref_clk");
if (IS_ERR(clk)) {
dev_err(dev, "ext_ref_clk clock not found\n");
@@ -1001,11 +1083,15 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
- if (wiz->type == AM64_WIZ_10G) {
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ case J7200_WIZ_10G:
ret = wiz_clock_register(wiz);
if (ret)
dev_err(dev, "Failed to register wiz clocks\n");
return ret;
+ default:
+ break;
}
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
@@ -1081,6 +1167,7 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
break;
case J721E_WIZ_10G:
+ case J7200_WIZ_10G:
if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
break;
@@ -1139,6 +1226,8 @@ static const struct regmap_config wiz_regmap_config = {
static struct wiz_data j721e_16g_data = {
.type = J721E_WIZ_16G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_16g,
.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
.clk_mux_sel = clk_mux_sel_16g,
@@ -1147,6 +1236,8 @@ static struct wiz_data j721e_16g_data = {
static struct wiz_data j721e_10g_data = {
.type = J721E_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_10g,
.clk_mux_sel = clk_mux_sel_10g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
@@ -1154,11 +1245,23 @@ static struct wiz_data j721e_10g_data = {
static struct wiz_data am64_10g_data = {
.type = AM64_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_10g,
.clk_mux_sel = clk_mux_sel_10g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j7200_pg2_10g_data = {
+ .type = J7200_WIZ_10G,
+ .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel,
+ .refclk_dig_sel = &sup_refclk_dig_sel_10g,
+ .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode,
+ .clk_mux_sel = clk_mux_sel_10g_2_refclk,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
@@ -1169,6 +1272,9 @@ static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
},
+ {
+ .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, wiz_id_table);
@@ -1266,6 +1372,16 @@ static int wiz_probe(struct platform_device *pdev)
goto err_addr_to_resource;
}
+ wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");
+ if (IS_ERR(wiz->scm_regmap)) {
+ if (wiz->type == J7200_WIZ_10G) {
+ dev_err(dev, "Couldn't get ti,scm regmap\n");
+ return -ENODEV;
+ }
+
+ wiz->scm_regmap = NULL;
+ }
+
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
if (ret) {
dev_err(dev, "Failed to read num-lanes property\n");
@@ -1327,6 +1443,10 @@ static int wiz_probe(struct platform_device *pdev)
goto err_addr_to_resource;
}
+ /* Enable supplemental Control override if available */
+ if (wiz->scm_regmap)
+ regmap_field_write(wiz->sup_legacy_clk_override, 1);
+
phy_reset_dev = &wiz->wiz_phy_reset_dev;
phy_reset_dev->dev = dev;
phy_reset_dev->ops = &wiz_phy_reset_ops,
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 6/7] phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
j7200-wiz-10g supports 2 reference clocks. However, the
control bits for these clocks is in a separate register that
sits in the System Control register space. Handle that register.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 138 ++++++++++++++++++++++++++++++---
1 file changed, 129 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 77accea6ec2f..cc2ab5152f07 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -15,6 +15,7 @@
#include <linux/gpio/consumer.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/mfd/syscon.h>
#include <linux/mux/consumer.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
@@ -23,6 +24,10 @@
#include <linux/regmap.h>
#include <linux/reset-controller.h>
+/* SCM offsets */
+#define SERDES_SUP_CTRL 0x4400
+
+/* SERDES offsets */
#define WIZ_SERDES_CTRL 0x404
#define WIZ_SERDES_TOP_CTRL 0x408
#define WIZ_SERDES_RST 0x40c
@@ -85,6 +90,18 @@ static const struct reg_field pma_cmn_refclk_dig_div =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
static const struct reg_field pma_cmn_refclk1_dig_div =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
+
+static const struct reg_field sup_pll0_refclk_mux_sel =
+ REG_FIELD(SERDES_SUP_CTRL, 0, 1);
+static const struct reg_field sup_pll1_refclk_mux_sel =
+ REG_FIELD(SERDES_SUP_CTRL, 2, 3);
+static const struct reg_field sup_pma_cmn_refclk1_int_mode =
+ REG_FIELD(SERDES_SUP_CTRL, 4, 5);
+static const struct reg_field sup_refclk_dig_sel_10g =
+ REG_FIELD(SERDES_SUP_CTRL, 6, 7);
+static const struct reg_field sup_legacy_clk_override =
+ REG_FIELD(SERDES_SUP_CTRL, 8, 8);
+
static const char * const output_clk_names[] = {
[TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
[TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
@@ -248,6 +265,27 @@ static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
},
};
+static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll0-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "pll1-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
+ .table = { 2, 3, 0 },
+ .node_name = "refclk-dig",
+ },
+};
+
static const struct clk_div_table clk_div_table[] = {
{ .val = 0, .div = 1, },
{ .val = 1, .div = 2, },
@@ -269,14 +307,18 @@ static const struct wiz_clk_div_sel clk_div_sel[] = {
enum wiz_type {
J721E_WIZ_16G,
- J721E_WIZ_10G,
+ J721E_WIZ_10G, /* Also for J7200 SR1.0 */
AM64_WIZ_10G,
+ J7200_WIZ_10G, /* J7200 SR2.0 */
};
struct wiz_data {
enum wiz_type type;
+ const struct reg_field *pll0_refclk_mux_sel;
+ const struct reg_field *pll1_refclk_mux_sel;
const struct reg_field *refclk_dig_sel;
const struct reg_field *pma_cmn_refclk1_dig_div;
+ const struct reg_field *pma_cmn_refclk1_int_mode;
const struct wiz_clk_mux_sel *clk_mux_sel;
unsigned int clk_div_sel_num;
};
@@ -286,6 +328,7 @@ struct wiz_data {
struct wiz {
struct regmap *regmap;
+ struct regmap *scm_regmap;
enum wiz_type type;
const struct wiz_clk_mux_sel *clk_mux_sel;
const struct wiz_clk_div_sel *clk_div_sel;
@@ -304,12 +347,14 @@ struct wiz {
struct regmap_field *p0_rxfclk_sel[WIZ_MAX_LANES];
struct regmap_field *p0_refclk_sel[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
+ struct regmap_field *pma_cmn_refclk1_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
struct regmap_field *pma_cmn_refclk1_dig_div;
struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
struct regmap_field *typec_ln10_swap;
+ struct regmap_field *sup_legacy_clk_override;
struct device *dev;
u32 num_lanes;
@@ -448,6 +493,7 @@ static int wiz_init(struct wiz *wiz)
static int wiz_regfield_init(struct wiz *wiz)
{
struct regmap *regmap = wiz->regmap;
+ struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */
int num_lanes = wiz->num_lanes;
struct device *dev = wiz->dev;
const struct wiz_data *data = wiz->data;
@@ -497,27 +543,46 @@ static int wiz_regfield_init(struct wiz *wiz)
}
}
+ if (wiz->scm_regmap) {
+ scm_regmap = wiz->scm_regmap;
+ wiz->sup_legacy_clk_override =
+ devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override);
+ if (IS_ERR(wiz->sup_legacy_clk_override)) {
+ dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n");
+ return PTR_ERR(wiz->sup_legacy_clk_override);
+ }
+ }
+
wiz->mux_sel_field[PLL0_REFCLK] =
- devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
+ devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
}
wiz->mux_sel_field[PLL1_REFCLK] =
- devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
+ devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
}
- wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, regmap,
+ wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,
*data->refclk_dig_sel);
if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
}
+ if (data->pma_cmn_refclk1_int_mode) {
+ wiz->pma_cmn_refclk1_int_mode =
+ devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode);
+ if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
+ dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
+ return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
+ }
+ }
+
for (i = 0; i < num_lanes; i++) {
wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
p_enable[i]);
@@ -906,9 +971,13 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
struct device_node *clk_node;
int i;
- if (wiz->type == AM64_WIZ_10G) {
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ case J7200_WIZ_10G:
of_clk_del_provider(dev->of_node);
return;
+ default:
+ break;
}
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
@@ -935,9 +1004,6 @@ static int wiz_clock_register(struct wiz *wiz)
int ret;
int i;
- if (wiz->type != AM64_WIZ_10G)
- return 0;
-
clk_index = TI_WIZ_PLL0_REFCLK;
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
@@ -987,6 +1053,22 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
+ if (wiz->data->pma_cmn_refclk1_int_mode) {
+ clk = devm_clk_get(dev, "core_ref1_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "core_ref1_clk clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
+
+ rate = clk_get_rate(clk);
+ if (rate >= 100000000)
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
+ else
+ regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
+ }
+
clk = devm_clk_get(dev, "ext_ref_clk");
if (IS_ERR(clk)) {
dev_err(dev, "ext_ref_clk clock not found\n");
@@ -1001,11 +1083,15 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
- if (wiz->type == AM64_WIZ_10G) {
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ case J7200_WIZ_10G:
ret = wiz_clock_register(wiz);
if (ret)
dev_err(dev, "Failed to register wiz clocks\n");
return ret;
+ default:
+ break;
}
for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
@@ -1081,6 +1167,7 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
break;
case J721E_WIZ_10G:
+ case J7200_WIZ_10G:
if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
break;
@@ -1139,6 +1226,8 @@ static const struct regmap_config wiz_regmap_config = {
static struct wiz_data j721e_16g_data = {
.type = J721E_WIZ_16G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_16g,
.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
.clk_mux_sel = clk_mux_sel_16g,
@@ -1147,6 +1236,8 @@ static struct wiz_data j721e_16g_data = {
static struct wiz_data j721e_10g_data = {
.type = J721E_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_10g,
.clk_mux_sel = clk_mux_sel_10g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
@@ -1154,11 +1245,23 @@ static struct wiz_data j721e_10g_data = {
static struct wiz_data am64_10g_data = {
.type = AM64_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
.refclk_dig_sel = &refclk_dig_sel_10g,
.clk_mux_sel = clk_mux_sel_10g,
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j7200_pg2_10g_data = {
+ .type = J7200_WIZ_10G,
+ .pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel,
+ .refclk_dig_sel = &sup_refclk_dig_sel_10g,
+ .pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode,
+ .clk_mux_sel = clk_mux_sel_10g_2_refclk,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
@@ -1169,6 +1272,9 @@ static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
},
+ {
+ .compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
+ },
{}
};
MODULE_DEVICE_TABLE(of, wiz_id_table);
@@ -1266,6 +1372,16 @@ static int wiz_probe(struct platform_device *pdev)
goto err_addr_to_resource;
}
+ wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");
+ if (IS_ERR(wiz->scm_regmap)) {
+ if (wiz->type == J7200_WIZ_10G) {
+ dev_err(dev, "Couldn't get ti,scm regmap\n");
+ return -ENODEV;
+ }
+
+ wiz->scm_regmap = NULL;
+ }
+
ret = of_property_read_u32(node, "num-lanes", &num_lanes);
if (ret) {
dev_err(dev, "Failed to read num-lanes property\n");
@@ -1327,6 +1443,10 @@ static int wiz_probe(struct platform_device *pdev)
goto err_addr_to_resource;
}
+ /* Enable supplemental Control override if available */
+ if (wiz->scm_regmap)
+ regmap_field_write(wiz->sup_legacy_clk_override, 1);
+
phy_reset_dev = &wiz->wiz_phy_reset_dev;
phy_reset_dev->dev = dev;
phy_reset_dev->ops = &wiz_phy_reset_ops,
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/7] phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate
2022-06-28 12:22 ` Roger Quadros
@ 2022-06-28 12:22 ` Roger Quadros
-1 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
For J7200-SR2.0 and AM64 we don't model Common refclock divider as
a clock divider as the divisor rate is fixed based on operating
reference clock frequency. We just program the recommended value
into the register. This simplifies the device tree and implementation
a lot.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index cc2ab5152f07..20af142580ad 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -24,6 +24,11 @@
#include <linux/regmap.h>
#include <linux/reset-controller.h>
+#define REF_CLK_19_2MHZ 19200000
+#define REF_CLK_25MHZ 25000000
+#define REF_CLK_100MHZ 100000000
+#define REF_CLK_156_25MHZ 156250000
+
/* SCM offsets */
#define SERDES_SUP_CTRL 0x4400
@@ -1053,6 +1058,25 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ case J7200_WIZ_10G:
+ switch (rate) {
+ case REF_CLK_100MHZ:
+ regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);
+ break;
+ case REF_CLK_156_25MHZ:
+ regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);
+ break;
+ default:
+ regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
if (wiz->data->pma_cmn_refclk1_int_mode) {
clk = devm_clk_get(dev, "core_ref1_clk");
if (IS_ERR(clk)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PATCH 7/7] phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate
@ 2022-06-28 12:22 ` Roger Quadros
0 siblings, 0 replies; 24+ messages in thread
From: Roger Quadros @ 2022-06-28 12:22 UTC (permalink / raw)
To: kishon, vkoul
Cc: vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree, Roger Quadros
For J7200-SR2.0 and AM64 we don't model Common refclock divider as
a clock divider as the divisor rate is fixed based on operating
reference clock frequency. We just program the recommended value
into the register. This simplifies the device tree and implementation
a lot.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index cc2ab5152f07..20af142580ad 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -24,6 +24,11 @@
#include <linux/regmap.h>
#include <linux/reset-controller.h>
+#define REF_CLK_19_2MHZ 19200000
+#define REF_CLK_25MHZ 25000000
+#define REF_CLK_100MHZ 100000000
+#define REF_CLK_156_25MHZ 156250000
+
/* SCM offsets */
#define SERDES_SUP_CTRL 0x4400
@@ -1053,6 +1058,25 @@ static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
else
regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
+ switch (wiz->type) {
+ case AM64_WIZ_10G:
+ case J7200_WIZ_10G:
+ switch (rate) {
+ case REF_CLK_100MHZ:
+ regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);
+ break;
+ case REF_CLK_156_25MHZ:
+ regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);
+ break;
+ default:
+ regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
if (wiz->data->pma_cmn_refclk1_int_mode) {
clk = devm_clk_get(dev, "core_ref1_clk");
if (IS_ERR(clk)) {
--
2.17.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: Add PHY_TYPE_USXGMII definition
2022-06-28 12:22 ` Roger Quadros
@ 2022-07-01 16:17 ` Rob Herring
-1 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2022-07-01 16:17 UTC (permalink / raw)
To: Roger Quadros
Cc: vkoul, vigneshr, linux-phy, sjakhade, kishon, linux-kernel,
t-patil, s-vadapalli, devicetree
On Tue, 28 Jun 2022 15:22:50 +0300, Roger Quadros wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add definition for USXGMII phy type.
>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> include/dt-bindings/phy/phy.h | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/7] dt-bindings: phy: Add PHY_TYPE_USXGMII definition
@ 2022-07-01 16:17 ` Rob Herring
0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2022-07-01 16:17 UTC (permalink / raw)
To: Roger Quadros
Cc: vkoul, vigneshr, linux-phy, sjakhade, kishon, linux-kernel,
t-patil, s-vadapalli, devicetree
On Tue, 28 Jun 2022 15:22:50 +0300, Roger Quadros wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add definition for USXGMII phy type.
>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> include/dt-bindings/phy/phy.h | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
2022-06-28 12:22 ` Roger Quadros
@ 2022-07-01 16:18 ` Rob Herring
-1 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2022-07-01 16:18 UTC (permalink / raw)
To: Roger Quadros
Cc: sjakhade, vigneshr, kishon, linux-phy, s-vadapalli, devicetree,
linux-kernel, vkoul, t-patil
On Tue, 28 Jun 2022 15:22:52 +0300, Roger Quadros wrote:
> Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div"
> as deprecated. The clock muxes are provided by the device driver
> so not required in device tree.
>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 4/7] dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes
@ 2022-07-01 16:18 ` Rob Herring
0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2022-07-01 16:18 UTC (permalink / raw)
To: Roger Quadros
Cc: sjakhade, vigneshr, kishon, linux-phy, s-vadapalli, devicetree,
linux-kernel, vkoul, t-patil
On Tue, 28 Jun 2022 15:22:52 +0300, Roger Quadros wrote:
> Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div"
> as deprecated. The clock muxes are provided by the device driver
> so not required in device tree.
>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
2022-06-28 12:22 ` Roger Quadros
@ 2022-07-01 16:19 ` Rob Herring
-1 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2022-07-01 16:19 UTC (permalink / raw)
To: Roger Quadros
Cc: t-patil, s-vadapalli, devicetree, linux-phy, vigneshr, kishon,
linux-kernel, sjakhade, vkoul
On Tue, 28 Jun 2022 15:22:53 +0300, Roger Quadros wrote:
> ti,j7200-wiz-10g supports an additional reference clock.
> Add compatible and the additional clock.
>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> .../bindings/phy/ti,phy-j721e-wiz.yaml | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g
@ 2022-07-01 16:19 ` Rob Herring
0 siblings, 0 replies; 24+ messages in thread
From: Rob Herring @ 2022-07-01 16:19 UTC (permalink / raw)
To: Roger Quadros
Cc: t-patil, s-vadapalli, devicetree, linux-phy, vigneshr, kishon,
linux-kernel, sjakhade, vkoul
On Tue, 28 Jun 2022 15:22:53 +0300, Roger Quadros wrote:
> ti,j7200-wiz-10g supports an additional reference clock.
> Add compatible and the additional clock.
>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Roger Quadros <rogerq@kernel.org>
> ---
> .../bindings/phy/ti,phy-j721e-wiz.yaml | 21 ++++++++++++++++++-
> 1 file changed, 20 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g
2022-06-28 12:22 ` Roger Quadros
@ 2022-08-30 5:13 ` Vinod Koul
-1 siblings, 0 replies; 24+ messages in thread
From: Vinod Koul @ 2022-08-30 5:13 UTC (permalink / raw)
To: Roger Quadros
Cc: kishon, vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree
On 28-06-22, 15:22, Roger Quadros wrote:
> Hi,
>
> The SERDES in J7200 SR2.0 supports 2 reference clocks.
> The second reference clock (core_ref1_clk) is hardwired to
> MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).
>
> Add a new compatible "j7200-wiz-10g" for this device.
>
> The external clocks to SERDES PLL refclock mapping is now
> controlled by a special register in System Control Module
> (SCM) space. Add a property "ti,scm" to reference it and
> configure it in the driver.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g
@ 2022-08-30 5:13 ` Vinod Koul
0 siblings, 0 replies; 24+ messages in thread
From: Vinod Koul @ 2022-08-30 5:13 UTC (permalink / raw)
To: Roger Quadros
Cc: kishon, vigneshr, t-patil, sjakhade, s-vadapalli, linux-phy,
linux-kernel, devicetree
On 28-06-22, 15:22, Roger Quadros wrote:
> Hi,
>
> The SERDES in J7200 SR2.0 supports 2 reference clocks.
> The second reference clock (core_ref1_clk) is hardwired to
> MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz).
>
> Add a new compatible "j7200-wiz-10g" for this device.
>
> The external clocks to SERDES PLL refclock mapping is now
> controlled by a special register in System Control Module
> (SCM) space. Add a property "ti,scm" to reference it and
> configure it in the driver.
Applied, thanks
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2022-08-30 5:13 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-28 12:22 [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-06-28 12:22 ` [PATCH 1/7] phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200 Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-06-28 12:22 ` [PATCH 2/7] dt-bindings: phy: Add PHY_TYPE_USXGMII definition Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-07-01 16:17 ` Rob Herring
2022-07-01 16:17 ` Rob Herring
2022-06-28 12:22 ` [PATCH 3/7] phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-06-28 12:22 ` [PATCH 4/7] dt-bindings: phy: ti,phy-j721e-wiz: deprecate clock MUX nodes Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-07-01 16:18 ` Rob Herring
2022-07-01 16:18 ` Rob Herring
2022-06-28 12:22 ` [PATCH 5/7] dt-bindings: phy: ti,phy-j721e-wiz: Add support for ti,j7200-wiz-10g Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-07-01 16:19 ` Rob Herring
2022-07-01 16:19 ` Rob Herring
2022-06-28 12:22 ` [PATCH 6/7] phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-06-28 12:22 ` [PATCH 7/7] phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate Roger Quadros
2022-06-28 12:22 ` Roger Quadros
2022-08-30 5:13 ` [PATCH 0/7] phy: ti: phy-j721e-wiz: Add support for j7200-wiz-10g Vinod Koul
2022-08-30 5:13 ` Vinod Koul
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