[PATCH 0/2] Add CAN support

[PATCH 0/2] Add CAN support

[Biju Das]

This patch series supports CAN{0,1} populated on RZ/N1D-DB board.

Biju Das (2):
  ARM: dts: r9a06g032: Add CAN nodes
  ARM: dts: r9a06g032-rzn1d400-db: Enable CAN{0,1}

 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 26 +++++++++++++++++++++
 arch/arm/boot/dts/r9a06g032.dtsi            | 18 ++++++++++++++
 2 files changed, 44 insertions(+)

-- 
2.25.1

[PATCH 1/2] ARM: dts: r9a06g032: Add CAN{0,1} nodes

[Biju Das]

Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 5b97fa85474f..48c936cf7be5 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -423,6 +423,24 @@ gic: interrupt-controller@44101000 {
 			interrupts =
 				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
+
+		can0: can@52104000 {
+			compatible = "nxp,sja1000";
+			reg = <0x52104000 0x800>;
+			reg-io-width = <4>;
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
+			status = "disabled";
+		};
+
+		can1: can@52105000 {
+			compatible = "nxp,sja1000";
+			reg = <0x52105000 0x800>;
+			reg-io-width = <4>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
+			status = "disabled";
+		};
 	};
 
 	timer {
-- 
2.25.1

[PATCH 2/2] ARM: dts: r9a06g032-rzn1d400-db: Enable CAN{0,1}

[Biju Das]

Enable CAN{0,1} on RZ/N1D-DB board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 26 +++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
index 4bf813335e21..49104c73eca3 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -26,6 +26,20 @@ aliases {
 	};
 };
 
+&can0 {
+	pinctrl-0 = <&pins_can0>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&can1 {
+	pinctrl-0 = <&pins_can1>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
 &eth_miic {
 	status = "okay";
 	renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
@@ -52,6 +66,18 @@ &mii_conv5 {
 };
 
 &pinctrl{
+	pins_can0: pins_can0 {
+		pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>,	/* CAN0_TXD */
+			 <RZN1_PINMUX(163, RZN1_FUNC_CAN)>;	/* CAN0_RXD */
+		drive-strength = <6>;
+	};
+
+	pins_can1: pins_can1 {
+		pinmux = <RZN1_PINMUX(109, RZN1_FUNC_CAN)>,	/* CAN1_TXD */
+			 <RZN1_PINMUX(110, RZN1_FUNC_CAN)>;	/* CAN1_RXD */
+		drive-strength = <6>;
+	};
+
 	pins_eth3: pins_eth3 {
 		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
 			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
-- 
2.25.1

Re: [PATCH 1/2] ARM: dts: r9a06g032: Add CAN{0,1} nodes

[Geert Uytterhoeven]

Hi Biju,

On Fri, Jul 1, 2022 at 6:23 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm/boot/dts/r9a06g032.dtsi
> +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> @@ -423,6 +423,24 @@ gic: interrupt-controller@44101000 {
>                         interrupts =
>                                 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
>                 };
> +
> +               can0: can@52104000 {
> +                       compatible = "nxp,sja1000";

Is this block 100% compatible to the nxp,sja1000 block, or do we
need an SoC-specific compatible value?

> +                       reg = <0x52104000 0x800>;
> +                       reg-io-width = <4>;
> +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&sysctrl R9A06G032_HCLK_CAN0>;

According to the (old) bindings, the clock rate is specified using the
non-standard "nxp,external-clock-frequency property" (seems like both
bindings and driver can use some overhaul), and defaults to 16 MHz.
According to the RZ/N1S documentation, the CAN clock is 48 MHz?

> +                       status = "disabled";
> +               };
> +
> +               can1: can@52105000 {
> +                       compatible = "nxp,sja1000";
> +                       reg = <0x52105000 0x800>;
> +                       reg-io-width = <4>;
> +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
> +                       status = "disabled";
> +               };
>         };

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 1/2] ARM: dts: r9a06g032: Add CAN{0,1} nodes

[Biju Das]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH 1/2] ARM: dts: r9a06g032: Add CAN{0,1} nodes
> 
> Hi Biju,
> 
> On Fri, Jul 1, 2022 at 6:23 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add CAN{0,1} nodes to R9A06G032 (RZ/N1) SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm/boot/dts/r9a06g032.dtsi
> > +++ b/arch/arm/boot/dts/r9a06g032.dtsi
> > @@ -423,6 +423,24 @@ gic: interrupt-controller@44101000 {
> >                         interrupts =
> >                                 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
> IRQ_TYPE_LEVEL_HIGH)>;
> >                 };
> > +
> > +               can0: can@52104000 {
> > +                       compatible = "nxp,sja1000";
> 
> Is this block 100% compatible to the nxp,sja1000 block, or do we need an
> SoC-specific compatible value?

You are right, We need Renesas SoC specific compatible value to accommodate the below features

1) No clock divider register (CDR) support.
2) No HW loopback(HW doesn't see tx messages on rx).
3) We can use the clk to get the rate  

> 
> > +                       reg = <0x52104000 0x800>;
> > +                       reg-io-width = <4>;
> > +                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
> 
> According to the (old) bindings, the clock rate is specified using the
> non-standard "nxp,external-clock-frequency property" (seems like both
> bindings and driver can use some overhaul), and defaults to 16 MHz.
> According to the RZ/N1S documentation, the CAN clock is 48 MHz?

Same for RZ/N1D. May be using SoC specific compatible as suggested above, we can use the get rate to get the clock similar to [1]?? Or set default of 48MHz for Renesas SoC?? 

[1] https://github.com/renesas-rz/rzn1_linux/commit/88817d783658bdf6cccfc1a6e8ad414ad7a7c177

Cheers,
Biju

> 
> > +                       status = "disabled";
> > +               };
> > +
> > +               can1: can@52105000 {
> > +                       compatible = "nxp,sja1000";
> > +                       reg = <0x52105000 0x800>;
> > +                       reg-io-width = <4>;
> > +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
> > +                       status = "disabled";
> > +               };
> >         };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds