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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
	Atish Patra <atishp@rivosinc.com>,
	Bin Meng <bin.meng@windriver.com>
Subject: [PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints
Date: Sun,  3 Jul 2022 10:12:31 +1000	[thread overview]
Message-ID: <20220703001234.439716-17-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220703001234.439716-1-alistair.francis@opensource.wdc.com>

From: Alistair Francis <alistair.francis@wdc.com>

We previously stored the device tree at a 16MB alignment from the end of
memory (or 3GB). This means we need at least 16MB of memory to be able
to do this. We don't actually need the FDT to be 16MB aligned, so let's
drop it down to 2MB so that we can support systems with less memory,
while also allowing FDT size expansion.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/992
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <20220608062015.317894-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/boot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2d80f40b31..06b4fc5ac3 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -227,11 +227,11 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
     /*
      * We should put fdt as far as possible to avoid kernel/initrd overwriting
      * its content. But it should be addressable by 32 bit system as well.
-     * Thus, put it at an 16MB aligned address that less than fdt size from the
+     * Thus, put it at an 2MB aligned address that less than fdt size from the
      * end of dram or 3GB whichever is lesser.
      */
     temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end;
-    fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
+    fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
 
     ret = fdt_pack(fdt);
     /* Should only fail if we've built a corrupted tree */
-- 
2.36.1



  parent reply	other threads:[~2022-07-03  0:33 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-03  0:12 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2022-07-03  0:12 ` [PULL v2 01/19] target/riscv: Remove condition guarding register zero for auipc and lui Alistair Francis
2022-07-03  0:12 ` [PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal Alistair Francis
2022-07-03  0:12 ` [PULL v2 03/19] target/riscv: Remove generate_exception_mtval Alistair Francis
2022-07-03  0:12 ` [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc Alistair Francis
2022-07-03  0:12 ` [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size Alistair Francis
2022-07-03  0:12 ` [PULL v2 06/19] target/riscv: Fix PMU CSR predicate function Alistair Francis
2022-07-03  0:12 ` [PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode Alistair Francis
2022-07-03  0:12 ` [PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu Alistair Francis
2022-07-03  0:12 ` [PULL v2 09/19] target/riscv: pmu: Make number of counters configurable Alistair Francis
2022-07-03  0:12 ` [PULL v2 10/19] target/riscv: Implement mcountinhibit CSR Alistair Francis
2022-07-03  0:12 ` [PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents Alistair Francis
2022-07-03  0:12 ` [PULL v2 12/19] target/riscv: Support mcycle/minstret write operation Alistair Francis
2022-07-03  0:12 ` [PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check Alistair Francis
2022-07-03  0:12 ` [PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11 Alistair Francis
2022-07-03  0:12 ` [PULL v2 15/19] target/riscv: Don't force update priv spec version to latest Alistair Francis
2022-07-03  0:12 ` Alistair Francis [this message]
2022-07-03  0:12 ` [PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit Alistair Francis
2022-07-03  0:12 ` [PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits Alistair Francis
2022-07-03  0:12 ` [PULL v2 19/19] target/riscv: Update default priority table for local interrupts Alistair Francis
2022-07-03  4:38 ` [PULL v2 00/19] riscv-to-apply queue Richard Henderson

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