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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
	Richard Henderson <richard.henderson@linaro.org>,
	Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 03/19] target/riscv: Remove generate_exception_mtval
Date: Sun,  3 Jul 2022 10:12:18 +1000	[thread overview]
Message-ID: <20220703001234.439716-4-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220703001234.439716-1-alistair.francis@opensource.wdc.com>

From: Richard Henderson <richard.henderson@linaro.org>

The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/translate.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a10f3f939c..7205a29603 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -230,14 +230,6 @@ static void generate_exception(DisasContext *ctx, int excp)
     ctx->base.is_jmp = DISAS_NORETURN;
 }
 
-static void generate_exception_mtval(DisasContext *ctx, int excp)
-{
-    gen_set_pc_imm(ctx, ctx->base.pc_next);
-    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
-    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
-    ctx->base.is_jmp = DISAS_NORETURN;
-}
-
 static void gen_exception_illegal(DisasContext *ctx)
 {
     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
@@ -247,7 +239,8 @@ static void gen_exception_illegal(DisasContext *ctx)
 
 static void gen_exception_inst_addr_mis(DisasContext *ctx)
 {
-    generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS);
+    tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
+    generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
 }
 
 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
-- 
2.36.1



  parent reply	other threads:[~2022-07-03  0:20 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-03  0:12 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2022-07-03  0:12 ` [PULL v2 01/19] target/riscv: Remove condition guarding register zero for auipc and lui Alistair Francis
2022-07-03  0:12 ` [PULL v2 02/19] target/riscv: Set env->bins in gen_exception_illegal Alistair Francis
2022-07-03  0:12 ` Alistair Francis [this message]
2022-07-03  0:12 ` [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc Alistair Francis
2022-07-03  0:12 ` [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size Alistair Francis
2022-07-03  0:12 ` [PULL v2 06/19] target/riscv: Fix PMU CSR predicate function Alistair Francis
2022-07-03  0:12 ` [PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode Alistair Francis
2022-07-03  0:12 ` [PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu Alistair Francis
2022-07-03  0:12 ` [PULL v2 09/19] target/riscv: pmu: Make number of counters configurable Alistair Francis
2022-07-03  0:12 ` [PULL v2 10/19] target/riscv: Implement mcountinhibit CSR Alistair Francis
2022-07-03  0:12 ` [PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents Alistair Francis
2022-07-03  0:12 ` [PULL v2 12/19] target/riscv: Support mcycle/minstret write operation Alistair Francis
2022-07-03  0:12 ` [PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check Alistair Francis
2022-07-03  0:12 ` [PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11 Alistair Francis
2022-07-03  0:12 ` [PULL v2 15/19] target/riscv: Don't force update priv spec version to latest Alistair Francis
2022-07-03  0:12 ` [PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints Alistair Francis
2022-07-03  0:12 ` [PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit Alistair Francis
2022-07-03  0:12 ` [PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits Alistair Francis
2022-07-03  0:12 ` [PULL v2 19/19] target/riscv: Update default priority table for local interrupts Alistair Francis
2022-07-03  4:38 ` [PULL v2 00/19] riscv-to-apply queue Richard Henderson

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