[PATCH 1/2] hw/i2c/aspeed: Allow machines to set I2CBus

[PATCH 1/2] hw/i2c/aspeed: Allow machines to set I2CBus

[Peter Delevoryas]

In a multi-SoC board, we want to allow machines to construct shared
I2CBus's, so that we can have two SoC I2C controllers attached to a single
I2CBus. We already expose read-only access, this just adds a method for
setting and using an external I2CBus in the Aspeed I2C bus controller.

One issue is that in order to use these methods, the machine needs to reach
into the SoC and call these methods on the I2C controller, and we would
prefer to keep the abstraction at the SoC level. If we create a set of
"aspeed_soc_i2c_get_bus/set_bus" methods though, they will just be
one-liners that don't do anything interesting. I would prefer to avoid that
if possible, because that doesn't seem scalable if we need to do the same
thing for all of the peripherals later.

In addition, we are already reaching into the Aspeed SoC to access the flash
controller to determine the boot rom size, so there is a precedent that we
need to reach into SoC peripherals for data sometimes.

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
---
 hw/i2c/aspeed_i2c.c         | 16 +++++++++++++++-
 include/hw/i2c/aspeed_i2c.h |  1 +
 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index 42c6d69b82..00bf58c7a3 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -1236,7 +1236,12 @@ static void aspeed_i2c_bus_realize(DeviceState *dev, Error **errp)
 
     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
 
-    s->bus = i2c_init_bus(dev, name);
+    /*
+     * If a bus hasn't been provided to the controller, create one from scratch.
+     */
+    if (!s->bus) {
+        s->bus = i2c_init_bus(dev, name);
+    }
     s->slave = i2c_slave_create_simple(s->bus, TYPE_ASPEED_I2C_BUS_SLAVE,
                                        0xff);
 
@@ -1420,3 +1425,12 @@ I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr)
 
     return bus;
 }
+
+void aspeed_i2c_set_bus(AspeedI2CState *s, int busnr, I2CBus *bus)
+{
+    AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(s);
+
+    if (busnr >= 0 && busnr < aic->num_busses) {
+        s->busses[busnr].bus = bus;
+    }
+}
diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h
index 300a89b343..c60f8b291d 100644
--- a/include/hw/i2c/aspeed_i2c.h
+++ b/include/hw/i2c/aspeed_i2c.h
@@ -376,5 +376,6 @@ static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
 }
 
 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
+void aspeed_i2c_set_bus(AspeedI2CState *s, int busnr, I2CBus *bus);
 
 #endif /* ASPEED_I2C_H */
-- 
2.37.0

[PATCH 2/2] fby35: Connect BMC to slot 0 BIC over I2C

[Peter Delevoryas]

Signed-off-by: Peter Delevoryas <peter@pjd.dev>
---
 hw/arm/fby35.c | 24 +++++++++++++++---------
 1 file changed, 15 insertions(+), 9 deletions(-)

diff --git a/hw/arm/fby35.c b/hw/arm/fby35.c
index 1972948318..88923d88eb 100644
--- a/hw/arm/fby35.c
+++ b/hw/arm/fby35.c
@@ -15,6 +15,7 @@
 #include "hw/arm/aspeed_soc.h"
 #include "hw/arm/boot.h"
 #include "hw/arm/fby35.h"
+#include "hw/i2c/i2c.h"
 #include "hw/i2c/i2c_mux_pca954x.h"
 
 #define TYPE_FBY35 MACHINE_TYPE_NAME("fby35")
@@ -83,7 +84,6 @@ static void fby35_bmc_init(Fby35State *s)
     memory_region_init_ram(&s->bmc_dram, OBJECT(s), "bmc-dram",
                            FBY35_BMC_RAM_SIZE, &error_abort);
 
-    object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
     object_property_set_int(OBJECT(&s->bmc), "ram-size", FBY35_BMC_RAM_SIZE,
                             &error_abort);
     object_property_set_link(OBJECT(&s->bmc), "memory", OBJECT(&s->bmc_memory),
@@ -129,7 +129,6 @@ static void fby35_bic_init(Fby35State *s)
 
     memory_region_init(&s->bic_memory, OBJECT(s), "bic-memory", UINT64_MAX);
 
-    object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
     qdev_connect_clock_in(DEVICE(&s->bic), "sysclk", s->bic_sysclk);
     object_property_set_link(OBJECT(&s->bic), "memory", OBJECT(&s->bic_memory),
                              &error_abort);
@@ -167,20 +166,27 @@ void fby35_cl_bic_i2c_init(AspeedSoCState *s)
     for (int i = 0; i < 8; i++) {
         i2c_slave_create_simple(ssd[i], "tmp105", 0x6a);
     }
-
-    /*
-     * FIXME: This should actually be the BMC, but both the ME and the BMC
-     * are IPMB endpoints, and the current ME implementation is generic
-     * enough to respond normally to some things.
-     */
-    i2c_slave_create_simple(i2c[6], "intel-me", 0x10);
 }
 
 static void fby35_init(MachineState *machine)
 {
     Fby35State *s = FBY35(machine);
+    I2CBus *slot_i2c[4];
+
+    object_initialize_child(OBJECT(s), "bmc", &s->bmc, "ast2600-a3");
+    object_initialize_child(OBJECT(s), "bic", &s->bic, "ast1030-a1");
 
     fby35_bmc_init(s);
+
+    for (int i = 0; i < ARRAY_SIZE(slot_i2c); i++) {
+        slot_i2c[i] = aspeed_i2c_get_bus(&s->bmc.i2c, i);
+    }
+
+    /*
+     * There are 4 server board slots in fby35, and the first 4 I2C buses of the
+     * BMC are routed to each server board's BIC.
+     */
+    aspeed_i2c_set_bus(&s->bic.i2c, 6, slot_i2c[0]);
     fby35_bic_init(s);
 }
 
-- 
2.37.0