* [Intel-gfx] [PATCH v5 00/14] GSC support for XeHP SDV and DG2 platforms
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: linux-kernel, Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx
Add GSC support for XeHP SDV and DG2 platforms.
The series includes changes for the mei driver:
- add ability to use polling instead of interrupts
- add ability to use extended timeouts
- setup extended operational memory for GSC
The series includes changes for the i915 driver:
- allocate extended operational memory for GSC
- GSC on XeHP SDV offsets and definitions
Greg KH, please review and ACK the MEI patches.
We are pushing these patches through gfx tree as
the auxiliary device belongs there.
V2: rebase over merged DG1 series and DG2 enablement patch,
fix commit messages
V3: rebase over latest tip
V4: add missed changelog in pxp dbugfs patch
V5: rebase over latest tip
fix changelog in pxp dbugfs patch
put HAX patch last to the ease of merging
Alexander Usyskin (5):
drm/i915/gsc: add slow_fw flag to the mei auxiliary device
drm/i915/gsc: add slow_fw flag to the gsc device definition
drm/i915/gsc: add GSC XeHP SDV platform definition
mei: gsc: wait for reset thread on stop
mei: extend timeouts on slow devices.
Daniele Ceraolo Spurio (1):
HAX: drm/i915: force INTEL_MEI_GSC on for CI
Tomas Winkler (5):
mei: gsc: use polling instead of interrupts
mei: mkhi: add memory ready command
mei: gsc: setup gsc extended operational memory
mei: debugfs: add pxp mode to devstate in debugfs
drm/i915/gsc: allocate extended operational memory in LMEM
Vitaly Lubart (3):
drm/i915/gsc: skip irq initialization if using polling
mei: bus: export common mkhi definitions into a separate header
mei: gsc: add transition to PXP mode in resume flow
drivers/gpu/drm/i915/Kconfig.debug | 1 +
drivers/gpu/drm/i915/gt/intel_gsc.c | 119 +++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
drivers/misc/mei/bus-fixup.c | 105 ++++++++++++++++--------
drivers/misc/mei/client.c | 14 ++--
drivers/misc/mei/debugfs.c | 17 ++++
drivers/misc/mei/gsc-me.c | 77 +++++++++++++++---
drivers/misc/mei/hbm.c | 12 +--
drivers/misc/mei/hw-me-regs.h | 7 ++
drivers/misc/mei/hw-me.c | 116 ++++++++++++++++++++++-----
drivers/misc/mei/hw-me.h | 14 +++-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 ++
drivers/misc/mei/init.c | 21 ++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 26 ++++++
drivers/misc/mei/mkhi.h | 57 +++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
include/linux/mei_aux.h | 2 +
19 files changed, 511 insertions(+), 91 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
--
2.34.1
^ permalink raw reply [flat|nested] 46+ messages in thread* [PATCH v5 01/14] drm/i915/gsc: skip irq initialization if using polling
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
From: Vitaly Lubart <vitaly.lubart@intel.com>
Some platforms require the host to poll on the
GSC registers instead of relaying on the interrupts.
For those platforms, irq initialization should be skipped
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 0e494028b81d..e0236ff1d072 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -40,6 +40,7 @@ struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+ bool use_polling;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -117,6 +118,10 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
}
+ /* skip irq initialization */
+ if (def->use_polling)
+ goto add_device;
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
@@ -129,6 +134,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
goto fail;
}
+add_device:
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
goto fail;
@@ -182,10 +188,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
return;
}
- if (gt->gsc.intf[intf_id].irq < 0) {
- drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set");
+ if (gt->gsc.intf[intf_id].irq < 0)
return;
- }
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
if (ret)
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v5 01/14] drm/i915/gsc: skip irq initialization if using polling
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Some platforms require the host to poll on the
GSC registers instead of relaying on the interrupts.
For those platforms, irq initialization should be skipped
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 0e494028b81d..e0236ff1d072 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -40,6 +40,7 @@ struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+ bool use_polling;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -117,6 +118,10 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
}
+ /* skip irq initialization */
+ if (def->use_polling)
+ goto add_device;
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
@@ -129,6 +134,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
goto fail;
}
+add_device:
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
goto fail;
@@ -182,10 +188,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
return;
}
- if (gt->gsc.intf[intf_id].irq < 0) {
- drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set");
+ if (gt->gsc.intf[intf_id].irq < 0)
return;
- }
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
if (ret)
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v5 02/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
Add slow_fw flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
include/linux/mei_aux.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a29f4064b9c0 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -11,6 +11,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ bool slow_fw;
};
#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v5 02/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
Add slow_fw flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
include/linux/mei_aux.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a29f4064b9c0 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -11,6 +11,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ bool slow_fw;
};
#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [PATCH v5 02/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-07 15:21 ` Rodrigo Vivi
-1 siblings, 0 replies; 46+ messages in thread
From: Rodrigo Vivi @ 2022-07-07 15:21 UTC (permalink / raw)
To: Alexander Usyskin
Cc: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, David Airlie,
Daniel Vetter, Tvrtko Ursulin, Tomas Winkler, Vitaly Lubart,
intel-gfx, linux-kernel, Daniele Ceraolo Spurio
On Wed, Jul 06, 2022 at 02:43:33PM +0300, Alexander Usyskin wrote:
> Add slow_fw flag to the mei auxiliary device info
> to inform the mei driver about slow underlying firmware.
> Such firmware will require to use larger operation timeouts.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> include/linux/mei_aux.h | 1 +
This patch has a wrong subject since it doesn't touch i915.
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
> index 587f25128848..a29f4064b9c0 100644
> --- a/include/linux/mei_aux.h
> +++ b/include/linux/mei_aux.h
> @@ -11,6 +11,7 @@ struct mei_aux_device {
> struct auxiliary_device aux_dev;
> int irq;
> struct resource bar;
> + bool slow_fw;
> };
>
> #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v5 02/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
@ 2022-07-07 15:21 ` Rodrigo Vivi
0 siblings, 0 replies; 46+ messages in thread
From: Rodrigo Vivi @ 2022-07-07 15:21 UTC (permalink / raw)
To: Alexander Usyskin
Cc: David Airlie, Greg Kroah-Hartman, intel-gfx, linux-kernel,
Tomas Winkler, Vitaly Lubart
On Wed, Jul 06, 2022 at 02:43:33PM +0300, Alexander Usyskin wrote:
> Add slow_fw flag to the mei auxiliary device info
> to inform the mei driver about slow underlying firmware.
> Such firmware will require to use larger operation timeouts.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> include/linux/mei_aux.h | 1 +
This patch has a wrong subject since it doesn't touch i915.
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
> index 587f25128848..a29f4064b9c0 100644
> --- a/include/linux/mei_aux.h
> +++ b/include/linux/mei_aux.h
> @@ -11,6 +11,7 @@ struct mei_aux_device {
> struct auxiliary_device aux_dev;
> int irq;
> struct resource bar;
> + bool slow_fw;
> };
>
> #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [PATCH v5 02/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
2022-07-07 15:21 ` [Intel-gfx] " Rodrigo Vivi
@ 2022-07-18 13:47 ` Winkler, Tomas
-1 siblings, 0 replies; 46+ messages in thread
From: Winkler, Tomas @ 2022-07-18 13:47 UTC (permalink / raw)
To: Vivi, Rodrigo, Usyskin, Alexander
Cc: David Airlie, Greg Kroah-Hartman, intel-gfx, linux-kernel,
Lubart, Vitaly
>
> On Wed, Jul 06, 2022 at 02:43:33PM +0300, Alexander Usyskin wrote:
> > Add slow_fw flag to the mei auxiliary device info to inform the mei
> > driver about slow underlying firmware.
> > Such firmware will require to use larger operation timeouts.
> >
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > ---
> > include/linux/mei_aux.h | 1 +
>
> This patch has a wrong subject since it doesn't touch i915.
This is in a shared file between drm and mei, but I can resend.
>
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index
> > 587f25128848..a29f4064b9c0 100644
> > --- a/include/linux/mei_aux.h
> > +++ b/include/linux/mei_aux.h
> > @@ -11,6 +11,7 @@ struct mei_aux_device {
> > struct auxiliary_device aux_dev;
> > int irq;
> > struct resource bar;
> > + bool slow_fw;
> > };
> >
> > #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [PATCH v5 02/14] drm/i915/gsc: add slow_fw flag to the mei auxiliary device
@ 2022-07-18 13:47 ` Winkler, Tomas
0 siblings, 0 replies; 46+ messages in thread
From: Winkler, Tomas @ 2022-07-18 13:47 UTC (permalink / raw)
To: Vivi, Rodrigo, Usyskin, Alexander
Cc: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, David Airlie,
Daniel Vetter, Tvrtko Ursulin, Lubart, Vitaly, intel-gfx,
linux-kernel, Ceraolo Spurio, Daniele
>
> On Wed, Jul 06, 2022 at 02:43:33PM +0300, Alexander Usyskin wrote:
> > Add slow_fw flag to the mei auxiliary device info to inform the mei
> > driver about slow underlying firmware.
> > Such firmware will require to use larger operation timeouts.
> >
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > ---
> > include/linux/mei_aux.h | 1 +
>
> This patch has a wrong subject since it doesn't touch i915.
This is in a shared file between drm and mei, but I can resend.
>
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h index
> > 587f25128848..a29f4064b9c0 100644
> > --- a/include/linux/mei_aux.h
> > +++ b/include/linux/mei_aux.h
> > @@ -11,6 +11,7 @@ struct mei_aux_device {
> > struct auxiliary_device aux_dev;
> > int irq;
> > struct resource bar;
> > + bool slow_fw;
> > };
> >
> > #define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 03/14] drm/i915/gsc: add slow_fw flag to the gsc device definition
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
Add slow_fw flag to the gsc device definition
and pass it to mei auxiliary device.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e0236ff1d072..f963c220bbff 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -41,6 +41,7 @@ struct gsc_def {
unsigned long bar;
size_t bar_size;
bool use_polling;
+ bool slow_fw;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -145,6 +146,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
adev->bar.end = adev->bar.start + def->bar_size - 1;
adev->bar.flags = IORESOURCE_MEM;
adev->bar.desc = IORES_DESC_NONE;
+ adev->slow_fw = def->slow_fw;
aux_dev = &adev->aux_dev;
aux_dev->name = def->name;
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 03/14] drm/i915/gsc: add slow_fw flag to the gsc device definition
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
Add slow_fw flag to the gsc device definition
and pass it to mei auxiliary device.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e0236ff1d072..f963c220bbff 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -41,6 +41,7 @@ struct gsc_def {
unsigned long bar;
size_t bar_size;
bool use_polling;
+ bool slow_fw;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -145,6 +146,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
adev->bar.end = adev->bar.start + def->bar_size - 1;
adev->bar.flags = IORESOURCE_MEM;
adev->bar.desc = IORES_DESC_NONE;
+ adev->slow_fw = def->slow_fw;
aux_dev = &adev->aux_dev;
aux_dev->name = def->name;
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 04/14] drm/i915/gsc: add GSC XeHP SDV platform definition
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: linux-kernel, Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx
Define GSC on XeHP SDV (Intel(R) dGPU without display)
XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index f963c220bbff..bfc307e49bf9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
+static const struct gsc_def gsc_def_xehpsdv[] = {
+ {
+ /* HECI1 not enabled on the device. */
+ },
+ {
+ .name = "mei-gscfi",
+ .bar = DG1_GSC_HECI2_BASE,
+ .bar_size = GSC_BAR_LENGTH,
+ .use_polling = true,
+ .slow_fw = true,
+ }
+};
+
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (IS_DG1(i915)) {
def = &gsc_def_dg1[intf_id];
+ } else if (IS_XEHPSDV(i915)) {
+ def = &gsc_def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = &gsc_def_dg2[intf_id];
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 04/14] drm/i915/gsc: add GSC XeHP SDV platform definition
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx, linux-kernel
Define GSC on XeHP SDV (Intel(R) dGPU without display)
XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index f963c220bbff..bfc307e49bf9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
+static const struct gsc_def gsc_def_xehpsdv[] = {
+ {
+ /* HECI1 not enabled on the device. */
+ },
+ {
+ .name = "mei-gscfi",
+ .bar = DG1_GSC_HECI2_BASE,
+ .bar_size = GSC_BAR_LENGTH,
+ .use_polling = true,
+ .slow_fw = true,
+ }
+};
+
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (IS_DG1(i915)) {
def = &gsc_def_dg1[intf_id];
+ } else if (IS_XEHPSDV(i915)) {
+ def = &gsc_def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = &gsc_def_dg2[intf_id];
} else {
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 05/14] mei: gsc: use polling instead of interrupts
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
From: Tomas Winkler <tomas.winkler@intel.com>
A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
a gsc register when gsc is sending an interrupt. The work-around is
to disable interrupts and to use polling instead.
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------
drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++---
drivers/misc/mei/hw-me.h | 12 ++++++++
3 files changed, 105 insertions(+), 13 deletions(-)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8145e9b62b6..2caba3a9ac35 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -13,6 +13,7 @@
#include <linux/ktime.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
+#include <linux/kthread.h>
#include "mei_dev.h"
#include "hw-me.h"
@@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
- ret = devm_request_threaded_irq(device, hw->irq,
- mei_me_irq_quick_handler,
- mei_me_irq_thread_handler,
- IRQF_ONESHOT, KBUILD_MODNAME, dev);
- if (ret) {
- dev_err(device, "irq register failed %d\n", ret);
- goto err;
+ /* use polling */
+ if (mei_me_hw_use_polling(hw)) {
+ mei_disable_interrupts(dev);
+ mei_clear_interrupts(dev);
+ init_waitqueue_head(&hw->wait_active);
+ hw->is_active = true; /* start in active mode for initialization */
+ hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
+ "kmegscirqd/%s", dev_name(device));
+ if (IS_ERR(hw->polling_thread)) {
+ ret = PTR_ERR(hw->polling_thread);
+ dev_err(device, "unable to create kernel thread: %d\n", ret);
+ goto err;
+ }
+ } else {
+ ret = devm_request_threaded_irq(device, hw->irq,
+ mei_me_irq_quick_handler,
+ mei_me_irq_thread_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
+ if (ret) {
+ dev_err(device, "irq register failed %d\n", ret);
+ goto err;
+ }
}
pm_runtime_get_noresume(device);
@@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
register_err:
mei_stop(dev);
- devm_free_irq(device, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(device, hw->irq, dev);
err:
dev_err(device, "probe failed: %d\n", ret);
@@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *aux_dev)
mei_stop(dev);
+ hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ kthread_stop(hw->polling_thread);
+
mei_deregister(dev);
pm_runtime_disable(&aux_dev->dev);
mei_disable_interrupts(dev);
- devm_free_irq(&aux_dev->dev, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(&aux_dev->dev, hw->irq, dev);
}
static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
@@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
if (mei_write_is_idle(dev)) {
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_ON;
+
+ if (mei_me_hw_use_polling(hw))
+ hw->is_active = false;
ret = 0;
} else {
ret = -EAGAIN;
@@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_OFF;
+ if (mei_me_hw_use_polling(hw)) {
+ hw->is_active = true;
+ wake_up(&hw->wait_active);
+ }
+
mutex_unlock(&dev->device_lock);
irq_ret = mei_me_irq_thread_handler(1, dev);
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index befa491e3344..46559517a902 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
+#include <linux/delay.h>
#include "mei_dev.h"
#include "hbm.h"
@@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
*/
static void mei_me_intr_enable(struct mei_device *dev)
{
- u32 hcsr = mei_hcsr_read(dev);
+ u32 hcsr;
+
+ if (mei_me_hw_use_polling(to_me_hw(dev)))
+ return;
- hcsr |= H_CSR_IE_MASK;
+ hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
mei_hcsr_set(dev, hcsr);
}
@@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ return;
+
synchronize_irq(hw->irq);
}
@@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *dev)
{
u32 hcsr = mei_hcsr_read(dev);
- hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
+ if (!mei_me_hw_use_polling(to_me_hw(dev)))
+ hcsr |= H_CSR_IE_MASK;
+
+ hcsr |= H_IG | H_RDY;
mei_hcsr_set(dev, hcsr);
}
@@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
- if (!intr_enable)
+ if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
hcsr &= ~H_CSR_IE_MASK;
dev->recvd_hw_ready = false;
@@ -1331,6 +1341,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
}
EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
+#define MEI_POLLING_TIMEOUT_ACTIVE 100
+#define MEI_POLLING_TIMEOUT_IDLE 500
+
+int mei_me_polling_thread(void *_dev)
+{
+ struct mei_device *dev = _dev;
+ irqreturn_t irq_ret;
+ long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+
+ dev_dbg(dev->dev, "kernel thread is running\n");
+ while (!kthread_should_stop()) {
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 hcsr;
+
+ wait_event_timeout(hw->wait_active,
+ hw->is_active || kthread_should_stop(),
+ msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
+
+ if (kthread_should_stop())
+ break;
+
+ hcsr = mei_hcsr_read(dev);
+ if (me_intr_src(hcsr)) {
+ polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+ irq_ret = mei_me_irq_thread_handler(1, dev);
+ if (irq_ret != IRQ_HANDLED)
+ dev_err(dev->dev, "irq_ret %d\n", irq_ret);
+ } else {
+ polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_IDLE);
+ }
+
+ schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mei_me_polling_thread);
+
static const struct mei_hw_ops mei_me_hw_ops = {
.trc_status = mei_me_trc_status,
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index a071c645e905..ca09274ac299 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -51,6 +51,8 @@ struct mei_cfg {
* @d0i3_supported: di03 support
* @hbuf_depth: depth of hardware host/write buffer in slots
* @read_fws: read FW status register handler
+ * @wait_active: the polling thread activity wait queue
+ * @is_active: the device is active
*/
struct mei_me_hw {
const struct mei_cfg *cfg;
@@ -60,10 +62,19 @@ struct mei_me_hw {
bool d0i3_supported;
u8 hbuf_depth;
int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
+ /* polling */
+ struct task_struct *polling_thread;
+ wait_queue_head_t wait_active;
+ bool is_active;
};
#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
+static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
+{
+ return hw->irq < 0;
+}
+
/**
* enum mei_cfg_idx - indices to platform specific configurations.
*
@@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev);
irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
+int mei_me_polling_thread(void *_dev);
#endif /* _MEI_INTERFACE_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 05/14] mei: gsc: use polling instead of interrupts
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, James Ausmus
From: Tomas Winkler <tomas.winkler@intel.com>
A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
a gsc register when gsc is sending an interrupt. The work-around is
to disable interrupts and to use polling instead.
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------
drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++---
drivers/misc/mei/hw-me.h | 12 ++++++++
3 files changed, 105 insertions(+), 13 deletions(-)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8145e9b62b6..2caba3a9ac35 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -13,6 +13,7 @@
#include <linux/ktime.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
+#include <linux/kthread.h>
#include "mei_dev.h"
#include "hw-me.h"
@@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
- ret = devm_request_threaded_irq(device, hw->irq,
- mei_me_irq_quick_handler,
- mei_me_irq_thread_handler,
- IRQF_ONESHOT, KBUILD_MODNAME, dev);
- if (ret) {
- dev_err(device, "irq register failed %d\n", ret);
- goto err;
+ /* use polling */
+ if (mei_me_hw_use_polling(hw)) {
+ mei_disable_interrupts(dev);
+ mei_clear_interrupts(dev);
+ init_waitqueue_head(&hw->wait_active);
+ hw->is_active = true; /* start in active mode for initialization */
+ hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
+ "kmegscirqd/%s", dev_name(device));
+ if (IS_ERR(hw->polling_thread)) {
+ ret = PTR_ERR(hw->polling_thread);
+ dev_err(device, "unable to create kernel thread: %d\n", ret);
+ goto err;
+ }
+ } else {
+ ret = devm_request_threaded_irq(device, hw->irq,
+ mei_me_irq_quick_handler,
+ mei_me_irq_thread_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
+ if (ret) {
+ dev_err(device, "irq register failed %d\n", ret);
+ goto err;
+ }
}
pm_runtime_get_noresume(device);
@@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
register_err:
mei_stop(dev);
- devm_free_irq(device, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(device, hw->irq, dev);
err:
dev_err(device, "probe failed: %d\n", ret);
@@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *aux_dev)
mei_stop(dev);
+ hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ kthread_stop(hw->polling_thread);
+
mei_deregister(dev);
pm_runtime_disable(&aux_dev->dev);
mei_disable_interrupts(dev);
- devm_free_irq(&aux_dev->dev, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(&aux_dev->dev, hw->irq, dev);
}
static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
@@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
if (mei_write_is_idle(dev)) {
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_ON;
+
+ if (mei_me_hw_use_polling(hw))
+ hw->is_active = false;
ret = 0;
} else {
ret = -EAGAIN;
@@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_OFF;
+ if (mei_me_hw_use_polling(hw)) {
+ hw->is_active = true;
+ wake_up(&hw->wait_active);
+ }
+
mutex_unlock(&dev->device_lock);
irq_ret = mei_me_irq_thread_handler(1, dev);
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index befa491e3344..46559517a902 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
+#include <linux/delay.h>
#include "mei_dev.h"
#include "hbm.h"
@@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
*/
static void mei_me_intr_enable(struct mei_device *dev)
{
- u32 hcsr = mei_hcsr_read(dev);
+ u32 hcsr;
+
+ if (mei_me_hw_use_polling(to_me_hw(dev)))
+ return;
- hcsr |= H_CSR_IE_MASK;
+ hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
mei_hcsr_set(dev, hcsr);
}
@@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ return;
+
synchronize_irq(hw->irq);
}
@@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *dev)
{
u32 hcsr = mei_hcsr_read(dev);
- hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
+ if (!mei_me_hw_use_polling(to_me_hw(dev)))
+ hcsr |= H_CSR_IE_MASK;
+
+ hcsr |= H_IG | H_RDY;
mei_hcsr_set(dev, hcsr);
}
@@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
- if (!intr_enable)
+ if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
hcsr &= ~H_CSR_IE_MASK;
dev->recvd_hw_ready = false;
@@ -1331,6 +1341,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
}
EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
+#define MEI_POLLING_TIMEOUT_ACTIVE 100
+#define MEI_POLLING_TIMEOUT_IDLE 500
+
+int mei_me_polling_thread(void *_dev)
+{
+ struct mei_device *dev = _dev;
+ irqreturn_t irq_ret;
+ long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+
+ dev_dbg(dev->dev, "kernel thread is running\n");
+ while (!kthread_should_stop()) {
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 hcsr;
+
+ wait_event_timeout(hw->wait_active,
+ hw->is_active || kthread_should_stop(),
+ msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
+
+ if (kthread_should_stop())
+ break;
+
+ hcsr = mei_hcsr_read(dev);
+ if (me_intr_src(hcsr)) {
+ polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+ irq_ret = mei_me_irq_thread_handler(1, dev);
+ if (irq_ret != IRQ_HANDLED)
+ dev_err(dev->dev, "irq_ret %d\n", irq_ret);
+ } else {
+ polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_IDLE);
+ }
+
+ schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mei_me_polling_thread);
+
static const struct mei_hw_ops mei_me_hw_ops = {
.trc_status = mei_me_trc_status,
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index a071c645e905..ca09274ac299 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -51,6 +51,8 @@ struct mei_cfg {
* @d0i3_supported: di03 support
* @hbuf_depth: depth of hardware host/write buffer in slots
* @read_fws: read FW status register handler
+ * @wait_active: the polling thread activity wait queue
+ * @is_active: the device is active
*/
struct mei_me_hw {
const struct mei_cfg *cfg;
@@ -60,10 +62,19 @@ struct mei_me_hw {
bool d0i3_supported;
u8 hbuf_depth;
int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
+ /* polling */
+ struct task_struct *polling_thread;
+ wait_queue_head_t wait_active;
+ bool is_active;
};
#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
+static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
+{
+ return hw->irq < 0;
+}
+
/**
* enum mei_cfg_idx - indices to platform specific configurations.
*
@@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev);
irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
+int mei_me_polling_thread(void *_dev);
#endif /* _MEI_INTERFACE_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 06/14] mei: gsc: wait for reset thread on stop
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: linux-kernel, Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx
Wait for reset work to complete before initiating
stop reset flow sequence.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index eb052005ca86..5bb6ba662cc0 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
mei_clear_interrupts(dev);
mei_synchronize_irq(dev);
+ /* to catch HW-initiated reset */
+ mei_cancel_work(dev);
mutex_lock(&dev->device_lock);
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v5 06/14] mei: gsc: wait for reset thread on stop
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx, linux-kernel
Wait for reset work to complete before initiating
stop reset flow sequence.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index eb052005ca86..5bb6ba662cc0 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
mei_clear_interrupts(dev);
mei_synchronize_irq(dev);
+ /* to catch HW-initiated reset */
+ mei_cancel_work(dev);
mutex_lock(&dev->device_lock);
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 07/14] mei: extend timeouts on slow devices.
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: linux-kernel, Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx
Parametrize operational timeouts in order
to support slow firmware on some graphic devices.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/bus-fixup.c | 3 +--
drivers/misc/mei/client.c | 14 +++++++-------
drivers/misc/mei/gsc-me.c | 2 +-
drivers/misc/mei/hbm.c | 12 ++++++------
drivers/misc/mei/hw-me.c | 30 ++++++++++++++++--------------
drivers/misc/mei/hw-me.h | 2 +-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 +++++
drivers/misc/mei/init.c | 19 ++++++++++++++++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 16 ++++++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
12 files changed, 74 insertions(+), 35 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..24e91a9ea558 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)
sizeof(struct mkhi_fw_ver))
#define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
static int mei_fwver(struct mei_cl_device *cldev)
{
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
ret = 0;
bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
- MKHI_RCV_TIMEOUT);
+ cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
* Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..e7a16d9b2241 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
cl->state == MEI_FILE_DISCONNECT_REPLY ||
cl->state == MEI_FILE_DISCONNECTED,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
rets = cl->status;
@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_client *me_cl,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!mei_cl_is_connected(cl)) {
@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
cl->notify_en == request ||
cl->status ||
!mei_cl_is_connected(cl),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->notify_en != request && !cl->status)
@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const struct file *fp,
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!cl->dma_mapped && !cl->status)
@@ -2415,7 +2415,7 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct file *fp)
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
!cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->dma_mapped && !cl->status)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 2caba3a9ac35..4f6c916282b7 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -48,7 +48,7 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
device = &aux_dev->dev;
- dev = mei_me_dev_init(device, cfg);
+ dev = mei_me_dev_init(device, cfg, adev->slow_fw);
if (!dev) {
ret = -ENOMEM;
goto err;
diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c
index cf2b8261da14..708765056af2 100644
--- a/drivers/misc/mei/hbm.c
+++ b/drivers/misc/mei/hbm.c
@@ -232,7 +232,7 @@ int mei_hbm_start_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
ret = wait_event_timeout(dev->wait_hbm_start,
dev->hbm_state != MEI_HBM_STARTING,
- mei_secs_to_jiffies(MEI_HBM_TIMEOUT));
+ dev->timeouts.hbm);
mutex_lock(&dev->device_lock);
if (ret == 0 && (dev->hbm_state <= MEI_HBM_STARTING)) {
@@ -275,7 +275,7 @@ int mei_hbm_start_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_STARTING;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -316,7 +316,7 @@ static int mei_hbm_dma_setup_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_DR_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -351,7 +351,7 @@ static int mei_hbm_capabilities_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_CAP_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -385,7 +385,7 @@ static int mei_hbm_enum_clients_req(struct mei_device *dev)
return ret;
}
dev->hbm_state = MEI_HBM_ENUM_CLIENTS;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -751,7 +751,7 @@ static int mei_hbm_prop_req(struct mei_device *dev, unsigned long start_idx)
return ret;
}
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 46559517a902..6a8e8f3cea7e 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -445,7 +445,7 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_hw_ready,
dev->recvd_hw_ready,
- mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
+ dev->timeouts.hw_ready);
mutex_lock(&dev->device_lock);
if (!dev->recvd_hw_ready) {
dev_err(dev->dev, "wait hw ready failed\n");
@@ -707,7 +707,6 @@ static void mei_me_pg_unset(struct mei_device *dev)
static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
dev->pg_event = MEI_PG_EVENT_WAIT;
@@ -718,7 +717,8 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
@@ -744,7 +744,6 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
@@ -756,7 +755,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
reply:
@@ -772,7 +772,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
@@ -887,8 +888,6 @@ static u32 mei_me_d0i3_unset(struct mei_device *dev)
static int mei_me_d0i3_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
- unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
u32 reg;
@@ -910,7 +909,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
@@ -930,7 +930,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.d0i3);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev)
static int mei_me_d0i3_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
int ret;
u32 reg;
@@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -1686,11 +1687,12 @@ EXPORT_SYMBOL_GPL(mei_me_get_cfg);
*
* @parent: device associated with physical device (pci/platform)
* @cfg: per device generation config
+ * @slow_fw: configure longer timeouts as FW is slow
*
* Return: The mei_device pointer on success, NULL on failure.
*/
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg)
+ const struct mei_cfg *cfg, bool slow_fw)
{
struct mei_device *dev;
struct mei_me_hw *hw;
@@ -1705,7 +1707,7 @@ struct mei_device *mei_me_dev_init(struct device *parent,
for (i = 0; i < DMA_DSCR_NUM; i++)
dev->dr_dscr[i].size = cfg->dma_size[i];
- mei_device_init(dev, parent, &mei_me_hw_ops);
+ mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
hw->cfg = cfg;
dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index ca09274ac299..0e9d90808bcf 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -131,7 +131,7 @@ enum mei_cfg_idx {
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg);
+ const struct mei_cfg *cfg, bool slow_fw);
int mei_me_pg_enter_sync(struct mei_device *dev);
int mei_me_pg_exit_sync(struct mei_device *dev);
diff --git a/drivers/misc/mei/hw-txe.c b/drivers/misc/mei/hw-txe.c
index 00652c137cc7..fccfa806bd63 100644
--- a/drivers/misc/mei/hw-txe.c
+++ b/drivers/misc/mei/hw-txe.c
@@ -1201,7 +1201,7 @@ struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
if (!dev)
return NULL;
- mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
+ mei_device_init(dev, &pdev->dev, false, &mei_txe_hw_ops);
hw = to_txe_hw(dev);
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index b46077b17114..9381e5c13b4f 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -16,11 +16,16 @@
#define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */
#define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */
+#define MEI_CL_CONNECT_TIMEOUT_SLOW 30 /* HPS: Client Connect Timeout, slow FW */
#define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout */
#define MEI_PGI_TIMEOUT 1 /* PG Isolation time response 1 sec */
#define MEI_D0I3_TIMEOUT 5 /* D0i3 set/unset max response time */
#define MEI_HBM_TIMEOUT 1 /* 1 second */
+#define MEI_HBM_TIMEOUT_SLOW 5 /* 5 second, slow FW */
+
+#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
+#define MKHI_RCV_TIMEOUT_SLOW 10000 /* receive timeout in msec, slow FW */
/*
* FW page size for DMA allocations
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 5bb6ba662cc0..ce030a882d0c 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -359,14 +359,16 @@ bool mei_write_is_idle(struct mei_device *dev)
EXPORT_SYMBOL_GPL(mei_write_is_idle);
/**
- * mei_device_init -- initialize mei_device structure
+ * mei_device_init - initialize mei_device structure
*
* @dev: the mei device
* @device: the device structure
+ * @slow_fw: configure longer timeouts as FW is slow
* @hw_ops: hw operations
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops)
{
/* setup our list array */
@@ -404,6 +406,21 @@ void mei_device_init(struct mei_device *dev,
dev->pg_event = MEI_PG_EVENT_IDLE;
dev->ops = hw_ops;
dev->dev = device;
+
+ dev->timeouts.hw_ready = mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT);
+ dev->timeouts.connect = MEI_CONNECT_TIMEOUT;
+ dev->timeouts.client_init = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->timeouts.pgi = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
+ dev->timeouts.d0i3 = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
+ if (slow_fw) {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT_SLOW);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT_SLOW);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT_SLOW);
+ } else {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT);
+ }
}
EXPORT_SYMBOL_GPL(mei_device_init);
diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c
index 786f7c8f7f61..261939b945ef 100644
--- a/drivers/misc/mei/main.c
+++ b/drivers/misc/mei/main.c
@@ -571,7 +571,7 @@ static int mei_ioctl_connect_vtag(struct file *file,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
}
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 694f866f87ef..16f59b3a45fc 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -415,6 +415,17 @@ struct mei_fw_version {
#define MEI_MAX_FW_VER_BLOCKS 3
+struct mei_dev_timeouts {
+ unsigned long hw_ready; /* Timeout on ready message, in jiffies */
+ int connect; /* HPS: at least 2 seconds, in seconds */
+ unsigned long cl_connect; /* HPS: Client Connect Timeout, in jiffies */
+ int client_init; /* HPS: Clients Enumeration Timeout, in seconds */
+ unsigned long pgi; /* PG Isolation time response, in jiffies */
+ unsigned int d0i3; /* D0i3 set/unset max response time, in jiffies */
+ unsigned long hbm; /* HBM operation timeout, in jiffies */
+ unsigned long mkhi_recv; /* receive timeout, in jiffies */
+};
+
/**
* struct mei_device - MEI private device struct
*
@@ -480,6 +491,8 @@ struct mei_fw_version {
* @allow_fixed_address: allow user space to connect a fixed client
* @override_fixed_address: force allow fixed address behavior
*
+ * @timeouts: actual timeout values
+ *
* @reset_work : work item for the device reset
* @bus_rescan_work : work item for the bus rescan
*
@@ -568,6 +581,8 @@ struct mei_device {
bool allow_fixed_address;
bool override_fixed_address;
+ struct mei_dev_timeouts timeouts;
+
struct work_struct reset_work;
struct work_struct bus_rescan_work;
@@ -632,6 +647,7 @@ static inline u32 mei_slots2data(int slots)
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops);
int mei_reset(struct mei_device *dev);
int mei_start(struct mei_device *dev);
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 5435604327a7..b5af4e79bd52 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -203,7 +203,7 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
/* allocates and initializes the mei dev structure */
- dev = mei_me_dev_init(&pdev->dev, cfg);
+ dev = mei_me_dev_init(&pdev->dev, cfg, false);
if (!dev) {
err = -ENOMEM;
goto end;
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 07/14] mei: extend timeouts on slow devices.
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx, linux-kernel
Parametrize operational timeouts in order
to support slow firmware on some graphic devices.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/bus-fixup.c | 3 +--
drivers/misc/mei/client.c | 14 +++++++-------
drivers/misc/mei/gsc-me.c | 2 +-
drivers/misc/mei/hbm.c | 12 ++++++------
drivers/misc/mei/hw-me.c | 30 ++++++++++++++++--------------
drivers/misc/mei/hw-me.h | 2 +-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 +++++
drivers/misc/mei/init.c | 19 ++++++++++++++++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 16 ++++++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
12 files changed, 74 insertions(+), 35 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..24e91a9ea558 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)
sizeof(struct mkhi_fw_ver))
#define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
static int mei_fwver(struct mei_cl_device *cldev)
{
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
ret = 0;
bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
- MKHI_RCV_TIMEOUT);
+ cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
* Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..e7a16d9b2241 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
cl->state == MEI_FILE_DISCONNECT_REPLY ||
cl->state == MEI_FILE_DISCONNECTED,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
rets = cl->status;
@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_client *me_cl,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!mei_cl_is_connected(cl)) {
@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
cl->notify_en == request ||
cl->status ||
!mei_cl_is_connected(cl),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->notify_en != request && !cl->status)
@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const struct file *fp,
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!cl->dma_mapped && !cl->status)
@@ -2415,7 +2415,7 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct file *fp)
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
!cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->dma_mapped && !cl->status)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 2caba3a9ac35..4f6c916282b7 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -48,7 +48,7 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
device = &aux_dev->dev;
- dev = mei_me_dev_init(device, cfg);
+ dev = mei_me_dev_init(device, cfg, adev->slow_fw);
if (!dev) {
ret = -ENOMEM;
goto err;
diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c
index cf2b8261da14..708765056af2 100644
--- a/drivers/misc/mei/hbm.c
+++ b/drivers/misc/mei/hbm.c
@@ -232,7 +232,7 @@ int mei_hbm_start_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
ret = wait_event_timeout(dev->wait_hbm_start,
dev->hbm_state != MEI_HBM_STARTING,
- mei_secs_to_jiffies(MEI_HBM_TIMEOUT));
+ dev->timeouts.hbm);
mutex_lock(&dev->device_lock);
if (ret == 0 && (dev->hbm_state <= MEI_HBM_STARTING)) {
@@ -275,7 +275,7 @@ int mei_hbm_start_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_STARTING;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -316,7 +316,7 @@ static int mei_hbm_dma_setup_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_DR_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -351,7 +351,7 @@ static int mei_hbm_capabilities_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_CAP_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -385,7 +385,7 @@ static int mei_hbm_enum_clients_req(struct mei_device *dev)
return ret;
}
dev->hbm_state = MEI_HBM_ENUM_CLIENTS;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -751,7 +751,7 @@ static int mei_hbm_prop_req(struct mei_device *dev, unsigned long start_idx)
return ret;
}
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 46559517a902..6a8e8f3cea7e 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -445,7 +445,7 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_hw_ready,
dev->recvd_hw_ready,
- mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
+ dev->timeouts.hw_ready);
mutex_lock(&dev->device_lock);
if (!dev->recvd_hw_ready) {
dev_err(dev->dev, "wait hw ready failed\n");
@@ -707,7 +707,6 @@ static void mei_me_pg_unset(struct mei_device *dev)
static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
dev->pg_event = MEI_PG_EVENT_WAIT;
@@ -718,7 +717,8 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
@@ -744,7 +744,6 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
@@ -756,7 +755,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
reply:
@@ -772,7 +772,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
@@ -887,8 +888,6 @@ static u32 mei_me_d0i3_unset(struct mei_device *dev)
static int mei_me_d0i3_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
- unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
u32 reg;
@@ -910,7 +909,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
@@ -930,7 +930,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.d0i3);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev)
static int mei_me_d0i3_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
int ret;
u32 reg;
@@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -1686,11 +1687,12 @@ EXPORT_SYMBOL_GPL(mei_me_get_cfg);
*
* @parent: device associated with physical device (pci/platform)
* @cfg: per device generation config
+ * @slow_fw: configure longer timeouts as FW is slow
*
* Return: The mei_device pointer on success, NULL on failure.
*/
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg)
+ const struct mei_cfg *cfg, bool slow_fw)
{
struct mei_device *dev;
struct mei_me_hw *hw;
@@ -1705,7 +1707,7 @@ struct mei_device *mei_me_dev_init(struct device *parent,
for (i = 0; i < DMA_DSCR_NUM; i++)
dev->dr_dscr[i].size = cfg->dma_size[i];
- mei_device_init(dev, parent, &mei_me_hw_ops);
+ mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
hw->cfg = cfg;
dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index ca09274ac299..0e9d90808bcf 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -131,7 +131,7 @@ enum mei_cfg_idx {
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg);
+ const struct mei_cfg *cfg, bool slow_fw);
int mei_me_pg_enter_sync(struct mei_device *dev);
int mei_me_pg_exit_sync(struct mei_device *dev);
diff --git a/drivers/misc/mei/hw-txe.c b/drivers/misc/mei/hw-txe.c
index 00652c137cc7..fccfa806bd63 100644
--- a/drivers/misc/mei/hw-txe.c
+++ b/drivers/misc/mei/hw-txe.c
@@ -1201,7 +1201,7 @@ struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
if (!dev)
return NULL;
- mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
+ mei_device_init(dev, &pdev->dev, false, &mei_txe_hw_ops);
hw = to_txe_hw(dev);
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index b46077b17114..9381e5c13b4f 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -16,11 +16,16 @@
#define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */
#define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */
+#define MEI_CL_CONNECT_TIMEOUT_SLOW 30 /* HPS: Client Connect Timeout, slow FW */
#define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout */
#define MEI_PGI_TIMEOUT 1 /* PG Isolation time response 1 sec */
#define MEI_D0I3_TIMEOUT 5 /* D0i3 set/unset max response time */
#define MEI_HBM_TIMEOUT 1 /* 1 second */
+#define MEI_HBM_TIMEOUT_SLOW 5 /* 5 second, slow FW */
+
+#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
+#define MKHI_RCV_TIMEOUT_SLOW 10000 /* receive timeout in msec, slow FW */
/*
* FW page size for DMA allocations
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 5bb6ba662cc0..ce030a882d0c 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -359,14 +359,16 @@ bool mei_write_is_idle(struct mei_device *dev)
EXPORT_SYMBOL_GPL(mei_write_is_idle);
/**
- * mei_device_init -- initialize mei_device structure
+ * mei_device_init - initialize mei_device structure
*
* @dev: the mei device
* @device: the device structure
+ * @slow_fw: configure longer timeouts as FW is slow
* @hw_ops: hw operations
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops)
{
/* setup our list array */
@@ -404,6 +406,21 @@ void mei_device_init(struct mei_device *dev,
dev->pg_event = MEI_PG_EVENT_IDLE;
dev->ops = hw_ops;
dev->dev = device;
+
+ dev->timeouts.hw_ready = mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT);
+ dev->timeouts.connect = MEI_CONNECT_TIMEOUT;
+ dev->timeouts.client_init = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->timeouts.pgi = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
+ dev->timeouts.d0i3 = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
+ if (slow_fw) {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT_SLOW);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT_SLOW);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT_SLOW);
+ } else {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT);
+ }
}
EXPORT_SYMBOL_GPL(mei_device_init);
diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c
index 786f7c8f7f61..261939b945ef 100644
--- a/drivers/misc/mei/main.c
+++ b/drivers/misc/mei/main.c
@@ -571,7 +571,7 @@ static int mei_ioctl_connect_vtag(struct file *file,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
}
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 694f866f87ef..16f59b3a45fc 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -415,6 +415,17 @@ struct mei_fw_version {
#define MEI_MAX_FW_VER_BLOCKS 3
+struct mei_dev_timeouts {
+ unsigned long hw_ready; /* Timeout on ready message, in jiffies */
+ int connect; /* HPS: at least 2 seconds, in seconds */
+ unsigned long cl_connect; /* HPS: Client Connect Timeout, in jiffies */
+ int client_init; /* HPS: Clients Enumeration Timeout, in seconds */
+ unsigned long pgi; /* PG Isolation time response, in jiffies */
+ unsigned int d0i3; /* D0i3 set/unset max response time, in jiffies */
+ unsigned long hbm; /* HBM operation timeout, in jiffies */
+ unsigned long mkhi_recv; /* receive timeout, in jiffies */
+};
+
/**
* struct mei_device - MEI private device struct
*
@@ -480,6 +491,8 @@ struct mei_fw_version {
* @allow_fixed_address: allow user space to connect a fixed client
* @override_fixed_address: force allow fixed address behavior
*
+ * @timeouts: actual timeout values
+ *
* @reset_work : work item for the device reset
* @bus_rescan_work : work item for the bus rescan
*
@@ -568,6 +581,8 @@ struct mei_device {
bool allow_fixed_address;
bool override_fixed_address;
+ struct mei_dev_timeouts timeouts;
+
struct work_struct reset_work;
struct work_struct bus_rescan_work;
@@ -632,6 +647,7 @@ static inline u32 mei_slots2data(int slots)
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops);
int mei_reset(struct mei_device *dev);
int mei_start(struct mei_device *dev);
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 5435604327a7..b5af4e79bd52 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -203,7 +203,7 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
/* allocates and initializes the mei dev structure */
- dev = mei_me_dev_init(&pdev->dev, cfg);
+ dev = mei_me_dev_init(&pdev->dev, cfg, false);
if (!dev) {
err = -ENOMEM;
goto end;
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 08/14] mei: bus: export common mkhi definitions into a separate header
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: linux-kernel, Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx
From: Vitaly Lubart <vitaly.lubart@intel.com>
Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 32 ++-----------------------
drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++
2 files changed, 47 insertions(+), 30 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 24e91a9ea558..190691abddc9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
#include "mei_dev.h"
#include "client.h"
+#include "mkhi.h"
#define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -80,6 +81,7 @@ static void whitelist(struct mei_cl_device *cldev)
}
#define OSTYPE_LINUX 2
+
struct mei_os_ver {
__le16 build;
__le16 reserved1;
@@ -89,20 +91,6 @@ struct mei_os_ver {
u8 reserved2;
} __packed;
-#define MKHI_FEATURE_PTT 0x10
-
-struct mkhi_rule_id {
- __le16 rule_type;
- u8 feature_id;
- u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
- struct mkhi_rule_id id;
- u8 len;
- u8 data[];
-} __packed;
-
struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +103,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
} __packed;
-#define MKHI_FWCAPS_GROUP_ID 0x3
-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
- u8 group_id;
- u8 command;
- u8 reserved;
- u8 result;
-} __packed;
-
-struct mkhi_msg {
- struct mkhi_msg_hdr hdr;
- u8 data[];
-} __packed;
-
#define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index 000000000000..27a9b476904e
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include "mei_dev.h"
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+#define MCHI_GROUP_ID 0xA
+
+struct mkhi_rule_id {
+ __le16 rule_type;
+ u8 feature_id;
+ u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+ struct mkhi_rule_id id;
+ u8 len;
+ u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+ u8 group_id;
+ u8 command;
+ u8 reserved;
+ u8 result;
+} __packed;
+
+struct mkhi_msg {
+ struct mkhi_msg_hdr hdr;
+ u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 08/14] mei: bus: export common mkhi definitions into a separate header
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx, linux-kernel
From: Vitaly Lubart <vitaly.lubart@intel.com>
Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 32 ++-----------------------
drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++
2 files changed, 47 insertions(+), 30 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 24e91a9ea558..190691abddc9 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
#include "mei_dev.h"
#include "client.h"
+#include "mkhi.h"
#define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -80,6 +81,7 @@ static void whitelist(struct mei_cl_device *cldev)
}
#define OSTYPE_LINUX 2
+
struct mei_os_ver {
__le16 build;
__le16 reserved1;
@@ -89,20 +91,6 @@ struct mei_os_ver {
u8 reserved2;
} __packed;
-#define MKHI_FEATURE_PTT 0x10
-
-struct mkhi_rule_id {
- __le16 rule_type;
- u8 feature_id;
- u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
- struct mkhi_rule_id id;
- u8 len;
- u8 data[];
-} __packed;
-
struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +103,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
} __packed;
-#define MKHI_FWCAPS_GROUP_ID 0x3
-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
- u8 group_id;
- u8 command;
- u8 reserved;
- u8 result;
-} __packed;
-
-struct mkhi_msg {
- struct mkhi_msg_hdr hdr;
- u8 data[];
-} __packed;
-
#define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index 000000000000..27a9b476904e
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include "mei_dev.h"
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+#define MCHI_GROUP_ID 0xA
+
+struct mkhi_rule_id {
+ __le16 rule_type;
+ u8 feature_id;
+ u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+ struct mkhi_rule_id id;
+ u8 len;
+ u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+ u8 group_id;
+ u8 command;
+ u8 reserved;
+ u8 result;
+} __packed;
+
+struct mkhi_msg {
+ struct mkhi_msg_hdr hdr;
+ u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 09/14] mei: mkhi: add memory ready command
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
From: Tomas Winkler <tomas.winkler@intel.com>
Add GSC memory ready command.
The command indicates to the firmware that
extend operation memory was setup and
the firmware may enter PXP mode.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/mkhi.h | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index 27a9b476904e..ea9fe487cb0f 100644
--- a/drivers/misc/mei/mkhi.h
+++ b/drivers/misc/mei/mkhi.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
* Intel Management Engine Interface (Intel MEI) Linux driver
*/
@@ -18,6 +18,13 @@
#define MCHI_GROUP_ID 0xA
+#define MKHI_GROUP_ID_GFX 0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1
+
struct mkhi_rule_id {
__le16 rule_type;
u8 feature_id;
@@ -42,4 +49,9 @@ struct mkhi_msg {
u8 data[];
} __packed;
+struct mkhi_gfx_mem_ready {
+ struct mkhi_msg_hdr hdr;
+ uint32_t flags;
+} __packed;
+
#endif /* _MEI_MKHI_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 09/14] mei: mkhi: add memory ready command
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
From: Tomas Winkler <tomas.winkler@intel.com>
Add GSC memory ready command.
The command indicates to the firmware that
extend operation memory was setup and
the firmware may enter PXP mode.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/mkhi.h | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index 27a9b476904e..ea9fe487cb0f 100644
--- a/drivers/misc/mei/mkhi.h
+++ b/drivers/misc/mei/mkhi.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
* Intel Management Engine Interface (Intel MEI) Linux driver
*/
@@ -18,6 +18,13 @@
#define MCHI_GROUP_ID 0xA
+#define MKHI_GROUP_ID_GFX 0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1
+
struct mkhi_rule_id {
__le16 rule_type;
u8 feature_id;
@@ -42,4 +49,9 @@ struct mkhi_msg {
u8 data[];
} __packed;
+struct mkhi_gfx_mem_ready {
+ struct mkhi_msg_hdr hdr;
+ uint32_t flags;
+} __packed;
+
#endif /* _MEI_MKHI_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 10/14] mei: gsc: setup gsc extended operational memory
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
From: Tomas Winkler <tomas.winkler@intel.com>
1. Retrieve extended operational memory physical pointers from the
auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
ready command.
4. Disable PXP device if GSC is not in PXP mode.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++-
drivers/misc/mei/gsc-me.c | 16 ++++++++
drivers/misc/mei/hw-me-regs.h | 7 ++++
drivers/misc/mei/hw-me.c | 28 +++++++++++++-
drivers/misc/mei/mei_dev.h | 10 +++++
include/linux/mei_aux.h | 1 +
6 files changed, 129 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 190691abddc9..d2929f68604d 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -189,6 +189,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
return ret;
}
+static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
+{
+ struct mkhi_gfx_mem_ready req = {0};
+ unsigned int mode = MEI_CL_IO_TX_INTERNAL;
+
+ req.hdr.group_id = MKHI_GROUP_ID_GFX;
+ req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
+ req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
+
+ dev_dbg(&cldev->dev, "Sending memory ready command\n");
+ return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode);
+}
+
static void mei_mkhi_fix(struct mei_cl_device *cldev)
{
int ret;
@@ -235,6 +248,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
dev_err(&cldev->dev, "FW version command failed %d\n", ret);
mei_cldev_disable(cldev);
}
+
+static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
+{
+ int ret;
+
+ /* No need to enable the client if nothing is needed from it */
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ (cldev->bus->pxp_mode != MEI_DEV_PXP_INIT))
+ return;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret)
+ return;
+
+ if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
+ ret = mei_gfx_memory_ready(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "memory ready command failed %d\n", ret);
+ else
+ dev_dbg(&cldev->dev, "memory ready command sent\n");
+ /* we go to reset after that */
+ cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
+ goto out;
+ }
+
+ ret = mei_fwver(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "FW version command failed %d\n",
+ ret);
+out:
+ mei_cldev_disable(cldev);
+}
+
/**
* mei_wd - wd client on the bus, change protocol version
* as the API has changed.
@@ -474,6 +520,26 @@ static void vt_support(struct mei_cl_device *cldev)
cldev->do_match = 1;
}
+/**
+ * pxp_isready - enable bus client if pxp is ready
+ *
+ * @cldev: me clients device
+ */
+static void pxp_isready(struct mei_cl_device *cldev)
+{
+ struct mei_device *bus = cldev->bus;
+
+ switch (bus->pxp_mode) {
+ case MEI_DEV_PXP_READY:
+ case MEI_DEV_PXP_DEFAULT:
+ cldev->do_match = 1;
+ break;
+ default:
+ cldev->do_match = 0;
+ break;
+ }
+}
+
#define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
static struct mei_fixup {
@@ -487,10 +553,10 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
- MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
+ MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
- MEI_FIXUP(MEI_UUID_PAVP, whitelist),
+ MEI_FIXUP(MEI_UUID_PAVP, pxp_isready),
};
/**
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 4f6c916282b7..c8a167b57cc9 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
return 0;
}
+static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)
+{
+ u32 low = lower_32_bits(mem->start);
+ u32 hi = upper_32_bits(mem->start);
+ u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
+
+ iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
+ iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
+ iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
+}
+
static int mei_gsc_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
/* use polling */
if (mei_me_hw_use_polling(hw)) {
mei_disable_interrupts(dev);
diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 15e8e2b322b1..8049f288f74c 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -127,6 +127,8 @@
# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
#define PCI_CFG_HFS_4 0x64
#define PCI_CFG_HFS_5 0x68
+# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
+# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
#define PCI_CFG_HFS_6 0x6C
/* MEI registers */
@@ -143,6 +145,11 @@
/* H_D0I3C - D0I3 Control */
#define H_D0I3C 0x800
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
+#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
+#define GSC_EXT_OP_MEM_VALID BIT(31)
+
/* register bits of H_CSR (Host Control Status register) */
/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
#define H_CBD 0xFF000000
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 6a8e8f3cea7e..c86d6018bc20 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *dev)
return (mecsr & ME_RST_HRA) == ME_RST_HRA;
}
+/**
+ * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
+ *
+ * @dev: the device structure
+ */
+static void mei_gsc_pxp_check(struct mei_device *dev)
+{
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 fwsts5 = 0;
+
+ if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
+ return;
+
+ hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
+ trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
+ if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
+ dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
+ dev->pxp_mode = MEI_DEV_PXP_READY;
+ } else {
+ dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
+ }
+}
+
/**
* mei_me_hw_ready_wait - wait until the me(hw) has turned ready
* or timeout is reached
@@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
return -ETIME;
}
+ mei_gsc_pxp_check(dev);
+
mei_me_hw_reset_release(dev);
dev->recvd_hw_ready = false;
return 0;
@@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
/* check if ME wants a reset */
if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
- dev_warn(dev->dev, "FW not ready: resetting.\n");
+ dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
+ dev->dev_state, dev->pxp_mode);
if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
dev->dev_state == MEI_DEV_POWER_DOWN)
mei_cl_all_disconnect(dev);
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 16f59b3a45fc..7c508bca9a00 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -62,6 +62,14 @@ enum mei_dev_state {
MEI_DEV_POWER_UP
};
+/* MEI PXP mode state */
+enum mei_dev_pxp_mode {
+ MEI_DEV_PXP_DEFAULT = 0,
+ MEI_DEV_PXP_INIT = 1,
+ MEI_DEV_PXP_SETUP = 2,
+ MEI_DEV_PXP_READY = 3,
+};
+
const char *mei_dev_state_str(int state);
enum mei_file_transaction_states {
@@ -454,6 +462,7 @@ struct mei_dev_timeouts {
* @reset_count : number of consecutive resets
* @dev_state : device state
* @hbm_state : state of host bus message protocol
+ * @pxp_mode : PXP device mode
* @init_clients_timer : HBM init handshake timeout
*
* @pg_event : power gating event
@@ -537,6 +546,7 @@ struct mei_device {
unsigned long reset_count;
enum mei_dev_state dev_state;
enum mei_hbm_state hbm_state;
+ enum mei_dev_pxp_mode pxp_mode;
u16 init_clients_timer;
/*
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index a29f4064b9c0..c3fc137a2aba 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -11,6 +11,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ struct resource ext_op_mem;
bool slow_fw;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 10/14] mei: gsc: setup gsc extended operational memory
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
From: Tomas Winkler <tomas.winkler@intel.com>
1. Retrieve extended operational memory physical pointers from the
auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
ready command.
4. Disable PXP device if GSC is not in PXP mode.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++-
drivers/misc/mei/gsc-me.c | 16 ++++++++
drivers/misc/mei/hw-me-regs.h | 7 ++++
drivers/misc/mei/hw-me.c | 28 +++++++++++++-
drivers/misc/mei/mei_dev.h | 10 +++++
include/linux/mei_aux.h | 1 +
6 files changed, 129 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 190691abddc9..d2929f68604d 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -189,6 +189,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
return ret;
}
+static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
+{
+ struct mkhi_gfx_mem_ready req = {0};
+ unsigned int mode = MEI_CL_IO_TX_INTERNAL;
+
+ req.hdr.group_id = MKHI_GROUP_ID_GFX;
+ req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
+ req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
+
+ dev_dbg(&cldev->dev, "Sending memory ready command\n");
+ return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode);
+}
+
static void mei_mkhi_fix(struct mei_cl_device *cldev)
{
int ret;
@@ -235,6 +248,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
dev_err(&cldev->dev, "FW version command failed %d\n", ret);
mei_cldev_disable(cldev);
}
+
+static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
+{
+ int ret;
+
+ /* No need to enable the client if nothing is needed from it */
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ (cldev->bus->pxp_mode != MEI_DEV_PXP_INIT))
+ return;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret)
+ return;
+
+ if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
+ ret = mei_gfx_memory_ready(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "memory ready command failed %d\n", ret);
+ else
+ dev_dbg(&cldev->dev, "memory ready command sent\n");
+ /* we go to reset after that */
+ cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
+ goto out;
+ }
+
+ ret = mei_fwver(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "FW version command failed %d\n",
+ ret);
+out:
+ mei_cldev_disable(cldev);
+}
+
/**
* mei_wd - wd client on the bus, change protocol version
* as the API has changed.
@@ -474,6 +520,26 @@ static void vt_support(struct mei_cl_device *cldev)
cldev->do_match = 1;
}
+/**
+ * pxp_isready - enable bus client if pxp is ready
+ *
+ * @cldev: me clients device
+ */
+static void pxp_isready(struct mei_cl_device *cldev)
+{
+ struct mei_device *bus = cldev->bus;
+
+ switch (bus->pxp_mode) {
+ case MEI_DEV_PXP_READY:
+ case MEI_DEV_PXP_DEFAULT:
+ cldev->do_match = 1;
+ break;
+ default:
+ cldev->do_match = 0;
+ break;
+ }
+}
+
#define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
static struct mei_fixup {
@@ -487,10 +553,10 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
- MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
+ MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
- MEI_FIXUP(MEI_UUID_PAVP, whitelist),
+ MEI_FIXUP(MEI_UUID_PAVP, pxp_isready),
};
/**
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 4f6c916282b7..c8a167b57cc9 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
return 0;
}
+static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)
+{
+ u32 low = lower_32_bits(mem->start);
+ u32 hi = upper_32_bits(mem->start);
+ u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
+
+ iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
+ iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
+ iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
+}
+
static int mei_gsc_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
/* use polling */
if (mei_me_hw_use_polling(hw)) {
mei_disable_interrupts(dev);
diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 15e8e2b322b1..8049f288f74c 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -127,6 +127,8 @@
# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
#define PCI_CFG_HFS_4 0x64
#define PCI_CFG_HFS_5 0x68
+# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
+# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
#define PCI_CFG_HFS_6 0x6C
/* MEI registers */
@@ -143,6 +145,11 @@
/* H_D0I3C - D0I3 Control */
#define H_D0I3C 0x800
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
+#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
+#define GSC_EXT_OP_MEM_VALID BIT(31)
+
/* register bits of H_CSR (Host Control Status register) */
/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
#define H_CBD 0xFF000000
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 6a8e8f3cea7e..c86d6018bc20 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *dev)
return (mecsr & ME_RST_HRA) == ME_RST_HRA;
}
+/**
+ * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
+ *
+ * @dev: the device structure
+ */
+static void mei_gsc_pxp_check(struct mei_device *dev)
+{
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 fwsts5 = 0;
+
+ if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
+ return;
+
+ hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
+ trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
+ if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
+ dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
+ dev->pxp_mode = MEI_DEV_PXP_READY;
+ } else {
+ dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
+ }
+}
+
/**
* mei_me_hw_ready_wait - wait until the me(hw) has turned ready
* or timeout is reached
@@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
return -ETIME;
}
+ mei_gsc_pxp_check(dev);
+
mei_me_hw_reset_release(dev);
dev->recvd_hw_ready = false;
return 0;
@@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
/* check if ME wants a reset */
if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
- dev_warn(dev->dev, "FW not ready: resetting.\n");
+ dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
+ dev->dev_state, dev->pxp_mode);
if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
dev->dev_state == MEI_DEV_POWER_DOWN)
mei_cl_all_disconnect(dev);
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 16f59b3a45fc..7c508bca9a00 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -62,6 +62,14 @@ enum mei_dev_state {
MEI_DEV_POWER_UP
};
+/* MEI PXP mode state */
+enum mei_dev_pxp_mode {
+ MEI_DEV_PXP_DEFAULT = 0,
+ MEI_DEV_PXP_INIT = 1,
+ MEI_DEV_PXP_SETUP = 2,
+ MEI_DEV_PXP_READY = 3,
+};
+
const char *mei_dev_state_str(int state);
enum mei_file_transaction_states {
@@ -454,6 +462,7 @@ struct mei_dev_timeouts {
* @reset_count : number of consecutive resets
* @dev_state : device state
* @hbm_state : state of host bus message protocol
+ * @pxp_mode : PXP device mode
* @init_clients_timer : HBM init handshake timeout
*
* @pg_event : power gating event
@@ -537,6 +546,7 @@ struct mei_device {
unsigned long reset_count;
enum mei_dev_state dev_state;
enum mei_hbm_state hbm_state;
+ enum mei_dev_pxp_mode pxp_mode;
u16 init_clients_timer;
/*
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index a29f4064b9c0..c3fc137a2aba 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -11,6 +11,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ struct resource ext_op_mem;
bool slow_fw;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 11/14] mei: gsc: add transition to PXP mode in resume flow
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Added transition to PXP mode in resume flow.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8a167b57cc9..71f247f5e7ca 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
static int __maybe_unused mei_gsc_pm_resume(struct device *device)
{
struct mei_device *dev = dev_get_drvdata(device);
+ struct auxiliary_device *aux_dev;
+ struct mei_aux_device *adev;
int err;
+ struct mei_me_hw *hw;
if (!dev)
return -ENODEV;
+ hw = to_me_hw(dev);
+ aux_dev = to_auxiliary_dev(device);
+ adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
err = mei_restart(dev);
if (err)
return err;
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [PATCH v5 11/14] mei: gsc: add transition to PXP mode in resume flow
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
From: Vitaly Lubart <vitaly.lubart@intel.com>
Added transition to PXP mode in resume flow.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8a167b57cc9..71f247f5e7ca 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
static int __maybe_unused mei_gsc_pm_resume(struct device *device)
{
struct mei_device *dev = dev_get_drvdata(device);
+ struct auxiliary_device *aux_dev;
+ struct mei_aux_device *adev;
int err;
+ struct mei_me_hw *hw;
if (!dev)
return -ENODEV;
+ hw = to_me_hw(dev);
+ aux_dev = to_auxiliary_dev(device);
+ adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
err = mei_restart(dev);
if (err)
return err;
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v5 12/14] mei: debugfs: add pxp mode to devstate in debugfs
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx, linux-kernel
From: Tomas Winkler <tomas.winkler@intel.com>
Add pxp mode devstate to debugfs to monitor pxp state machine progress.
This is useful to debug issues in scenarios in which the pxp state
needs to be re-initialized, like during power transitions such as
suspend/resume. With this debugfs the state could be monitored
to ensure that pxp is in the ready state.
CC: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/debugfs.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index 1ce61e9e24fc..4074fec866a6 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
+static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
+{
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
+ switch (state) {
+ MEI_PXP_MODE(DEFAULT);
+ MEI_PXP_MODE(INIT);
+ MEI_PXP_MODE(SETUP);
+ MEI_PXP_MODE(READY);
+ default:
+ return "unknown";
+ }
+#undef MEI_PXP_MODE
+}
+
static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
{
struct mei_device *dev = m->private;
@@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
seq_printf(m, "pg: %s, %s\n",
mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
mei_pg_state_str(mei_pg_state(dev)));
+
+ seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
+
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v5 12/14] mei: debugfs: add pxp mode to devstate in debugfs
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: linux-kernel, Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx
From: Tomas Winkler <tomas.winkler@intel.com>
Add pxp mode devstate to debugfs to monitor pxp state machine progress.
This is useful to debug issues in scenarios in which the pxp state
needs to be re-initialized, like during power transitions such as
suspend/resume. With this debugfs the state could be monitored
to ensure that pxp is in the ready state.
CC: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/debugfs.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index 1ce61e9e24fc..4074fec866a6 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
+static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
+{
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
+ switch (state) {
+ MEI_PXP_MODE(DEFAULT);
+ MEI_PXP_MODE(INIT);
+ MEI_PXP_MODE(SETUP);
+ MEI_PXP_MODE(READY);
+ default:
+ return "unknown";
+ }
+#undef MEI_PXP_MODE
+}
+
static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
{
struct mei_device *dev = m->private;
@@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
seq_printf(m, "pg: %s, %s\n",
mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
mei_pg_state_str(mei_pg_state(dev)));
+
+ seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
+
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH v5 13/14] drm/i915/gsc: allocate extended operational memory in LMEM
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Alan Previn, Daniele Ceraolo Spurio
From: Tomas Winkler <tomas.winkler@intel.com>
GSC requires more operational memory than available on chip.
Reserve 4M of LMEM for GSC operation. The memory is provided to the
GSC as struct resource to the auxiliary data of the child device.
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 92 ++++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
2 files changed, 88 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index bfc307e49bf9..4d87519d5773 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
#include <linux/mei_aux.h>
#include "i915_drv.h"
#include "i915_reg.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_gsc.h"
#include "gt/intel_gt.h"
@@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
}
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
+{
+ struct intel_gt *gt = gsc_to_gt(gsc);
+ struct drm_i915_gem_object *obj;
+ void *vaddr;
+ int err;
+
+ obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
+ goto out_put;
+ }
+
+ vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ drm_err(>->i915->drm, "Failed to map gsc memory\n");
+ goto out_unpin;
+ }
+
+ memset(vaddr, 0, obj->base.size);
+
+ i915_gem_object_unpin_map(obj);
+
+ intf->gem_obj = obj;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
+
+ if (!obj)
+ return;
+
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+
+ i915_gem_object_put(obj);
+}
+
struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
bool use_polling;
bool slow_fw;
+ size_t lmem_size;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+ .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -90,26 +148,33 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
}
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+ struct intel_gsc *gsc, unsigned int intf_id)
{
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(&intf->adev->aux_dev);
auxiliary_device_uninit(&intf->adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+ gsc_ext_om_destroy(intf);
}
static void gsc_init_one(struct drm_i915_private *i915,
- struct intel_gsc_intf *intf,
- unsigned int intf_id)
+ struct intel_gsc *gsc,
+ unsigned int intf_id)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct mei_aux_device *adev;
struct auxiliary_device *aux_dev;
const struct gsc_def *def;
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
int ret;
intf->irq = -1;
@@ -141,7 +206,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
- return;
+ goto fail;
}
ret = gsc_irq_init(intf->irq);
@@ -155,6 +220,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (!adev)
goto fail;
+ if (def->lmem_size) {
+ dev_dbg(&pdev->dev, "setting up GSC lmem\n");
+
+ if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
+ dev_err(&pdev->dev, "setting up gsc extended operational memory failed\n");
+ kfree(adev);
+ goto fail;
+ }
+
+ adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
+ adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
+ }
+
adev->irq = intf->irq;
adev->bar.parent = &pdev->resource[0];
adev->bar.start = def->bar + pdev->resource[0].start;
@@ -188,7 +266,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
fail:
- gsc_destroy_one(intf);
+ gsc_destroy_one(i915, gsc, intf->id);
}
static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
@@ -229,7 +307,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_init_one(i915, &gsc->intf[i], i);
+ gsc_init_one(i915, gsc, i);
}
void intel_gsc_fini(struct intel_gsc *gsc)
@@ -241,5 +319,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_destroy_one(&gsc->intf[i]);
+ gsc_destroy_one(gt->i915, gsc, i);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
index 68582f912b21..fcac1775e9c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.h
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
@@ -20,11 +20,14 @@ struct mei_aux_device;
/**
* struct intel_gsc - graphics security controller
+ *
+ * @gem_obj: scratch memory GSC operations
* @intf : gsc interface
*/
struct intel_gsc {
struct intel_gsc_intf {
struct mei_aux_device *adev;
+ struct drm_i915_gem_object *gem_obj;
int irq;
unsigned int id;
} intf[INTEL_GSC_NUM_INTERFACES];
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* [Intel-gfx] [PATCH v5 13/14] drm/i915/gsc: allocate extended operational memory in LMEM
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Alan Previn, intel-gfx, Alexander Usyskin, linux-kernel,
Tomas Winkler, Vitaly Lubart
From: Tomas Winkler <tomas.winkler@intel.com>
GSC requires more operational memory than available on chip.
Reserve 4M of LMEM for GSC operation. The memory is provided to the
GSC as struct resource to the auxiliary data of the child device.
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 92 ++++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
2 files changed, 88 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index bfc307e49bf9..4d87519d5773 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
#include <linux/mei_aux.h>
#include "i915_drv.h"
#include "i915_reg.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_gsc.h"
#include "gt/intel_gt.h"
@@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
}
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
+{
+ struct intel_gt *gt = gsc_to_gt(gsc);
+ struct drm_i915_gem_object *obj;
+ void *vaddr;
+ int err;
+
+ obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
+ goto out_put;
+ }
+
+ vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ drm_err(>->i915->drm, "Failed to map gsc memory\n");
+ goto out_unpin;
+ }
+
+ memset(vaddr, 0, obj->base.size);
+
+ i915_gem_object_unpin_map(obj);
+
+ intf->gem_obj = obj;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
+
+ if (!obj)
+ return;
+
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+
+ i915_gem_object_put(obj);
+}
+
struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
bool use_polling;
bool slow_fw;
+ size_t lmem_size;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+ .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -90,26 +148,33 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
}
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+ struct intel_gsc *gsc, unsigned int intf_id)
{
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(&intf->adev->aux_dev);
auxiliary_device_uninit(&intf->adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+ gsc_ext_om_destroy(intf);
}
static void gsc_init_one(struct drm_i915_private *i915,
- struct intel_gsc_intf *intf,
- unsigned int intf_id)
+ struct intel_gsc *gsc,
+ unsigned int intf_id)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct mei_aux_device *adev;
struct auxiliary_device *aux_dev;
const struct gsc_def *def;
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
int ret;
intf->irq = -1;
@@ -141,7 +206,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
- return;
+ goto fail;
}
ret = gsc_irq_init(intf->irq);
@@ -155,6 +220,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (!adev)
goto fail;
+ if (def->lmem_size) {
+ dev_dbg(&pdev->dev, "setting up GSC lmem\n");
+
+ if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
+ dev_err(&pdev->dev, "setting up gsc extended operational memory failed\n");
+ kfree(adev);
+ goto fail;
+ }
+
+ adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
+ adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
+ }
+
adev->irq = intf->irq;
adev->bar.parent = &pdev->resource[0];
adev->bar.start = def->bar + pdev->resource[0].start;
@@ -188,7 +266,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
fail:
- gsc_destroy_one(intf);
+ gsc_destroy_one(i915, gsc, intf->id);
}
static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
@@ -229,7 +307,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_init_one(i915, &gsc->intf[i], i);
+ gsc_init_one(i915, gsc, i);
}
void intel_gsc_fini(struct intel_gsc *gsc)
@@ -241,5 +319,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_destroy_one(&gsc->intf[i]);
+ gsc_destroy_one(gt->i915, gsc, i);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
index 68582f912b21..fcac1775e9c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.h
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
@@ -20,11 +20,14 @@ struct mei_aux_device;
/**
* struct intel_gsc - graphics security controller
+ *
+ * @gem_obj: scratch memory GSC operations
* @intf : gsc interface
*/
struct intel_gsc {
struct intel_gsc_intf {
struct mei_aux_device *adev;
+ struct drm_i915_gem_object *gem_obj;
int irq;
unsigned int id;
} intf[INTEL_GSC_NUM_INTERFACES];
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread* Re: [v5,13/14] drm/i915/gsc: allocate extended operational memory in LMEM
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-08-02 17:29 ` Teres Alexis, Alan Previn
-1 siblings, 0 replies; 46+ messages in thread
From: Teres Alexis, Alan Previn @ 2022-08-02 17:29 UTC (permalink / raw)
To: airlied, gregkh, Vivi, Rodrigo, joonas.lahtinen, Usyskin,
Alexander, tvrtko.ursulin, daniel, jani.nikula
Cc: Winkler, Tomas, intel-gfx, linux-kernel, Lubart, Vitaly
Looks good, just a minor nit.
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
On Wed, 2022-07-06 at 14:43 +0300, Alexander Usyskin wrote:
> From: Tomas Winkler <tomas.winkler@intel.com>
>
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 92 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
> 2 files changed, 88 insertions(+), 7 deletions(-)
>
> + if (def->lmem_size) {
> + dev_dbg(&pdev->dev, "setting up GSC lmem\n");
>
NIT: Any reason we are not being consistent and using drm_err / drm_debug (same below)? either way, ensuring we get PCI
device id info in the dmesg output we are good.
> +
> + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> + dev_err(&pdev->dev, "setting up gsc extended operational memory failed\n");
> + kfree(adev);
> + goto fail;
> + }
> +
> + adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
> + adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
> + }
> +
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [v5, 13/14] drm/i915/gsc: allocate extended operational memory in LMEM
@ 2022-08-02 17:29 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 46+ messages in thread
From: Teres Alexis, Alan Previn @ 2022-08-02 17:29 UTC (permalink / raw)
To: airlied, gregkh, Vivi, Rodrigo, joonas.lahtinen, Usyskin,
Alexander, tvrtko.ursulin, daniel, jani.nikula
Cc: Winkler, Tomas, Lubart, Vitaly, intel-gfx, linux-kernel
Looks good, just a minor nit.
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
On Wed, 2022-07-06 at 14:43 +0300, Alexander Usyskin wrote:
> From: Tomas Winkler <tomas.winkler@intel.com>
>
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 92 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
> 2 files changed, 88 insertions(+), 7 deletions(-)
>
> + if (def->lmem_size) {
> + dev_dbg(&pdev->dev, "setting up GSC lmem\n");
>
NIT: Any reason we are not being consistent and using drm_err / drm_debug (same below)? either way, ensuring we get PCI
device id info in the dmesg output we are good.
> +
> + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> + dev_err(&pdev->dev, "setting up gsc extended operational memory failed\n");
> + kfree(adev);
> + goto fail;
> + }
> +
> + adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
> + adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
> + }
> +
^ permalink raw reply [flat|nested] 46+ messages in thread* RE: [v5,13/14] drm/i915/gsc: allocate extended operational memory in LMEM
2022-08-02 17:29 ` [Intel-gfx] [v5, 13/14] " Teres Alexis, Alan Previn
@ 2022-08-02 18:49 ` Winkler, Tomas
-1 siblings, 0 replies; 46+ messages in thread
From: Winkler, Tomas @ 2022-08-02 18:49 UTC (permalink / raw)
To: Teres Alexis, Alan Previn, airlied, gregkh, Vivi, Rodrigo,
joonas.lahtinen, Usyskin, Alexander, tvrtko.ursulin, daniel,
jani.nikula
Cc: intel-gfx, linux-kernel, Lubart, Vitaly
>
> Looks good, just a minor nit.
>
> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
>
>
> On Wed, 2022-07-06 at 14:43 +0300, Alexander Usyskin wrote:
> > From: Tomas Winkler <tomas.winkler@intel.com>
> >
> > GSC requires more operational memory than available on chip.
> > Reserve 4M of LMEM for GSC operation. The memory is provided to the
> > GSC as struct resource to the auxiliary data of the child device.
> >
> > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gsc.c | 92
> > ++++++++++++++++++++++++++--- drivers/gpu/drm/i915/gt/intel_gsc.h
> |
> > 3 +
> > 2 files changed, 88 insertions(+), 7 deletions(-)
> >
> > + if (def->lmem_size) {
> > + dev_dbg(&pdev->dev, "setting up GSC lmem\n");
> >
> NIT: Any reason we are not being consistent and using drm_err / drm_debug
> (same below)? either way, ensuring we get PCI device id info in the dmesg
> output we are good.
Thanks, will fix.
> > +
> > + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> > + dev_err(&pdev->dev, "setting up gsc extended
> operational memory failed\n");
> > + kfree(adev);
> > + goto fail;
> > + }
> > +
> > + adev->ext_op_mem.start =
> i915_gem_object_get_dma_address(intf->gem_obj, 0);
> > + adev->ext_op_mem.end = adev->ext_op_mem.start + def-
> >lmem_size;
> > + }
> > +
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [Intel-gfx] [v5, 13/14] drm/i915/gsc: allocate extended operational memory in LMEM
@ 2022-08-02 18:49 ` Winkler, Tomas
0 siblings, 0 replies; 46+ messages in thread
From: Winkler, Tomas @ 2022-08-02 18:49 UTC (permalink / raw)
To: Teres Alexis, Alan Previn, airlied, gregkh, Vivi, Rodrigo,
joonas.lahtinen, Usyskin, Alexander, tvrtko.ursulin, daniel,
jani.nikula
Cc: intel-gfx, linux-kernel, Lubart, Vitaly
>
> Looks good, just a minor nit.
>
> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
>
>
> On Wed, 2022-07-06 at 14:43 +0300, Alexander Usyskin wrote:
> > From: Tomas Winkler <tomas.winkler@intel.com>
> >
> > GSC requires more operational memory than available on chip.
> > Reserve 4M of LMEM for GSC operation. The memory is provided to the
> > GSC as struct resource to the auxiliary data of the child device.
> >
> > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Signed-off-by: Daniele Ceraolo Spurio
> > <daniele.ceraolospurio@intel.com>
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gsc.c | 92
> > ++++++++++++++++++++++++++--- drivers/gpu/drm/i915/gt/intel_gsc.h
> |
> > 3 +
> > 2 files changed, 88 insertions(+), 7 deletions(-)
> >
> > + if (def->lmem_size) {
> > + dev_dbg(&pdev->dev, "setting up GSC lmem\n");
> >
> NIT: Any reason we are not being consistent and using drm_err / drm_debug
> (same below)? either way, ensuring we get PCI device id info in the dmesg
> output we are good.
Thanks, will fix.
> > +
> > + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> > + dev_err(&pdev->dev, "setting up gsc extended
> operational memory failed\n");
> > + kfree(adev);
> > + goto fail;
> > + }
> > +
> > + adev->ext_op_mem.start =
> i915_gem_object_get_dma_address(intf->gem_obj, 0);
> > + adev->ext_op_mem.end = adev->ext_op_mem.start + def-
> >lmem_size;
> > + }
> > +
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH v5 14/14] HAX: drm/i915: force INTEL_MEI_GSC on for CI
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-06 11:43 ` Alexander Usyskin
-1 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: Tomas Winkler, Alexander Usyskin, Vitaly Lubart, intel-gfx,
linux-kernel, Daniele Ceraolo Spurio
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
After the new config option is merged we'll enable it by default in the
CI config, but for now just force it on via the i915 Kconfig so we can
get pre-merge CI results for it.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/Kconfig.debug | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..be4ef485d6c1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -48,6 +48,7 @@ config DRM_I915_DEBUG
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
+ select INTEL_MEI_GSC
select BROKEN # for prototype uAPI
default n
help
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] [PATCH v5 14/14] HAX: drm/i915: force INTEL_MEI_GSC on for CI
@ 2022-07-06 11:43 ` Alexander Usyskin
0 siblings, 0 replies; 46+ messages in thread
From: Alexander Usyskin @ 2022-07-06 11:43 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jani Nikula, Joonas Lahtinen, Rodrigo Vivi,
David Airlie, Daniel Vetter, Tvrtko Ursulin
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Tomas Winkler, Vitaly Lubart
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
After the new config option is merged we'll enable it by default in the
CI config, but for now just force it on via the i915 Kconfig so we can
get pre-merge CI results for it.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/Kconfig.debug | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..be4ef485d6c1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -48,6 +48,7 @@ config DRM_I915_DEBUG
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
+ select INTEL_MEI_GSC
select BROKEN # for prototype uAPI
default n
help
--
2.34.1
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GSC support for XeHP SDV and DG2 platforms (rev5)
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
` (14 preceding siblings ...)
(?)
@ 2022-07-06 12:03 ` Patchwork
-1 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2022-07-06 12:03 UTC (permalink / raw)
To: Alexander Usyskin; +Cc: intel-gfx
== Series Details ==
Series: GSC support for XeHP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/102339/
State : warning
== Summary ==
Error: dim checkpatch failed
063c66ed39c4 drm/i915/gsc: skip irq initialization if using polling
e199641a3bfd drm/i915/gsc: add slow_fw flag to the mei auxiliary device
3a3aef152444 drm/i915/gsc: add slow_fw flag to the gsc device definition
7183775ef399 drm/i915/gsc: add GSC XeHP SDV platform definition
ec13d3de378a mei: gsc: use polling instead of interrupts
7223884a32f3 mei: gsc: wait for reset thread on stop
6cf3605aef85 mei: extend timeouts on slow devices.
56873de7e258 mei: bus: export common mkhi definitions into a separate header
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 101 lines checked
6787036d81c1 mei: mkhi: add memory ready command
-:47: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#47: FILE: drivers/misc/mei/mkhi.h:54:
+ uint32_t flags;
total: 0 errors, 0 warnings, 1 checks, 29 lines checked
9517951c0ed6 mei: gsc: setup gsc extended operational memory
-:51: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'cldev->bus->pxp_mode != MEI_DEV_PXP_INIT'
#51: FILE: drivers/misc/mei/bus-fixup.c:257:
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ (cldev->bus->pxp_mode != MEI_DEV_PXP_INIT))
total: 0 errors, 0 warnings, 1 checks, 224 lines checked
ce035839905a mei: gsc: add transition to PXP mode in resume flow
b9184715fcd5 mei: debugfs: add pxp mode to devstate in debugfs
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#26: FILE: drivers/misc/mei/debugfs.c:91:
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
total: 1 errors, 0 warnings, 0 checks, 29 lines checked
0e4a7f81c549 drm/i915/gsc: allocate extended operational memory in LMEM
-:110: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#110: FILE: drivers/gpu/drm/i915/gt/intel_gsc.c:152:
+static void gsc_destroy_one(struct drm_i915_private *i915,
+ struct intel_gsc *gsc, unsigned int intf_id)
total: 0 errors, 0 warnings, 1 checks, 181 lines checked
ba0c192cac32 HAX: drm/i915: force INTEL_MEI_GSC on for CI
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for GSC support for XeHP SDV and DG2 platforms (rev5)
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
` (15 preceding siblings ...)
(?)
@ 2022-07-06 12:03 ` Patchwork
-1 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2022-07-06 12:03 UTC (permalink / raw)
To: Alexander Usyskin; +Cc: intel-gfx
== Series Details ==
Series: GSC support for XeHP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/102339/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for GSC support for XeHP SDV and DG2 platforms (rev5)
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
` (16 preceding siblings ...)
(?)
@ 2022-07-06 12:25 ` Patchwork
-1 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2022-07-06 12:25 UTC (permalink / raw)
To: Alexander Usyskin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10189 bytes --]
== Series Details ==
Series: GSC support for XeHP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/102339/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11850 -> Patchwork_102339v5
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/index.html
Participating hosts (47 -> 41)
------------------------------
Additional (1): fi-bxt-dsi
Missing (7): fi-ilk-m540 fi-hsw-4200u bat-adlm-1 bat-adlp-4 fi-ctg-p8600 bat-jsl-3 bat-rpls-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_102339v5:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload:
- {bat-rpls-2}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-rpls-2/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-rpls-2/igt@i915_module_load@reload.html
New tests
---------
New tests have been introduced between CI_DRM_11850 and Patchwork_102339v5:
### New IGT tests (9) ###
* igt@gem_exec_basic@basic@bcs0-lmem0:
- Statuses : 4 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_basic@basic@rcs0-lmem0:
- Statuses : 4 pass(s)
- Exec time: [0.00] s
* igt@gem_exec_basic@basic@vcs0-lmem0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@vcs1-lmem0:
- Statuses : 4 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@vecs0-lmem0:
- Statuses : 4 pass(s)
- Exec time: [0.0, 0.00] s
* igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a2:
- Statuses : 2 pass(s)
- Exec time: [0.62, 0.74] s
* igt@kms_flip@basic-flip-vs-modeset@d-hdmi-a2:
- Statuses : 2 pass(s)
- Exec time: [0.58, 0.73] s
* igt@kms_flip@basic-flip-vs-wf_vblank@d-hdmi-a2:
- Statuses : 2 pass(s)
- Exec time: [0.90, 1.16] s
* igt@kms_flip@basic-plain-flip@d-hdmi-a2:
- Statuses : 2 pass(s)
- Exec time: [0.62, 0.72] s
Known issues
------------
Here are the changes found in Patchwork_102339v5 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-bxt-dsi: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-bxt-dsi/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-bxt-dsi: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-bxt-dsi/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_blits@basic:
- fi-bxt-dsi: NOTRUN -> [SKIP][5] ([fdo#109271]) +12 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-bxt-dsi/igt@gem_tiled_blits@basic.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][6] -> [DMESG-FAIL][7] ([i915#4494] / [i915#4957])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][8] -> [DMESG-FAIL][9] ([i915#4528])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/fi-blb-e6850/igt@i915_selftest@live@requests.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bxt-dsi: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-bxt-dsi/igt@kms_chamelium@hdmi-edid-read.html
#### Possible fixes ####
* igt@fbdev@read:
- {bat-rpls-2}: [SKIP][11] ([i915#2582]) -> [PASS][12] +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-rpls-2/igt@fbdev@read.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-rpls-2/igt@fbdev@read.html
* igt@i915_selftest@live@client:
- {bat-dg2-9}: [DMESG-WARN][13] ([i915#5763]) -> [PASS][14] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-dg2-9/igt@i915_selftest@live@client.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-dg2-9/igt@i915_selftest@live@client.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [DMESG-WARN][15] ([i915#5904]) -> [PASS][16] +34 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [DMESG-WARN][17] ([i915#5904] / [i915#62]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@too-high:
- fi-cfl-8109u: [DMESG-WARN][19] ([i915#62]) -> [PASS][20] +82 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/fi-cfl-8109u/igt@kms_addfb_basic@too-high.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/fi-cfl-8109u/igt@kms_addfb_basic@too-high.html
* igt@kms_busy@basic@modeset:
- {bat-adln-1}: [DMESG-WARN][21] ([i915#3576]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-adln-1/igt@kms_busy@basic@modeset.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-adln-1/igt@kms_busy@basic@modeset.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][23] ([i915#3576]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
* igt@kms_frontbuffer_tracking@basic:
- {bat-rpls-2}: [SKIP][25] ([i915#1849]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-rpls-2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-fence-flip:
- {bat-rpls-2}: [SKIP][27] ([fdo#109295] / [i915#1845] / [i915#3708]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/bat-rpls-2/igt@prime_vgem@basic-fence-flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6297]: https://gitlab.freedesktop.org/drm/intel/issues/6297
Build changes
-------------
* Linux: CI_DRM_11850 -> Patchwork_102339v5
CI-20190529: 20190529
CI_DRM_11850: 295e0e9b3a5d5ef71096cfac07684be807f5a8c0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6555: 1a3ffecd400b8f82c35745fa2e07992f6bdeede2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102339v5: 295e0e9b3a5d5ef71096cfac07684be807f5a8c0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
fe489ff16e0f HAX: drm/i915: force INTEL_MEI_GSC on for CI
adc2e0cdff79 drm/i915/gsc: allocate extended operational memory in LMEM
a54cd3e5cf2e mei: debugfs: add pxp mode to devstate in debugfs
b7815328436b mei: gsc: add transition to PXP mode in resume flow
681b1fb79a65 mei: gsc: setup gsc extended operational memory
2f4363c50800 mei: mkhi: add memory ready command
255c14d51ae8 mei: bus: export common mkhi definitions into a separate header
2692a974ce85 mei: extend timeouts on slow devices.
8fb24855769d mei: gsc: wait for reset thread on stop
4112cc0582b4 mei: gsc: use polling instead of interrupts
51a3966a1c86 drm/i915/gsc: add GSC XeHP SDV platform definition
f1c2ac15a286 drm/i915/gsc: add slow_fw flag to the gsc device definition
38bfeba72c07 drm/i915/gsc: add slow_fw flag to the mei auxiliary device
a669e45687ca drm/i915/gsc: skip irq initialization if using polling
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/index.html
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^ permalink raw reply [flat|nested] 46+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for GSC support for XeHP SDV and DG2 platforms (rev5)
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
` (17 preceding siblings ...)
(?)
@ 2022-07-06 17:49 ` Patchwork
-1 siblings, 0 replies; 46+ messages in thread
From: Patchwork @ 2022-07-06 17:49 UTC (permalink / raw)
To: Alexander Usyskin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 61660 bytes --]
== Series Details ==
Series: GSC support for XeHP SDV and DG2 platforms (rev5)
URL : https://patchwork.freedesktop.org/series/102339/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11850_full -> Patchwork_102339v5_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_102339v5_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_102339v5_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 13)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_102339v5_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@flip-vs-cursor@varying-size:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html
New tests
---------
New tests have been introduced between CI_DRM_11850_full and Patchwork_102339v5_full:
### New IGT tests (2) ###
* igt@kms_atomic_transition@plane-all-transition-nonblocking@hdmi-a-2-pipe-a:
- Statuses : 1 pass(s)
- Exec time: [4.24] s
* igt@kms_atomic_transition@plane-all-transition-nonblocking@hdmi-a-2-pipe-b:
- Statuses : 1 pass(s)
- Exec time: [4.26] s
Known issues
------------
Here are the changes found in Patchwork_102339v5_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-skl: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [FAIL][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48]) ([i915#5032])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl7/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl7/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl7/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl6/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl6/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl6/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl5/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl5/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl4/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl4/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl3/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl3/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl2/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl2/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl1/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl1/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl1/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl10/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl10/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl10/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl7/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl7/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl7/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl6/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl5/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl5/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl4/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl3/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl3/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl2/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl2/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl10/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl10/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl10/boot.html
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][49], [PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [FAIL][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73]) ([i915#4392]) -> ([PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk6/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk8/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk8/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk7/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk7/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk3/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk5/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk5/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk7/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk5/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk6/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk6/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk1/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk1/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk1/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk2/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk2/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk2/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk9/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk9/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk9/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk3/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk9/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk3/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk8/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk3/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk1/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk1/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk1/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk2/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk8/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk8/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk8/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk7/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk7/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk7/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk6/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk6/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk6/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk5/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk5/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk5/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk2/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk3/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk2/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk3/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk3/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][99] -> [FAIL][100] ([i915#6268])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@hang:
- shard-skl: NOTRUN -> [SKIP][101] ([fdo#109271]) +119 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@gem_ctx_persistence@hang.html
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#280])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][103] -> [TIMEOUT][104] ([i915#3070])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb3/igt@gem_eio@unwedge-stress.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb3/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][105] -> [FAIL][106] ([i915#2842])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-tglb1/igt@gem_exec_fair@basic-none-share@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][107] -> [FAIL][108] ([i915#2842]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][109] -> [FAIL][110] ([i915#2842])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][111] ([i915#2842])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_whisper@basic-fds-priority-all:
- shard-glk: [PASS][112] -> [DMESG-WARN][113] ([i915#118])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk6/igt@gem_exec_whisper@basic-fds-priority-all.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk6/igt@gem_exec_whisper@basic-fds-priority-all.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#2190])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#4613]) +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-glk: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#4613])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-skl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#4613]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][118] ([i915#4613])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-kbl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#4613])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][120] ([i915#2658])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@evict-single-offset:
- shard-apl: NOTRUN -> [FAIL][121] ([i915#4171])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@gem_softpin@evict-single-offset.html
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: NOTRUN -> [DMESG-WARN][122] ([i915#180])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@gem_workarounds@suspend-resume-context.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-snb: [PASS][123] -> [SKIP][124] ([fdo#109271])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-snb2/igt@gem_workarounds@suspend-resume-fd.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-snb6/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][125] ([i915#2527] / [i915#2856])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][126] -> [DMESG-WARN][127] ([i915#1982])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl7/igt@i915_module_load@reload-with-fault-injection.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#1937])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: NOTRUN -> [SKIP][129] ([fdo#111644] / [i915#1397] / [i915#2411])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][130] -> [INCOMPLETE][131] ([i915#3921])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-snb5/igt@i915_selftest@live@hangcheck.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][132] -> [DMESG-WARN][133] ([i915#180]) +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][134] ([i915#5286]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][135] ([fdo#111615])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#3886]) +3 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#3886]) +3 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#3886]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#3886]) +2 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs:
- shard-kbl: NOTRUN -> [SKIP][140] ([fdo#109271]) +81 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_ccs@pipe-c-random-ccs-data-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][141] ([fdo#109271]) +59 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl7/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-apl: NOTRUN -> [SKIP][142] ([fdo#109271] / [fdo#111827]) +5 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][143] ([fdo#109271] / [fdo#111827]) +4 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271] / [fdo#111827]) +7 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-0-5:
- shard-kbl: NOTRUN -> [SKIP][145] ([fdo#109271] / [fdo#111827]) +6 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-0-5.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-tglb: NOTRUN -> [SKIP][146] ([fdo#109284] / [fdo#111827]) +3 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@srm:
- shard-tglb: NOTRUN -> [SKIP][147] ([i915#1063])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_content_protection@srm.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][148] -> [FAIL][149] ([i915#2346])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor@toggle:
- shard-iclb: [PASS][150] -> [FAIL][151] ([i915#2346]) +2 similar issues
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank:
- shard-tglb: NOTRUN -> [SKIP][152] ([fdo#109274] / [fdo#111825] / [i915#3637])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-tglb: NOTRUN -> [SKIP][153] ([i915#2672])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][154] ([i915#2672]) +3 similar issues
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][155] ([i915#3555])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
- shard-glk: [PASS][156] -> [FAIL][157] ([i915#1888] / [i915#2546])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
- shard-tglb: NOTRUN -> [SKIP][158] ([fdo#109280] / [fdo#111825]) +2 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][159] ([fdo#108145] / [i915#265])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][160] ([fdo#108145] / [i915#265])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][161] ([fdo#108145] / [i915#265])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][162] ([i915#265])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-2:
- shard-glk: NOTRUN -> [SKIP][163] ([fdo#109271]) +51 similar issues
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][164] -> [SKIP][165] ([i915#5235]) +2 similar issues
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb4/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-tglb: NOTRUN -> [SKIP][166] ([i915#2920])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][167] ([fdo#109271] / [i915#658])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][168] ([fdo#109271] / [i915#658]) +1 similar issue
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl10/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr2_su@page_flip-p010:
- shard-glk: NOTRUN -> [SKIP][169] ([fdo#109271] / [i915#658]) +1 similar issue
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-kbl: NOTRUN -> [SKIP][170] ([fdo#109271] / [i915#658])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][171] -> [SKIP][172] ([fdo#109441]) +2 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [PASS][173] -> [SKIP][174] ([i915#5519])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-tglb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb3/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
- shard-iclb: [PASS][175] -> [SKIP][176] ([i915#5519])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][177] ([IGT#2])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_sysfs_edid_timing.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][178] ([fdo#109271] / [i915#2437])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@kms_writeback@writeback-pixel-formats.html
* igt@sw_sync@sync_multi_timeline_wait:
- shard-apl: NOTRUN -> [FAIL][179] ([i915#6140])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@sw_sync@sync_multi_timeline_wait.html
* igt@sysfs_clients@fair-0:
- shard-glk: NOTRUN -> [SKIP][180] ([fdo#109271] / [i915#2994])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@recycle-many:
- shard-kbl: NOTRUN -> [SKIP][181] ([fdo#109271] / [i915#2994])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@split-25:
- shard-skl: NOTRUN -> [SKIP][182] ([fdo#109271] / [i915#2994])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl9/igt@sysfs_clients@split-25.html
* igt@sysfs_clients@split-50:
- shard-apl: NOTRUN -> [SKIP][183] ([fdo#109271] / [i915#2994])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [SKIP][184] ([i915#4525]) -> [PASS][185] +1 similar issue
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb7/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][186] ([i915#2842]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][188] ([i915#2842]) -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: [FAIL][190] ([i915#2842]) -> [PASS][191] +1 similar issue
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl4/igt@gem_exec_fair@basic-none@vcs1.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][192] ([i915#2842]) -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][194] ([i915#2849]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][196] ([i915#454]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [DMESG-WARN][198] ([i915#180]) -> [PASS][199] +2 similar issues
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@i915_suspend@debugfs-reader.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@i915_suspend@debugfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: [FAIL][200] ([i915#2521]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_cursor_legacy@cursor-vs-flip@toggle:
- shard-iclb: [FAIL][202] ([i915#5072]) -> [PASS][203]
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb5/igt@kms_cursor_legacy@cursor-vs-flip@toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][204] ([i915#2346]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [FAIL][206] ([i915#2122]) -> [PASS][207] +2 similar issues
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][208] ([i915#180]) -> [PASS][209] +2 similar issues
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl4/igt@kms_flip@flip-vs-suspend@a-dp1.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-dp1:
- shard-kbl: [FAIL][210] ([i915#2122]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-dp1.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [DMESG-WARN][212] ([i915#180] / [i915#1982]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-tglb: [INCOMPLETE][214] -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-tglb8/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb1/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-iclb: [SKIP][216] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][217]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb4/igt@kms_psr2_su@page_flip-xrgb8888.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb2/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [SKIP][218] ([fdo#109441]) -> [PASS][219] +1 similar issue
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb4/igt@kms_psr@psr2_sprite_blt.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][220] ([i915#1722]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl7/igt@perf@polling-small-buf.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/igt@perf@polling-small-buf.html
* igt@perf@stress-open-close:
- shard-glk: [INCOMPLETE][222] ([i915#5213]) -> [PASS][223]
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-glk3/igt@perf@stress-open-close.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-glk9/igt@perf@stress-open-close.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][224] ([i915#4525]) -> [FAIL][225] ([i915#6117])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: [FAIL][226] ([i915#2842]) -> [FAIL][227] ([i915#2849])
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-tglb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][228] ([i915#588]) -> [SKIP][229] ([i915#658])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-iclb: [WARN][230] ([i915#2684]) -> [FAIL][231] ([i915#2684])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc:
- shard-skl: [SKIP][232] ([fdo#109271]) -> [SKIP][233] ([fdo#109271] / [i915#1888])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl10/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl10/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][234] ([i915#2920]) -> [SKIP][235] ([i915#658]) +1 similar issue
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-iclb: [SKIP][236] ([i915#658]) -> [SKIP][237] ([i915#2920]) +1 similar issue
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb4/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][238] ([i915#2920]) -> [SKIP][239] ([fdo#111068] / [i915#658])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@perf_pmu@module-unload:
- shard-skl: [FAIL][240] ([i915#6054]) -> [DMESG-WARN][241] ([i915#1982])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-skl2/igt@perf_pmu@module-unload.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-skl1/igt@perf_pmu@module-unload.html
* igt@runner@aborted:
- shard-apl: ([FAIL][242], [FAIL][243], [FAIL][244], [FAIL][245], [FAIL][246]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][247], [FAIL][248]) ([i915#3002] / [i915#4312] / [i915#5257])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl1/igt@runner@aborted.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl4/igt@runner@aborted.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl8/igt@runner@aborted.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl4/igt@runner@aborted.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-apl4/igt@runner@aborted.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl8/igt@runner@aborted.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-apl6/igt@runner@aborted.html
- shard-kbl: ([FAIL][249], [FAIL][250], [FAIL][251], [FAIL][252], [FAIL][253], [FAIL][254], [FAIL][255], [FAIL][256], [FAIL][257], [FAIL][258], [FAIL][259], [FAIL][260], [FAIL][261], [FAIL][262], [FAIL][263], [FAIL][264]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][265], [FAIL][266], [FAIL][267], [FAIL][268], [FAIL][269], [FAIL][270], [FAIL][271], [FAIL][272], [FAIL][273], [FAIL][274], [FAIL][275], [FAIL][276], [FAIL][277], [FAIL][278]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@runner@aborted.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@runner@aborted.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl4/igt@runner@aborted.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@runner@aborted.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@runner@aborted.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@runner@aborted.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@runner@aborted.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl4/igt@runner@aborted.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@runner@aborted.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@runner@aborted.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl4/igt@runner@aborted.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@runner@aborted.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl4/igt@runner@aborted.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl1/igt@runner@aborted.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@runner@aborted.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11850/shard-kbl7/igt@runner@aborted.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl4/igt@runner@aborted.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl4/igt@runner@aborted.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@runner@aborted.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@runner@aborted.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@runner@aborted.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@runner@aborted.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl4/igt@runner@aborted.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@runner@aborted.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl4/igt@runner@aborted.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@runner@aborted.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@runner@aborted.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@runner@aborted.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl1/igt@runner@aborted.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/shard-kbl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4462]: https://gitlab.freedesktop.org/drm/intel/issues/4462
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6054]: https://gitlab.freedesktop.org/drm/intel/issues/6054
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6331]: https://gitlab.freedesktop.org/drm/intel/issues/6331
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
Build changes
-------------
* Linux: CI_DRM_11850 -> Patchwork_102339v5
CI-20190529: 20190529
CI_DRM_11850: 295e0e9b3a5d5ef71096cfac07684be807f5a8c0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6555: 1a3ffecd400b8f82c35745fa2e07992f6bdeede2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_102339v5: 295e0e9b3a5d5ef71096cfac07684be807f5a8c0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_102339v5/index.html
[-- Attachment #2: Type: text/html, Size: 61777 bytes --]
^ permalink raw reply [flat|nested] 46+ messages in thread* Re: [PATCH v5 00/14] GSC support for XeHP SDV and DG2 platforms
2022-07-06 11:43 ` [Intel-gfx] " Alexander Usyskin
@ 2022-07-08 13:34 ` Greg Kroah-Hartman
-1 siblings, 0 replies; 46+ messages in thread
From: Greg Kroah-Hartman @ 2022-07-08 13:34 UTC (permalink / raw)
To: Alexander Usyskin
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, David Airlie,
Daniel Vetter, Tvrtko Ursulin, Tomas Winkler, Vitaly Lubart,
intel-gfx, linux-kernel
On Wed, Jul 06, 2022 at 02:43:31PM +0300, Alexander Usyskin wrote:
> Add GSC support for XeHP SDV and DG2 platforms.
>
> The series includes changes for the mei driver:
> - add ability to use polling instead of interrupts
> - add ability to use extended timeouts
> - setup extended operational memory for GSC
>
> The series includes changes for the i915 driver:
> - allocate extended operational memory for GSC
> - GSC on XeHP SDV offsets and definitions
>
> Greg KH, please review and ACK the MEI patches.
> We are pushing these patches through gfx tree as
> the auxiliary device belongs there.
>
> V2: rebase over merged DG1 series and DG2 enablement patch,
> fix commit messages
>
> V3: rebase over latest tip
>
> V4: add missed changelog in pxp dbugfs patch
>
> V5: rebase over latest tip
> fix changelog in pxp dbugfs patch
> put HAX patch last to the ease of merging
You did more than just this from v4 to v5 :(
It's as if you want to make it hard to review these...
greg k-h
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Intel-gfx] [PATCH v5 00/14] GSC support for XeHP SDV and DG2 platforms
@ 2022-07-08 13:34 ` Greg Kroah-Hartman
0 siblings, 0 replies; 46+ messages in thread
From: Greg Kroah-Hartman @ 2022-07-08 13:34 UTC (permalink / raw)
To: Alexander Usyskin
Cc: David Airlie, intel-gfx, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
On Wed, Jul 06, 2022 at 02:43:31PM +0300, Alexander Usyskin wrote:
> Add GSC support for XeHP SDV and DG2 platforms.
>
> The series includes changes for the mei driver:
> - add ability to use polling instead of interrupts
> - add ability to use extended timeouts
> - setup extended operational memory for GSC
>
> The series includes changes for the i915 driver:
> - allocate extended operational memory for GSC
> - GSC on XeHP SDV offsets and definitions
>
> Greg KH, please review and ACK the MEI patches.
> We are pushing these patches through gfx tree as
> the auxiliary device belongs there.
>
> V2: rebase over merged DG1 series and DG2 enablement patch,
> fix commit messages
>
> V3: rebase over latest tip
>
> V4: add missed changelog in pxp dbugfs patch
>
> V5: rebase over latest tip
> fix changelog in pxp dbugfs patch
> put HAX patch last to the ease of merging
You did more than just this from v4 to v5 :(
It's as if you want to make it hard to review these...
greg k-h
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH v5 00/14] GSC support for XeHP SDV and DG2 platforms
2022-07-08 13:34 ` [Intel-gfx] " Greg Kroah-Hartman
@ 2022-07-08 13:57 ` Rodrigo Vivi
-1 siblings, 0 replies; 46+ messages in thread
From: Rodrigo Vivi @ 2022-07-08 13:57 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Alexander Usyskin, Jani Nikula, Joonas Lahtinen, David Airlie,
Daniel Vetter, Tvrtko Ursulin, Tomas Winkler, Vitaly Lubart,
intel-gfx, linux-kernel
On Fri, Jul 08, 2022 at 03:34:43PM +0200, Greg Kroah-Hartman wrote:
> On Wed, Jul 06, 2022 at 02:43:31PM +0300, Alexander Usyskin wrote:
> > Add GSC support for XeHP SDV and DG2 platforms.
> >
> > The series includes changes for the mei driver:
> > - add ability to use polling instead of interrupts
> > - add ability to use extended timeouts
> > - setup extended operational memory for GSC
> >
> > The series includes changes for the i915 driver:
> > - allocate extended operational memory for GSC
> > - GSC on XeHP SDV offsets and definitions
> >
> > Greg KH, please review and ACK the MEI patches.
> > We are pushing these patches through gfx tree as
> > the auxiliary device belongs there.
> >
> > V2: rebase over merged DG1 series and DG2 enablement patch,
> > fix commit messages
> >
> > V3: rebase over latest tip
> >
> > V4: add missed changelog in pxp dbugfs patch
> >
> > V5: rebase over latest tip
> > fix changelog in pxp dbugfs patch
> > put HAX patch last to the ease of merging
>
> You did more than just this from v4 to v5 :(
>
> It's as if you want to make it hard to review these...
I just checked the code and it looks the same to me.
well, yeap, changing the order of other commits during the rebase
was not mentioned. So we don't know the reason...
But at least now the HAX is the last patch what makes more sense.
But I don't believe this should block the review and require a v6
just to add this comment in the cover letter, or it should?
Rodrigo.
>
> greg k-h
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [Intel-gfx] [PATCH v5 00/14] GSC support for XeHP SDV and DG2 platforms
@ 2022-07-08 13:57 ` Rodrigo Vivi
0 siblings, 0 replies; 46+ messages in thread
From: Rodrigo Vivi @ 2022-07-08 13:57 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: David Airlie, intel-gfx, Alexander Usyskin, linux-kernel,
Tomas Winkler, Vitaly Lubart
On Fri, Jul 08, 2022 at 03:34:43PM +0200, Greg Kroah-Hartman wrote:
> On Wed, Jul 06, 2022 at 02:43:31PM +0300, Alexander Usyskin wrote:
> > Add GSC support for XeHP SDV and DG2 platforms.
> >
> > The series includes changes for the mei driver:
> > - add ability to use polling instead of interrupts
> > - add ability to use extended timeouts
> > - setup extended operational memory for GSC
> >
> > The series includes changes for the i915 driver:
> > - allocate extended operational memory for GSC
> > - GSC on XeHP SDV offsets and definitions
> >
> > Greg KH, please review and ACK the MEI patches.
> > We are pushing these patches through gfx tree as
> > the auxiliary device belongs there.
> >
> > V2: rebase over merged DG1 series and DG2 enablement patch,
> > fix commit messages
> >
> > V3: rebase over latest tip
> >
> > V4: add missed changelog in pxp dbugfs patch
> >
> > V5: rebase over latest tip
> > fix changelog in pxp dbugfs patch
> > put HAX patch last to the ease of merging
>
> You did more than just this from v4 to v5 :(
>
> It's as if you want to make it hard to review these...
I just checked the code and it looks the same to me.
well, yeap, changing the order of other commits during the rebase
was not mentioned. So we don't know the reason...
But at least now the HAX is the last patch what makes more sense.
But I don't believe this should block the review and require a v6
just to add this comment in the cover letter, or it should?
Rodrigo.
>
> greg k-h
^ permalink raw reply [flat|nested] 46+ messages in thread