* [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances
@ 2022-07-04 16:57 Thierry Reding
2022-07-04 16:57 ` [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema Thierry Reding
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Thierry Reding @ 2022-07-04 16:57 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Jon Hunter, Prathamesh Shete, Vidya Sagar, devicetree,
linux-tegra, linux-gpio
From: Thierry Reding <treding@nvidia.com>
This patch series changes the pin controller DT description on Tegra194
in order to properly describe how the hardware works. Currently a
simplified description is used that merges two pin controller instances
(called AON and main) into a single DT node. This has some disadvantages
such as creating a complicated mapping between the pins in those pin
controllers and the corresponding GPIO controllers (which are already
separated).
As a prerequisite, the first patch in this series converts the device
tree bindings to json-schema. A second patch then adds an additional
compatible string for the AON instance (along with more details about
each controller's pins) and finally patch 3 converts the driver to
cope with these changes. A fourth patch makes the corresponding
changes in the Tegra194 DTS file.
Note that while this changes the DT node in an incompatible way, this
doesn't have any practical implications for backwards-compatibility. The
reason for this is that device trees have only reconfigured a very
narrow subset of pins of the main controller, so the new driver will
remain backwards-compatible with old device trees.
Changes in v2:
- address Rob's review comments on the DT bindings
Thierry
Thierry Reding (4):
dt-bindings: pinctrl: tegra: Convert to json-schema
dt-bindings: pinctrl: tegra194: Separate instances
pinctrl: tegra: Separate Tegra194 instances
arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
.../bindings/clock/nvidia,tegra124-dfll.yaml | 2 +-
.../pinctrl/nvidia,tegra-pinmux-common.yaml | 195 ++++++++++++
.../pinctrl/nvidia,tegra114-pinmux.txt | 131 --------
.../pinctrl/nvidia,tegra114-pinmux.yaml | 162 ++++++++++
.../pinctrl/nvidia,tegra124-pinmux.txt | 153 ----------
.../pinctrl/nvidia,tegra124-pinmux.yaml | 182 +++++++++++
.../pinctrl/nvidia,tegra194-pinmux.txt | 107 -------
.../pinctrl/nvidia,tegra194-pinmux.yaml | 285 +++++++++++++++++
.../pinctrl/nvidia,tegra20-pinmux.txt | 143 ---------
.../pinctrl/nvidia,tegra20-pinmux.yaml | 107 +++++++
.../pinctrl/nvidia,tegra210-pinmux.txt | 166 ----------
.../pinctrl/nvidia,tegra210-pinmux.yaml | 146 +++++++++
.../pinctrl/nvidia,tegra30-pinmux.txt | 144 ---------
.../pinctrl/nvidia,tegra30-pinmux.yaml | 176 +++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 13 +-
drivers/pinctrl/tegra/pinctrl-tegra.c | 33 +-
drivers/pinctrl/tegra/pinctrl-tegra.h | 2 +
drivers/pinctrl/tegra/pinctrl-tegra194.c | 286 ++++++++++--------
18 files changed, 1437 insertions(+), 996 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
--
2.36.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema
2022-07-04 16:57 [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
@ 2022-07-04 16:57 ` Thierry Reding
2022-07-06 15:38 ` Rob Herring
2022-07-04 16:58 ` [PATCH v2 2/4] dt-bindings: pinctrl: tegra194: Separate instances Thierry Reding
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Thierry Reding @ 2022-07-04 16:57 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Jon Hunter, Prathamesh Shete, Vidya Sagar, devicetree,
linux-tegra, linux-gpio
From: Thierry Reding <treding@nvidia.com>
Convert the NVIDIA Tegra pinmux controller bindings from the free-form
text format to json-schema.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- wrap lines at 80 characters instead of the standard 100 characters in Linux
- use GPL-2.0-only instead of GPL-2.0+ license for DT bindings
- reorder additionalProperties for better readability
- move common definitions into a shared schema
- remove consumer snippets from examples
.../bindings/clock/nvidia,tegra124-dfll.yaml | 2 +-
.../pinctrl/nvidia,tegra-pinmux-common.yaml | 195 ++++++++++++++++++
.../pinctrl/nvidia,tegra114-pinmux.txt | 131 ------------
.../pinctrl/nvidia,tegra114-pinmux.yaml | 162 +++++++++++++++
.../pinctrl/nvidia,tegra124-pinmux.txt | 153 --------------
.../pinctrl/nvidia,tegra124-pinmux.yaml | 182 ++++++++++++++++
.../pinctrl/nvidia,tegra194-pinmux.txt | 107 ----------
.../pinctrl/nvidia,tegra194-pinmux.yaml | 88 ++++++++
.../pinctrl/nvidia,tegra20-pinmux.txt | 143 -------------
.../pinctrl/nvidia,tegra20-pinmux.yaml | 107 ++++++++++
.../pinctrl/nvidia,tegra210-pinmux.txt | 166 ---------------
.../pinctrl/nvidia,tegra210-pinmux.yaml | 146 +++++++++++++
.../pinctrl/nvidia,tegra30-pinmux.txt | 144 -------------
.../pinctrl/nvidia,tegra30-pinmux.yaml | 176 ++++++++++++++++
14 files changed, 1057 insertions(+), 845 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
index 85234a48b590..96c54c215f77 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
@@ -219,7 +219,7 @@ examples:
/*
* pinmux nodes added for completeness. Binding doc can be found in:
- * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
+ * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
*/
pinmux: pinmux@700008d4 {
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
new file mode 100644
index 000000000000..cb6b722b89af
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
@@ -0,0 +1,195 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jonathan Hunter <jonathanh@nvidia.com>
+
+definitions:
+ pinconf-node:
+ type: object
+ description: |
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of
+ the phrase "pin configuration node".
+
+ Tegra's pin configuration nodes act as a container for an arbitrary number
+ of subnodes. Each of these subnodes represents some desired configuration
+ for a pin, a group, or a list of pins or groups. This configuration can
+ include the mux function to select on those pin(s)/ group(s), and various
+ pin configuration parameters, such as pull-up, tristate, drive strength,
+ etc.
+
+ The name of each subnode is not important; all subnodes should be
+ enumerated and processed purely based on their content.
+
+ Each subnode only affects those parameters that are explicitly listed. In
+ other words, a subnode that lists a mux function but no pin configuration
+ parameters implies no information about any pin configuration parameters.
+
+ Similarly, a pin subnode that describes a pullup parameter implies no
+ information about e.g. the mux function or tristate parameter. For this
+ reason, even seemingly boolean values are actually tristates in this
+ binding: unspecified, off, or on. Unspecified is represented as an absent
+ property, and off/on are represented as integer values 0 and 1.
+
+ Note that many of these properties are only valid for certain specific pins
+ or groups. See the Tegra TRM and various pinmux spreadsheets for complete
+ details regarding which groups support which functionality. The Linux
+ pinctrl driver may also be a useful reference, since it consolidates,
+ disambiguates, and corrects data from all those sources.
+
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ type: object
+ properties:
+ nvidia,pins:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: An array of strings. Each string contains the name of
+ a pin or group. Valid values for these names are listed below.
+
+ nvidia,function:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: A string containing the name of the function to mux to
+ the pin or group. Valid values for function names are listed
+ below. See the Tegra TRM to determine which are valid for each
+ pin or group.
+
+ nvidia,pull:
+ description: Pull-down/up setting to apply to the pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: none
+ const: 0
+ - description: down
+ const: 1
+ - description: up
+ const: 2
+
+ nvidia,tristate:
+ description: Tristate setting to apply to the pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: drive
+ const: 0
+ - description: tristate
+ const: 1
+
+ nvidia,schmitt:
+ description: Enable Schmitt trigger on the input.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: disable Schmitt trigger on the input
+ const: 0
+ - description: enable Schmitt trigger on the input
+ const: 1
+
+ nvidia,pull-down-strength:
+ description: Controls drive strength. 0 is weakest. The range of
+ valid values depends on the pingroup. See "CAL_DRVDN" in the
+ Tegra TRM.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ nvidia,pull-up-strength:
+ description: Controls drive strength. 0 is weakest. The range of
+ valid values depends on the pingroup. See "CAL_DRVUP" in the
+ Tegra TRM.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ high-speed-mode:
+ description: Enable high speed mode the pins.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: normal speed mode
+ const: 0
+ - description: high speed mode
+ const: 1
+
+ low-power-mode:
+ description: Controls the drive power or current. Valid values are
+ from 0 through 3, where 0 specifies the least power and 3 specifies
+ the most power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the
+ Tegra TRM.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2, 3 ]
+
+ enable-input:
+ description: Enable the pin's input path.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: disable input (i.e. output only)
+ const: 0
+ - description: enable input
+ const: 1
+
+ open-drain:
+ description: Open-drain configuration for the pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: disable open-drain
+ const: 0
+ - description: enable open-drain
+ const: 1
+
+ lock:
+ description: Lock the pin configuration against further changes until
+ reset.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: disable pin configuration lock
+ const: 0
+ - description: enable pin configuration lock
+ const: 1
+
+ io-reset:
+ description: reset the I/O path
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+
+ rcv-sel:
+ description: select VIL/VIH receivers
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: normal receivers
+ const: 0
+ - description: high-voltage receivers
+ const: 1
+
+ drive-type:
+ description: Drive type to configure for the pin.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2, 3 ]
+
+ io-hv:
+ description: Select high-voltage receivers.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ oneOf:
+ - description: Use normal receivers.
+ const: 0
+ - description: Use high-voltage receivers.
+ const: 1
+
+ slew-rate-rising:
+ description: Controls rising signal slew rate. 0 is fastest. The
+ range of valid values depends on the pingroup. See "DRVDN_SLWR" in
+ the Tegra TRM.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ slew-rate-falling:
+ description: Controls falling signal slew rate. 0 is fastest. The
+ range of valid values depends on the pingroup. See "DRVUP_SLWF" in
+ the Tegra TRM.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+properties:
+ reg:
+ minItems: 1
+ maxItems: 4
+
+additionalProperties: true
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
deleted file mode 100644
index fb70856c5b51..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
+++ /dev/null
@@ -1,131 +0,0 @@
-NVIDIA Tegra114 pinmux controller
-
-The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
-pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
-nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
-a baseline, and only documents the differences between the two bindings.
-
-Required properties:
-- compatible: "nvidia,tegra114-pinmux"
-- reg: Should contain the register physical address and length for each of
- the pad control and mux registers. The first bank of address must be the
- driver strength pad control register address and second bank address must
- be pinmux register address.
-
-Tegra114 adds the following optional properties for pin configuration subnodes:
-- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
-- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
-- nvidia,lock: Integer. Lock the pin configuration against further changes
- until reset. 0: no, 1: yes.
-- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
-- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
-- nvidia,drive-type: Integer. Valid range 0...3.
-
-As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
-which groups support which functionality.
-
-Valid values for pin and group names are:
-
- per-pin mux groups:
-
- These all support nvidia,function, nvidia,tristate, nvidia,pull,
- nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
- nvidia,io-reset and nvidia,rcv-sel.
-
- ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
- ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
- ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
- dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
- sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
- sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
- ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
- uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
- uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
- gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
- clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
- gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
- gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
- gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
- gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
- gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
- gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
- gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
- gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
- sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
- sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
- pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
- pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
- kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
- kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
- kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
- kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
- cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
- dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
- dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
- gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
- gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
- sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
- sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
- gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
- sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
-
- drive groups:
-
- These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
- nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
- support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
- and nvidia,drive-type.
-
- ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
- dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
- gmh, owr, uda.
-
-Valid values for nvidia,functions are:
-
- blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
- displaya_alt, displayb, dtv, emc_dll, extperiph1, extperiph2,
- extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr,
- i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, nand, nand_alt, owr, pmi,
- pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, rsvd2, rsvd3,
- rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3,
- spi4, spi5, spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi,
- usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3
-
-Example:
-
- pinmux: pinmux {
- compatible = "nvidia,tegra114-pinmux";
- reg = <0x70000868 0x148 /* Pad control registers */
- 0x70003000 0x40c>; /* PinMux registers */
- };
-
-Example board file extract:
-
- pinctrl {
- sdmmc4_default: pinmux {
- sdmmc4_clk_pcc4 {
- nvidia,pins = "sdmmc4_clk_pcc4",
- nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc4_dat0_paa0 {
- nvidia,pins = "sdmmc4_dat0_paa0",
- "sdmmc4_dat1_paa1",
- "sdmmc4_dat2_paa2",
- "sdmmc4_dat3_paa3",
- "sdmmc4_dat4_paa4",
- "sdmmc4_dat5_paa5",
- "sdmmc4_dat6_paa6",
- "sdmmc4_dat7_paa7";
- nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- };
- };
-
- sdhci@78000400 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc4_default>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
new file mode 100644
index 000000000000..e0a3f58b5535
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra114 pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra114-pinmux
+
+ reg:
+ items:
+ - description: pad control registers
+ - description: mux registers
+
+additionalProperties:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ additionalProperties: false
+ properties:
+ nvidia,pins:
+ items:
+ enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
+ ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+ ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
+ ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
+ dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
+ sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
+ sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
+ clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
+ uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
+ uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
+ uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
+ pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4,
+ dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
+ clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
+ gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2,
+ gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3,
+ gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
+ gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
+ gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+ gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
+ gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1,
+ gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3,
+ gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+ sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
+ sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
+ sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
+ sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
+ cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
+ pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0,
+ kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4,
+ kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0,
+ kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1,
+ kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+ kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5,
+ core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0,
+ dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2,
+ clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2,
+ dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
+ gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
+ gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
+ gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
+ sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
+ sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
+ sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3,
+ usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5,
+ sdmmc3_clk_lb_out_pee4, reset_out_n,
+ # drive groups
+ drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
+ drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
+ drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
+ drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
+ drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
+ drive_gmg, drive_gmh, drive_owr, drive_uda ]
+
+ nvidia,function:
+ enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
+ displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1,
+ extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
+ i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
+ nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron,
+ reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2,
+ sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5,
+ spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb,
+ vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ]
+
+ nvidia,enable-input:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
+
+ nvidia,open-drain:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
+
+ nvidia,lock:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
+
+ nvidia,io-reset:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-reset'
+
+ nvidia,rcv-sel:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/rcv-sel'
+
+ nvidia,high-speed-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
+
+ nvidia,low-power-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/low-power-mode'
+
+ nvidia,drive-type:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/drive-type'
+
+ nvidia,slew-rate-rising:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
+
+ nvidia,slew-rate-falling:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
+
+ required:
+ - nvidia,pins
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ pinmux@70000868 {
+ compatible = "nvidia,tegra114-pinmux";
+ reg = <0x70000868 0x148>, /* Pad control registers */
+ <0x70003000 0x40c>; /* PinMux registers */
+
+ pinmux {
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
deleted file mode 100644
index f4d06bb0b55a..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
+++ /dev/null
@@ -1,153 +0,0 @@
-NVIDIA Tegra124 pinmux controller
-
-The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30
-pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
-nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
-a baseline, and only documents the differences between the two bindings.
-
-Required properties:
-- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
- Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
-- reg: Should contain a list of base address and size pairs for:
- -- first entry - the drive strength and pad control registers.
- -- second entry - the pinmux registers
- -- third entry - the MIPI_PAD_CTRL register
-
-Tegra124 adds the following optional properties for pin configuration subnodes.
-The macros for options are defined in the
- include/dt-binding/pinctrl/pinctrl-tegra.h.
-- nvidia,enable-input: Integer. Enable the pin's input path.
- enable :TEGRA_PIN_ENABLE and
- disable or output only: TEGRA_PIN_DISABLE.
-- nvidia,open-drain: Integer.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,lock: Integer. Lock the pin configuration against further changes
- until reset.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,io-reset: Integer. Reset the IO path.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
- normal: TEGRA_PIN_DISABLE
- high: TEGRA_PIN_ENABLE
-
-Please refer the Tegra TRM for complete details regarding which groups
-support which functionality.
-
-Valid values for pin and group names are:
-
- per-pin mux groups:
-
- These all support nvidia,function, nvidia,tristate, nvidia,pull,
- nvidia,enable-input. Some support nvidia,lock nvidia,open-drain,
- nvidia,io-reset and nvidia,rcv-sel.
-
- ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
- ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
- ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
- dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
- sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
- sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
- ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
- uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
- uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4,
- gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6,
- dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1,
- pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6,
- pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
- pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4,
- sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2,
- sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
- sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1,
- cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck,
- pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
- kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
- kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
- kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1,
- kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6,
- kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
- clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
- dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6,
- spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3,
- dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
- gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7,
- sdmmc3_clk_pa6, sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6,
- sdmmc3_dat2_pb5, sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1,
- pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, pex_l1_rst_n_pdd5,
- pex_l1_clkreq_n_pdd6, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
- sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
- usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, sdmmc3_clk_lb_in_pee5,
- gmi_clk_lb, reset_out_n, kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1,
- pff2, dp_hpd_pff0,
-
- drive groups:
-
- These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
- nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
- support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
- and nvidia,drive-type.
-
- ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
- dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
- gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
-
- MIPI pad control groups:
-
- These support only the nvidia,function property.
-
- dsi_b
-
-Valid values for nvidia,functions are:
-
- blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
- displaya_alt, displayb, dtv, extperiph1, extperiph2, extperiph3,
- gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0,
- i2s1, i2s2, i2s3, i2s4, irda, kbc, owr, pmi, pwm0, pwm1, pwm2, pwm3,
- pwron, reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3,
- sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
- uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
- vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
- dp, rtck, sys, clk tmds, csi, dsi_b
-
-Example:
-
- pinmux: pinmux {
- compatible = "nvidia,tegra124-pinmux";
- reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
- <0x0 0x70003000 0x0 0x434>, /* Mux registers */
- <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
- };
-
-Example pinmux entries:
-
- pinctrl {
- sdmmc4_default: pinmux {
- sdmmc4_clk_pcc4 {
- nvidia,pins = "sdmmc4_clk_pcc4",
- nvidia,function = "sdmmc4";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- };
-
- sdmmc4_dat0_paa0 {
- nvidia,pins = "sdmmc4_dat0_paa0",
- "sdmmc4_dat1_paa1",
- "sdmmc4_dat2_paa2",
- "sdmmc4_dat3_paa3",
- "sdmmc4_dat4_paa4",
- "sdmmc4_dat5_paa5",
- "sdmmc4_dat6_paa6",
- "sdmmc4_dat7_paa7";
- nvidia,function = "sdmmc4";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- };
- };
- };
-
- sdhci@78000400 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc4_default>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
new file mode 100644
index 000000000000..7b0336cfa684
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra124 Pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+description: The Tegra124 pinctrl binding is very similar to the Tegra20 and
+ Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
+ nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
+ baseline, and only documents the differences between the two bindings.
+
+properties:
+ compatible:
+ oneOf:
+ - const: nvidia,tegra124-pinmux
+ - items:
+ - const: nvidia,tegra132-pinmux
+ - const: nvidia,tegra124-pinmux
+
+ reg:
+ items:
+ - description: driver strength and pad control registers
+ - description: pinmux registers
+ - description: MIPI_PAD_CTRL registers
+
+additionalProperties:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ additionalProperties: false
+ properties:
+ nvidia,pins:
+ items:
+ enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
+ ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
+ ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
+ ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
+ dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
+ sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
+ sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
+ clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
+ uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
+ uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
+ uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
+ pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4,
+ dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
+ clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4,
+ pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0,
+ ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
+ pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
+ sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
+ sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
+ sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
+ sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
+ cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
+ pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7,
+ kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3,
+ kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
+ kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3,
+ kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7,
+ kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3,
+ kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7,
+ clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
+ clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
+ dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4,
+ spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4,
+ dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
+ gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
+ gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
+ gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
+ sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
+ sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
+ pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6,
+ hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
+ gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
+ usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4,
+ sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n,
+ kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2,
+ dp_hpd_pff0,
+ # drive groups
+ drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
+ drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
+ drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
+ drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
+ drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
+ drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv,
+ drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3,
+ drive_ao0, drive_hv0, drive_sdio4, drive_ao4,
+ # MIPI pad control groups
+ mipi_pad_ctrl_dsi_b ]
+
+ nvidia,function:
+ enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
+ displaya, displaya_alt, displayb, dtv, extperiph1,
+ extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
+ i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
+ owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1,
+ rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc,
+ spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
+ uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
+ vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla,
+ pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ]
+
+ nvidia,enable-input:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
+
+ nvidia,open-drain:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
+
+ nvidia,lock:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
+
+ nvidia,io-reset:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-reset'
+
+ nvidia,rcv-sel:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/rcv-sel'
+
+ nvidia,high-speed-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
+
+ nvidia,low-power-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/low-power-mode'
+
+ nvidia,drive-type:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/drive-type'
+
+ nvidia,slew-rate-rising:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
+
+ nvidia,slew-rate-falling:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
+
+ required:
+ - nvidia,pins
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra124-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+ pinmux@70000868 {
+ compatible = "nvidia,tegra124-pinmux";
+ reg = <0x70000868 0x164>, /* Pad control registers */
+ <0x70003000 0x434>, /* Mux registers */
+ <0x70000820 0x8>; /* MIPI pad control */
+
+ sdmmc4_default: pinmux {
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
deleted file mode 100644
index 90d38f710635..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-NVIDIA Tegra194 pinmux controller
-
-Required properties:
-- compatible: "nvidia,tegra194-pinmux"
-- reg: Should contain a list of base address and size pairs for:
- - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
- - second entry: The PINMUX_AUX_* registers (pinmux)
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Tegra's pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, tristate, drive strength, etc.
-
-See the TRM to determine which properties and values apply to each pin/group.
-Macro values for property values are defined in
-include/dt-binding/pinctrl/pinctrl-tegra.h.
-
-Required subnode-properties:
-- nvidia,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- nvidia,function: A string containing the name of the function to mux to the
- pin or group.
-- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
- 0: none, 1: down, 2: up.
-- nvidia,tristate: Integer.
- 0: drive, 1: tristate.
-- nvidia,enable-input: Integer. Enable the pin's input path.
- enable :TEGRA_PIN_ENABLE and
- disable or output only: TEGRA_PIN_DISABLE.
-- nvidia,open-drain: Integer.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,lock: Integer. Lock the pin configuration against further changes
- until reset.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,io-hv: Integer. Select high-voltage receivers.
- normal: TEGRA_PIN_DISABLE
- high: TEGRA_PIN_ENABLE
-- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
- normal: TEGRA_PIN_DISABLE
- high: TEGRA_PIN_ENABLE
-- nvidia,drive-type: Integer. Valid range 0...3.
-- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
- The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
- Tegra TRM.
-- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
- The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
- Tegra TRM.
-
-Valid values for pin and group names (nvidia,pin) are:
-
- These correspond to Tegra PADCTL_* (pinmux) registers.
-
- Mux groups:
-
- These correspond to Tegra PADCTL_* (pinmux) registers. Any property
- that exists in those registers may be set for the following pin names.
-
- pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
-
- Drive groups:
-
- These registers controls a single pin for which a mux group exists.
- See the list above for the pin name to use when configuring the pinmux.
-
- pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
-
-Valid values for nvidia,functions are:
-
- pe5
-
-Power Domain:
- pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 are part of PCIE C5 power
- partition. Client devices must enable this partition before accessing
- these pins here.
-
-
-Example:
-
- tegra_pinctrl: pinmux: pinmux@2430000 {
- compatible = "nvidia,tegra194-pinmux";
- reg = <0x2430000 0x17000
- 0xc300000 0x4000>;
-
- pinctrl-names = "pex_rst";
- pinctrl-0 = <&pex_rst_c5_out_state>;
-
- pex_rst_c5_out_state: pex_rst_c5_out {
- pex_rst {
- nvidia,pins = "pex_l5_rst_n_pgg1";
- nvidia,schmitt = <TEGRA_PIN_DISABLE>;
- nvidia,lpdr = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,io-hv = <TEGRA_PIN_ENABLE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
new file mode 100644
index 000000000000..322e146d52dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 Pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra194-pinmux
+
+ reg:
+ items:
+ - description: APB_MISC_GP_*_PADCTRL registers (pad control)
+ - description: PINMUX_AUX_* registers (pinmux)
+
+additionalProperties:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ additionalProperties: false
+ properties:
+ nvidia,pins:
+ description: An array of strings. Each string contains the name of a
+ pin or group. Valid values for these names are listed below.
+
+ Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins are
+ part of PCIE C5 power partition. Client devices must enable this
+ partition before accessing the configuration for these pins.
+ items:
+ enum: [ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
+ # drive groups
+ drive_pex_l5_clkreq_n_pgg0, drive_pex_l5_rst_n_pgg1 ]
+
+ nvidia,function:
+ enum: [ pe5 ]
+
+ nvidia,enable-input:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
+
+ nvidia,open-drain:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
+
+ nvidia,lock:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
+
+ nvidia,io-hv:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-hv'
+
+ nvidia,drive-type:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/drive-type'
+
+ required:
+ - nvidia,pins
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+ pinmux@2430000 {
+ compatible = "nvidia,tegra194-pinmux";
+ reg = <0x2430000 0x17000>,
+ <0xc300000 0x04000>;
+
+ pinctrl-names = "pex_rst";
+ pinctrl-0 = <&pex_rst_c5_out_state>;
+
+ pex_rst_c5_out_state: pex_rst_c5_out {
+ pex_rst {
+ nvidia,pins = "pex_l5_rst_n_pgg1";
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
deleted file mode 100644
index 3c8ce28baad6..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
+++ /dev/null
@@ -1,143 +0,0 @@
-NVIDIA Tegra20 pinmux controller
-
-Required properties:
-- compatible: "nvidia,tegra20-pinmux"
-- reg: Should contain the register physical address and length for each of
- the tri-state, mux, pull-up/down, and pad control register sets.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Tegra's pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, tristate, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function or tristate parameter. For this
-reason, even seemingly boolean values are actually tristates in this binding:
-unspecified, off, or on. Unspecified is represented as an absent property,
-and off/on are represented as integer values 0 and 1.
-
-Required subnode-properties:
-- nvidia,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- nvidia,function: A string containing the name of the function to mux to the
- pin or group. Valid values for function names are listed below. See the Tegra
- TRM to determine which are valid for each pin or group.
-- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
- 0: none, 1: down, 2: up.
-- nvidia,tristate: Integer.
- 0: drive, 1: tristate.
-- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
- 0: no, 1: yes.
-- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
- 0: no, 1: yes.
-- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
- most power. Controls the drive power or current. See "Low Power Mode"
- or "LPMD1" and "LPMD0" in the Tegra TRM.
-- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
- The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
- Tegra TRM.
-- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
- The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
- Tegra TRM.
-- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
- fastest. The range of valid values depends on the pingroup. See
- "DRVDN_SLWR" in the Tegra TRM.
-- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
- fastest. The range of valid values depends on the pingroup. See
- "DRVUP_SLWF" in the Tegra TRM.
-
-Note that many of these properties are only valid for certain specific pins
-or groups. See the Tegra TRM and various pinmux spreadsheets for complete
-details regarding which groups support which functionality. The Linux pinctrl
-driver may also be a useful reference, since it consolidates, disambiguates,
-and corrects data from all those sources.
-
-Valid values for pin and group names are:
-
- mux groups:
-
- These all support nvidia,function, nvidia,tristate, and many support
- nvidia,pull.
-
- ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
- ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
- gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
- ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
- ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
- lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
- owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
- spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
- uca, ucb, uda.
-
- tristate groups:
-
- These only support nvidia,pull.
-
- ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
- ld19_18, ld21_20, ld23_22.
-
- drive groups:
-
- With some exceptions, these support nvidia,high-speed-mode,
- nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
- nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
-
- drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
- drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
- drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
- drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
- drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
- drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
- drive_uda.
-
-Valid values for nvidia,functions are:
-
- ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5,
- displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int,
- hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
- osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3,
- pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck,
- sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt,
- spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
- vi, vi_sensor_clk, xio
-
-Example:
-
- pinctrl@70000000 {
- compatible = "nvidia,tegra20-pinmux";
- reg = < 0x70000014 0x10 /* Tri-state registers */
- 0x70000080 0x20 /* Mux registers */
- 0x700000a0 0x14 /* Pull-up/down registers */
- 0x70000868 0xa8 >; /* Pad control registers */
- };
-
-Example board file extract:
-
- pinctrl@70000000 {
- sdio4_default: sdio4_default {
- atb {
- nvidia,pins = "atb", "gma", "gme";
- nvidia,function = "sdio4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- };
- };
-
- sdhci@c8000600 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdio4_default>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
new file mode 100644
index 000000000000..caa4df68ad0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra20 Pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra20-pinmux
+
+ reg:
+ items:
+ - description: tri-state registers
+ - description: mux register
+ - description: pull-up/down registers
+ - description: pad control registers
+
+additionalProperties:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ additionalProperties: false
+ properties:
+ nvidia,pins:
+ items:
+ enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1,
+ dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
+ gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx,
+ irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1,
+ ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
+ ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2,
+ lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck,
+ lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb,
+ sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia,
+ spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac,
+ uad, uca, ucb, uda,
+ # tristate groups
+ ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
+ lc, ld17_0, ld19_18, ld21_20, ld23_22,
+ # drive groups
+ drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1,
+ drive_cdev2, drive_csus, drive_dap1, drive_dap2,
+ drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2,
+ drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
+ drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2,
+ drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk,
+ drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb,
+ drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ]
+
+ nvidia,function:
+ enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4,
+ dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi,
+ gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio,
+ mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1,
+ pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
+ pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2,
+ sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3,
+ spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
+ vi, vi_sensor_clk, xio ]
+
+ nvidia,high-speed-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
+
+ nvidia,low-power-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/low-power-mode'
+
+ nvidia,slew-rate-rising:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
+
+ nvidia,slew-rate-falling:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
+
+ required:
+ - nvidia,pins
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra20-car.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pinctrl@70000000 {
+ compatible = "nvidia,tegra20-pinmux";
+ reg = <0x70000014 0x10>, /* Tri-state registers */
+ <0x70000080 0x20>, /* Mux registers */
+ <0x700000a0 0x14>, /* Pull-up/down registers */
+ <0x70000868 0xa8>; /* Pad control registers */
+
+ pinmux {
+ atb {
+ nvidia,pins = "atb", "gma", "gme";
+ nvidia,function = "sdio4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
deleted file mode 100644
index 85f211436b8e..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
+++ /dev/null
@@ -1,166 +0,0 @@
-NVIDIA Tegra210 pinmux controller
-
-Required properties:
-- compatible: "nvidia,tegra210-pinmux"
-- reg: Should contain a list of base address and size pairs for:
- - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
- - second entry: The PINMUX_AUX_* registers (pinmux)
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Tegra's pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, tristate, drive strength, etc.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function or tristate parameter. For this
-reason, even seemingly boolean values are actually tristates in this binding:
-unspecified, off, or on. Unspecified is represented as an absent property,
-and off/on are represented as integer values 0 and 1.
-
-See the TRM to determine which properties and values apply to each pin/group.
-Macro values for property values are defined in
-include/dt-binding/pinctrl/pinctrl-tegra.h.
-
-Required subnode-properties:
-- nvidia,pins : An array of strings. Each string contains the name of a pin or
- group. Valid values for these names are listed below.
-
-Optional subnode-properties:
-- nvidia,function: A string containing the name of the function to mux to the
- pin or group.
-- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
- 0: none, 1: down, 2: up.
-- nvidia,tristate: Integer.
- 0: drive, 1: tristate.
-- nvidia,enable-input: Integer. Enable the pin's input path.
- enable :TEGRA_PIN_ENABLE and
- disable or output only: TEGRA_PIN_DISABLE.
-- nvidia,open-drain: Integer.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,lock: Integer. Lock the pin configuration against further changes
- until reset.
- enable: TEGRA_PIN_ENABLE.
- disable: TEGRA_PIN_DISABLE.
-- nvidia,io-hv: Integer. Select high-voltage receivers.
- normal: TEGRA_PIN_DISABLE
- high: TEGRA_PIN_ENABLE
-- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
- normal: TEGRA_PIN_DISABLE
- high: TEGRA_PIN_ENABLE
-- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
- normal: TEGRA_PIN_DISABLE
- high: TEGRA_PIN_ENABLE
-- nvidia,drive-type: Integer. Valid range 0...3.
-- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
- The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
- Tegra TRM.
-- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
- The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
- Tegra TRM.
-- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
- fastest. The range of valid values depends on the pingroup. See
- "DRVDN_SLWR" in the Tegra TRM.
-- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
- fastest. The range of valid values depends on the pingroup. See
- "DRVUP_SLWF" in the Tegra TRM.
-
-Valid values for pin and group names (nvidia,pin) are:
-
- Mux groups:
-
- These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property
- that exists in those registers may be set for the following pin names.
-
- In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL
- register. Where that is true, and property that exists in that register
- may also be set on the following pin names.
-
- als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, ap_wake_nfc_ph7,
- aud_mclk_pbb0, batt_bcl, bt_rst_ph4, bt_wake_ap_ph5, button_home_py1,
- button_power_on_px5, button_slide_sw_py0, button_vol_down_px7,
- button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, cam1_strobe_pt1,
- cam2_mclk_ps1, cam2_pwdn_pt0, cam_af_en_ps5, cam_flash_en_ps6,
- cam_i2c_scl_ps2, cam_i2c_sda_ps3, cam_rst_ps4cam_rst_ps4, clk_32k_in,
- clk_32k_out_py5, clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
- dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, dap2_dout_paa3,
- dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, dap4_dout_pj6, dap4_fs_pj4,
- dap4_sclk_pj7, dmic1_clk_pe0, dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3,
- dmic3_clk_pe4, dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
- gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, gen2_i2c_sda_pj3,
- gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, gpio_x1_aud_pbb3, gpio_x3_aud_pbb4,
- gps_en_pi2, gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, jtag_rtck,
- lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, lcd_gpio2_pv4, lcd_rst_pv2,
- lcd_te_py2, modem_wake_ap_px0, motion_int_px2, nfc_en_pi0, nfc_int_pi1,
- pa6, pcc7, pe6, pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
- pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, pk0, pk1, pk2,
- pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4,
- pwr_int_n, pz0, pz1, pz2, pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
- qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
- sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, sdmmc1_dat0_pm5,
- sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, sdmmc1_dat3_pm2, sdmmc3_clk_pp0,
- sdmmc3_cmd_pp1, sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
- sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, spi1_cs0_pc3,
- spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, spi1_sck_pc2, spi2_cs0_pb7,
- spi2_cs1_pdd0, spi2_miso_pb5, spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6,
- spi4_miso_pd0, spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
- touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, uart1_rx_pu1,
- uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, uart2_rx_pg1, uart2_tx_pg0,
- uart3_cts_pd4, uart3_rts_pd3, uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7,
- uart4_rts_pi6, uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
- usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, wifi_wake_ap_ph2
-
- Drive groups:
-
- These correspond to the Tegra APB_MISC_GP_*_PADCTRL (pad control)
- registers. Note that where one of these registers controls a single pin
- for which a PINMUX_AUX_* exists, see the list above for the pin name to
- use when configuring the pinmux.
-
- pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
- pz0, pz1, pz2, pz3, pz4, pz5, sdmmc1, sdmmc2, sdmmc3, sdmmc4
-
-Valid values for nvidia,functions are:
-
- aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, displayb,
- dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, i2c2, i2c3, i2cpmu, i2cvi,
- i2s1, i2s2, i2s3, i2s4a, i2s4b, i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0,
- pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
- sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, spi3, spi4,
- sys, touch, uart, uarta, uartb, uartc, uartd, usb, vgp1, vgp2, vgp3, vgp4,
- vgp5, vgp6, vimclk, vimclk2
-
-Example:
-
- pinmux: pinmux@70000800 {
- compatible = "nvidia,tegra210-pinmux";
- reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */
- <0x0 0x70003000 0x0 0x1000>; /* Mux registers */
-
- pinctrl-names = "boot";
- pinctrl-0 = <&state_boot>;
-
- state_boot: pinmux {
- gen1_i2c_scl_pj1 {
- nvidia,pins = "gen1_i2c_scl_pj1",
- nvidia,function = "i2c1";
- nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,open-drain = <TEGRA_PIN_ENABLE>;
- nvidia,io-hv = <TEGRA_PIN_ENABLE>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
new file mode 100644
index 000000000000..22e91178e377
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra210 Pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra210-pinmux
+
+ reg:
+ items:
+ - description: APB_MISC_GP_*_PADCTRL register (pad control)
+ - description: PINMUX_AUX_* registers (pinmux)
+
+additionalProperties:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ additionalProperties: false
+ properties:
+ nvidia,pins:
+ items:
+ enum: [ als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3,
+ ap_wake_nfc_ph7, aud_mclk_pbb0, batt_bcl, bt_rst_ph4,
+ bt_wake_ap_ph5, button_home_py1, button_power_on_px5,
+ button_slide_sw_py0, button_vol_down_px7,
+ button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7,
+ cam1_strobe_pt1, cam2_mclk_ps1, cam2_pwdn_pt0,
+ cam_af_en_ps5, cam_flash_en_ps6, cam_i2c_scl_ps2,
+ cam_i2c_sda_ps3, cam_rst_ps4, clk_32k_in, clk_32k_out_py5,
+ clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
+ dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2,
+ dap2_dout_paa3, dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5,
+ dap4_dout_pj6, dap4_fs_pj4, dap4_sclk_pj7, dmic1_clk_pe0,
+ dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, dmic3_clk_pe4,
+ dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
+ gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2,
+ gen2_i2c_sda_pj3, gen3_i2c_scl_pf0, gen3_i2c_sda_pf1,
+ gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, gps_en_pi2,
+ gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1,
+ jtag_rtck, lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3,
+ lcd_gpio2_pv4, lcd_rst_pv2, lcd_te_py2, modem_wake_ap_px0,
+ motion_int_px2, nfc_en_pi0, nfc_int_pi1, pa6, pcc7, pe6,
+ pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
+ pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6,
+ pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
+ pwr_i2c_scl_py3, pwr_i2c_sda_py4, pwr_int_n, pz0, pz1, pz2,
+ pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
+ qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
+ sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1,
+ sdmmc1_dat0_pm5, sdmmc1_dat1_pm4, sdmmc1_dat2_pm3,
+ sdmmc1_dat3_pm2, sdmmc3_clk_pp0, sdmmc3_cmd_pp1,
+ sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
+ sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2,
+ spi1_cs0_pc3, spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0,
+ spi1_sck_pc2, spi2_cs0_pb7, spi2_cs1_pdd0, spi2_miso_pb5,
+ spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, spi4_miso_pd0,
+ spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
+ touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2,
+ uart1_rx_pu1, uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2,
+ uart2_rx_pg1, uart2_tx_pg0, uart3_cts_pd4, uart3_rts_pd3,
+ uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, uart4_rts_pi6,
+ uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
+ usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1,
+ wifi_wake_ap_ph2,
+ # drive groups
+ drive_pa6, drive_pcc7, drive_pe6, drive_pe7, drive_ph6,
+ drive_pk0, drive_pk1, drive_pk2, drive_pk3, drive_pk4,
+ drive_pk5, drive_pk6, drive_pk7, drive_pl0, drive_pl1,
+ drive_pz0, drive_pz1, drive_pz2, drive_pz3, drive_pz4,
+ drive_pz5, drive_sdmmc1, drive_sdmmc2, drive_sdmmc3,
+ drive_sdmmc4 ]
+
+ nvidia,function:
+ enum: [ aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya,
+ displayb, dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1,
+ i2c2, i2c3, i2cpmu, i2cvi, i2s1, i2s2, i2s3, i2s4a, i2s4b,
+ i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, pe1, pmi, pwm0,
+ pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
+ sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2,
+ spi3, spi4, sys, touch, uart, uarta, uartb, uartc, uartd,
+ usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vimclk, vimclk2 ]
+
+ nvidia,enable-input:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
+
+ nvidia,open-drain:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
+
+ nvidia,lock:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
+
+ nvidia,io-hv:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-hv'
+
+ nvidia,high-speed-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
+
+ nvidia,drive-type:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/drive-type'
+
+ nvidia,slew-rate-rising:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
+
+ nvidia,slew-rate-falling:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
+
+ required:
+ - nvidia,pins
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+ pinmux: pinmux@70000800 {
+ compatible = "nvidia,tegra210-pinmux";
+ reg = <0x700008d4 0x02a8>, /* Pad control registers */
+ <0x70003000 0x1000>; /* Mux registers */
+
+ pinctrl-names = "boot";
+ pinctrl-0 = <&state_boot>;
+
+ state_boot: pinmux {
+ gen1_i2c_scl_pj1 {
+ nvidia,pins = "gen1_i2c_scl_pj1";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
deleted file mode 100644
index 0e6354c11e6d..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
+++ /dev/null
@@ -1,144 +0,0 @@
-NVIDIA Tegra30 pinmux controller
-
-The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
-as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
-that binding as a baseline, and only documents the differences between the
-two bindings.
-
-Required properties:
-- compatible: "nvidia,tegra30-pinmux"
-- reg: Should contain the register physical address and length for each of
- the pad control and mux registers.
-
-Tegra30 adds the following optional properties for pin configuration subnodes:
-- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
-- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
-- nvidia,lock: Integer. Lock the pin configuration against further changes
- until reset. 0: no, 1: yes.
-- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
-
-As with Tegra20, see the Tegra TRM for complete details regarding which groups
-support which functionality.
-
-Valid values for pin and group names are:
-
- per-pin mux groups:
-
- These all support nvidia,function, nvidia,tristate, nvidia,pull,
- nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
- nvidia,io-reset.
-
- clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
- dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
- gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
- sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
- uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
- lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
- sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
- lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
- lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
- lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
- gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
- gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
- gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
- gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
- gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
- gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
- uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
- gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
- vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
- vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
- lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
- dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
- lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
- ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
- ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
- dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
- kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
- kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
- kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
- kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
- kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
- vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
- sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
- pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
- lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
- clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
- spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
- spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
- sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
- sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
- sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
- sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
- sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
- cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
- cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
- clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
- pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
- pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
- pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
- clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
- pwr_int_n.
-
- drive groups:
-
- These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
- nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
- support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
-
- ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
- dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
- gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
- uart3, uda, vi1.
-
-Valid values for nvidia,functions are:
-
- blink, cec, clk_12m_out, clk_32k_in, core_pwr_req, cpu_pwr_req, crt,
- dap, ddr, dev3, displaya, displayb, dtv, extperiph1, extperiph2,
- extperiph3, gmi, gmi_alt, hda, hdcp, hdmi, hsi, i2c1, i2c2, i2c3,
- i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, invalid, kbc, mio, nand,
- nand_alt, owr, pcie, pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2,
- rsvd3, rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif, spi1,
- spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test, trace, uarta,
- uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
- vi, vi_alt1, vi_alt2, vi_alt3
-
-Example:
-
- pinctrl@70000000 {
- compatible = "nvidia,tegra30-pinmux";
- reg = < 0x70000868 0xd0 /* Pad control registers */
- 0x70003000 0x3e0 >; /* Mux registers */
- };
-
-Example board file extract:
-
- pinctrl@70000000 {
- sdmmc4_default: pinmux {
- sdmmc4_clk_pcc4 {
- nvidia,pins = "sdmmc4_clk_pcc4",
- "sdmmc4_rst_n_pcc3";
- nvidia,function = "sdmmc4";
- nvidia,pull = <0>;
- nvidia,tristate = <0>;
- };
- sdmmc4_dat0_paa0 {
- nvidia,pins = "sdmmc4_dat0_paa0",
- "sdmmc4_dat1_paa1",
- "sdmmc4_dat2_paa2",
- "sdmmc4_dat3_paa3",
- "sdmmc4_dat4_paa4",
- "sdmmc4_dat5_paa5",
- "sdmmc4_dat6_paa6",
- "sdmmc4_dat7_paa7";
- nvidia,function = "sdmmc4";
- nvidia,pull = <2>;
- nvidia,tristate = <0>;
- };
- };
- };
-
- sdhci@78000400 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc4_default>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
new file mode 100644
index 000000000000..ac4ec5def08d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra30 pinmux Controller
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra30-pinmux
+
+ reg:
+ items:
+ - description: pad control registers
+ - description: mux registers
+
+additionalProperties:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ additionalProperties: false
+ properties:
+ nvidia,pins:
+ items:
+ enum: [ clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2,
+ dap2_sclk_pa3, dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6,
+ sdmmc3_cmd_pa7, gmi_a17_pb0, gmi_a18_pb1, lcd_pwr0_pb2,
+ lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
+ sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0,
+ lcd_pwr1_pc1, uart2_txd_pc2, uart2_rxd_pc3,
+ gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, lcd_pwr2_pc6,
+ gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1,
+ lcd_dc1_pd2, sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5,
+ vi_vsync_pd6, vi_hsync_pd7, lcd_d0_pe0, lcd_d1_pe1,
+ lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, lcd_d6_pe6,
+ lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2,
+ lcd_d11_pf3, lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6,
+ lcd_d15_pf7, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
+ gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
+ gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
+ gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
+ gmi_ad15_ph7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2,
+ gmi_cs6_n_pi3, gmi_rst_n_pi4, gmi_iordy_pi5, gmi_cs7_n_pi6,
+ gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, gmi_cs1_n_pj2,
+ lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
+ uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1,
+ gmi_cs4_n_pk2, gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5,
+ spdif_in_pk6, gmi_a19_pk7, vi_d2_pl0, vi_d3_pl1, vi_d4_pl2,
+ vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, vi_d8_pl6, vi_d9_pl7,
+ lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
+ lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7,
+ dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3,
+ lcd_cs0_n_pn4, lcd_sdout_pn5, lcd_dc0_pn6, hdmi_int_pn7,
+ ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
+ ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5,
+ ulpi_data5_po6, ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1,
+ dap3_dout_pp2, dap3_sclk_pp3, dap4_fs_pp4, dap4_din_pp5,
+ dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, kb_col1_pq1,
+ kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
+ kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1,
+ kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5,
+ kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, kb_row9_ps1,
+ kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, kb_row13_ps5,
+ kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
+ vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5,
+ gen2_i2c_sda_pt6, sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4,
+ pu5, pu6, jtag_rtck_pu7, pv0, pv1, pv2, pv3, ddc_scl_pv4,
+ ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, lcd_cs1_n_pw0,
+ lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
+ clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0,
+ spi2_miso_px1, spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4,
+ spi1_sck_px5, spi1_cs0_n_px6, spi1_miso_px7, ulpi_clk_py0,
+ ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, sdmmc1_dat3_py4,
+ sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
+ sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3,
+ lcd_sck_pz4, sys_clk_req_pz5, pwr_i2c_scl_pz6,
+ pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1,
+ sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
+ sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
+ cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
+ pbb7, cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3,
+ sdmmc4_clk_pcc4, clk2_req_pcc5, pex_l2_rst_n_pcc6,
+ pex_l2_clkreq_n_pcc7, pex_l0_prsnt_n_pdd0,
+ pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3,
+ pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
+ pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0,
+ clk3_req_pee1, clk1_req_pee2, hdmi_cec_pee3, clk_32k_in,
+ core_pwr_req, cpu_pwr_req, owr, pwr_int_n,
+ # drive groups
+ drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
+ drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_cec,
+ drive_crt, drive_csus, drive_dap1, drive_dap2, drive_dap3,
+ drive_dap4, drive_dbg, drive_ddc, drive_dev3, drive_gma,
+ drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_gmf,
+ drive_gmg, drive_gmh, drive_gpv, drive_lcd1, drive_lcd2,
+ drive_owr, drive_sdio1, drive_sdio2, drive_sdio3,
+ drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
+ drive_uda, drive_vi1 ]
+
+ nvidia,function:
+ enum: [ blink, cec, clk_12m_out, clk_32k_in, core_pwr_req,
+ cpu_pwr_req, crt, dap, ddr, dev3, displaya, displayb, dtv,
+ extperiph1, extperiph2, extperiph3, gmi, gmi_alt, hda, hdcp,
+ hdmi, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2,
+ i2s3, i2s4, invalid, kbc, mio, nand, nand_alt, owr, pcie,
+ pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2, rsvd3,
+ rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif,
+ spi1, spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test,
+ trace, uarta, uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2,
+ vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt2, vi_alt3 ]
+
+ nvidia,enable-input:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
+
+ nvidia,open-drain:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
+
+ nvidia,lock:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
+
+ nvidia,io-reset:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-reset'
+
+ nvidia,high-speed-mode:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
+
+ nvidia,slew-rate-rising:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
+
+ nvidia,slew-rate-falling:
+ $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
+
+ required:
+ - nvidia,pins
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ pinctrl@70000000 {
+ compatible = "nvidia,tegra30-pinmux";
+ reg = <0x70000868 0x0d0>, /* Pad control registers */
+ <0x70003000 0x3e0>; /* Mux registers */
+
+ pinmux {
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4",
+ "sdmmc4_rst_n_pcc3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <0>;
+ nvidia,tristate = <0>;
+ };
+
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0",
+ "sdmmc4_dat1_paa1",
+ "sdmmc4_dat2_paa2",
+ "sdmmc4_dat3_paa3",
+ "sdmmc4_dat4_paa4",
+ "sdmmc4_dat5_paa5",
+ "sdmmc4_dat6_paa6",
+ "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <2>;
+ nvidia,tristate = <0>;
+ };
+ };
+ };
+...
--
2.36.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/4] dt-bindings: pinctrl: tegra194: Separate instances
2022-07-04 16:57 [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
2022-07-04 16:57 ` [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema Thierry Reding
@ 2022-07-04 16:58 ` Thierry Reding
2022-07-09 23:21 ` Linus Walleij
2022-07-04 16:58 ` [PATCH v2 3/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Thierry Reding @ 2022-07-04 16:58 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Jon Hunter, Prathamesh Shete, Vidya Sagar, devicetree,
linux-tegra, linux-gpio
From: Thierry Reding <treding@nvidia.com>
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux and
GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Note that while this changes the DT node in an incompatible way, this
doesn't have any practical implications for backwards-compatibility. The
reason for this is that device trees have only reconfigured a very
narrow subset of pins of the main controller, so the new driver will
remain backwards-compatible with old device trees.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add missing "type: object" to patternProperties nodes
- add note about backwards-compatibility
.../pinctrl/nvidia,tegra194-pinmux.yaml | 235 ++++++++++++++++--
1 file changed, 216 insertions(+), 19 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
index 322e146d52dd..0dd2ff6ace0f 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
@@ -1,4 +1,4 @@
-# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
@@ -12,12 +12,13 @@ maintainers:
properties:
compatible:
- const: nvidia,tegra194-pinmux
+ enum:
+ - nvidia,tegra194-pinmux
+ - nvidia,tegra194-pinmux-aon
reg:
items:
- - description: APB_MISC_GP_*_PADCTRL registers (pad control)
- - description: PINMUX_AUX_* registers (pinmux)
+ - description: pinmux registers
additionalProperties:
$ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
@@ -25,20 +26,17 @@ additionalProperties:
"^pinmux(-[a-z0-9-_]+)?$":
additionalProperties: false
properties:
- nvidia,pins:
- description: An array of strings. Each string contains the name of a
- pin or group. Valid values for these names are listed below.
-
- Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins are
- part of PCIE C5 power partition. Client devices must enable this
- partition before accessing the configuration for these pins.
- items:
- enum: [ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
- # drive groups
- drive_pex_l5_clkreq_n_pgg0, drive_pex_l5_rst_n_pgg1 ]
-
nvidia,function:
- enum: [ pe5 ]
+ enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1,
+ displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
+ dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3,
+ extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8,
+ i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi,
+ nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0,
+ rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs,
+ soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc,
+ uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
+ vgp6, wdt ]
nvidia,enable-input:
$ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
@@ -58,6 +56,206 @@ additionalProperties:
required:
- nvidia,pins
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: nvidia,tegra194-pinmux
+ then:
+ type: object
+ additionalProperties:
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ type: object
+ properties:
+ nvidia,pins:
+ description: An array of strings. Each string contains the name
+ of a pin or group. Valid values for these names are listed
+ below.
+
+ Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins
+ are part of PCIE C5 power partition. Client devices must
+ enable this partition before accessing the configuration for
+ these pins.
+ items:
+ enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2,
+ dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5,
+ dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0,
+ cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1,
+ qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4,
+ qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7,
+ qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2,
+ qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1,
+ eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4,
+ eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7,
+ eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2,
+ eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5,
+ soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2,
+ soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5,
+ soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0,
+ soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3,
+ uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6,
+ dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1,
+ dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
+ sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2,
+ sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5,
+ pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
+ pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3,
+ pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5,
+ pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7,
+ pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
+ pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0,
+ dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
+ dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5,
+ soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0,
+ soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0,
+ sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3,
+ sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0,
+ extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3,
+ soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6,
+ soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1,
+ soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4,
+ soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7,
+ soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2,
+ uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5,
+ dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2,
+ dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5,
+ soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0,
+ dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3,
+ dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6,
+ dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0,
+ directdc1_in_pv1, directdc1_out0_pv2,
+ directdc1_out1_pv3, directdc1_out2_pv4,
+ directdc1_out3_pv5, directdc1_out4_pv6,
+ directdc1_out5_pv7, directdc1_out6_pw0,
+ directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1,
+ gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5,
+ uart2_rts_px6, uart2_cts_px7, spi3_sck_py0,
+ spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3,
+ spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6,
+ uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1,
+ usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4,
+ spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7,
+ ufs0_ref_clk_pff0, ufs0_rst_pff1,
+ pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
+ directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs,
+ sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4,
+ sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0,
+ sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp,
+ sdmmc3_hv_trim, eqos_comp, qspi_comp,
+ # drive groups
+ drive_soc_gpio33_pt0, drive_soc_gpio32_ps7,
+ drive_soc_gpio31_ps6, drive_soc_gpio30_ps5,
+ drive_aud_mclk_ps4, drive_dap1_fs_ps3,
+ drive_dap1_din_ps2, drive_dap1_dout_ps1,
+ drive_dap1_sclk_ps0, drive_dap3_fs_pt4,
+ drive_dap3_din_pt3, drive_dap3_dout_pt2,
+ drive_dap3_sclk_pt1, drive_dap5_fs_pu0,
+ drive_dap5_din_pt7, drive_dap5_dout_pt6,
+ drive_dap5_sclk_pt5, drive_dap6_fs_pa3,
+ drive_dap6_din_pa2, drive_dap6_dout_pa1,
+ drive_dap6_sclk_pa0, drive_dap4_fs_pa7,
+ drive_dap4_din_pa6, drive_dap4_dout_pa5,
+ drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1,
+ drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3,
+ drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4,
+ drive_soc_gpio41_pq5, drive_soc_gpio42_pq6,
+ drive_soc_gpio43_pq7, drive_soc_gpio44_pr0,
+ drive_soc_gpio45_pr1, drive_soc_gpio20_pq0,
+ drive_soc_gpio21_pq1, drive_soc_gpio22_pq2,
+ drive_soc_gpio23_pq3, drive_soc_gpio04_pp4,
+ drive_soc_gpio05_pp5, drive_soc_gpio06_pp6,
+ drive_soc_gpio07_pp7, drive_uart1_cts_pr5,
+ drive_uart1_rts_pr4, drive_uart1_rx_pr3,
+ drive_uart1_tx_pr2, drive_dap2_din_pi1,
+ drive_dap2_dout_pi0, drive_dap2_fs_pi2,
+ drive_dap2_sclk_ph7, drive_uart4_cts_ph6,
+ drive_uart4_rts_ph5, drive_uart4_rx_ph4,
+ drive_uart4_tx_ph3, drive_soc_gpio03_pg3,
+ drive_soc_gpio02_pg2, drive_soc_gpio01_pg1,
+ drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3,
+ drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4,
+ drive_soc_gpio09_pg5, drive_soc_gpio10_pg6,
+ drive_soc_gpio11_pg7, drive_soc_gpio12_ph0,
+ drive_soc_gpio13_ph1, drive_soc_gpio14_ph2,
+ drive_soc_gpio50_pm5, drive_soc_gpio51_pm6,
+ drive_soc_gpio52_pm7, drive_soc_gpio53_pn0,
+ drive_soc_gpio54_pn1, drive_soc_gpio55_pn2,
+ drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1,
+ drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3,
+ drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4,
+ drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2,
+ drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0,
+ drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5,
+ drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7,
+ drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1,
+ drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0,
+ drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1,
+ drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0,
+ drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5,
+ drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
+ drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5,
+ drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3,
+ drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1,
+ drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0,
+ drive_spi3_miso_py1, drive_spi1_cs0_pz6,
+ drive_spi3_cs0_py3, drive_spi1_miso_pz4,
+ drive_spi3_cs1_py4, drive_gp_pwm3_px3,
+ drive_gp_pwm2_px2, drive_spi1_sck_pz3,
+ drive_spi3_sck_py0, drive_spi1_cs1_pz7,
+ drive_spi1_mosi_pz5, drive_spi3_mosi_py2,
+ drive_cv_pwr_req_px1, drive_uart2_tx_px4,
+ drive_uart2_rx_px5, drive_uart2_rts_px6,
+ drive_uart2_cts_px7, drive_uart5_rx_py6,
+ drive_uart5_tx_py5, drive_uart5_rts_py7,
+ drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1,
+ drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1,
+ drive_ufs0_ref_clk_pff0 ]
+
+ - if:
+ properties:
+ compatible:
+ const: nvidia,tegra194-pinmux-aon
+ then:
+ type: object
+ additionalProperties:
+ patternProperties:
+ "^pinmux(-[a-z0-9-_]+)?$":
+ type: object
+ properties:
+ nvidia,pins:
+ items:
+ enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2,
+ can0_din_paa3, can0_stb_paa4, can0_en_paa5,
+ can0_wake_paa6, can0_err_paa7, can1_stb_pbb0,
+ can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3,
+ spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
+ spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5,
+ uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
+ gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2,
+ safe_state_pee0, vcomp_alert_pee1,
+ ao_retention_n_pee2, batt_oc_pee3, power_on_pee4,
+ pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n,
+ shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in,
+ # drive groups
+ drive_shutdown_n, drive_pmu_int_n,
+ drive_safe_state_pee0, drive_vcomp_alert_pee1,
+ drive_soc_pwr_req, drive_batt_oc_pee3,
+ drive_clk_32k_in, drive_power_on_pee4,
+ drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6,
+ drive_ao_retention_n_pee2, drive_touch_clk_pcc4,
+ drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
+ drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
+ drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
+ drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
+ drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
+ drive_can1_dout_paa0, drive_can1_din_paa1,
+ drive_can0_dout_paa2, drive_can0_din_paa3,
+ drive_can0_stb_paa4, drive_can0_en_paa5,
+ drive_can0_wake_paa6, drive_can0_err_paa7,
+ drive_can1_stb_pbb0, drive_can1_en_pbb1,
+ drive_can1_wake_pbb2, drive_can1_err_pbb3 ]
+
required:
- compatible
- reg
@@ -68,8 +266,7 @@ examples:
pinmux@2430000 {
compatible = "nvidia,tegra194-pinmux";
- reg = <0x2430000 0x17000>,
- <0xc300000 0x04000>;
+ reg = <0x2430000 0x17000>;
pinctrl-names = "pex_rst";
pinctrl-0 = <&pex_rst_c5_out_state>;
--
2.36.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/4] pinctrl: tegra: Separate Tegra194 instances
2022-07-04 16:57 [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
2022-07-04 16:57 ` [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema Thierry Reding
2022-07-04 16:58 ` [PATCH v2 2/4] dt-bindings: pinctrl: tegra194: Separate instances Thierry Reding
@ 2022-07-04 16:58 ` Thierry Reding
2022-07-04 16:58 ` [PATCH v2 4/4] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194 Thierry Reding
2022-07-09 23:24 ` [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Linus Walleij
4 siblings, 0 replies; 11+ messages in thread
From: Thierry Reding @ 2022-07-04 16:58 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Jon Hunter, Prathamesh Shete, Vidya Sagar, devicetree,
linux-tegra, linux-gpio
From: Thierry Reding <treding@nvidia.com>
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux
and GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/pinctrl/tegra/pinctrl-tegra.c | 33 ++-
drivers/pinctrl/tegra/pinctrl-tegra.h | 2 +
drivers/pinctrl/tegra/pinctrl-tegra194.c | 286 +++++++++++++----------
3 files changed, 173 insertions(+), 148 deletions(-)
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
index 50bd26a30ac0..0fcbaa425ff5 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
@@ -668,19 +668,6 @@ static const struct pinconf_ops tegra_pinconf_ops = {
#endif
};
-static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
- .name = "Tegra GPIOs",
- .id = 0,
- .base = 0,
-};
-
-static struct pinctrl_desc tegra_pinctrl_desc = {
- .pctlops = &tegra_pinctrl_ops,
- .pmxops = &tegra_pinmux_ops,
- .confops = &tegra_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
{
int i = 0;
@@ -831,10 +818,18 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
}
}
- tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
- tegra_pinctrl_desc.name = dev_name(&pdev->dev);
- tegra_pinctrl_desc.pins = pmx->soc->pins;
- tegra_pinctrl_desc.npins = pmx->soc->npins;
+ pmx->gpio_range.name = "Tegra GPIOs";
+ pmx->gpio_range.id = 0;
+ pmx->gpio_range.base = 0;
+ pmx->gpio_range.npins = pmx->soc->ngpios;
+
+ pmx->desc.pctlops = &tegra_pinctrl_ops;
+ pmx->desc.pmxops = &tegra_pinmux_ops;
+ pmx->desc.confops = &tegra_pinconf_ops;
+ pmx->desc.owner = THIS_MODULE;
+ pmx->desc.name = dev_name(&pdev->dev);
+ pmx->desc.pins = pmx->soc->pins;
+ pmx->desc.npins = pmx->soc->npins;
for (i = 0; ; i++) {
res = platform_get_resource(pdev, IORESOURCE_MEM, i);
@@ -860,7 +855,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
return PTR_ERR(pmx->regs[i]);
}
- pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
+ pmx->pctl = devm_pinctrl_register(&pdev->dev, &pmx->desc, pmx);
if (IS_ERR(pmx->pctl)) {
dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
return PTR_ERR(pmx->pctl);
@@ -869,7 +864,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,
tegra_pinctrl_clear_parked_bits(pmx);
if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
- pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
+ pinctrl_add_gpio_range(pmx->pctl, &pmx->gpio_range);
platform_set_drvdata(pdev, pmx);
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h
index f8269858eb78..6130cba7cce5 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra.h
+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h
@@ -15,6 +15,8 @@ struct tegra_pmx {
const struct tegra_pinctrl_soc_data *soc;
const char **group_pins;
+ struct pinctrl_gpio_range gpio_range;
+ struct pinctrl_desc desc;
int nbanks;
void __iomem **regs;
u32 *backup_regs;
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra194.c b/drivers/pinctrl/tegra/pinctrl-tegra194.c
index f6c5d5e6dbb6..277973c88434 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra194.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra194.c
@@ -16,6 +16,7 @@
#include <linux/init.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@@ -23,7 +24,7 @@
#include "pinctrl-tegra.h"
/* Define unique ID for each pins */
-enum pin_id {
+enum {
TEGRA_PIN_DAP6_SCLK_PA0,
TEGRA_PIN_DAP6_DOUT_PA1,
TEGRA_PIN_DAP6_DIN_PA2,
@@ -189,6 +190,31 @@ enum pin_id {
TEGRA_PIN_SPI1_MOSI_PZ5,
TEGRA_PIN_SPI1_CS0_PZ6,
TEGRA_PIN_SPI1_CS1_PZ7,
+ TEGRA_PIN_UFS0_REF_CLK_PFF0,
+ TEGRA_PIN_UFS0_RST_PFF1,
+ TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
+ TEGRA_PIN_PEX_L5_RST_N_PGG1,
+ TEGRA_PIN_DIRECTDC_COMP,
+ TEGRA_PIN_SDMMC4_CLK,
+ TEGRA_PIN_SDMMC4_CMD,
+ TEGRA_PIN_SDMMC4_DQS,
+ TEGRA_PIN_SDMMC4_DAT7,
+ TEGRA_PIN_SDMMC4_DAT6,
+ TEGRA_PIN_SDMMC4_DAT5,
+ TEGRA_PIN_SDMMC4_DAT4,
+ TEGRA_PIN_SDMMC4_DAT3,
+ TEGRA_PIN_SDMMC4_DAT2,
+ TEGRA_PIN_SDMMC4_DAT1,
+ TEGRA_PIN_SDMMC4_DAT0,
+ TEGRA_PIN_SDMMC1_COMP,
+ TEGRA_PIN_SDMMC1_HV_TRIM,
+ TEGRA_PIN_SDMMC3_COMP,
+ TEGRA_PIN_SDMMC3_HV_TRIM,
+ TEGRA_PIN_EQOS_COMP,
+ TEGRA_PIN_QSPI_COMP,
+};
+
+enum {
TEGRA_PIN_CAN1_DOUT_PAA0,
TEGRA_PIN_CAN1_DIN_PAA1,
TEGRA_PIN_CAN0_DOUT_PAA2,
@@ -219,28 +245,6 @@ enum pin_id {
TEGRA_PIN_POWER_ON_PEE4,
TEGRA_PIN_PWR_I2C_SCL_PEE5,
TEGRA_PIN_PWR_I2C_SDA_PEE6,
- TEGRA_PIN_UFS0_REF_CLK_PFF0,
- TEGRA_PIN_UFS0_RST_PFF1,
- TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0,
- TEGRA_PIN_PEX_L5_RST_N_PGG1,
- TEGRA_PIN_DIRECTDC_COMP,
- TEGRA_PIN_SDMMC4_CLK,
- TEGRA_PIN_SDMMC4_CMD,
- TEGRA_PIN_SDMMC4_DQS,
- TEGRA_PIN_SDMMC4_DAT7,
- TEGRA_PIN_SDMMC4_DAT6,
- TEGRA_PIN_SDMMC4_DAT5,
- TEGRA_PIN_SDMMC4_DAT4,
- TEGRA_PIN_SDMMC4_DAT3,
- TEGRA_PIN_SDMMC4_DAT2,
- TEGRA_PIN_SDMMC4_DAT1,
- TEGRA_PIN_SDMMC4_DAT0,
- TEGRA_PIN_SDMMC1_COMP,
- TEGRA_PIN_SDMMC1_HV_TRIM,
- TEGRA_PIN_SDMMC3_COMP,
- TEGRA_PIN_SDMMC3_HV_TRIM,
- TEGRA_PIN_EQOS_COMP,
- TEGRA_PIN_QSPI_COMP,
TEGRA_PIN_SYS_RESET_N,
TEGRA_PIN_SHUTDOWN_N,
TEGRA_PIN_PMU_INT_N,
@@ -415,36 +419,6 @@ static const struct pinctrl_pin_desc tegra194_pins[] = {
PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PZ5, "SPI1_MOSI_PZ5"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PZ6, "SPI1_CS0_PZ6"),
PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PZ7, "SPI1_CS1_PZ7"),
- PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
- PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
- PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
- PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
- PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
- PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
- PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
- PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
- PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
- PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
- PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
- PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
- PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
- PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
- PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
- PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
- PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
- PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
- PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
- PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
- PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
- PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
- PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
- PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
- PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PFF0, "UFS0_REF_CLK_PFF0"),
PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PFF1, "UFS0_RST_PFF1"),
PINCTRL_PIN(TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0, "PEX_L5_CLKREQ_N_PGG0"),
@@ -467,11 +441,6 @@ static const struct pinctrl_pin_desc tegra194_pins[] = {
PINCTRL_PIN(TEGRA_PIN_SDMMC3_HV_TRIM, "SDMMC3_HV_TRIM"),
PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
- PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
- PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
- PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
- PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
- PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
};
static const unsigned int dap6_sclk_pa0_pins[] = {
@@ -1379,29 +1348,7 @@ static struct tegra_function tegra194_functions[] = {
.drvtype_bit = 13, \
.lpdr_bit = e_lpdr, \
-#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 1)
-#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 1)
+/* main drive pin groups */
#define drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
@@ -1509,17 +1456,6 @@ static struct tegra_function tegra194_functions[] = {
#define drive_sdmmc3_dat0_po2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_cmd_po1 DRV_PINGROUP_ENTRY_Y(0xa02c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
#define drive_sdmmc3_clk_po0 DRV_PINGROUP_ENTRY_Y(0xa034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
-#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
-#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
#define drive_gpu_pwr_req_px0 DRV_PINGROUP_ENTRY_Y(0xD004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi3_miso_py1 DRV_PINGROUP_ENTRY_Y(0xD00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
#define drive_spi1_cs0_pz6 DRV_PINGROUP_ENTRY_Y(0xD014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
@@ -1600,6 +1536,42 @@ static struct tegra_function tegra194_functions[] = {
#define drive_directdc1_in_pv1 DRV_PINGROUP_ENTRY_N(no_entry)
#define drive_directdc1_clk_pv0 DRV_PINGROUP_ENTRY_N(no_entry)
+/* AON drive pin groups */
+#define drive_shutdown_n DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_pmu_int_n DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_safe_state_pee0 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_vcomp_alert_pee1 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_batt_oc_pee3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_power_on_pee4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_pwr_i2c_scl_pee5 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_pwr_i2c_sda_pee6 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_ao_retention_n_pee2 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_touch_clk_pcc4 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_uart3_rx_pcc6 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_uart3_tx_pcc5 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_gen8_i2c_sda_pdd2 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_gen8_i2c_scl_pdd1 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_spi2_mosi_pcc2 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_gen2_i2c_scl_pcc7 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_spi2_cs0_pcc3 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_gen2_i2c_sda_pdd0 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_spi2_sck_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_spi2_miso_pcc1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
+#define drive_can1_dout_paa0 DRV_PINGROUP_ENTRY_Y(0x3004, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can1_din_paa1 DRV_PINGROUP_ENTRY_Y(0x300c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can0_dout_paa2 DRV_PINGROUP_ENTRY_Y(0x3014, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can0_din_paa3 DRV_PINGROUP_ENTRY_Y(0x301c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can0_stb_paa4 DRV_PINGROUP_ENTRY_Y(0x3024, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can0_en_paa5 DRV_PINGROUP_ENTRY_Y(0x302c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can0_wake_paa6 DRV_PINGROUP_ENTRY_Y(0x3034, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can0_err_paa7 DRV_PINGROUP_ENTRY_Y(0x303c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can1_stb_pbb0 DRV_PINGROUP_ENTRY_Y(0x3044, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can1_en_pbb1 DRV_PINGROUP_ENTRY_Y(0x304c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can1_wake_pbb2 DRV_PINGROUP_ENTRY_Y(0x3054, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+#define drive_can1_err_pbb3 DRV_PINGROUP_ENTRY_Y(0x305c, 28, 2, 30, 2, -1, -1, -1, -1, 0)
+
#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in, io_rail) \
{ \
@@ -1622,30 +1594,6 @@ static struct tegra_function tegra194_functions[] = {
}
static const struct tegra_pingroup tegra194_groups[] = {
-
- PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
- PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
- PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 1, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
PINGROUP(soc_gpio33_pt0, RSVD0, SPDIF, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(soc_gpio32_ps7, RSVD0, SPDIF, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
PINGROUP(soc_gpio31_ps6, RSVD0, SDMMC1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_audio"),
@@ -1805,17 +1753,6 @@ static const struct tegra_pingroup tegra194_groups[] = {
PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, Y, -1, -1, N, "vddio_sdmmc4"),
- PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 1, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 1, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 1, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 1, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
- PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 1, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
PINGROUP(gpu_pwr_req_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0xD000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi3_miso_py1, SPI3, RSVD1, RSVD2, RSVD3, 0xD008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
PINGROUP(spi1_cs0_pz6, SPI1, RSVD1, RSVD2, RSVD3, 0xD010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_uart"),
@@ -1857,13 +1794,104 @@ static const struct tegra_pinctrl_soc_data tegra194_pinctrl = {
.sfsel_in_mux = true,
};
+static const struct pinctrl_pin_desc tegra194_aon_pins[] = {
+ PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PAA0, "CAN1_DOUT_PAA0"),
+ PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PAA1, "CAN1_DIN_PAA1"),
+ PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PAA2, "CAN0_DOUT_PAA2"),
+ PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PAA3, "CAN0_DIN_PAA3"),
+ PINCTRL_PIN(TEGRA_PIN_CAN0_STB_PAA4, "CAN0_STB_PAA4"),
+ PINCTRL_PIN(TEGRA_PIN_CAN0_EN_PAA5, "CAN0_EN_PAA5"),
+ PINCTRL_PIN(TEGRA_PIN_CAN0_WAKE_PAA6, "CAN0_WAKE_PAA6"),
+ PINCTRL_PIN(TEGRA_PIN_CAN0_ERR_PAA7, "CAN0_ERR_PAA7"),
+ PINCTRL_PIN(TEGRA_PIN_CAN1_STB_PBB0, "CAN1_STB_PBB0"),
+ PINCTRL_PIN(TEGRA_PIN_CAN1_EN_PBB1, "CAN1_EN_PBB1"),
+ PINCTRL_PIN(TEGRA_PIN_CAN1_WAKE_PBB2, "CAN1_WAKE_PBB2"),
+ PINCTRL_PIN(TEGRA_PIN_CAN1_ERR_PBB3, "CAN1_ERR_PBB3"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PCC0, "SPI2_SCK_PCC0"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PCC1, "SPI2_MISO_PCC1"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PCC2, "SPI2_MOSI_PCC2"),
+ PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PCC3, "SPI2_CS0_PCC3"),
+ PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PCC4, "TOUCH_CLK_PCC4"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_TX_PCC5, "UART3_TX_PCC5"),
+ PINCTRL_PIN(TEGRA_PIN_UART3_RX_PCC6, "UART3_RX_PCC6"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PCC7, "GEN2_I2C_SCL_PCC7"),
+ PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PDD0, "GEN2_I2C_SDA_PDD0"),
+ PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PDD1, "GEN8_I2C_SCL_PDD1"),
+ PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PDD2, "GEN8_I2C_SDA_PDD2"),
+ PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PEE0, "SAFE_STATE_PEE0"),
+ PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PEE1, "VCOMP_ALERT_PEE1"),
+ PINCTRL_PIN(TEGRA_PIN_AO_RETENTION_N_PEE2, "AO_RETENTION_N_PEE2"),
+ PINCTRL_PIN(TEGRA_PIN_BATT_OC_PEE3, "BATT_OC_PEE3"),
+ PINCTRL_PIN(TEGRA_PIN_POWER_ON_PEE4, "POWER_ON_PEE4"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PEE5, "PWR_I2C_SCL_PEE5"),
+ PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PEE6, "PWR_I2C_SDA_PEE6"),
+ PINCTRL_PIN(TEGRA_PIN_SYS_RESET_N, "SYS_RESET_N"),
+ PINCTRL_PIN(TEGRA_PIN_SHUTDOWN_N, "SHUTDOWN_N"),
+ PINCTRL_PIN(TEGRA_PIN_PMU_INT_N, "PMU_INT_N"),
+ PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
+ PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
+};
+
+static const struct tegra_pingroup tegra194_aon_groups[] = {
+ PINGROUP(shutdown_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, 5, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(pmu_int_n, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(safe_state_pee0, SCE, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(vcomp_alert_pee1, SOC, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(batt_oc_pee3, SOC, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, -1, 8, -1, -1, -1, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(power_on_pee4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(pwr_i2c_scl_pee5, I2C5, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(pwr_i2c_sda_pee6, I2C5, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(ao_retention_n_pee2, GPIO, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_sys"),
+ PINGROUP(touch_clk_pcc4, GP, TOUCH, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(uart3_rx_pcc6, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(uart3_tx_pcc5, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(gen8_i2c_sda_pdd2, I2C8, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(gen8_i2c_scl_pdd1, I2C8, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(spi2_mosi_pcc2, SPI2, UARTG, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(gen2_i2c_scl_pcc7, I2C2, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(spi2_cs0_pcc3, SPI2, UARTG, RSVD2, RSVD3, 0x2038, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(gen2_i2c_sda_pdd0, I2C2, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(spi2_sck_pcc0, SPI2, UARTG, RSVD2, RSVD3, 0x2048, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(spi2_miso_pcc1, SPI2, UARTG, RSVD2, RSVD3, 0x2050, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N, "vddio_ao"),
+ PINGROUP(can1_dout_paa0, CAN1, RSVD1, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can1_din_paa1, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can0_dout_paa2, CAN0, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can0_din_paa3, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can0_stb_paa4, RSVD0, WDT, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can0_en_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can0_wake_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can0_err_paa7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can1_stb_pbb0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can1_en_pbb1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can1_wake_pbb2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+ PINGROUP(can1_err_pbb3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y, "vddio_ao_hv"),
+};
+
+static const struct tegra_pinctrl_soc_data tegra194_pinctrl_aon = {
+ .pins = tegra194_aon_pins,
+ .npins = ARRAY_SIZE(tegra194_aon_pins),
+ .functions = tegra194_functions,
+ .nfunctions = ARRAY_SIZE(tegra194_functions),
+ .groups = tegra194_aon_groups,
+ .ngroups = ARRAY_SIZE(tegra194_aon_groups),
+ .hsm_in_mux = true,
+ .schmitt_in_mux = true,
+ .drvtype_in_mux = true,
+ .sfsel_in_mux = true,
+};
+
static int tegra194_pinctrl_probe(struct platform_device *pdev)
{
- return tegra_pinctrl_probe(pdev, &tegra194_pinctrl);
+ const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);
+
+ return tegra_pinctrl_probe(pdev, soc);
}
static const struct of_device_id tegra194_pinctrl_of_match[] = {
- { .compatible = "nvidia,tegra194-pinmux", },
+ { .compatible = "nvidia,tegra194-pinmux", .data = &tegra194_pinctrl },
+ { .compatible = "nvidia,tegra194-pinmux-aon", .data = &tegra194_pinctrl_aon },
{ },
};
--
2.36.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/4] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194
2022-07-04 16:57 [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
` (2 preceding siblings ...)
2022-07-04 16:58 ` [PATCH v2 3/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
@ 2022-07-04 16:58 ` Thierry Reding
2022-07-09 23:24 ` [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Linus Walleij
4 siblings, 0 replies; 11+ messages in thread
From: Thierry Reding @ 2022-07-04 16:58 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski
Cc: Jon Hunter, Prathamesh Shete, Vidya Sagar, devicetree,
linux-tegra, linux-gpio
From: Thierry Reding <treding@nvidia.com>
The registers for the AON pinmux reside in a partition different from
the registers for the main pinmux. Instead of treating them as one and
the same device, split them up so that they are each their own devices.
Also add gpio-ranges properties to the corresponding GPIO controllers
such that the pinmux and GPIO controllers can be paired up properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 78277b538002..2638e480e7da 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -86,6 +86,7 @@ gpio: gpio@2200000 {
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
+ gpio-ranges = <&pinmux 0 0 169>;
};
cbb-noc@2300000 {
@@ -626,9 +627,7 @@ tegra_asrc: asrc@2910000 {
pinmux: pinmux@2430000 {
compatible = "nvidia,tegra194-pinmux";
- reg = <0x2430000 0x17000>,
- <0xc300000 0x4000>;
-
+ reg = <0x2430000 0x17000>;
status = "okay";
pex_rst_c5_out_state: pex_rst_c5_out {
@@ -1638,6 +1637,14 @@ gpio_aon: gpio@c2f0000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-range = <&pinmux_aon 0 0 30>;
+ };
+
+ pinmux_aon: pinmux@c300000 {
+ compatible = "nvidia,tegra194-pinmux-aon";
+ reg = <0xc300000 0x4000>;
+
+ status = "okay";
};
pwm4: pwm@c340000 {
--
2.36.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema
2022-07-04 16:57 ` [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema Thierry Reding
@ 2022-07-06 15:38 ` Rob Herring
2022-07-06 20:28 ` Thierry Reding
0 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2022-07-06 15:38 UTC (permalink / raw)
To: Thierry Reding
Cc: Linus Walleij, Krzysztof Kozlowski, Jon Hunter, Prathamesh Shete,
Vidya Sagar, devicetree, linux-tegra, linux-gpio
On Mon, Jul 04, 2022 at 06:57:59PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the NVIDIA Tegra pinmux controller bindings from the free-form
> text format to json-schema.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - wrap lines at 80 characters instead of the standard 100 characters in Linux
> - use GPL-2.0-only instead of GPL-2.0+ license for DT bindings
> - reorder additionalProperties for better readability
> - move common definitions into a shared schema
> - remove consumer snippets from examples
>
> .../bindings/clock/nvidia,tegra124-dfll.yaml | 2 +-
> .../pinctrl/nvidia,tegra-pinmux-common.yaml | 195 ++++++++++++++++++
> .../pinctrl/nvidia,tegra114-pinmux.txt | 131 ------------
> .../pinctrl/nvidia,tegra114-pinmux.yaml | 162 +++++++++++++++
> .../pinctrl/nvidia,tegra124-pinmux.txt | 153 --------------
> .../pinctrl/nvidia,tegra124-pinmux.yaml | 182 ++++++++++++++++
> .../pinctrl/nvidia,tegra194-pinmux.txt | 107 ----------
> .../pinctrl/nvidia,tegra194-pinmux.yaml | 88 ++++++++
> .../pinctrl/nvidia,tegra20-pinmux.txt | 143 -------------
> .../pinctrl/nvidia,tegra20-pinmux.yaml | 107 ++++++++++
> .../pinctrl/nvidia,tegra210-pinmux.txt | 166 ---------------
> .../pinctrl/nvidia,tegra210-pinmux.yaml | 146 +++++++++++++
> .../pinctrl/nvidia,tegra30-pinmux.txt | 144 -------------
> .../pinctrl/nvidia,tegra30-pinmux.yaml | 176 ++++++++++++++++
> 14 files changed, 1057 insertions(+), 845 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> index 85234a48b590..96c54c215f77 100644
> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> @@ -219,7 +219,7 @@ examples:
>
> /*
> * pinmux nodes added for completeness. Binding doc can be found in:
> - * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
> + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
> */
>
> pinmux: pinmux@700008d4 {
> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> new file mode 100644
> index 000000000000..cb6b722b89af
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> @@ -0,0 +1,195 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra Pinmux Controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jonathan Hunter <jonathanh@nvidia.com>
> +
> +definitions:
This likely doesn't work because 'definitions' doesn't get fixups
applied. '$defs' would, but in general I prefer avoiding this pattern
except when really needed. I don't think it helps here. More below.
> + pinconf-node:
> + type: object
> + description: |
> + Please refer to pinctrl-bindings.txt in this directory for details of the
> + common pinctrl bindings used by client devices, including the meaning of
> + the phrase "pin configuration node".
> +
> + Tegra's pin configuration nodes act as a container for an arbitrary number
> + of subnodes. Each of these subnodes represents some desired configuration
> + for a pin, a group, or a list of pins or groups. This configuration can
> + include the mux function to select on those pin(s)/ group(s), and various
> + pin configuration parameters, such as pull-up, tristate, drive strength,
> + etc.
> +
> + The name of each subnode is not important; all subnodes should be
> + enumerated and processed purely based on their content.
> +
> + Each subnode only affects those parameters that are explicitly listed. In
> + other words, a subnode that lists a mux function but no pin configuration
> + parameters implies no information about any pin configuration parameters.
> +
> + Similarly, a pin subnode that describes a pullup parameter implies no
> + information about e.g. the mux function or tristate parameter. For this
> + reason, even seemingly boolean values are actually tristates in this
> + binding: unspecified, off, or on. Unspecified is represented as an absent
> + property, and off/on are represented as integer values 0 and 1.
> +
> + Note that many of these properties are only valid for certain specific pins
> + or groups. See the Tegra TRM and various pinmux spreadsheets for complete
> + details regarding which groups support which functionality. The Linux
> + pinctrl driver may also be a useful reference, since it consolidates,
> + disambiguates, and corrects data from all those sources.
> +
> + patternProperties:
> + "^pinmux(-[a-z0-9-_]+)?$":
Drop this and make all the below be at the top level (i.e. no indent).
> + type: object
> + properties:
> + nvidia,pins:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + description: An array of strings. Each string contains the name of
> + a pin or group. Valid values for these names are listed below.
> +
> + nvidia,function:
> + $ref: /schemas/types.yaml#/definitions/string
> + description: A string containing the name of the function to mux to
> + the pin or group. Valid values for function names are listed
> + below. See the Tegra TRM to determine which are valid for each
> + pin or group.
> +
> + nvidia,pull:
> + description: Pull-down/up setting to apply to the pin.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: none
> + const: 0
> + - description: down
> + const: 1
> + - description: up
> + const: 2
> +
> + nvidia,tristate:
> + description: Tristate setting to apply to the pin.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: drive
> + const: 0
> + - description: tristate
> + const: 1
> +
> + nvidia,schmitt:
> + description: Enable Schmitt trigger on the input.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: disable Schmitt trigger on the input
> + const: 0
> + - description: enable Schmitt trigger on the input
> + const: 1
> +
> + nvidia,pull-down-strength:
> + description: Controls drive strength. 0 is weakest. The range of
> + valid values depends on the pingroup. See "CAL_DRVDN" in the
> + Tegra TRM.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + nvidia,pull-up-strength:
> + description: Controls drive strength. 0 is weakest. The range of
> + valid values depends on the pingroup. See "CAL_DRVUP" in the
> + Tegra TRM.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + high-speed-mode:
Why do all these need to be definitions? They all have the same name and
apply to the pinmux nodes. Just move them there with the right name.
> + description: Enable high speed mode the pins.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: normal speed mode
> + const: 0
> + - description: high speed mode
> + const: 1
> +
> + low-power-mode:
> + description: Controls the drive power or current. Valid values are
> + from 0 through 3, where 0 specifies the least power and 3 specifies
> + the most power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the
> + Tegra TRM.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1, 2, 3 ]
> +
> + enable-input:
> + description: Enable the pin's input path.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: disable input (i.e. output only)
> + const: 0
> + - description: enable input
> + const: 1
> +
> + open-drain:
> + description: Open-drain configuration for the pin.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: disable open-drain
> + const: 0
> + - description: enable open-drain
> + const: 1
> +
> + lock:
> + description: Lock the pin configuration against further changes until
> + reset.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: disable pin configuration lock
> + const: 0
> + - description: enable pin configuration lock
> + const: 1
> +
> + io-reset:
> + description: reset the I/O path
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1 ]
> +
> + rcv-sel:
> + description: select VIL/VIH receivers
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: normal receivers
> + const: 0
> + - description: high-voltage receivers
> + const: 1
> +
> + drive-type:
> + description: Drive type to configure for the pin.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [ 0, 1, 2, 3 ]
> +
> + io-hv:
> + description: Select high-voltage receivers.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + oneOf:
> + - description: Use normal receivers.
> + const: 0
> + - description: Use high-voltage receivers.
> + const: 1
> +
> + slew-rate-rising:
> + description: Controls rising signal slew rate. 0 is fastest. The
> + range of valid values depends on the pingroup. See "DRVDN_SLWR" in
> + the Tegra TRM.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> + slew-rate-falling:
> + description: Controls falling signal slew rate. 0 is fastest. The
> + range of valid values depends on the pingroup. See "DRVUP_SLWF" in
> + the Tegra TRM.
> + $ref: /schemas/types.yaml#/definitions/uint32
> +
> +properties:
> + reg:
> + minItems: 1
> + maxItems: 4
This doesn't get used anywhere.
> +
> +additionalProperties: true
> +...
> diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> new file mode 100644
> index 000000000000..e0a3f58b5535
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> @@ -0,0 +1,162 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra114 pinmux Controller
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> +
> +properties:
> + compatible:
> + const: nvidia,tegra114-pinmux
> +
> + reg:
> + items:
> + - description: pad control registers
> + - description: mux registers
> +
> +additionalProperties:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
> + patternProperties:
> + "^pinmux(-[a-z0-9-_]+)?$":
> + additionalProperties: false
The reference to the common schema should then be here.
If you want to keep which properties apply, then keep
'additionalProperties' and just list them out:
nvidia,enable-input: true
> + properties:
> + nvidia,pins:
> + items:
> + enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
> + ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
> + ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
> + ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
> + dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
> + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
> + sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
> + clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
> + uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
> + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
> + uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
> + pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4,
> + dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
> + clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
> + gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2,
> + gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3,
> + gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
> + gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
> + gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
> + gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
> + gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1,
> + gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3,
> + gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
> + sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
> + sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
> + sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
> + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
> + cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
> + pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0,
> + kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4,
> + kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0,
> + kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1,
> + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
> + kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5,
> + core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0,
> + dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2,
> + clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2,
> + dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
> + gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
> + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
> + gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
> + sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
> + sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
> + sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3,
> + usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5,
> + sdmmc3_clk_lb_out_pee4, reset_out_n,
> + # drive groups
> + drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
> + drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
> + drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
> + drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
> + drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
> + drive_gmg, drive_gmh, drive_owr, drive_uda ]
> +
> + nvidia,function:
> + enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
> + displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1,
> + extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
> + i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
> + nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron,
> + reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2,
> + sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5,
> + spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb,
> + vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ]
> +
> + nvidia,enable-input:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
> +
> + nvidia,open-drain:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
> +
> + nvidia,lock:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
> +
> + nvidia,io-reset:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-reset'
> +
> + nvidia,rcv-sel:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/rcv-sel'
> +
> + nvidia,high-speed-mode:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
> +
> + nvidia,low-power-mode:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/low-power-mode'
> +
> + nvidia,drive-type:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/drive-type'
> +
> + nvidia,slew-rate-rising:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
> +
> + nvidia,slew-rate-falling:
> + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
> +
> + required:
> + - nvidia,pins
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + pinmux@70000868 {
> + compatible = "nvidia,tegra114-pinmux";
> + reg = <0x70000868 0x148>, /* Pad control registers */
> + <0x70003000 0x40c>; /* PinMux registers */
> +
> + pinmux {
> + sdmmc4_clk_pcc4 {
Humm, this doesn't even match the schema. The child and grandchild are
swapped. It's saying any child node has only child nodes named
"^pinmux(-[a-z0-9-_]+)?$".
Please test your patches. This didn't apply, so no automated checks ran.
But that's not a free testing service anyways. :(
Rob
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema
2022-07-06 15:38 ` Rob Herring
@ 2022-07-06 20:28 ` Thierry Reding
2022-07-12 21:45 ` Rob Herring
0 siblings, 1 reply; 11+ messages in thread
From: Thierry Reding @ 2022-07-06 20:28 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Krzysztof Kozlowski, Jon Hunter, Prathamesh Shete,
Vidya Sagar, devicetree, linux-tegra, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 22830 bytes --]
On Wed, Jul 06, 2022 at 09:38:22AM -0600, Rob Herring wrote:
> On Mon, Jul 04, 2022 at 06:57:59PM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Convert the NVIDIA Tegra pinmux controller bindings from the free-form
> > text format to json-schema.
> >
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > Changes in v2:
> > - wrap lines at 80 characters instead of the standard 100 characters in Linux
> > - use GPL-2.0-only instead of GPL-2.0+ license for DT bindings
> > - reorder additionalProperties for better readability
> > - move common definitions into a shared schema
> > - remove consumer snippets from examples
> >
> > .../bindings/clock/nvidia,tegra124-dfll.yaml | 2 +-
> > .../pinctrl/nvidia,tegra-pinmux-common.yaml | 195 ++++++++++++++++++
> > .../pinctrl/nvidia,tegra114-pinmux.txt | 131 ------------
> > .../pinctrl/nvidia,tegra114-pinmux.yaml | 162 +++++++++++++++
> > .../pinctrl/nvidia,tegra124-pinmux.txt | 153 --------------
> > .../pinctrl/nvidia,tegra124-pinmux.yaml | 182 ++++++++++++++++
> > .../pinctrl/nvidia,tegra194-pinmux.txt | 107 ----------
> > .../pinctrl/nvidia,tegra194-pinmux.yaml | 88 ++++++++
> > .../pinctrl/nvidia,tegra20-pinmux.txt | 143 -------------
> > .../pinctrl/nvidia,tegra20-pinmux.yaml | 107 ++++++++++
> > .../pinctrl/nvidia,tegra210-pinmux.txt | 166 ---------------
> > .../pinctrl/nvidia,tegra210-pinmux.yaml | 146 +++++++++++++
> > .../pinctrl/nvidia,tegra30-pinmux.txt | 144 -------------
> > .../pinctrl/nvidia,tegra30-pinmux.yaml | 176 ++++++++++++++++
> > 14 files changed, 1057 insertions(+), 845 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> > index 85234a48b590..96c54c215f77 100644
> > --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> > +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> > @@ -219,7 +219,7 @@ examples:
> >
> > /*
> > * pinmux nodes added for completeness. Binding doc can be found in:
> > - * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
> > + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
> > */
> >
> > pinmux: pinmux@700008d4 {
> > diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> > new file mode 100644
> > index 000000000000..cb6b722b89af
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> > @@ -0,0 +1,195 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra Pinmux Controller
> > +
> > +maintainers:
> > + - Thierry Reding <thierry.reding@gmail.com>
> > + - Jonathan Hunter <jonathanh@nvidia.com>
> > +
> > +definitions:
>
> This likely doesn't work because 'definitions' doesn't get fixups
> applied. '$defs' would, but in general I prefer avoiding this pattern
> except when really needed. I don't think it helps here. More below.
>
> > + pinconf-node:
> > + type: object
> > + description: |
> > + Please refer to pinctrl-bindings.txt in this directory for details of the
> > + common pinctrl bindings used by client devices, including the meaning of
> > + the phrase "pin configuration node".
> > +
> > + Tegra's pin configuration nodes act as a container for an arbitrary number
> > + of subnodes. Each of these subnodes represents some desired configuration
> > + for a pin, a group, or a list of pins or groups. This configuration can
> > + include the mux function to select on those pin(s)/ group(s), and various
> > + pin configuration parameters, such as pull-up, tristate, drive strength,
> > + etc.
> > +
> > + The name of each subnode is not important; all subnodes should be
> > + enumerated and processed purely based on their content.
> > +
> > + Each subnode only affects those parameters that are explicitly listed. In
> > + other words, a subnode that lists a mux function but no pin configuration
> > + parameters implies no information about any pin configuration parameters.
> > +
> > + Similarly, a pin subnode that describes a pullup parameter implies no
> > + information about e.g. the mux function or tristate parameter. For this
> > + reason, even seemingly boolean values are actually tristates in this
> > + binding: unspecified, off, or on. Unspecified is represented as an absent
> > + property, and off/on are represented as integer values 0 and 1.
> > +
> > + Note that many of these properties are only valid for certain specific pins
> > + or groups. See the Tegra TRM and various pinmux spreadsheets for complete
> > + details regarding which groups support which functionality. The Linux
> > + pinctrl driver may also be a useful reference, since it consolidates,
> > + disambiguates, and corrects data from all those sources.
> > +
> > + patternProperties:
> > + "^pinmux(-[a-z0-9-_]+)?$":
>
> Drop this and make all the below be at the top level (i.e. no indent).
The intention was to include the general structure as well as the
description in each of the derived schemas. Some of the description
could perhaps be dropped, but especially the bit about the tristate
nature of some of these properties should stay in because it has caused
confusion in the past.
Is there any other way that the description can be shared with your
proposal (other than duplicating it in each binding document).
>
> > + type: object
> > + properties:
> > + nvidia,pins:
> > + $ref: /schemas/types.yaml#/definitions/string-array
> > + description: An array of strings. Each string contains the name of
> > + a pin or group. Valid values for these names are listed below.
> > +
> > + nvidia,function:
> > + $ref: /schemas/types.yaml#/definitions/string
> > + description: A string containing the name of the function to mux to
> > + the pin or group. Valid values for function names are listed
> > + below. See the Tegra TRM to determine which are valid for each
> > + pin or group.
> > +
> > + nvidia,pull:
> > + description: Pull-down/up setting to apply to the pin.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: none
> > + const: 0
> > + - description: down
> > + const: 1
> > + - description: up
> > + const: 2
> > +
> > + nvidia,tristate:
> > + description: Tristate setting to apply to the pin.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: drive
> > + const: 0
> > + - description: tristate
> > + const: 1
> > +
> > + nvidia,schmitt:
> > + description: Enable Schmitt trigger on the input.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: disable Schmitt trigger on the input
> > + const: 0
> > + - description: enable Schmitt trigger on the input
> > + const: 1
> > +
> > + nvidia,pull-down-strength:
> > + description: Controls drive strength. 0 is weakest. The range of
> > + valid values depends on the pingroup. See "CAL_DRVDN" in the
> > + Tegra TRM.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + nvidia,pull-up-strength:
> > + description: Controls drive strength. 0 is weakest. The range of
> > + valid values depends on the pingroup. See "CAL_DRVUP" in the
> > + Tegra TRM.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + high-speed-mode:
>
> Why do all these need to be definitions? They all have the same name and
> apply to the pinmux nodes. Just move them there with the right name.
All of the ones that are separate definitions are properties that appear
for only a subset of the IP generations. So the idea was to create a
definition and then derived bindings could cherry-pick these as
necessary to complement the pinconf-node definition.
If I move these definitions to the top level, then they'll end up
validating properly on devices where they shouldn't exist. Alternatively
I'd have to duplicate all of these across various derivative bindings
which gets us mostly back to the previous version of the patch (i.e. we
don't save very much by only factoring out the truly common properties).
> > + description: Enable high speed mode the pins.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: normal speed mode
> > + const: 0
> > + - description: high speed mode
> > + const: 1
> > +
> > + low-power-mode:
> > + description: Controls the drive power or current. Valid values are
> > + from 0 through 3, where 0 specifies the least power and 3 specifies
> > + the most power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the
> > + Tegra TRM.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [ 0, 1, 2, 3 ]
> > +
> > + enable-input:
> > + description: Enable the pin's input path.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: disable input (i.e. output only)
> > + const: 0
> > + - description: enable input
> > + const: 1
> > +
> > + open-drain:
> > + description: Open-drain configuration for the pin.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: disable open-drain
> > + const: 0
> > + - description: enable open-drain
> > + const: 1
> > +
> > + lock:
> > + description: Lock the pin configuration against further changes until
> > + reset.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: disable pin configuration lock
> > + const: 0
> > + - description: enable pin configuration lock
> > + const: 1
> > +
> > + io-reset:
> > + description: reset the I/O path
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [ 0, 1 ]
> > +
> > + rcv-sel:
> > + description: select VIL/VIH receivers
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: normal receivers
> > + const: 0
> > + - description: high-voltage receivers
> > + const: 1
> > +
> > + drive-type:
> > + description: Drive type to configure for the pin.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [ 0, 1, 2, 3 ]
> > +
> > + io-hv:
> > + description: Select high-voltage receivers.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + oneOf:
> > + - description: Use normal receivers.
> > + const: 0
> > + - description: Use high-voltage receivers.
> > + const: 1
> > +
> > + slew-rate-rising:
> > + description: Controls rising signal slew rate. 0 is fastest. The
> > + range of valid values depends on the pingroup. See "DRVDN_SLWR" in
> > + the Tegra TRM.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > + slew-rate-falling:
> > + description: Controls falling signal slew rate. 0 is fastest. The
> > + range of valid values depends on the pingroup. See "DRVUP_SLWF" in
> > + the Tegra TRM.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > +properties:
> > + reg:
> > + minItems: 1
> > + maxItems: 4
>
> This doesn't get used anywhere.
I think I needed the properties keyword here because the tooling would
otherwise consider this schema invalid. Perhaps if I restructure this
that error will go away as well.
> > +
> > +additionalProperties: true
> > +...
>
>
> > diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> > new file mode 100644
> > index 000000000000..e0a3f58b5535
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> > @@ -0,0 +1,162 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra114 pinmux Controller
> > +
> > +maintainers:
> > + - Thierry Reding <thierry.reding@gmail.com>
> > + - Jon Hunter <jonathanh@nvidia.com>
> > +
> > +properties:
> > + compatible:
> > + const: nvidia,tegra114-pinmux
> > +
> > + reg:
> > + items:
> > + - description: pad control registers
> > + - description: mux registers
> > +
> > +additionalProperties:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/pinconf-node'
> > + patternProperties:
> > + "^pinmux(-[a-z0-9-_]+)?$":
> > + additionalProperties: false
>
> The reference to the common schema should then be here.
>
> If you want to keep which properties apply, then keep
> 'additionalProperties' and just list them out:
>
> nvidia,enable-input: true
But then if I define the schema for nvidia,enable-input in the common
schema, it'll validate for all derivative schemas as well, won't it? Or
would I have to explicitly exclude those that aren't applicable to a
given derivative schema using something like:
nvidia,enable-input: false
>
> > + properties:
> > + nvidia,pins:
> > + items:
> > + enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
> > + ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
> > + ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
> > + ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
> > + dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
> > + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
> > + sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
> > + clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
> > + uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
> > + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
> > + uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
> > + pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4,
> > + dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
> > + clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
> > + gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2,
> > + gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3,
> > + gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
> > + gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
> > + gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
> > + gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
> > + gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1,
> > + gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3,
> > + gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
> > + sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
> > + sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
> > + sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
> > + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
> > + cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
> > + pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0,
> > + kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4,
> > + kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0,
> > + kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1,
> > + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
> > + kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5,
> > + core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0,
> > + dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2,
> > + clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2,
> > + dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
> > + gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
> > + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
> > + gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
> > + sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
> > + sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
> > + sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3,
> > + usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5,
> > + sdmmc3_clk_lb_out_pee4, reset_out_n,
> > + # drive groups
> > + drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
> > + drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
> > + drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
> > + drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
> > + drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
> > + drive_gmg, drive_gmh, drive_owr, drive_uda ]
> > +
> > + nvidia,function:
> > + enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
> > + displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1,
> > + extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
> > + i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
> > + nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron,
> > + reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2,
> > + sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5,
> > + spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb,
> > + vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ]
> > +
> > + nvidia,enable-input:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/enable-input'
> > +
> > + nvidia,open-drain:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/open-drain'
> > +
> > + nvidia,lock:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/lock'
> > +
> > + nvidia,io-reset:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/io-reset'
> > +
> > + nvidia,rcv-sel:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/rcv-sel'
> > +
> > + nvidia,high-speed-mode:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/high-speed-mode'
> > +
> > + nvidia,low-power-mode:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/low-power-mode'
> > +
> > + nvidia,drive-type:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/drive-type'
> > +
> > + nvidia,slew-rate-rising:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-rising'
> > +
> > + nvidia,slew-rate-falling:
> > + $ref: 'nvidia,tegra-pinmux-common.yaml#/definitions/slew-rate-falling'
> > +
> > + required:
> > + - nvidia,pins
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +examples:
> > + - |
> > + pinmux@70000868 {
> > + compatible = "nvidia,tegra114-pinmux";
> > + reg = <0x70000868 0x148>, /* Pad control registers */
> > + <0x70003000 0x40c>; /* PinMux registers */
> > +
> > + pinmux {
> > + sdmmc4_clk_pcc4 {
>
> Humm, this doesn't even match the schema. The child and grandchild are
> swapped. It's saying any child node has only child nodes named
> "^pinmux(-[a-z0-9-_]+)?$".
>
> Please test your patches. This didn't apply, so no automated checks ran.
> But that's not a free testing service anyways. :(
I messed this up as I was rebasing, so the fixes for this ended up in an
unrelated patch, but the end result still worked for me... =(
Thierry
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: pinctrl: tegra194: Separate instances
2022-07-04 16:58 ` [PATCH v2 2/4] dt-bindings: pinctrl: tegra194: Separate instances Thierry Reding
@ 2022-07-09 23:21 ` Linus Walleij
0 siblings, 0 replies; 11+ messages in thread
From: Linus Walleij @ 2022-07-09 23:21 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Krzysztof Kozlowski, Jon Hunter, Prathamesh Shete,
Vidya Sagar, devicetree, linux-tegra, linux-gpio
On Mon, Jul 4, 2022 at 6:58 PM Thierry Reding <thierry.reding@gmail.com> wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Tegra194 has two separate instances of the pin controller, one called
> AON (in the always-on domain) and another called "main".
Maybe this information should be in the bindings themselves
too?
Other than that:
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances
2022-07-04 16:57 [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
` (3 preceding siblings ...)
2022-07-04 16:58 ` [PATCH v2 4/4] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194 Thierry Reding
@ 2022-07-09 23:24 ` Linus Walleij
4 siblings, 0 replies; 11+ messages in thread
From: Linus Walleij @ 2022-07-09 23:24 UTC (permalink / raw)
To: Thierry Reding
Cc: Rob Herring, Krzysztof Kozlowski, Jon Hunter, Prathamesh Shete,
Vidya Sagar, devicetree, linux-tegra, linux-gpio
On Mon, Jul 4, 2022 at 6:58 PM Thierry Reding <thierry.reding@gmail.com> wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> This patch series changes the pin controller DT description on Tegra194
> in order to properly describe how the hardware works. Currently a
> simplified description is used that merges two pin controller instances
> (called AON and main) into a single DT node. This has some disadvantages
> such as creating a complicated mapping between the pins in those pin
> controllers and the corresponding GPIO controllers (which are already
> separated).
>
> As a prerequisite, the first patch in this series converts the device
> tree bindings to json-schema. A second patch then adds an additional
> compatible string for the AON instance (along with more details about
> each controller's pins) and finally patch 3 converts the driver to
> cope with these changes. A fourth patch makes the corresponding
> changes in the Tegra194 DTS file.
>
> Note that while this changes the DT node in an incompatible way, this
> doesn't have any practical implications for backwards-compatibility. The
> reason for this is that device trees have only reconfigured a very
> narrow subset of pins of the main controller, so the new driver will
> remain backwards-compatible with old device trees.
Works for me, this is much closer to the hardware and therefore
better (fixing a bug in the old bindings essentially).
The whole set:
Acked-by: Linus Walleij <linus.walleij@linaro.org>
I can merge patches 1-3 whenever we have Rob's ACK.
I assume you will take patch 4 thru the SoC tree?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema
2022-07-06 20:28 ` Thierry Reding
@ 2022-07-12 21:45 ` Rob Herring
2022-08-16 11:33 ` Thierry Reding
0 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2022-07-12 21:45 UTC (permalink / raw)
To: Thierry Reding
Cc: Linus Walleij, Krzysztof Kozlowski, Jon Hunter, Prathamesh Shete,
Vidya Sagar, devicetree, linux-tegra, linux-gpio
On Wed, Jul 06, 2022 at 10:28:34PM +0200, Thierry Reding wrote:
> On Wed, Jul 06, 2022 at 09:38:22AM -0600, Rob Herring wrote:
> > On Mon, Jul 04, 2022 at 06:57:59PM +0200, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Convert the NVIDIA Tegra pinmux controller bindings from the free-form
> > > text format to json-schema.
> > >
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > > Changes in v2:
> > > - wrap lines at 80 characters instead of the standard 100 characters in Linux
> > > - use GPL-2.0-only instead of GPL-2.0+ license for DT bindings
> > > - reorder additionalProperties for better readability
> > > - move common definitions into a shared schema
> > > - remove consumer snippets from examples
> > >
> > > .../bindings/clock/nvidia,tegra124-dfll.yaml | 2 +-
> > > .../pinctrl/nvidia,tegra-pinmux-common.yaml | 195 ++++++++++++++++++
> > > .../pinctrl/nvidia,tegra114-pinmux.txt | 131 ------------
> > > .../pinctrl/nvidia,tegra114-pinmux.yaml | 162 +++++++++++++++
> > > .../pinctrl/nvidia,tegra124-pinmux.txt | 153 --------------
> > > .../pinctrl/nvidia,tegra124-pinmux.yaml | 182 ++++++++++++++++
> > > .../pinctrl/nvidia,tegra194-pinmux.txt | 107 ----------
> > > .../pinctrl/nvidia,tegra194-pinmux.yaml | 88 ++++++++
> > > .../pinctrl/nvidia,tegra20-pinmux.txt | 143 -------------
> > > .../pinctrl/nvidia,tegra20-pinmux.yaml | 107 ++++++++++
> > > .../pinctrl/nvidia,tegra210-pinmux.txt | 166 ---------------
> > > .../pinctrl/nvidia,tegra210-pinmux.yaml | 146 +++++++++++++
> > > .../pinctrl/nvidia,tegra30-pinmux.txt | 144 -------------
> > > .../pinctrl/nvidia,tegra30-pinmux.yaml | 176 ++++++++++++++++
> > > 14 files changed, 1057 insertions(+), 845 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.txt
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.txt
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.txt
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.txt
> > > create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> > > index 85234a48b590..96c54c215f77 100644
> > > --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> > > +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.yaml
> > > @@ -219,7 +219,7 @@ examples:
> > >
> > > /*
> > > * pinmux nodes added for completeness. Binding doc can be found in:
> > > - * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
> > > + * Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
> > > */
> > >
> > > pinmux: pinmux@700008d4 {
> > > diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> > > new file mode 100644
> > > index 000000000000..cb6b722b89af
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml
> > > @@ -0,0 +1,195 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NVIDIA Tegra Pinmux Controller
> > > +
> > > +maintainers:
> > > + - Thierry Reding <thierry.reding@gmail.com>
> > > + - Jonathan Hunter <jonathanh@nvidia.com>
> > > +
> > > +definitions:
> >
> > This likely doesn't work because 'definitions' doesn't get fixups
> > applied. '$defs' would, but in general I prefer avoiding this pattern
> > except when really needed. I don't think it helps here. More below.
> >
> > > + pinconf-node:
> > > + type: object
> > > + description: |
> > > + Please refer to pinctrl-bindings.txt in this directory for details of the
> > > + common pinctrl bindings used by client devices, including the meaning of
> > > + the phrase "pin configuration node".
> > > +
> > > + Tegra's pin configuration nodes act as a container for an arbitrary number
> > > + of subnodes. Each of these subnodes represents some desired configuration
> > > + for a pin, a group, or a list of pins or groups. This configuration can
> > > + include the mux function to select on those pin(s)/ group(s), and various
> > > + pin configuration parameters, such as pull-up, tristate, drive strength,
> > > + etc.
> > > +
> > > + The name of each subnode is not important; all subnodes should be
> > > + enumerated and processed purely based on their content.
> > > +
> > > + Each subnode only affects those parameters that are explicitly listed. In
> > > + other words, a subnode that lists a mux function but no pin configuration
> > > + parameters implies no information about any pin configuration parameters.
> > > +
> > > + Similarly, a pin subnode that describes a pullup parameter implies no
> > > + information about e.g. the mux function or tristate parameter. For this
> > > + reason, even seemingly boolean values are actually tristates in this
> > > + binding: unspecified, off, or on. Unspecified is represented as an absent
> > > + property, and off/on are represented as integer values 0 and 1.
> > > +
> > > + Note that many of these properties are only valid for certain specific pins
> > > + or groups. See the Tegra TRM and various pinmux spreadsheets for complete
> > > + details regarding which groups support which functionality. The Linux
> > > + pinctrl driver may also be a useful reference, since it consolidates,
> > > + disambiguates, and corrects data from all those sources.
> > > +
> > > + patternProperties:
> > > + "^pinmux(-[a-z0-9-_]+)?$":
> >
> > Drop this and make all the below be at the top level (i.e. no indent).
>
> The intention was to include the general structure as well as the
> description in each of the derived schemas. Some of the description
> could perhaps be dropped, but especially the bit about the tristate
> nature of some of these properties should stay in because it has caused
> confusion in the past.
>
> Is there any other way that the description can be shared with your
> proposal (other than duplicating it in each binding document).
The 'description' above? You can move that to top-level too.
> > > + type: object
> > > + properties:
> > > + nvidia,pins:
> > > + $ref: /schemas/types.yaml#/definitions/string-array
> > > + description: An array of strings. Each string contains the name of
> > > + a pin or group. Valid values for these names are listed below.
> > > +
> > > + nvidia,function:
> > > + $ref: /schemas/types.yaml#/definitions/string
> > > + description: A string containing the name of the function to mux to
> > > + the pin or group. Valid values for function names are listed
> > > + below. See the Tegra TRM to determine which are valid for each
> > > + pin or group.
> > > +
> > > + nvidia,pull:
> > > + description: Pull-down/up setting to apply to the pin.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: none
> > > + const: 0
> > > + - description: down
> > > + const: 1
> > > + - description: up
> > > + const: 2
> > > +
> > > + nvidia,tristate:
> > > + description: Tristate setting to apply to the pin.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: drive
> > > + const: 0
> > > + - description: tristate
> > > + const: 1
> > > +
> > > + nvidia,schmitt:
> > > + description: Enable Schmitt trigger on the input.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: disable Schmitt trigger on the input
> > > + const: 0
> > > + - description: enable Schmitt trigger on the input
> > > + const: 1
> > > +
> > > + nvidia,pull-down-strength:
> > > + description: Controls drive strength. 0 is weakest. The range of
> > > + valid values depends on the pingroup. See "CAL_DRVDN" in the
> > > + Tegra TRM.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > + nvidia,pull-up-strength:
> > > + description: Controls drive strength. 0 is weakest. The range of
> > > + valid values depends on the pingroup. See "CAL_DRVUP" in the
> > > + Tegra TRM.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > + high-speed-mode:
> >
> > Why do all these need to be definitions? They all have the same name and
> > apply to the pinmux nodes. Just move them there with the right name.
>
> All of the ones that are separate definitions are properties that appear
> for only a subset of the IP generations. So the idea was to create a
> definition and then derived bindings could cherry-pick these as
> necessary to complement the pinconf-node definition.
>
> If I move these definitions to the top level, then they'll end up
> validating properly on devices where they shouldn't exist. Alternatively
> I'd have to duplicate all of these across various derivative bindings
> which gets us mostly back to the previous version of the patch (i.e. we
> don't save very much by only factoring out the truly common properties).
Not if you use 'additionalProperties: false'. Since it doesn't see into
$ref's like unevaluatedProperties does, you have to list out which
properties you are using in the derived binding:
$ref: list-of-common-props.yaml#
properties:
high-speed-mode: true
additionalProperties: false
list-of-common-props.yaml could have a gazillion properties in
it, but anything not listed locally will be disallowed.
> > > + description: Enable high speed mode the pins.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: normal speed mode
> > > + const: 0
> > > + - description: high speed mode
> > > + const: 1
> > > +
> > > + low-power-mode:
> > > + description: Controls the drive power or current. Valid values are
> > > + from 0 through 3, where 0 specifies the least power and 3 specifies
> > > + the most power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the
> > > + Tegra TRM.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [ 0, 1, 2, 3 ]
> > > +
> > > + enable-input:
> > > + description: Enable the pin's input path.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: disable input (i.e. output only)
> > > + const: 0
> > > + - description: enable input
> > > + const: 1
> > > +
> > > + open-drain:
> > > + description: Open-drain configuration for the pin.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: disable open-drain
> > > + const: 0
> > > + - description: enable open-drain
> > > + const: 1
> > > +
> > > + lock:
> > > + description: Lock the pin configuration against further changes until
> > > + reset.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: disable pin configuration lock
> > > + const: 0
> > > + - description: enable pin configuration lock
> > > + const: 1
> > > +
> > > + io-reset:
> > > + description: reset the I/O path
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [ 0, 1 ]
> > > +
> > > + rcv-sel:
> > > + description: select VIL/VIH receivers
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: normal receivers
> > > + const: 0
> > > + - description: high-voltage receivers
> > > + const: 1
> > > +
> > > + drive-type:
> > > + description: Drive type to configure for the pin.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [ 0, 1, 2, 3 ]
> > > +
> > > + io-hv:
> > > + description: Select high-voltage receivers.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + oneOf:
> > > + - description: Use normal receivers.
> > > + const: 0
> > > + - description: Use high-voltage receivers.
> > > + const: 1
> > > +
> > > + slew-rate-rising:
> > > + description: Controls rising signal slew rate. 0 is fastest. The
> > > + range of valid values depends on the pingroup. See "DRVDN_SLWR" in
> > > + the Tegra TRM.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > + slew-rate-falling:
> > > + description: Controls falling signal slew rate. 0 is fastest. The
> > > + range of valid values depends on the pingroup. See "DRVUP_SLWF" in
> > > + the Tegra TRM.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > +
> > > +properties:
> > > + reg:
> > > + minItems: 1
> > > + maxItems: 4
> >
> > This doesn't get used anywhere.
>
> I think I needed the properties keyword here because the tooling would
> otherwise consider this schema invalid. Perhaps if I restructure this
> that error will go away as well.
Probably so. All part of keeping people within the lines. :)
Rob
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema
2022-07-12 21:45 ` Rob Herring
@ 2022-08-16 11:33 ` Thierry Reding
0 siblings, 0 replies; 11+ messages in thread
From: Thierry Reding @ 2022-08-16 11:33 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Krzysztof Kozlowski, Jon Hunter, Prathamesh Shete,
Vidya Sagar, devicetree, linux-tegra, linux-gpio
[-- Attachment #1.1: Type: text/plain, Size: 4841 bytes --]
On Tue, Jul 12, 2022 at 03:45:04PM -0600, Rob Herring wrote:
> On Wed, Jul 06, 2022 at 10:28:34PM +0200, Thierry Reding wrote:
> > All of the ones that are separate definitions are properties that appear
> > for only a subset of the IP generations. So the idea was to create a
> > definition and then derived bindings could cherry-pick these as
> > necessary to complement the pinconf-node definition.
> >
> > If I move these definitions to the top level, then they'll end up
> > validating properly on devices where they shouldn't exist. Alternatively
> > I'd have to duplicate all of these across various derivative bindings
> > which gets us mostly back to the previous version of the patch (i.e. we
> > don't save very much by only factoring out the truly common properties).
>
> Not if you use 'additionalProperties: false'. Since it doesn't see into
> $ref's like unevaluatedProperties does, you have to list out which
> properties you are using in the derived binding:
>
> $ref: list-of-common-props.yaml#
>
> properties:
> high-speed-mode: true
>
> additionalProperties: false
>
> list-of-common-props.yaml could have a gazillion properties in
> it, but anything not listed locally will be disallowed.
I tried to restructure as you suggested and things do look better.
Unfortunately I can't find a way to get the result to validate properly.
The problem I'm running into is that these are vendor-specific
properties (with the "nvidia," prefix) and therefore the tools complain
when I list them as above, like so:
.../Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml: patternProperties:^pinmux(-[a-z0-9-_]+)?$:properties:nvidia,drive-type: True is not of type 'object'
hint: Vendor specific properties must have a type and description unless they have a defined, common suffix.
from schema $id: http://devicetree.org/meta-schemas/vendor-props.yaml#
.../Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml: patternProperties:^pinmux(-[a-z0-9-_]+)?$:properties:nvidia,drive-type: More than one condition true in oneOf schema:
{'description': 'Vendor specific properties must have a type and '
'description unless they have a defined, common '
'suffix.',
'oneOf': [{'additionalProperties': False,
'description': 'A vendor boolean property can use "type: '
'boolean"',
'properties': {'deprecated': True,
'description': True,
'type': {'const': 'boolean'}},
'required': ['type', 'description']},
{'additionalProperties': False,
'description': 'A vendor string property with exact values '
'has an implicit type',
'oneOf': [{'required': ['enum']}, {'required': ['const']}],
'properties': {'const': {'type': 'string'},
'deprecated': True,
'description': True,
'enum': {'items': {'type': 'string'}}},
'required': ['description']},
{'description': 'A vendor property needs a $ref to '
'types.yaml',
'oneOf': [{'required': ['$ref']}, {'required': ['allOf']}],
'properties': {'$ref': {'pattern': 'types.yaml#/definitions/'},
'allOf': {'items': [{'properties': {'$ref': {'pattern': 'types.yaml#/definitions/'}},
'required': ['$ref']}]}},
'required': ['description']},
{'description': 'A vendor property can have a $ref to a a '
'$defs schema',
'properties': {'$ref': {'pattern': '^#/(definitions|\\$defs)/'}},
'required': ['$ref']}],
'type': 'object'}
hint: Vendor specific properties must have a type and description unless they have a defined, common suffix.
from schema $id: http://devicetree.org/meta-schemas/vendor-props.yaml#
I'm attaching two example files (not the actual patch, because that'd
make this a bit more difficult to review) but this happens for all the
derivatives.
I've been scratching my head for a while now and tried different
combinations, but I can't think of a way to make this work. I'm also not
sure if I'm reading that error report right, but it sounds like the
tooling wants the vendor properties to be fully defined, even for the
simple cases where I just want to mark them as valid (i.e. cancel out
the effect of 'additionalProperties: false'). Is there some special
mechanism that I could somehow enable regular behaviour for these
vendor-specific properties?
Any other ideas on how to fix this?
Thierry
[-- Attachment #1.2: nvidia,tegra-pinmux-common.yaml --]
[-- Type: text/plain, Size: 6407 bytes --]
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jonathan Hunter <jonathanh@nvidia.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of
the phrase "pin configuration node".
Tegra's pin configuration nodes act as a container for an arbitrary number
of subnodes. Each of these subnodes represents some desired configuration
for a pin, a group, or a list of pins or groups. This configuration can
include the mux function to select on those pin(s)/ group(s), and various
pin configuration parameters, such as pull-up, tristate, drive strength,
etc.
The name of each subnode is not important; all subnodes should be
enumerated and processed purely based on their content.
Each subnode only affects those parameters that are explicitly listed. In
other words, a subnode that lists a mux function but no pin configuration
parameters implies no information about any pin configuration parameters.
Similarly, a pin subnode that describes a pullup parameter implies no
information about e.g. the mux function or tristate parameter. For this
reason, even seemingly boolean values are actually tristates in this
binding: unspecified, off, or on. Unspecified is represented as an absent
property, and off/on are represented as integer values 0 and 1.
Note that many of these properties are only valid for certain specific pins
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
details regarding which groups support which functionality. The Linux
pinctrl driver may also be a useful reference, since it consolidates,
disambiguates, and corrects data from all those sources.
properties:
nvidia,pins:
$ref: /schemas/types.yaml#/definitions/string-array
description: An array of strings. Each string contains the name of a pin
or group. Valid values for these names are listed below.
nvidia,function:
$ref: /schemas/types.yaml#/definitions/string
description: A string containing the name of the function to mux to the
pin or group. Valid values for function names are listed below. See the
Tegra TRM to determine which are valid for each pin or group.
nvidia,pull:
description: Pull-down/up setting to apply to the pin.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: none
const: 0
- description: down
const: 1
- description: up
const: 2
nvidia,tristate:
description: Tristate setting to apply to the pin.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: drive
const: 0
- description: tristate
const: 1
nvidia,schmitt:
description: Enable Schmitt trigger on the input.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: disable Schmitt trigger on the input
const: 0
- description: enable Schmitt trigger on the input
const: 1
nvidia,pull-down-strength:
description: Controls drive strength. 0 is weakest. The range of valid
values depends on the pingroup. See "CAL_DRVDN" in the Tegra TRM.
$ref: /schemas/types.yaml#/definitions/uint32
nvidia,pull-up-strength:
description: Controls drive strength. 0 is weakest. The range of valid
values depends on the pingroup. See "CAL_DRVUP" in the Tegra TRM.
$ref: /schemas/types.yaml#/definitions/uint32
nvidia,high-speed-mode:
description: Enable high speed mode the pins.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: normal speed mode
const: 0
- description: high speed mode
const: 1
nvidia,low-power-mode:
description: Controls the drive power or current. Valid values are from 0
through 3, where 0 specifies the least power and 3 specifies the most
power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the Tegra TRM.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2, 3 ]
nvidia,enable-input:
description: Enable the pin's input path.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: disable input (i.e. output only)
const: 0
- description: enable input
const: 1
nvidia,open-drain:
description: Open-drain configuration for the pin.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: disable open-drain
const: 0
- description: enable open-drain
const: 1
nvidia,lock:
description: Lock the pin configuration against further changes until
reset.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: disable pin configuration lock
const: 0
- description: enable pin configuration lock
const: 1
nvidia,io-reset:
description: reset the I/O path
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]
nvidia,rcv-sel:
description: select VIL/VIH receivers
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: normal receivers
const: 0
- description: high-voltage receivers
const: 1
nvidia,drive-type:
description: Drive type to configure for the pin.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1, 2, 3 ]
nvidia,io-hv:
description: Select high-voltage receivers.
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: Use normal receivers.
const: 0
- description: Use high-voltage receivers.
const: 1
nvidia,slew-rate-rising:
description: Controls rising signal slew rate. 0 is fastest. The range of
valid values depends on the pingroup. See "DRVDN_SLWR" in the Tegra TRM.
$ref: /schemas/types.yaml#/definitions/uint32
nvidia,slew-rate-falling:
description: Controls falling signal slew rate. 0 is fastest. The range of
valid values depends on the pingroup. See "DRVUP_SLWF" in the Tegra TRM.
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: true
...
[-- Attachment #1.3: nvidia,tegra194-pinmux.yaml --]
[-- Type: text/plain, Size: 14296 bytes --]
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra194 Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
enum:
- nvidia,tegra194-pinmux
- nvidia,tegra194-pinmux-aon
reg:
items:
- description: pinmux registers
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
$ref: nvidia,tegra-pinmux-common.yaml
additionalProperties: false
properties:
nvidia,function:
enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1,
displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3,
extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8,
i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi,
nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0,
rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs,
soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc,
uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
vgp6, wdt ]
nvidia,enable-input: true
nvidia,open-drain: true
nvidia,lock: true
nvidia,io-hv: true
nvidia,drive-type: true
required:
- nvidia,pins
additionalProperties: false
allOf:
- if:
properties:
compatible:
const: nvidia,tegra194-pinmux
then:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
nvidia,pins:
description: An array of strings. Each string contains the name
of a pin or group. Valid values for these names are listed
below.
Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins
are part of PCIE C5 power partition. Client devices must
enable this partition before accessing the configuration for
these pins.
items:
enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2,
dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5,
dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0,
cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1,
qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4,
qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7,
qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2,
qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1,
eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4,
eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7,
eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2,
eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5,
soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2,
soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5,
soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0,
soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3,
uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6,
dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1,
dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2,
sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5,
pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3,
pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5,
pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7,
pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0,
dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5,
soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0,
soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0,
sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3,
sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0,
extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3,
soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6,
soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1,
soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4,
soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7,
soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2,
uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5,
dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2,
dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5,
soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0,
dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3,
dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6,
dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0,
directdc1_in_pv1, directdc1_out0_pv2,
directdc1_out1_pv3, directdc1_out2_pv4,
directdc1_out3_pv5, directdc1_out4_pv6,
directdc1_out5_pv7, directdc1_out6_pw0,
directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1,
gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5,
uart2_rts_px6, uart2_cts_px7, spi3_sck_py0,
spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3,
spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6,
uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1,
usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4,
spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7,
ufs0_ref_clk_pff0, ufs0_rst_pff1,
pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs,
sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4,
sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0,
sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp,
sdmmc3_hv_trim, eqos_comp, qspi_comp,
# drive groups
drive_soc_gpio33_pt0, drive_soc_gpio32_ps7,
drive_soc_gpio31_ps6, drive_soc_gpio30_ps5,
drive_aud_mclk_ps4, drive_dap1_fs_ps3,
drive_dap1_din_ps2, drive_dap1_dout_ps1,
drive_dap1_sclk_ps0, drive_dap3_fs_pt4,
drive_dap3_din_pt3, drive_dap3_dout_pt2,
drive_dap3_sclk_pt1, drive_dap5_fs_pu0,
drive_dap5_din_pt7, drive_dap5_dout_pt6,
drive_dap5_sclk_pt5, drive_dap6_fs_pa3,
drive_dap6_din_pa2, drive_dap6_dout_pa1,
drive_dap6_sclk_pa0, drive_dap4_fs_pa7,
drive_dap4_din_pa6, drive_dap4_dout_pa5,
drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1,
drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3,
drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4,
drive_soc_gpio41_pq5, drive_soc_gpio42_pq6,
drive_soc_gpio43_pq7, drive_soc_gpio44_pr0,
drive_soc_gpio45_pr1, drive_soc_gpio20_pq0,
drive_soc_gpio21_pq1, drive_soc_gpio22_pq2,
drive_soc_gpio23_pq3, drive_soc_gpio04_pp4,
drive_soc_gpio05_pp5, drive_soc_gpio06_pp6,
drive_soc_gpio07_pp7, drive_uart1_cts_pr5,
drive_uart1_rts_pr4, drive_uart1_rx_pr3,
drive_uart1_tx_pr2, drive_dap2_din_pi1,
drive_dap2_dout_pi0, drive_dap2_fs_pi2,
drive_dap2_sclk_ph7, drive_uart4_cts_ph6,
drive_uart4_rts_ph5, drive_uart4_rx_ph4,
drive_uart4_tx_ph3, drive_soc_gpio03_pg3,
drive_soc_gpio02_pg2, drive_soc_gpio01_pg1,
drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3,
drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4,
drive_soc_gpio09_pg5, drive_soc_gpio10_pg6,
drive_soc_gpio11_pg7, drive_soc_gpio12_ph0,
drive_soc_gpio13_ph1, drive_soc_gpio14_ph2,
drive_soc_gpio50_pm5, drive_soc_gpio51_pm6,
drive_soc_gpio52_pm7, drive_soc_gpio53_pn0,
drive_soc_gpio54_pn1, drive_soc_gpio55_pn2,
drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1,
drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3,
drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4,
drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2,
drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0,
drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5,
drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7,
drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1,
drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0,
drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1,
drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0,
drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5,
drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5,
drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3,
drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1,
drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0,
drive_spi3_miso_py1, drive_spi1_cs0_pz6,
drive_spi3_cs0_py3, drive_spi1_miso_pz4,
drive_spi3_cs1_py4, drive_gp_pwm3_px3,
drive_gp_pwm2_px2, drive_spi1_sck_pz3,
drive_spi3_sck_py0, drive_spi1_cs1_pz7,
drive_spi1_mosi_pz5, drive_spi3_mosi_py2,
drive_cv_pwr_req_px1, drive_uart2_tx_px4,
drive_uart2_rx_px5, drive_uart2_rts_px6,
drive_uart2_cts_px7, drive_uart5_rx_py6,
drive_uart5_tx_py5, drive_uart5_rts_py7,
drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1,
drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1,
drive_ufs0_ref_clk_pff0 ]
- if:
properties:
compatible:
const: nvidia,tegra194-pinmux-aon
then:
patternProperties:
"^pinmux(-[a-z0-9-_]+)?$":
type: object
properties:
nvidia,pins:
items:
enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2,
can0_din_paa3, can0_stb_paa4, can0_en_paa5,
can0_wake_paa6, can0_err_paa7, can1_stb_pbb0,
can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3,
spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5,
uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2,
safe_state_pee0, vcomp_alert_pee1,
ao_retention_n_pee2, batt_oc_pee3, power_on_pee4,
pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n,
shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in,
# drive groups
drive_shutdown_n, drive_pmu_int_n,
drive_safe_state_pee0, drive_vcomp_alert_pee1,
drive_soc_pwr_req, drive_batt_oc_pee3,
drive_clk_32k_in, drive_power_on_pee4,
drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6,
drive_ao_retention_n_pee2, drive_touch_clk_pcc4,
drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
drive_can1_dout_paa0, drive_can1_din_paa1,
drive_can0_dout_paa2, drive_can0_din_paa3,
drive_can0_stb_paa4, drive_can0_en_paa5,
drive_can0_wake_paa6, drive_can0_err_paa7,
drive_can1_stb_pbb0, drive_can1_en_pbb1,
drive_can1_wake_pbb2, drive_can1_err_pbb3 ]
required:
- compatible
- reg
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@2430000 {
compatible = "nvidia,tegra194-pinmux";
reg = <0x2430000 0x17000>;
pinctrl-names = "pex_rst";
pinctrl-0 = <&pex_rst_c5_out_state>;
pex_rst_c5_out_state: pex_rst_c5_out {
pex_rst {
nvidia,pins = "pex_l5_rst_n_pgg1";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
};
};
...
[-- Attachment #2: signature.asc --]
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2022-07-04 16:57 [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
2022-07-04 16:57 ` [PATCH v2 1/4] dt-bindings: pinctrl: tegra: Convert to json-schema Thierry Reding
2022-07-06 15:38 ` Rob Herring
2022-07-06 20:28 ` Thierry Reding
2022-07-12 21:45 ` Rob Herring
2022-08-16 11:33 ` Thierry Reding
2022-07-04 16:58 ` [PATCH v2 2/4] dt-bindings: pinctrl: tegra194: Separate instances Thierry Reding
2022-07-09 23:21 ` Linus Walleij
2022-07-04 16:58 ` [PATCH v2 3/4] pinctrl: tegra: Separate Tegra194 instances Thierry Reding
2022-07-04 16:58 ` [PATCH v2 4/4] arm64: tegra: Separate AON pinmux from main pinmux on Tegra194 Thierry Reding
2022-07-09 23:24 ` [PATCH v2 0/4] pinctrl: tegra: Separate Tegra194 instances Linus Walleij
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