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From: Sumit Garg <sumit.garg@linaro.org>
To: u-boot@lists.denx.de
Cc: rfried.dev@gmail.com, peng.fan@nxp.com, jh80.chung@samsung.com,
	sjg@chromium.org, trini@konsulko.com, dsankouski@gmail.com,
	stephan@gerhold.net, vinod.koul@linaro.org,
	nicolas.dechesne@linaro.org, mworsfold@impinj.com,
	daniel.thompson@linaro.org, pbrobinson@gmail.com,
	Sumit Garg <sumit.garg@linaro.org>
Subject: [PATCH v3 7/9] pinctrl: qcom: Add pinctrl driver for QCS404 SoC
Date: Tue, 12 Jul 2022 12:42:10 +0530	[thread overview]
Message-ID: <20220712071212.2188390-8-sumit.garg@linaro.org> (raw)
In-Reply-To: <20220712071212.2188390-1-sumit.garg@linaro.org>

Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
---
 arch/arm/mach-snapdragon/Makefile             |  1 +
 arch/arm/mach-snapdragon/pinctrl-qcs404.c     | 55 +++++++++++++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |  1 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  1 +
 4 files changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 962855eb8c..cb8c1aa8d2 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -15,4 +15,5 @@ obj-y += dram.o
 obj-y += pinctrl-snapdragon.o
 obj-y += pinctrl-apq8016.o
 obj-y += pinctrl-apq8096.o
+obj-y += pinctrl-qcs404.o
 obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
new file mode 100644
index 0000000000..889ead0f57
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 pinctrl
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_RCLK",
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart2", 1},
+};
+
+static const char *qcs404_get_function_name(struct udevice *dev,
+					    unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs404_get_pin_name(struct udevice *dev,
+				       unsigned int selector)
+{
+	if (selector < 120) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 120];
+	}
+}
+
+static unsigned int qcs404_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data qcs404_data = {
+	.pin_count = 126,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = qcs404_get_function_name,
+	.get_function_mux = qcs404_get_function_mux,
+	.get_pin_name = qcs404_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index d1c560dd40..c2148a5d0a 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
 #ifdef CONFIG_SDM845
 	{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
 #endif
+	{ .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
 	{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index ea524312a0..178ee01a41 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,5 +28,6 @@ struct pinctrl_function {
 extern struct msm_pinctrl_data apq8016_data;
 extern struct msm_pinctrl_data apq8096_data;
 extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data qcs404_data;
 
 #endif
-- 
2.25.1


  parent reply	other threads:[~2022-07-12  7:13 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-12  7:12 [PATCH v3 0/9] New boards support: db845c and qcs404-evb Sumit Garg
2022-07-12  7:12 ` [PATCH v3 1/9] board: starqltechn: Align DT node overrides with sdm845.dtsi Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-12  7:12 ` [PATCH v3 2/9] arm64: dts: sdm845: Remove redundant u-boot DT properties Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-12  7:12 ` [PATCH v3 3/9] clocks: sdm845: Import qcom,gcc-sdm845.h Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-12  7:12 ` [PATCH v3 4/9] uart: sdm845: Fix debug UART pinmux Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-12  7:12 ` [PATCH v3 5/9] board: qualcomm: Add support for dragonboard845c Sumit Garg
2022-07-25 21:21   ` Tom Rini
2023-08-23 23:57   ` Simon Glass
2023-08-24 10:43     ` Sumit Garg
2023-08-28 17:54       ` Simon Glass
2023-08-28 20:23         ` Peter Robinson
2023-08-28 22:09           ` Simon Glass
2023-08-29 10:24             ` Sumit Garg
2023-09-10 23:14               ` Simon Glass
2022-07-12  7:12 ` [PATCH v3 6/9] mmc: msm_sdhci: Add SDCC version 5.0.0 support Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-12  7:12 ` Sumit Garg [this message]
2022-07-25 21:21   ` [PATCH v3 7/9] pinctrl: qcom: Add pinctrl driver for QCS404 SoC Tom Rini
2022-07-12  7:12 ` [PATCH v3 8/9] clocks: qcom: Add clock " Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-12  7:12 ` [PATCH v3 9/9] board: qualcomm: Add support for QCS404 EVB Sumit Garg
2022-07-13 19:31   ` Stephan Gerhold
2022-07-14  7:40     ` Sumit Garg
2022-07-14 18:27       ` Stephan Gerhold
2022-07-15 10:24         ` Sumit Garg
2022-07-25 21:21   ` Tom Rini
2022-07-19  5:31 ` [PATCH v3 0/9] New boards support: db845c and qcs404-evb Sumit Garg
2022-07-19 11:01   ` Tom Rini
2022-07-19 11:09     ` Sumit Garg

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