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From: "Maíra Canal" <mairacanal@riseup.net>
To: Harry Wentland <harry.wentland@amd.com>,
	Leo Li <sunpeng.li@amd.com>,
	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>,
	christian.koenig@amd.com, Xinhui.Pan@amd.com,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
	Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: magalilemes00@gmail.com, tales.aparecida@gmail.com,
	linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org,
	mwen@igalia.com, "Maíra Canal" <mairacanal@riseup.net>,
	"Isabella Basso" <isabbasso@riseup.net>,
	andrealmeid@riseup.net
Subject: [PATCH 01/12] drm/amdgpu: Write masked value to control register
Date: Thu, 14 Jul 2022 13:44:56 -0300	[thread overview]
Message-ID: <20220714164507.561751-1-mairacanal@riseup.net> (raw)

On the dce_v6_0 and dce_v8_0 hpd tear down callback, the tmp variable
should be written into the control register instead of 0.

Fixes: b00861b9 ("drm/amd/amdgpu: port of DCE v6 to new headers (v3)")
Fixes: 2285b91c ("drm/amdgpu/dce8: simplify hpd code")
Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index f5a29526684d..0a7b1c002822 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -339,7 +339,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 
 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 		tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
-		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 780a8aa972fe..f57f4a25cf5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -333,7 +333,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 
 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 		tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
-		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 	}
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: "Maíra Canal" <mairacanal@riseup.net>
To: Harry Wentland <harry.wentland@amd.com>,
	Leo Li <sunpeng.li@amd.com>,
	Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>,
	Alex Deucher <alexander.deucher@amd.com>,
	christian.koenig@amd.com, Xinhui.Pan@amd.com,
	David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>,
	Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>,
	Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	mwen@igalia.com, andrealmeid@riseup.net,
	"Isabella Basso" <isabbasso@riseup.net>,
	magalilemes00@gmail.com, tales.aparecida@gmail.com,
	"Maíra Canal" <mairacanal@riseup.net>
Subject: [PATCH 01/12] drm/amdgpu: Write masked value to control register
Date: Thu, 14 Jul 2022 13:44:56 -0300	[thread overview]
Message-ID: <20220714164507.561751-1-mairacanal@riseup.net> (raw)

On the dce_v6_0 and dce_v8_0 hpd tear down callback, the tmp variable
should be written into the control register instead of 0.

Fixes: b00861b9 ("drm/amd/amdgpu: port of DCE v6 to new headers (v3)")
Fixes: 2285b91c ("drm/amdgpu/dce8: simplify hpd code")
Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +-
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index f5a29526684d..0a7b1c002822 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -339,7 +339,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 
 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 		tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
-		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 780a8aa972fe..f57f4a25cf5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -333,7 +333,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev)
 
 		tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
 		tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
-		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+		WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
 		amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
 	}
-- 
2.36.1


             reply	other threads:[~2022-07-14 16:45 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-14 16:44 Maíra Canal [this message]
2022-07-14 16:44 ` [PATCH 01/12] drm/amdgpu: Write masked value to control register Maíra Canal
2022-07-14 16:44 ` [PATCH 02/12] drm/amd/display: Change get_pipe_idx function scope Maíra Canal
2022-07-14 16:44   ` Maíra Canal
2022-07-18 18:52   ` Alex Deucher
2022-07-18 18:52     ` Alex Deucher
2022-07-14 16:44 ` [PATCH 03/12] drm/amd/display: Remove unused clk_src variable Maíra Canal
2022-07-14 16:44   ` Maíra Canal
2022-07-18 18:53   ` Alex Deucher
2022-07-18 18:53     ` Alex Deucher
2022-07-14 16:44 ` [PATCH 04/12] drm/amd/display: Remove unused dml32_CalculatedoublePipeDPPCLKAndSCLThroughput function Maíra Canal
2022-07-14 16:44   ` Maíra Canal
2022-07-18 18:54   ` Alex Deucher
2022-07-18 18:54     ` Alex Deucher
2022-07-14 16:45 ` [PATCH 05/12] drm/amd/display: Remove unused NumberOfStates variable Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-18 18:55   ` Alex Deucher
2022-07-18 18:55     ` Alex Deucher
2022-07-14 16:45 ` [PATCH 06/12] drm/amd/display: Remove unused variables from dml_rq_dlg_get_dlg_params Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-18 18:56   ` Alex Deucher
2022-07-18 18:56     ` Alex Deucher
2022-07-14 16:45 ` [PATCH 07/12] drm/amd/display: Remove unused value0 variable Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-18 18:58   ` Alex Deucher
2022-07-18 18:58     ` Alex Deucher
2022-07-14 16:45 ` [PATCH 08/12] drm/amd/display: Remove unused variables from dcn10_stream_encoder Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-18 18:59   ` Alex Deucher
2022-07-18 18:59     ` Alex Deucher
2022-07-14 16:45 ` [PATCH 09/12] drm/amd/display: Remove unused MaxUsedBW variable Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-18 19:00   ` Alex Deucher
2022-07-18 19:00     ` Alex Deucher
2022-07-14 16:45 ` [PATCH 10/12] drm/amd/display: Remove parameters from dml30_CalculateWriteBackDISPCLK Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-18 19:02   ` Alex Deucher
2022-07-18 19:02     ` Alex Deucher
2022-07-19 10:49     ` Maíra Canal
2022-07-19 10:49       ` Maíra Canal
2022-07-19 13:03       ` Alex Deucher
2022-07-19 13:03         ` Alex Deucher
2022-07-14 16:45 ` [PATCH 11/12] drm/amd/display: Remove duplicated CalculateWriteBackDISPCLK Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-14 16:45 ` [PATCH 12/12] drm/amd/display: Rewrite CalculateWriteBackDISPCLK function Maíra Canal
2022-07-14 16:45   ` Maíra Canal
2022-07-15  1:53   ` André Almeida
2022-07-15  1:53     ` André Almeida
2022-07-14 19:04 ` [PATCH 01/12] drm/amdgpu: Write masked value to control register André Almeida
2022-07-14 19:04   ` André Almeida
2022-07-14 19:14   ` Alex Deucher
2022-07-14 19:14     ` Alex Deucher
2022-07-14 19:20     ` André Almeida
2022-07-14 19:20       ` André Almeida
2022-07-15  1:56 ` André Almeida
2022-07-18 19:07 ` Alex Deucher
2022-07-18 19:07   ` Alex Deucher

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