[PATCH 0/3] arm64/sysreg: Automatic generation of ID_AA64MMFR1_EL1

[PATCH 0/3] arm64/sysreg: Automatic generation of ID_AA64MMFR1_EL1

[Kristina Martsenko]

This series converts one more system register (ID_AA64MMFR1_EL1) to use the
recently added automatic generation script.

Note, this series applies on top of Mark's latest sysreg conversion series [1].

[1] https://lore.kernel.org/all/20220707181220.3373540-1-broonie@kernel.org/


Kristina Martsenko (3):
  arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK
  arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields
  arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation

 arch/arm64/include/asm/cache.h                |  4 --
 arch/arm64/include/asm/cpufeature.h           |  8 +--
 arch/arm64/include/asm/el2_setup.h            |  2 +-
 arch/arm64/include/asm/sysreg.h               | 23 ------
 arch/arm64/kernel/cpufeature.c                | 36 +++++-----
 arch/arm64/kernel/hyp-stub.S                  |  4 +-
 arch/arm64/kernel/idreg-override.c            |  2 +-
 arch/arm64/kernel/proton-pack.c               |  2 +-
 .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 12 ++--
 arch/arm64/kvm/hyp/nvhe/pkvm.c                |  2 +-
 arch/arm64/kvm/sys_regs.c                     |  2 +-
 arch/arm64/tools/sysreg                       | 71 +++++++++++++++++++
 12 files changed, 106 insertions(+), 62 deletions(-)

-- 
2.25.1


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[PATCH 1/3] arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK

[Kristina Martsenko]

A recent change renamed CTR_DMINLINE_SHIFT to CTR_EL0_DminLine_SHIFT but
didn't fully update CTR_CACHE_MINLINE_MASK. As CTR_CACHE_MINLINE_MASK is
not used anywhere anyway, just remove it.

Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
---
 arch/arm64/include/asm/cache.h | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index ca9b487112cc..119e4aa02eb1 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -45,10 +45,6 @@ static inline unsigned int arch_slab_minalign(void)
 #define arch_slab_minalign() arch_slab_minalign()
 #endif
 
-#define CTR_CACHE_MINLINE_MASK	\
-	(0xf << CTR_EL0_DMINLINE_SHIFT | \
-	 CTR_EL0_IMINLINE_MASK << CTR_EL0_IMINLINE_SHIFT)
-
 #define CTR_L1IP(ctr)		SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
 
 #define ICACHEF_ALIASING	0
-- 
2.25.1


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[PATCH 2/3] arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields

[Kristina Martsenko]

In preparation for converting the ID_AA64MMFR1_EL1 system register
defines to automatic generation, rename them to follow the conventions
used by other automatically generated registers:

 * Add _EL1 in the register name.

 * Rename fields to match the names in the ARM ARM:
   * LOR -> LO
   * HPD -> HPDS
   * VHE -> VH
   * HADBS -> HAFDBS
   * SPECSEI -> SpecSEI
   * VMIDBITS -> VMIDBits

There should be no functional change as a result of this patch.

Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
---
 arch/arm64/include/asm/cpufeature.h           |  8 ++--
 arch/arm64/include/asm/el2_setup.h            |  2 +-
 arch/arm64/include/asm/sysreg.h               | 40 +++++++++----------
 arch/arm64/kernel/cpufeature.c                | 36 ++++++++---------
 arch/arm64/kernel/hyp-stub.S                  |  4 +-
 arch/arm64/kernel/idreg-override.c            |  2 +-
 arch/arm64/kernel/proton-pack.c               |  2 +-
 .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 12 +++---
 arch/arm64/kvm/hyp/nvhe/pkvm.c                |  2 +-
 arch/arm64/kvm/sys_regs.c                     |  2 +-
 10 files changed, 55 insertions(+), 55 deletions(-)

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index db6d1405d8d2..f151949fec03 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -868,14 +868,14 @@ static inline bool cpu_has_hw_af(void)
 
 	mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 	return cpuid_feature_extract_unsigned_field(mmfr1,
-						ID_AA64MMFR1_HADBS_SHIFT);
+						ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
 }
 
 static inline bool cpu_has_pan(void)
 {
 	u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 	return cpuid_feature_extract_unsigned_field(mmfr1,
-						    ID_AA64MMFR1_PAN_SHIFT);
+						    ID_AA64MMFR1_EL1_PAN_SHIFT);
 }
 
 #ifdef CONFIG_ARM64_AMU_EXTN
@@ -896,8 +896,8 @@ static inline unsigned int get_vmid_bits(u64 mmfr1)
 	int vmid_bits;
 
 	vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
-						ID_AA64MMFR1_VMIDBITS_SHIFT);
-	if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16)
+						ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
+	if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
 		return 16;
 
 	/*
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 5b94a3b520f8..2fd47267c844 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -83,7 +83,7 @@
 /* LORegions */
 .macro __init_el2_lor
 	mrs	x1, id_aa64mmfr1_el1
-	ubfx	x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4
+	ubfx	x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4
 	cbz	x0, .Lskip_lor_\@
 	msr_s	SYS_LORC_EL1, xzr
 .Lskip_lor_\@:
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0893c63651d1..be76b329c0bc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -763,26 +763,26 @@
 #endif
 
 /* id_aa64mmfr1 */
-#define ID_AA64MMFR1_ECBHB_SHIFT	60
-#define ID_AA64MMFR1_TIDCP1_SHIFT	52
-#define ID_AA64MMFR1_HCX_SHIFT		40
-#define ID_AA64MMFR1_AFP_SHIFT		44
-#define ID_AA64MMFR1_ETS_SHIFT		36
-#define ID_AA64MMFR1_TWED_SHIFT		32
-#define ID_AA64MMFR1_XNX_SHIFT		28
-#define ID_AA64MMFR1_SPECSEI_SHIFT	24
-#define ID_AA64MMFR1_PAN_SHIFT		20
-#define ID_AA64MMFR1_LOR_SHIFT		16
-#define ID_AA64MMFR1_HPD_SHIFT		12
-#define ID_AA64MMFR1_VHE_SHIFT		8
-#define ID_AA64MMFR1_VMIDBITS_SHIFT	4
-#define ID_AA64MMFR1_HADBS_SHIFT	0
-
-#define ID_AA64MMFR1_VMIDBITS_8		0
-#define ID_AA64MMFR1_VMIDBITS_16	2
-
-#define ID_AA64MMFR1_TIDCP1_NI		0
-#define ID_AA64MMFR1_TIDCP1_IMP		1
+#define ID_AA64MMFR1_EL1_ECBHB_SHIFT		60
+#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT		52
+#define ID_AA64MMFR1_EL1_HCX_SHIFT		40
+#define ID_AA64MMFR1_EL1_AFP_SHIFT		44
+#define ID_AA64MMFR1_EL1_ETS_SHIFT		36
+#define ID_AA64MMFR1_EL1_TWED_SHIFT		32
+#define ID_AA64MMFR1_EL1_XNX_SHIFT		28
+#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT		24
+#define ID_AA64MMFR1_EL1_PAN_SHIFT		20
+#define ID_AA64MMFR1_EL1_LO_SHIFT		16
+#define ID_AA64MMFR1_EL1_HPDS_SHIFT		12
+#define ID_AA64MMFR1_EL1_VH_SHIFT		8
+#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT		4
+#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT		0
+
+#define ID_AA64MMFR1_EL1_VMIDBits_8		0
+#define ID_AA64MMFR1_EL1_VMIDBits_16		2
+
+#define ID_AA64MMFR1_EL1_TIDCP1_NI		0
+#define ID_AA64MMFR1_EL1_TIDCP1_IMP		1
 
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_E0PD_SHIFT		60
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 591664da7b89..ba70a1c8b7e8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -361,18 +361,18 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TIDCP1_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_AFP_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0),
 	ARM64_FTR_END,
 };
 
@@ -2087,7 +2087,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
 		.matches = has_cpuid_feature,
 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
-		.field_pos = ID_AA64MMFR1_PAN_SHIFT,
+		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
 		.field_width = 4,
 		.sign = FTR_UNSIGNED,
 		.min_field_value = 1,
@@ -2101,7 +2101,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
 		.matches = has_cpuid_feature,
 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
-		.field_pos = ID_AA64MMFR1_PAN_SHIFT,
+		.field_pos = ID_AA64MMFR1_EL1_PAN_SHIFT,
 		.field_width = 4,
 		.sign = FTR_UNSIGNED,
 		.min_field_value = 3,
@@ -2315,7 +2315,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.capability = ARM64_HW_DBM,
 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
 		.sign = FTR_UNSIGNED,
-		.field_pos = ID_AA64MMFR1_HADBS_SHIFT,
+		.field_pos = ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
 		.field_width = 4,
 		.min_field_value = 2,
 		.matches = has_hw_dbm,
@@ -2587,9 +2587,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
 		.sign = FTR_UNSIGNED,
-		.field_pos = ID_AA64MMFR1_TIDCP1_SHIFT,
+		.field_pos = ID_AA64MMFR1_EL1_TIDCP1_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64MMFR1_TIDCP1_IMP,
+		.min_field_value = ID_AA64MMFR1_EL1_TIDCP1_IMP,
 		.matches = has_cpuid_feature,
 		.cpu_enable = cpu_trap_el0_impdef,
 	},
@@ -2724,7 +2724,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_EL1_MTE_MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3),
 #endif /* CONFIG_ARM64_MTE */
 	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
-	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
+	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
 	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
 	HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
 #ifdef CONFIG_ARM64_SME
diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S
index eae2273dd990..fcbd6bb9c27f 100644
--- a/arch/arm64/kernel/hyp-stub.S
+++ b/arch/arm64/kernel/hyp-stub.S
@@ -142,7 +142,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 	msr_s	SYS_SMPRIMAP_EL2, xzr		// Make all priorities equal
 
 	mrs	x1, id_aa64mmfr1_el1		// HCRX_EL2 present?
-	ubfx	x1, x1, #ID_AA64MMFR1_HCX_SHIFT, #4
+	ubfx	x1, x1, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4
 	cbz	x1, .Lskip_sme
 
 	mrs_s	x1, SYS_HCRX_EL2
@@ -157,7 +157,7 @@ SYM_CODE_START_LOCAL(__finalise_el2)
 	tbnz	x1, #0, 1f
 
 	// Needs to be VHE capable, obviously
-	check_override id_aa64mmfr1 ID_AA64MMFR1_VHE_SHIFT 2f 1f
+	check_override id_aa64mmfr1 ID_AA64MMFR1_EL1_VH_SHIFT 2f 1f
 
 1:	mov_q	x0, HVC_STUB_ERR
 	eret
diff --git a/arch/arm64/kernel/idreg-override.c b/arch/arm64/kernel/idreg-override.c
index af81ec51366a..77d1d1f7dc15 100644
--- a/arch/arm64/kernel/idreg-override.c
+++ b/arch/arm64/kernel/idreg-override.c
@@ -50,7 +50,7 @@ static const struct ftr_set_desc mmfr1 __initconst = {
 	.name		= "id_aa64mmfr1",
 	.override	= &id_aa64mmfr1_override,
 	.fields		= {
-		FIELD("vh", ID_AA64MMFR1_VHE_SHIFT, mmfr1_vh_filter),
+		FIELD("vh", ID_AA64MMFR1_EL1_VH_SHIFT, mmfr1_vh_filter),
 		{}
 	},
 };
diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pack.c
index 40be3a7c2c53..561d84d82f34 100644
--- a/arch/arm64/kernel/proton-pack.c
+++ b/arch/arm64/kernel/proton-pack.c
@@ -945,7 +945,7 @@ static bool supports_ecbhb(int scope)
 		mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
 
 	return cpuid_feature_extract_unsigned_field(mmfr1,
-						    ID_AA64MMFR1_ECBHB_SHIFT);
+						    ID_AA64MMFR1_EL1_ECBHB_SHIFT);
 }
 
 bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry,
diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 2f2ce19e4cba..3b4867c953d7 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -100,12 +100,12 @@
  * - Enhanced Translation Synchronization
  */
 #define PVM_ID_AA64MMFR1_ALLOW (\
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_HADBS) | \
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_VMIDBITS) | \
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_HPD) | \
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_PAN) | \
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_SPECSEI) | \
-	ARM64_FEATURE_MASK(ID_AA64MMFR1_ETS) \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HAFDBS) | \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_VMIDBits) | \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_HPDS) | \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_PAN) | \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_SpecSEI) | \
+	ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_ETS) \
 	)
 
 /*
diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index dbdc384d796c..22010686f59d 100644
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -143,7 +143,7 @@ static void pvm_init_traps_aa64mmfr1(struct kvm_vcpu *vcpu)
 	u64 hcr_set = 0;
 
 	/* Trap LOR */
-	if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_LOR), feature_ids))
+	if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR1_EL1_LO), feature_ids))
 		hcr_set |= HCR_TLOR;
 
 	vcpu->arch.hcr_el2 |= hcr_set;
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 5037dda33a24..12ea6b14af14 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -280,7 +280,7 @@ static bool trap_loregion(struct kvm_vcpu *vcpu,
 	u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
 	u32 sr = reg_to_encoding(r);
 
-	if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
+	if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
 		kvm_inject_undefined(vcpu);
 		return false;
 	}
-- 
2.25.1


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[PATCH 3/3] arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation

[Kristina Martsenko]

Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a,
no functional changes.

Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 23 -----------
 arch/arm64/tools/sysreg         | 71 +++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+), 23 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index be76b329c0bc..6f66f2189e88 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -200,7 +200,6 @@
 #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
 
 #define SYS_ID_AA64MMFR0_EL1		sys_reg(3, 0, 0, 7, 0)
-#define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
 
 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
@@ -762,28 +761,6 @@
 #define ID_AA64MMFR0_PARANGE_MAX	ID_AA64MMFR0_PARANGE_48
 #endif
 
-/* id_aa64mmfr1 */
-#define ID_AA64MMFR1_EL1_ECBHB_SHIFT		60
-#define ID_AA64MMFR1_EL1_TIDCP1_SHIFT		52
-#define ID_AA64MMFR1_EL1_HCX_SHIFT		40
-#define ID_AA64MMFR1_EL1_AFP_SHIFT		44
-#define ID_AA64MMFR1_EL1_ETS_SHIFT		36
-#define ID_AA64MMFR1_EL1_TWED_SHIFT		32
-#define ID_AA64MMFR1_EL1_XNX_SHIFT		28
-#define ID_AA64MMFR1_EL1_SpecSEI_SHIFT		24
-#define ID_AA64MMFR1_EL1_PAN_SHIFT		20
-#define ID_AA64MMFR1_EL1_LO_SHIFT		16
-#define ID_AA64MMFR1_EL1_HPDS_SHIFT		12
-#define ID_AA64MMFR1_EL1_VH_SHIFT		8
-#define ID_AA64MMFR1_EL1_VMIDBits_SHIFT		4
-#define ID_AA64MMFR1_EL1_HAFDBS_SHIFT		0
-
-#define ID_AA64MMFR1_EL1_VMIDBits_8		0
-#define ID_AA64MMFR1_EL1_VMIDBits_16		2
-
-#define ID_AA64MMFR1_EL1_TIDCP1_NI		0
-#define ID_AA64MMFR1_EL1_TIDCP1_IMP		1
-
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_E0PD_SHIFT		60
 #define ID_AA64MMFR2_EVT_SHIFT		56
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 1ffde974d766..24cf02daaa6a 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -358,6 +358,77 @@ Enum	3:0	WFxT
 EndEnum
 EndSysreg
 
+Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
+Enum	63:60	ECBHB
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	59:56	CMOW
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	55:52	TIDCP1
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	51:48	nTLBPA
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	47:44	AFP
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	43:40	HCX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	39:36	ETS
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	35:32	TWED
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	31:28	XNX
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	27:24	SpecSEI
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	23:20	PAN
+	0b0000	NI
+	0b0001	IMP
+	0b0010	PAN2
+	0b0011	PAN3
+EndEnum
+Enum	19:16	LO
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	15:12	HPDS
+	0b0000	NI
+	0b0001	IMP
+	0b0010	HPDS2
+EndEnum
+Enum	11:8	VH
+	0b0000	NI
+	0b0001	IMP
+EndEnum
+Enum	7:4	VMIDBits
+	0b0000	8
+	0b0010	16
+EndEnum
+Enum	3:0	HAFDBS
+	0b0000	NI
+	0b0001	AF
+	0b0010	DBM
+EndEnum
+EndSysreg
+
 Sysreg	SCTLR_EL1	3	0	1	0	0
 Field	63	TIDCP
 Field	62	SPINMASK
-- 
2.25.1


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Re: [PATCH 1/3] arm64: cache: Remove unused CTR_CACHE_MINLINE_MASK

[Mark Brown]

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On Mon, Jul 18, 2022 at 12:29:24PM +0100, Kristina Martsenko wrote:
> A recent change renamed CTR_DMINLINE_SHIFT to CTR_EL0_DminLine_SHIFT but
> didn't fully update CTR_CACHE_MINLINE_MASK. As CTR_CACHE_MINLINE_MASK is
> not used anywhere anyway, just remove it.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH 3/3] arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation

[Mark Brown]

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On Mon, Jul 18, 2022 at 12:29:26PM +0100, Kristina Martsenko wrote:

> Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a,
> no functional changes.

> +Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
> +Enum	63:60	ECBHB
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum

This is RES0 in DDI0487H.a, but was already present upstream so it's
fine just not quite what the changelog said.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH 2/3] arm64/sysreg: Standardise naming for ID_AA64MMFR1_EL1 fields

[Mark Brown]

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On Mon, Jul 18, 2022 at 12:29:25PM +0100, Kristina Martsenko wrote:
> In preparation for converting the ID_AA64MMFR1_EL1 system register
> defines to automatic generation, rename them to follow the conventions
> used by other automatically generated registers:
> 
>  * Add _EL1 in the register name.
> 
>  * Rename fields to match the names in the ARM ARM:
>    * LOR -> LO
>    * HPD -> HPDS
>    * VHE -> VH
>    * HADBS -> HAFDBS
>    * SPECSEI -> SpecSEI
>    * VMIDBITS -> VMIDBits
> 
> There should be no functional change as a result of this patch.

FWIW I tend to do these as several individual patches because it is
easier to verify a single mechanical change at once (especially the
bigger ones like adding _EL1) than to keep multiple changes in mind
at once when checking if the patch is doing what it should.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH 3/3] arm64/sysreg: Convert ID_AA64MMFR1_EL1 to automatic generation

[Kristina Martsenko]

On 18/07/2022 13:02, Mark Brown wrote:
> On Mon, Jul 18, 2022 at 12:29:26PM +0100, Kristina Martsenko wrote:
> 
>> Convert ID_AA64MMFR1_EL1 to be automatically generated as per DDI0487H.a,
>> no functional changes.
> 
>> +Sysreg	ID_AA64MMFR1_EL1	3	0	0	7	1
>> +Enum	63:60	ECBHB
>> +	0b0000	NI
>> +	0b0001	IMP
>> +EndEnum
> 
> This is RES0 in DDI0487H.a, but was already present upstream so it's
> fine just not quite what the changelog said.

Good point, I'll update the commit message if I need to send a new version.

Thanks,
Kristina


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Re: [PATCH 0/3] arm64/sysreg: Automatic generation of ID_AA64MMFR1_EL1

[Mark Brown]

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On Mon, Jul 18, 2022 at 12:29:23PM +0100, Kristina Martsenko wrote:
> This series converts one more system register (ID_AA64MMFR1_EL1) to use the
> recently added automatic generation script.

I've got more of these conversions in my backlog for after the merge
window, this didn't get applied so are you OK with me including the
series with these new ones when I send them out?  Seems sensible to
combine things.

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Re: [PATCH 0/3] arm64/sysreg: Automatic generation of ID_AA64MMFR1_EL1

[Kristina Martsenko]

On 01/08/2022 17:14, Mark Brown wrote:
> On Mon, Jul 18, 2022 at 12:29:23PM +0100, Kristina Martsenko wrote:
>> This series converts one more system register (ID_AA64MMFR1_EL1) to use the
>> recently added automatic generation script.
> 
> I've got more of these conversions in my backlog for after the merge
> window, this didn't get applied so are you OK with me including the
> series with these new ones when I send them out?  Seems sensible to
> combine things.

Sure, that makes sense to me. Thanks.

Kristina

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