* [PATCH 00/22] ARM: Add Rockchip RV1126 support
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch series add basic core support for Rockchip RV1126.
Tested in Edgeble AI Edge Compute Module 0.
Anyone interested, please have a look on this repo [1]
[1] https://github.com/edgeble/linux-next/commits/ecm0-v4
Any inputs?
Jagan.
Elaine Zhang (1):
clk: rockchip: Add MUXTBL variant
Jagan Teki (20):
dt-bindings: power: rockchip: Document RV1126 power-controller
dt-bindings: power: Add power-domain header for RV1126
soc: rockchip: power-domain: Add RV1126 power domains
dt-bindings: power: rockchip: Document RV1126 PMU IO domains
dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
pinctrl: rockchip: Add RV1126 pinctrl support
dt-bindings: clock: rockchip: Document RV1126 CRU
clk: rockchip: Add RV1126 clock controller
dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
dt-bindings: soc: rockchip: Document RV1126 grf
dt-bindings: soc: rockchip: Document RV1126 pmugrf
dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
ARM: dts: rockchip: Add Rockchip RV1126 SoC
dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0
ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier
ARM: configs: Add RV1126 ECM0 fragment config
Jianqun Xu (1):
soc: rockchip: io-domain: Add RV1126 IO domains
.../devicetree/bindings/arm/rockchip.yaml | 6 +
.../bindings/clock/rockchip,rv1126-cru.yaml | 70 ++
.../devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
.../devicetree/bindings/mfd/syscon.yaml | 1 +
.../bindings/mmc/rockchip-dw-mshc.yaml | 1 +
.../bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
.../power/rockchip,power-controller.yaml | 2 +
.../bindings/power/rockchip-io-domain.yaml | 30 +
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
.../devicetree/bindings/soc/rockchip/grf.yaml | 2 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 2 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rockchip-pinconf.dtsi | 115 ++
.../rv1126-edge-compute-module-0-carrier.dts | 38 +
.../dts/rv1126-edge-compute-module-0.dtsi | 329 +++++
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 +++++
arch/arm/boot/dts/rv1126.dtsi | 500 ++++++++
arch/arm/configs/rv1126-ecm0.config | 3 +
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1126.c | 1107 +++++++++++++++++
drivers/clk/rockchip/clk.c | 27 +-
drivers/clk/rockchip/clk.h | 36 +
drivers/pinctrl/pinctrl-rockchip.c | 333 ++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
drivers/soc/rockchip/io-domain.c | 20 +
drivers/soc/rockchip/pm_domains.c | 29 +
include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++
include/dt-bindings/power/rv1126-power.h | 34 +
30 files changed, 3620 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
create mode 100644 arch/arm/boot/dts/rockchip-pinconf.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
create mode 100644 arch/arm/configs/rv1126-ecm0.config
create mode 100644 drivers/clk/rockchip/clk-rv1126.c
create mode 100644 include/dt-bindings/clock/rv1126-cru.h
create mode 100644 include/dt-bindings/power/rv1126-power.h
--
2.25.1
^ permalink raw reply [flat|nested] 144+ messages in thread
* [PATCH 00/22] ARM: Add Rockchip RV1126 support
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch series add basic core support for Rockchip RV1126.
Tested in Edgeble AI Edge Compute Module 0.
Anyone interested, please have a look on this repo [1]
[1] https://github.com/edgeble/linux-next/commits/ecm0-v4
Any inputs?
Jagan.
Elaine Zhang (1):
clk: rockchip: Add MUXTBL variant
Jagan Teki (20):
dt-bindings: power: rockchip: Document RV1126 power-controller
dt-bindings: power: Add power-domain header for RV1126
soc: rockchip: power-domain: Add RV1126 power domains
dt-bindings: power: rockchip: Document RV1126 PMU IO domains
dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
pinctrl: rockchip: Add RV1126 pinctrl support
dt-bindings: clock: rockchip: Document RV1126 CRU
clk: rockchip: Add RV1126 clock controller
dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
dt-bindings: soc: rockchip: Document RV1126 grf
dt-bindings: soc: rockchip: Document RV1126 pmugrf
dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
ARM: dts: rockchip: Add Rockchip RV1126 SoC
dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0
ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier
ARM: configs: Add RV1126 ECM0 fragment config
Jianqun Xu (1):
soc: rockchip: io-domain: Add RV1126 IO domains
.../devicetree/bindings/arm/rockchip.yaml | 6 +
.../bindings/clock/rockchip,rv1126-cru.yaml | 70 ++
.../devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
.../devicetree/bindings/mfd/syscon.yaml | 1 +
.../bindings/mmc/rockchip-dw-mshc.yaml | 1 +
.../bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
.../power/rockchip,power-controller.yaml | 2 +
.../bindings/power/rockchip-io-domain.yaml | 30 +
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
.../devicetree/bindings/soc/rockchip/grf.yaml | 2 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 2 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rockchip-pinconf.dtsi | 115 ++
.../rv1126-edge-compute-module-0-carrier.dts | 38 +
.../dts/rv1126-edge-compute-module-0.dtsi | 329 +++++
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 +++++
arch/arm/boot/dts/rv1126.dtsi | 500 ++++++++
arch/arm/configs/rv1126-ecm0.config | 3 +
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1126.c | 1107 +++++++++++++++++
drivers/clk/rockchip/clk.c | 27 +-
drivers/clk/rockchip/clk.h | 36 +
drivers/pinctrl/pinctrl-rockchip.c | 333 ++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
drivers/soc/rockchip/io-domain.c | 20 +
drivers/soc/rockchip/pm_domains.c | 29 +
include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++
include/dt-bindings/power/rv1126-power.h | 34 +
30 files changed, 3620 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
create mode 100644 arch/arm/boot/dts/rockchip-pinconf.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
create mode 100644 arch/arm/configs/rv1126-ecm0.config
create mode 100644 drivers/clk/rockchip/clk-rv1126.c
create mode 100644 include/dt-bindings/clock/rv1126-cru.h
create mode 100644 include/dt-bindings/power/rv1126-power.h
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* [PATCH 00/22] ARM: Add Rockchip RV1126 support
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch series add basic core support for Rockchip RV1126.
Tested in Edgeble AI Edge Compute Module 0.
Anyone interested, please have a look on this repo [1]
[1] https://github.com/edgeble/linux-next/commits/ecm0-v4
Any inputs?
Jagan.
Elaine Zhang (1):
clk: rockchip: Add MUXTBL variant
Jagan Teki (20):
dt-bindings: power: rockchip: Document RV1126 power-controller
dt-bindings: power: Add power-domain header for RV1126
soc: rockchip: power-domain: Add RV1126 power domains
dt-bindings: power: rockchip: Document RV1126 PMU IO domains
dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
pinctrl: rockchip: Add RV1126 pinctrl support
dt-bindings: clock: rockchip: Document RV1126 CRU
clk: rockchip: Add RV1126 clock controller
dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
dt-bindings: soc: rockchip: Document RV1126 grf
dt-bindings: soc: rockchip: Document RV1126 pmugrf
dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
ARM: dts: rockchip: Add Rockchip RV1126 SoC
dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0
ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier
ARM: configs: Add RV1126 ECM0 fragment config
Jianqun Xu (1):
soc: rockchip: io-domain: Add RV1126 IO domains
.../devicetree/bindings/arm/rockchip.yaml | 6 +
.../bindings/clock/rockchip,rv1126-cru.yaml | 70 ++
.../devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
.../devicetree/bindings/mfd/syscon.yaml | 1 +
.../bindings/mmc/rockchip-dw-mshc.yaml | 1 +
.../bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
.../power/rockchip,power-controller.yaml | 2 +
.../bindings/power/rockchip-io-domain.yaml | 30 +
.../bindings/serial/snps-dw-apb-uart.yaml | 1 +
.../devicetree/bindings/soc/rockchip/grf.yaml | 2 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 2 +-
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rockchip-pinconf.dtsi | 115 ++
.../rv1126-edge-compute-module-0-carrier.dts | 38 +
.../dts/rv1126-edge-compute-module-0.dtsi | 329 +++++
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 +++++
arch/arm/boot/dts/rv1126.dtsi | 500 ++++++++
arch/arm/configs/rv1126-ecm0.config | 3 +
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1126.c | 1107 +++++++++++++++++
drivers/clk/rockchip/clk.c | 27 +-
drivers/clk/rockchip/clk.h | 36 +
drivers/pinctrl/pinctrl-rockchip.c | 333 ++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
drivers/soc/rockchip/io-domain.c | 20 +
drivers/soc/rockchip/pm_domains.c | 29 +
include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++
include/dt-bindings/power/rv1126-power.h | 34 +
30 files changed, 3620 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
create mode 100644 arch/arm/boot/dts/rockchip-pinconf.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
create mode 100644 arch/arm/configs/rv1126-ecm0.config
create mode 100644 drivers/clk/rockchip/clk-rv1126.c
create mode 100644 include/dt-bindings/clock/rv1126-cru.h
create mode 100644 include/dt-bindings/power/rv1126-power.h
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document dt-bindings for RV1126 power-controller.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
index 3deb0fc8dfd3..602f08a76f2c 100644
--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -41,6 +41,7 @@ properties:
- rockchip,rk3368-power-controller
- rockchip,rk3399-power-controller
- rockchip,rk3568-power-controller
+ - rockchip,rv1126-power-controller
"#power-domain-cells":
const: 1
@@ -119,6 +120,7 @@ $defs:
"include/dt-bindings/power/rk3368-power.h"
"include/dt-bindings/power/rk3399-power.h"
"include/dt-bindings/power/rk3568-power.h"
+ "include/dt-bindings/power/rv1126-power.h"
clocks:
minItems: 1
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document dt-bindings for RV1126 power-controller.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
index 3deb0fc8dfd3..602f08a76f2c 100644
--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -41,6 +41,7 @@ properties:
- rockchip,rk3368-power-controller
- rockchip,rk3399-power-controller
- rockchip,rk3568-power-controller
+ - rockchip,rv1126-power-controller
"#power-domain-cells":
const: 1
@@ -119,6 +120,7 @@ $defs:
"include/dt-bindings/power/rk3368-power.h"
"include/dt-bindings/power/rk3399-power.h"
"include/dt-bindings/power/rk3568-power.h"
+ "include/dt-bindings/power/rv1126-power.h"
clocks:
minItems: 1
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document dt-bindings for RV1126 power-controller.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
index 3deb0fc8dfd3..602f08a76f2c 100644
--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
@@ -41,6 +41,7 @@ properties:
- rockchip,rk3368-power-controller
- rockchip,rk3399-power-controller
- rockchip,rk3568-power-controller
+ - rockchip,rv1126-power-controller
"#power-domain-cells":
const: 1
@@ -119,6 +120,7 @@ $defs:
"include/dt-bindings/power/rk3368-power.h"
"include/dt-bindings/power/rk3399-power.h"
"include/dt-bindings/power/rk3568-power.h"
+ "include/dt-bindings/power/rv1126-power.h"
clocks:
minItems: 1
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Elaine Zhang
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 include/dt-bindings/power/rv1126-power.h
diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
new file mode 100644
index 000000000000..f15930ff06f7
--- /dev/null
+++ b/include/dt-bindings/power/rv1126-power.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
+#define __DT_BINDINGS_POWER_RV1126_POWER_H__
+
+/* VD_CORE */
+#define RV1126_PD_CPU_0 0
+#define RV1126_PD_CPU_1 1
+#define RV1126_PD_CPU_2 2
+#define RV1126_PD_CPU_3 3
+#define RV1126_PD_CORE_ALIVE 4
+
+/* VD_PMU */
+#define RV1126_PD_PMU 5
+#define RV1126_PD_PMU_ALIVE 6
+
+/* VD_NPU */
+#define RV1126_PD_NPU 7
+
+/* VD_VEPU */
+#define RV1126_PD_VEPU 8
+
+/* VD_LOGIC */
+#define RV1126_PD_VI 9
+#define RV1126_PD_VO 10
+#define RV1126_PD_ISPP 11
+#define RV1126_PD_VDPU 12
+#define RV1126_PD_CRYPTO 13
+#define RV1126_PD_DDR 14
+#define RV1126_PD_NVM 15
+#define RV1126_PD_SDIO 16
+#define RV1126_PD_USB 17
+#define RV1126_PD_LOGIC_ALIVE 18
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Elaine Zhang
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 include/dt-bindings/power/rv1126-power.h
diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
new file mode 100644
index 000000000000..f15930ff06f7
--- /dev/null
+++ b/include/dt-bindings/power/rv1126-power.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
+#define __DT_BINDINGS_POWER_RV1126_POWER_H__
+
+/* VD_CORE */
+#define RV1126_PD_CPU_0 0
+#define RV1126_PD_CPU_1 1
+#define RV1126_PD_CPU_2 2
+#define RV1126_PD_CPU_3 3
+#define RV1126_PD_CORE_ALIVE 4
+
+/* VD_PMU */
+#define RV1126_PD_PMU 5
+#define RV1126_PD_PMU_ALIVE 6
+
+/* VD_NPU */
+#define RV1126_PD_NPU 7
+
+/* VD_VEPU */
+#define RV1126_PD_VEPU 8
+
+/* VD_LOGIC */
+#define RV1126_PD_VI 9
+#define RV1126_PD_VO 10
+#define RV1126_PD_ISPP 11
+#define RV1126_PD_VDPU 12
+#define RV1126_PD_CRYPTO 13
+#define RV1126_PD_DDR 14
+#define RV1126_PD_NVM 15
+#define RV1126_PD_SDIO 16
+#define RV1126_PD_USB 17
+#define RV1126_PD_LOGIC_ALIVE 18
+
+#endif
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Elaine Zhang
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 include/dt-bindings/power/rv1126-power.h
diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
new file mode 100644
index 000000000000..f15930ff06f7
--- /dev/null
+++ b/include/dt-bindings/power/rv1126-power.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
+#define __DT_BINDINGS_POWER_RV1126_POWER_H__
+
+/* VD_CORE */
+#define RV1126_PD_CPU_0 0
+#define RV1126_PD_CPU_1 1
+#define RV1126_PD_CPU_2 2
+#define RV1126_PD_CPU_3 3
+#define RV1126_PD_CORE_ALIVE 4
+
+/* VD_PMU */
+#define RV1126_PD_PMU 5
+#define RV1126_PD_PMU_ALIVE 6
+
+/* VD_NPU */
+#define RV1126_PD_NPU 7
+
+/* VD_VEPU */
+#define RV1126_PD_VEPU 8
+
+/* VD_LOGIC */
+#define RV1126_PD_VI 9
+#define RV1126_PD_VO 10
+#define RV1126_PD_ISPP 11
+#define RV1126_PD_VDPU 12
+#define RV1126_PD_CRYPTO 13
+#define RV1126_PD_DDR 14
+#define RV1126_PD_NVM 15
+#define RV1126_PD_SDIO 16
+#define RV1126_PD_USB 17
+#define RV1126_PD_LOGIC_ALIVE 18
+
+#endif
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 03/22] soc: rockchip: power-domain: Add RV1126 power domains
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Elaine Zhang
Add power domains support for RV1126 SoC.
Cypto, VO and NPU domains will add it future patches.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/soc/rockchip/pm_domains.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 89795abac951..7b41cd19f013 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -19,6 +19,7 @@
#include <linux/mfd/syscon.h>
#include <soc/rockchip/pm_domains.h>
#include <dt-bindings/power/px30-power.h>
+#include <dt-bindings/power/rv1126-power.h>
#include <dt-bindings/power/rk3036-power.h>
#include <dt-bindings/power/rk3066-power.h>
#include <dt-bindings/power/rk3128-power.h>
@@ -126,6 +127,9 @@ struct rockchip_pmu {
#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
+
#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
@@ -855,6 +859,16 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
};
+static const struct rockchip_domain_info rv1126_pm_domains[] = {
+ [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
+ [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
+ [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
+ [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
+ [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
+ [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
+ [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
+};
+
static const struct rockchip_domain_info rk3036_pm_domains[] = {
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
@@ -1128,6 +1142,17 @@ static const struct rockchip_pmu_info rk3568_pmu = {
.domain_info = rk3568_pm_domains,
};
+static const struct rockchip_pmu_info rv1126_pmu = {
+ .pwr_offset = 0x110,
+ .status_offset = 0x108,
+ .req_offset = 0xc0,
+ .idle_offset = 0xd8,
+ .ack_offset = 0xd0,
+
+ .num_domains = ARRAY_SIZE(rv1126_pm_domains),
+ .domain_info = rv1126_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1177,6 +1202,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3568-power-controller",
.data = (void *)&rk3568_pmu,
},
+ {
+ .compatible = "rockchip,rv1126-power-controller",
+ .data = (void *)&rv1126_pmu,
+ },
{ /* sentinel */ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 03/22] soc: rockchip: power-domain: Add RV1126 power domains
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Elaine Zhang
Add power domains support for RV1126 SoC.
Cypto, VO and NPU domains will add it future patches.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/soc/rockchip/pm_domains.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 89795abac951..7b41cd19f013 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -19,6 +19,7 @@
#include <linux/mfd/syscon.h>
#include <soc/rockchip/pm_domains.h>
#include <dt-bindings/power/px30-power.h>
+#include <dt-bindings/power/rv1126-power.h>
#include <dt-bindings/power/rk3036-power.h>
#include <dt-bindings/power/rk3066-power.h>
#include <dt-bindings/power/rk3128-power.h>
@@ -126,6 +127,9 @@ struct rockchip_pmu {
#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
+
#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
@@ -855,6 +859,16 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
};
+static const struct rockchip_domain_info rv1126_pm_domains[] = {
+ [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
+ [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
+ [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
+ [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
+ [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
+ [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
+ [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
+};
+
static const struct rockchip_domain_info rk3036_pm_domains[] = {
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
@@ -1128,6 +1142,17 @@ static const struct rockchip_pmu_info rk3568_pmu = {
.domain_info = rk3568_pm_domains,
};
+static const struct rockchip_pmu_info rv1126_pmu = {
+ .pwr_offset = 0x110,
+ .status_offset = 0x108,
+ .req_offset = 0xc0,
+ .idle_offset = 0xd8,
+ .ack_offset = 0xd0,
+
+ .num_domains = ARRAY_SIZE(rv1126_pm_domains),
+ .domain_info = rv1126_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1177,6 +1202,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3568-power-controller",
.data = (void *)&rk3568_pmu,
},
+ {
+ .compatible = "rockchip,rv1126-power-controller",
+ .data = (void *)&rv1126_pmu,
+ },
{ /* sentinel */ },
};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 03/22] soc: rockchip: power-domain: Add RV1126 power domains
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Elaine Zhang
Add power domains support for RV1126 SoC.
Cypto, VO and NPU domains will add it future patches.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/soc/rockchip/pm_domains.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/drivers/soc/rockchip/pm_domains.c b/drivers/soc/rockchip/pm_domains.c
index 89795abac951..7b41cd19f013 100644
--- a/drivers/soc/rockchip/pm_domains.c
+++ b/drivers/soc/rockchip/pm_domains.c
@@ -19,6 +19,7 @@
#include <linux/mfd/syscon.h>
#include <soc/rockchip/pm_domains.h>
#include <dt-bindings/power/px30-power.h>
+#include <dt-bindings/power/rv1126-power.h>
#include <dt-bindings/power/rk3036-power.h>
#include <dt-bindings/power/rk3066-power.h>
#include <dt-bindings/power/rk3128-power.h>
@@ -126,6 +127,9 @@ struct rockchip_pmu {
#define DOMAIN_PX30(name, pwr, status, req, wakeup) \
DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
+#define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
+
#define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
@@ -855,6 +859,16 @@ static const struct rockchip_domain_info px30_pm_domains[] = {
[PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
};
+static const struct rockchip_domain_info rv1126_pm_domains[] = {
+ [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
+ [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
+ [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
+ [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
+ [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
+ [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
+ [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
+};
+
static const struct rockchip_domain_info rk3036_pm_domains[] = {
[RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
[RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
@@ -1128,6 +1142,17 @@ static const struct rockchip_pmu_info rk3568_pmu = {
.domain_info = rk3568_pm_domains,
};
+static const struct rockchip_pmu_info rv1126_pmu = {
+ .pwr_offset = 0x110,
+ .status_offset = 0x108,
+ .req_offset = 0xc0,
+ .idle_offset = 0xd8,
+ .ack_offset = 0xd0,
+
+ .num_domains = ARRAY_SIZE(rv1126_pm_domains),
+ .domain_info = rv1126_pm_domains,
+};
+
static const struct of_device_id rockchip_pm_domain_dt_match[] = {
{
.compatible = "rockchip,px30-power-controller",
@@ -1177,6 +1202,10 @@ static const struct of_device_id rockchip_pm_domain_dt_match[] = {
.compatible = "rockchip,rk3568-power-controller",
.data = (void *)&rk3568_pmu,
},
+ {
+ .compatible = "rockchip,rv1126-power-controller",
+ .data = (void *)&rv1126_pmu,
+ },
{ /* sentinel */ },
};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document dt-bindings for RV1126 PMU IO domains.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../bindings/power/rockchip-io-domain.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
index 1727bf108979..d71fc72d4464 100644
--- a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
@@ -58,6 +58,7 @@ properties:
- rockchip,rk3568-pmu-io-voltage-domain
- rockchip,rv1108-io-voltage-domain
- rockchip,rv1108-pmu-io-voltage-domain
+ - rockchip,rv1126-pmu-io-voltage-domain
required:
- compatible
@@ -78,6 +79,7 @@ allOf:
- $ref: "#/$defs/rk3568-pmu"
- $ref: "#/$defs/rv1108"
- $ref: "#/$defs/rv1108-pmu"
+ - $ref: "#/$defs/rv1126-pmu"
$defs:
px30:
@@ -344,6 +346,34 @@ $defs:
pmu-supply:
description: The supply connected to PMUIO_VDD.
+ rv1126-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rv1126-pmu-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+ vccio5-supply:
+ description: The supply connected to VCCIO5.
+ vccio6-supply:
+ description: The supply connected to VCCIO6.
+ vccio7-supply:
+ description: The supply connected to VCCIO7.
+ pmuio0-supply:
+ description: The supply connected to PMUIO0.
+ pmuio1-supply:
+ description: The supply connected to PMUIO1.
+
examples:
- |
io-domains {
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document dt-bindings for RV1126 PMU IO domains.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../bindings/power/rockchip-io-domain.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
index 1727bf108979..d71fc72d4464 100644
--- a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
@@ -58,6 +58,7 @@ properties:
- rockchip,rk3568-pmu-io-voltage-domain
- rockchip,rv1108-io-voltage-domain
- rockchip,rv1108-pmu-io-voltage-domain
+ - rockchip,rv1126-pmu-io-voltage-domain
required:
- compatible
@@ -78,6 +79,7 @@ allOf:
- $ref: "#/$defs/rk3568-pmu"
- $ref: "#/$defs/rv1108"
- $ref: "#/$defs/rv1108-pmu"
+ - $ref: "#/$defs/rv1126-pmu"
$defs:
px30:
@@ -344,6 +346,34 @@ $defs:
pmu-supply:
description: The supply connected to PMUIO_VDD.
+ rv1126-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rv1126-pmu-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+ vccio5-supply:
+ description: The supply connected to VCCIO5.
+ vccio6-supply:
+ description: The supply connected to VCCIO6.
+ vccio7-supply:
+ description: The supply connected to VCCIO7.
+ pmuio0-supply:
+ description: The supply connected to PMUIO0.
+ pmuio1-supply:
+ description: The supply connected to PMUIO1.
+
examples:
- |
io-domains {
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document dt-bindings for RV1126 PMU IO domains.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../bindings/power/rockchip-io-domain.yaml | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
index 1727bf108979..d71fc72d4464 100644
--- a/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
+++ b/Documentation/devicetree/bindings/power/rockchip-io-domain.yaml
@@ -58,6 +58,7 @@ properties:
- rockchip,rk3568-pmu-io-voltage-domain
- rockchip,rv1108-io-voltage-domain
- rockchip,rv1108-pmu-io-voltage-domain
+ - rockchip,rv1126-pmu-io-voltage-domain
required:
- compatible
@@ -78,6 +79,7 @@ allOf:
- $ref: "#/$defs/rk3568-pmu"
- $ref: "#/$defs/rv1108"
- $ref: "#/$defs/rv1108-pmu"
+ - $ref: "#/$defs/rv1126-pmu"
$defs:
px30:
@@ -344,6 +346,34 @@ $defs:
pmu-supply:
description: The supply connected to PMUIO_VDD.
+ rv1126-pmu:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rv1126-pmu-io-voltage-domain
+
+ then:
+ properties:
+ vccio1-supply:
+ description: The supply connected to VCCIO1.
+ vccio2-supply:
+ description: The supply connected to VCCIO2.
+ vccio3-supply:
+ description: The supply connected to VCCIO3.
+ vccio4-supply:
+ description: The supply connected to VCCIO4.
+ vccio5-supply:
+ description: The supply connected to VCCIO5.
+ vccio6-supply:
+ description: The supply connected to VCCIO6.
+ vccio7-supply:
+ description: The supply connected to VCCIO7.
+ pmuio0-supply:
+ description: The supply connected to PMUIO0.
+ pmuio1-supply:
+ description: The supply connected to PMUIO1.
+
examples:
- |
io-domains {
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 05/22] soc: rockchip: io-domain: Add RV1126 IO domains
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jianqun Xu,
Liam Girdwood, Mark Brown, Jagan Teki
From: Jianqun Xu <jay.xu@rock-chips.com>
Add IO domains support for RV1126 SoC.
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/soc/rockchip/io-domain.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
index 9df513d1219b..6619256c2d11 100644
--- a/drivers/soc/rockchip/io-domain.c
+++ b/drivers/soc/rockchip/io-domain.c
@@ -491,6 +491,22 @@ static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
},
};
+static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = {
+ .grf_offset = 0x140,
+ .supply_names = {
+ NULL,
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio4",
+ "vccio5",
+ "vccio6",
+ "vccio7",
+ "pmuio0",
+ "pmuio1",
+ },
+};
+
static const struct of_device_id rockchip_iodomain_match[] = {
{
.compatible = "rockchip,px30-io-voltage-domain",
@@ -544,6 +560,10 @@ static const struct of_device_id rockchip_iodomain_match[] = {
.compatible = "rockchip,rv1108-pmu-io-voltage-domain",
.data = &soc_data_rv1108_pmu
},
+ {
+ .compatible = "rockchip,rv1126-pmu-io-voltage-domain",
+ .data = &soc_data_rv1126_pmu
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 05/22] soc: rockchip: io-domain: Add RV1126 IO domains
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jianqun Xu,
Liam Girdwood, Mark Brown, Jagan Teki
From: Jianqun Xu <jay.xu@rock-chips.com>
Add IO domains support for RV1126 SoC.
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/soc/rockchip/io-domain.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
index 9df513d1219b..6619256c2d11 100644
--- a/drivers/soc/rockchip/io-domain.c
+++ b/drivers/soc/rockchip/io-domain.c
@@ -491,6 +491,22 @@ static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
},
};
+static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = {
+ .grf_offset = 0x140,
+ .supply_names = {
+ NULL,
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio4",
+ "vccio5",
+ "vccio6",
+ "vccio7",
+ "pmuio0",
+ "pmuio1",
+ },
+};
+
static const struct of_device_id rockchip_iodomain_match[] = {
{
.compatible = "rockchip,px30-io-voltage-domain",
@@ -544,6 +560,10 @@ static const struct of_device_id rockchip_iodomain_match[] = {
.compatible = "rockchip,rv1108-pmu-io-voltage-domain",
.data = &soc_data_rv1108_pmu
},
+ {
+ .compatible = "rockchip,rv1126-pmu-io-voltage-domain",
+ .data = &soc_data_rv1126_pmu
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 05/22] soc: rockchip: io-domain: Add RV1126 IO domains
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jianqun Xu,
Liam Girdwood, Mark Brown, Jagan Teki
From: Jianqun Xu <jay.xu@rock-chips.com>
Add IO domains support for RV1126 SoC.
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/soc/rockchip/io-domain.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c
index 9df513d1219b..6619256c2d11 100644
--- a/drivers/soc/rockchip/io-domain.c
+++ b/drivers/soc/rockchip/io-domain.c
@@ -491,6 +491,22 @@ static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
},
};
+static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = {
+ .grf_offset = 0x140,
+ .supply_names = {
+ NULL,
+ "vccio1",
+ "vccio2",
+ "vccio3",
+ "vccio4",
+ "vccio5",
+ "vccio6",
+ "vccio7",
+ "pmuio0",
+ "pmuio1",
+ },
+};
+
static const struct of_device_id rockchip_iodomain_match[] = {
{
.compatible = "rockchip,px30-io-voltage-domain",
@@ -544,6 +560,10 @@ static const struct of_device_id rockchip_iodomain_match[] = {
.compatible = "rockchip,rv1108-pmu-io-voltage-domain",
.data = &soc_data_rv1108_pmu
},
+ {
+ .compatible = "rockchip,rv1126-pmu-io-voltage-domain",
+ .data = &soc_data_rv1126_pmu
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-gpio, Linus Walleij
Document dt-bindings for RV1126 SoC pinctrl support.
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
index 677a285ca416..b486f41df65f 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -47,6 +47,7 @@ properties:
- rockchip,rk3568-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
+ - rockchip,rv1126-pinctrl
rockchip,grf:
$ref: "/schemas/types.yaml#/definitions/phandle"
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-gpio, Linus Walleij
Document dt-bindings for RV1126 SoC pinctrl support.
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
index 677a285ca416..b486f41df65f 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -47,6 +47,7 @@ properties:
- rockchip,rk3568-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
+ - rockchip,rv1126-pinctrl
rockchip,grf:
$ref: "/schemas/types.yaml#/definitions/phandle"
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-gpio, Linus Walleij
Document dt-bindings for RV1126 SoC pinctrl support.
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
index 677a285ca416..b486f41df65f 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
@@ -47,6 +47,7 @@ properties:
- rockchip,rk3568-pinctrl
- rockchip,rk3588-pinctrl
- rockchip,rv1108-pinctrl
+ - rockchip,rv1126-pinctrl
rockchip,grf:
$ref: "/schemas/types.yaml#/definitions/phandle"
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 07/22] pinctrl: rockchip: Add RV1126 pinctrl support
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-gpio, Linus Walleij, Jianqun Xu, Sugar Zhang
RV1126 has five GPIOs groups - GPIO0 in PD_MMU and GPIO1-4
in PD_BUS.
In GPIO0, up to Lower C group GPIO0_C[3:0] is part of PMU
but rest of the groups from there are part of GRF.
Added pinctrl support for RV1126 and the pull, drv and schmitt
calculations are inferred from [1] authored by Jianqun Xu.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/pinctrl/pinctrl-rockchip.c
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/pinctrl/pinctrl-rockchip.c | 333 ++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 327 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 32e41395fc76..a91061f9c2ac 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -57,6 +57,7 @@
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
+#define IOMUX_L_SOURCE_PMU BIT(6)
#define PIN_BANK(id, pins, label) \
{ \
@@ -147,6 +148,21 @@
.pull_type[3] = pull3, \
}
+#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
+ iom3, offset0, offset1, offset2, \
+ offset3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = offset0 }, \
+ { .type = iom1, .offset = offset1 }, \
+ { .type = iom2, .offset = offset2 }, \
+ { .type = iom3, .offset = offset3 }, \
+ }, \
+ }
+
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
@@ -443,6 +459,37 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
+static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
+ {
+ .num = 0,
+ .pin = 20,
+ .reg = 0x10000,
+ .bit = 0,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 21,
+ .reg = 0x10000,
+ .bit = 4,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 22,
+ .reg = 0x10000,
+ .bit = 8,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 23,
+ .reg = 0x10000,
+ .bit = 12,
+ .mask = 0xf
+ },
+};
+
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
@@ -642,6 +689,103 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
};
+static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
+ RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
+ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
+
+ RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
+ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
+ RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
+
+ RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
+ RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
+ RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
+
+ RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
+ RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
+ RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
+ RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
+
+ RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
+ RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
+ RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
+ RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
+ RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
+
+ RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
+ RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
+ RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
+ RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
+
+ RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
+ RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
+};
+
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
@@ -877,8 +1021,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? info->regmap_pmu : info->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = info->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
+ else
+ regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -987,8 +1135,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? info->regmap_pmu : info->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = info->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
+ else
+ regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -1268,6 +1420,119 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
+#define RV1126_PULL_PMU_OFFSET 0x40
+#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
+#define RV1126_PULL_PINS_PER_REG 8
+#define RV1126_PULL_BITS_PER_PIN 2
+#define RV1126_PULL_BANK_STRIDE 16
+#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
+
+static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
+ *bit = pin_num % RV1126_PULL_PINS_PER_REG;
+ *bit *= RV1126_PULL_BITS_PER_PIN;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_PULL_PMU_OFFSET;
+ } else {
+ *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
+ *regmap = info->regmap_base;
+ *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
+ *bit *= RV1126_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1126_DRV_PMU_OFFSET 0x20
+#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
+#define RV1126_DRV_BITS_PER_PIN 4
+#define RV1126_DRV_PINS_PER_REG 4
+#define RV1126_DRV_BANK_STRIDE 32
+
+static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
+ *reg -= 0x4;
+ *bit = pin_num % RV1126_DRV_PINS_PER_REG;
+ *bit *= RV1126_DRV_BITS_PER_PIN;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_DRV_PMU_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
+ *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1126_DRV_PINS_PER_REG;
+ *bit *= RV1126_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1126_SCHMITT_PMU_OFFSET 0x60
+#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
+#define RV1126_SCHMITT_BANK_STRIDE 16
+#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
+#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
+
+static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ int pins_per_reg;
+
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
+ *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_SCHMITT_PMU_OFFSET;
+ pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
+ pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
+ *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
+ }
+ *reg += ((pin_num / pins_per_reg) * 4);
+ *bit = pin_num % pins_per_reg;
+
+ return 0;
+}
+
#define RK3308_SCHMITT_PINS_PER_REG 8
#define RK3308_SCHMITT_BANK_STRIDE 16
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
@@ -1998,6 +2263,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
goto config;
}
+ if (ctrl->type == RV1126) {
+ rmask_bits = RV1126_DRV_BITS_PER_PIN;
+ ret = strength;
+ goto config;
+ }
+
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
@@ -2168,6 +2439,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
+ case RV1126:
case RK3188:
case RK3288:
case RK3308:
@@ -2416,6 +2688,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
+ case RV1126:
case RK3188:
case RK3288:
case RK3308:
@@ -2889,12 +3162,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
@@ -2919,7 +3194,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT |
IOMUX_WIDTH_2BIT)) ? 8 : 4;
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs += inc;
else
grf_offs += inc;
@@ -3178,6 +3453,48 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
+static struct rockchip_pin_bank rv1126_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10010, 0x10018, 0x10020, 0x10028),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
+ IOMUX_WIDTH_4BIT, 0, 0, 0),
+};
+
+static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
+ .pin_banks = rv1126_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
+ .label = "RV1126-GPIO",
+ .type = RV1126,
+ .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = rv1126_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
+ .iomux_recalced = rv1126_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
+ .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
+ .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -3568,6 +3885,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
+ { .compatible = "rockchip,rv1126-pinctrl",
+ .data = &rv1126_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index ec46f8815ac9..4759f336941e 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -186,6 +186,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1108,
+ RV1126,
RK2928,
RK3066B,
RK3128,
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 07/22] pinctrl: rockchip: Add RV1126 pinctrl support
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-gpio, Linus Walleij, Jianqun Xu, Sugar Zhang
RV1126 has five GPIOs groups - GPIO0 in PD_MMU and GPIO1-4
in PD_BUS.
In GPIO0, up to Lower C group GPIO0_C[3:0] is part of PMU
but rest of the groups from there are part of GRF.
Added pinctrl support for RV1126 and the pull, drv and schmitt
calculations are inferred from [1] authored by Jianqun Xu.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/pinctrl/pinctrl-rockchip.c
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/pinctrl/pinctrl-rockchip.c | 333 ++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 327 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 32e41395fc76..a91061f9c2ac 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -57,6 +57,7 @@
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
+#define IOMUX_L_SOURCE_PMU BIT(6)
#define PIN_BANK(id, pins, label) \
{ \
@@ -147,6 +148,21 @@
.pull_type[3] = pull3, \
}
+#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
+ iom3, offset0, offset1, offset2, \
+ offset3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = offset0 }, \
+ { .type = iom1, .offset = offset1 }, \
+ { .type = iom2, .offset = offset2 }, \
+ { .type = iom3, .offset = offset3 }, \
+ }, \
+ }
+
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
@@ -443,6 +459,37 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
+static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
+ {
+ .num = 0,
+ .pin = 20,
+ .reg = 0x10000,
+ .bit = 0,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 21,
+ .reg = 0x10000,
+ .bit = 4,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 22,
+ .reg = 0x10000,
+ .bit = 8,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 23,
+ .reg = 0x10000,
+ .bit = 12,
+ .mask = 0xf
+ },
+};
+
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
@@ -642,6 +689,103 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
};
+static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
+ RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
+ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
+
+ RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
+ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
+ RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
+
+ RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
+ RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
+ RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
+
+ RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
+ RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
+ RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
+ RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
+
+ RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
+ RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
+ RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
+ RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
+ RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
+
+ RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
+ RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
+ RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
+ RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
+
+ RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
+ RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
+};
+
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
@@ -877,8 +1021,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? info->regmap_pmu : info->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = info->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
+ else
+ regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -987,8 +1135,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? info->regmap_pmu : info->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = info->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
+ else
+ regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -1268,6 +1420,119 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
+#define RV1126_PULL_PMU_OFFSET 0x40
+#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
+#define RV1126_PULL_PINS_PER_REG 8
+#define RV1126_PULL_BITS_PER_PIN 2
+#define RV1126_PULL_BANK_STRIDE 16
+#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
+
+static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
+ *bit = pin_num % RV1126_PULL_PINS_PER_REG;
+ *bit *= RV1126_PULL_BITS_PER_PIN;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_PULL_PMU_OFFSET;
+ } else {
+ *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
+ *regmap = info->regmap_base;
+ *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
+ *bit *= RV1126_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1126_DRV_PMU_OFFSET 0x20
+#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
+#define RV1126_DRV_BITS_PER_PIN 4
+#define RV1126_DRV_PINS_PER_REG 4
+#define RV1126_DRV_BANK_STRIDE 32
+
+static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
+ *reg -= 0x4;
+ *bit = pin_num % RV1126_DRV_PINS_PER_REG;
+ *bit *= RV1126_DRV_BITS_PER_PIN;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_DRV_PMU_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
+ *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1126_DRV_PINS_PER_REG;
+ *bit *= RV1126_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1126_SCHMITT_PMU_OFFSET 0x60
+#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
+#define RV1126_SCHMITT_BANK_STRIDE 16
+#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
+#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
+
+static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ int pins_per_reg;
+
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
+ *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_SCHMITT_PMU_OFFSET;
+ pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
+ pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
+ *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
+ }
+ *reg += ((pin_num / pins_per_reg) * 4);
+ *bit = pin_num % pins_per_reg;
+
+ return 0;
+}
+
#define RK3308_SCHMITT_PINS_PER_REG 8
#define RK3308_SCHMITT_BANK_STRIDE 16
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
@@ -1998,6 +2263,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
goto config;
}
+ if (ctrl->type == RV1126) {
+ rmask_bits = RV1126_DRV_BITS_PER_PIN;
+ ret = strength;
+ goto config;
+ }
+
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
@@ -2168,6 +2439,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
+ case RV1126:
case RK3188:
case RK3288:
case RK3308:
@@ -2416,6 +2688,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
+ case RV1126:
case RK3188:
case RK3288:
case RK3308:
@@ -2889,12 +3162,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
@@ -2919,7 +3194,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT |
IOMUX_WIDTH_2BIT)) ? 8 : 4;
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs += inc;
else
grf_offs += inc;
@@ -3178,6 +3453,48 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
+static struct rockchip_pin_bank rv1126_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10010, 0x10018, 0x10020, 0x10028),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
+ IOMUX_WIDTH_4BIT, 0, 0, 0),
+};
+
+static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
+ .pin_banks = rv1126_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
+ .label = "RV1126-GPIO",
+ .type = RV1126,
+ .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = rv1126_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
+ .iomux_recalced = rv1126_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
+ .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
+ .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -3568,6 +3885,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
+ { .compatible = "rockchip,rv1126-pinctrl",
+ .data = &rv1126_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index ec46f8815ac9..4759f336941e 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -186,6 +186,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1108,
+ RV1126,
RK2928,
RK3066B,
RK3128,
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 07/22] pinctrl: rockchip: Add RV1126 pinctrl support
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-gpio, Linus Walleij, Jianqun Xu, Sugar Zhang
RV1126 has five GPIOs groups - GPIO0 in PD_MMU and GPIO1-4
in PD_BUS.
In GPIO0, up to Lower C group GPIO0_C[3:0] is part of PMU
but rest of the groups from there are part of GRF.
Added pinctrl support for RV1126 and the pull, drv and schmitt
calculations are inferred from [1] authored by Jianqun Xu.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/pinctrl/pinctrl-rockchip.c
Cc: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/pinctrl/pinctrl-rockchip.c | 333 ++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 327 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 32e41395fc76..a91061f9c2ac 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -57,6 +57,7 @@
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
+#define IOMUX_L_SOURCE_PMU BIT(6)
#define PIN_BANK(id, pins, label) \
{ \
@@ -147,6 +148,21 @@
.pull_type[3] = pull3, \
}
+#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \
+ iom3, offset0, offset1, offset2, \
+ offset3) \
+ { \
+ .bank_num = id, \
+ .nr_pins = pins, \
+ .name = label, \
+ .iomux = { \
+ { .type = iom0, .offset = offset0 }, \
+ { .type = iom1, .offset = offset1 }, \
+ { .type = iom2, .offset = offset2 }, \
+ { .type = iom3, .offset = offset3 }, \
+ }, \
+ }
+
#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
iom2, iom3, drv0, drv1, drv2, \
drv3, offset0, offset1, \
@@ -443,6 +459,37 @@ static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
},
};
+static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = {
+ {
+ .num = 0,
+ .pin = 20,
+ .reg = 0x10000,
+ .bit = 0,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 21,
+ .reg = 0x10000,
+ .bit = 4,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 22,
+ .reg = 0x10000,
+ .bit = 8,
+ .mask = 0xf
+ },
+ {
+ .num = 0,
+ .pin = 23,
+ .reg = 0x10000,
+ .bit = 12,
+ .mask = 0xf
+ },
+};
+
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
@@ -642,6 +689,103 @@ static struct rockchip_mux_route_data px30_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
};
+static struct rockchip_mux_route_data rv1126_mux_route_data[] = {
+ RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
+ RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
+
+ RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
+ RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
+ RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
+
+ RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
+ RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
+ RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
+
+ RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
+ RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
+ RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
+ RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
+ RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
+
+ RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
+ RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
+
+ RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
+ RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
+ RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
+ RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
+ RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
+
+ RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
+ RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
+ RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
+
+ RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
+ RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
+ RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
+ RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
+
+ RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
+ RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
+ RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
+
+ RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
+ RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
+};
+
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
@@ -877,8 +1021,12 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
return RK_FUNC_GPIO;
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? info->regmap_pmu : info->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = info->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
+ else
+ regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -987,8 +1135,12 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
dev_dbg(dev, "setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
- regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
- ? info->regmap_pmu : info->regmap_base;
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = info->regmap_pmu;
+ else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU)
+ regmap = (pin % 8 < 4) ? info->regmap_pmu : info->regmap_base;
+ else
+ regmap = info->regmap_base;
/* get basic quadrupel of mux registers and the correct reg inside */
mux_type = bank->iomux[iomux_num].type;
@@ -1268,6 +1420,119 @@ static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
+#define RV1126_PULL_PMU_OFFSET 0x40
+#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108
+#define RV1126_PULL_PINS_PER_REG 8
+#define RV1126_PULL_BITS_PER_PIN 2
+#define RV1126_PULL_BANK_STRIDE 16
+#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */
+
+static int rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4);
+ *bit = pin_num % RV1126_PULL_PINS_PER_REG;
+ *bit *= RV1126_PULL_BITS_PER_PIN;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_PULL_PMU_OFFSET;
+ } else {
+ *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET;
+ *regmap = info->regmap_base;
+ *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RV1126_PULL_PINS_PER_REG);
+ *bit *= RV1126_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1126_DRV_PMU_OFFSET 0x20
+#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090
+#define RV1126_DRV_BITS_PER_PIN 4
+#define RV1126_DRV_PINS_PER_REG 4
+#define RV1126_DRV_BANK_STRIDE 32
+
+static int rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* The first 24 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4);
+ *reg -= 0x4;
+ *bit = pin_num % RV1126_DRV_PINS_PER_REG;
+ *bit *= RV1126_DRV_BITS_PER_PIN;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_DRV_PMU_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET;
+ *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1126_DRV_PINS_PER_REG;
+ *bit *= RV1126_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1126_SCHMITT_PMU_OFFSET 0x60
+#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188
+#define RV1126_SCHMITT_BANK_STRIDE 16
+#define RV1126_SCHMITT_PINS_PER_GRF_REG 8
+#define RV1126_SCHMITT_PINS_PER_PMU_REG 8
+
+static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+ int pins_per_reg;
+
+ if (bank->bank_num == 0) {
+ if (RV1126_GPIO_C4_D7(pin_num)) {
+ *regmap = info->regmap_base;
+ *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
+ *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4);
+ *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG;
+ return 0;
+ }
+ *regmap = info->regmap_pmu;
+ *reg = RV1126_SCHMITT_PMU_OFFSET;
+ pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET;
+ pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG;
+ *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE;
+ }
+ *reg += ((pin_num / pins_per_reg) * 4);
+ *bit = pin_num % pins_per_reg;
+
+ return 0;
+}
+
#define RK3308_SCHMITT_PINS_PER_REG 8
#define RK3308_SCHMITT_BANK_STRIDE 16
#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
@@ -1998,6 +2263,12 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
goto config;
}
+ if (ctrl->type == RV1126) {
+ rmask_bits = RV1126_DRV_BITS_PER_PIN;
+ ret = strength;
+ goto config;
+ }
+
ret = -EINVAL;
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
if (rockchip_perpin_drv_list[drv_type][i] == strength) {
@@ -2168,6 +2439,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1108:
+ case RV1126:
case RK3188:
case RK3288:
case RK3308:
@@ -2416,6 +2688,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1108:
+ case RV1126:
case RK3188:
case RK3288:
case RK3308:
@@ -2889,12 +3162,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
pmu_offs : grf_offs;
}
@@ -2919,7 +3194,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
inc = (iom->type & (IOMUX_WIDTH_4BIT |
IOMUX_WIDTH_3BIT |
IOMUX_WIDTH_2BIT)) ? 8 : 4;
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs += inc;
else
grf_offs += inc;
@@ -3178,6 +3453,48 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
+static struct rockchip_pin_bank rv1126_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10010, 0x10018, 0x10020, 0x10028),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4",
+ IOMUX_WIDTH_4BIT, 0, 0, 0),
+};
+
+static struct rockchip_pin_ctrl rv1126_pin_ctrl = {
+ .pin_banks = rv1126_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1126_pin_banks),
+ .label = "RV1126-GPIO",
+ .type = RV1126,
+ .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = rv1126_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data),
+ .iomux_recalced = rv1126_mux_recalced_data,
+ .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data),
+ .pull_calc_reg = rv1126_calc_pull_reg_and_bit,
+ .drv_calc_reg = rv1126_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rv1126_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
@@ -3568,6 +3885,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
+ { .compatible = "rockchip,rv1126-pinctrl",
+ .data = &rv1126_pin_ctrl },
{ .compatible = "rockchip,rk2928-pinctrl",
.data = &rk2928_pin_ctrl },
{ .compatible = "rockchip,rk3036-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index ec46f8815ac9..4759f336941e 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -186,6 +186,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1108,
+ RV1126,
RK2928,
RK3066B,
RK3128,
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 08/22] clk: rockchip: Add MUXTBL variant
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang,
linux-clk, Michael Turquette, Stephen Boyd, Jagan Teki
From: Elaine Zhang <zhangqing@rock-chips.com>
A clock branch consisting of a mux with non-standard
select values.
The parent in Mux table is sorted by priority.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/clk.c | 27 +++++++++++++++++++++------
drivers/clk/rockchip/clk.h | 17 +++++++++++++++++
2 files changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index bb8a844309bf..e63d4f20b479 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -40,6 +40,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
+ u32 *mux_table,
int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
@@ -62,6 +63,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
+ mux->table = mux_table;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
@@ -270,6 +272,8 @@ static struct clk *rockchip_clk_register_frac_branch(
frac_mux->shift = child->mux_shift;
frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
+ if (child->mux_table)
+ frac_mux->table = child->mux_table;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
@@ -444,11 +448,21 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
- clk = clk_register_mux(NULL, list->name,
- list->parent_names, list->num_parents,
- flags, ctx->reg_base + list->muxdiv_offset,
- list->mux_shift, list->mux_width,
- list->mux_flags, &ctx->lock);
+ if (list->mux_table)
+ clk = clk_register_mux_table(NULL, list->name,
+ list->parent_names, list->num_parents,
+ flags,
+ ctx->reg_base + list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags, list->mux_table,
+ &ctx->lock);
+ else
+ clk = clk_register_mux(NULL, list->name,
+ list->parent_names, list->num_parents,
+ flags,
+ ctx->reg_base + list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags, &ctx->lock);
break;
case branch_muxgrf:
clk = rockchip_clk_register_muxgrf(list->name,
@@ -506,7 +520,8 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
ctx->reg_base, list->muxdiv_offset,
list->mux_shift,
list->mux_width, list->mux_flags,
- list->div_offset, list->div_shift, list->div_width,
+ list->mux_table, list->div_offset,
+ list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7aa45cc70287..93937fb1d368 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -448,6 +448,7 @@ struct rockchip_clk_branch {
u8 mux_shift;
u8 mux_width;
u8 mux_flags;
+ u32 *mux_table;
int div_offset;
u8 div_shift;
u8 div_width;
@@ -680,6 +681,22 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
+#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
+ { \
+ .id = _id, \
+ .branch_type = branch_mux, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = f, \
+ .muxdiv_offset = o, \
+ .mux_shift = s, \
+ .mux_width = w, \
+ .mux_flags = mf, \
+ .gate_offset = -1, \
+ .mux_table = mt, \
+ }
+
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
{ \
.id = _id, \
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 08/22] clk: rockchip: Add MUXTBL variant
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang,
linux-clk, Michael Turquette, Stephen Boyd, Jagan Teki
From: Elaine Zhang <zhangqing@rock-chips.com>
A clock branch consisting of a mux with non-standard
select values.
The parent in Mux table is sorted by priority.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/clk.c | 27 +++++++++++++++++++++------
drivers/clk/rockchip/clk.h | 17 +++++++++++++++++
2 files changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index bb8a844309bf..e63d4f20b479 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -40,6 +40,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
+ u32 *mux_table,
int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
@@ -62,6 +63,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
+ mux->table = mux_table;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
@@ -270,6 +272,8 @@ static struct clk *rockchip_clk_register_frac_branch(
frac_mux->shift = child->mux_shift;
frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
+ if (child->mux_table)
+ frac_mux->table = child->mux_table;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
@@ -444,11 +448,21 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
- clk = clk_register_mux(NULL, list->name,
- list->parent_names, list->num_parents,
- flags, ctx->reg_base + list->muxdiv_offset,
- list->mux_shift, list->mux_width,
- list->mux_flags, &ctx->lock);
+ if (list->mux_table)
+ clk = clk_register_mux_table(NULL, list->name,
+ list->parent_names, list->num_parents,
+ flags,
+ ctx->reg_base + list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags, list->mux_table,
+ &ctx->lock);
+ else
+ clk = clk_register_mux(NULL, list->name,
+ list->parent_names, list->num_parents,
+ flags,
+ ctx->reg_base + list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags, &ctx->lock);
break;
case branch_muxgrf:
clk = rockchip_clk_register_muxgrf(list->name,
@@ -506,7 +520,8 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
ctx->reg_base, list->muxdiv_offset,
list->mux_shift,
list->mux_width, list->mux_flags,
- list->div_offset, list->div_shift, list->div_width,
+ list->mux_table, list->div_offset,
+ list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7aa45cc70287..93937fb1d368 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -448,6 +448,7 @@ struct rockchip_clk_branch {
u8 mux_shift;
u8 mux_width;
u8 mux_flags;
+ u32 *mux_table;
int div_offset;
u8 div_shift;
u8 div_width;
@@ -680,6 +681,22 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
+#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
+ { \
+ .id = _id, \
+ .branch_type = branch_mux, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = f, \
+ .muxdiv_offset = o, \
+ .mux_shift = s, \
+ .mux_width = w, \
+ .mux_flags = mf, \
+ .gate_offset = -1, \
+ .mux_table = mt, \
+ }
+
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
{ \
.id = _id, \
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 08/22] clk: rockchip: Add MUXTBL variant
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang,
linux-clk, Michael Turquette, Stephen Boyd, Jagan Teki
From: Elaine Zhang <zhangqing@rock-chips.com>
A clock branch consisting of a mux with non-standard
select values.
The parent in Mux table is sorted by priority.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/clk.c | 27 +++++++++++++++++++++------
drivers/clk/rockchip/clk.h | 17 +++++++++++++++++
2 files changed, 38 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index bb8a844309bf..e63d4f20b479 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -40,6 +40,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
const char *const *parent_names, u8 num_parents,
void __iomem *base,
int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
+ u32 *mux_table,
int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
struct clk_div_table *div_table, int gate_offset,
u8 gate_shift, u8 gate_flags, unsigned long flags,
@@ -62,6 +63,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
mux->shift = mux_shift;
mux->mask = BIT(mux_width) - 1;
mux->flags = mux_flags;
+ mux->table = mux_table;
mux->lock = lock;
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
: &clk_mux_ops;
@@ -270,6 +272,8 @@ static struct clk *rockchip_clk_register_frac_branch(
frac_mux->shift = child->mux_shift;
frac_mux->mask = BIT(child->mux_width) - 1;
frac_mux->flags = child->mux_flags;
+ if (child->mux_table)
+ frac_mux->table = child->mux_table;
frac_mux->lock = lock;
frac_mux->hw.init = &init;
@@ -444,11 +448,21 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
/* catch simple muxes */
switch (list->branch_type) {
case branch_mux:
- clk = clk_register_mux(NULL, list->name,
- list->parent_names, list->num_parents,
- flags, ctx->reg_base + list->muxdiv_offset,
- list->mux_shift, list->mux_width,
- list->mux_flags, &ctx->lock);
+ if (list->mux_table)
+ clk = clk_register_mux_table(NULL, list->name,
+ list->parent_names, list->num_parents,
+ flags,
+ ctx->reg_base + list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags, list->mux_table,
+ &ctx->lock);
+ else
+ clk = clk_register_mux(NULL, list->name,
+ list->parent_names, list->num_parents,
+ flags,
+ ctx->reg_base + list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags, &ctx->lock);
break;
case branch_muxgrf:
clk = rockchip_clk_register_muxgrf(list->name,
@@ -506,7 +520,8 @@ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
ctx->reg_base, list->muxdiv_offset,
list->mux_shift,
list->mux_width, list->mux_flags,
- list->div_offset, list->div_shift, list->div_width,
+ list->mux_table, list->div_offset,
+ list->div_shift, list->div_width,
list->div_flags, list->div_table,
list->gate_offset, list->gate_shift,
list->gate_flags, flags, &ctx->lock);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7aa45cc70287..93937fb1d368 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -448,6 +448,7 @@ struct rockchip_clk_branch {
u8 mux_shift;
u8 mux_width;
u8 mux_flags;
+ u32 *mux_table;
int div_offset;
u8 div_shift;
u8 div_width;
@@ -680,6 +681,22 @@ struct rockchip_clk_branch {
.gate_offset = -1, \
}
+#define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
+ { \
+ .id = _id, \
+ .branch_type = branch_mux, \
+ .name = cname, \
+ .parent_names = pnames, \
+ .num_parents = ARRAY_SIZE(pnames), \
+ .flags = f, \
+ .muxdiv_offset = o, \
+ .mux_shift = s, \
+ .mux_width = w, \
+ .mux_flags = mf, \
+ .gate_offset = -1, \
+ .mux_table = mt, \
+ }
+
#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
{ \
.id = _id, \
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-clk, Michael Turquette, Stephen Boyd
Document dt-bindings for Rockchip RV1126 clock controller.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
new file mode 100644
index 000000000000..cf4f11709125
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP RV1126 Family Clock Control Module Binding
+
+maintainers:
+ - Jagan Teki <jagan@edgeble.ai>
+ - Finley Xiao <finley.xiao@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RV1126 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rv1126-cru
+ - rockchip,rv1126-pmucru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-clk, Michael Turquette, Stephen Boyd
Document dt-bindings for Rockchip RV1126 clock controller.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
new file mode 100644
index 000000000000..cf4f11709125
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP RV1126 Family Clock Control Module Binding
+
+maintainers:
+ - Jagan Teki <jagan@edgeble.ai>
+ - Finley Xiao <finley.xiao@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RV1126 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rv1126-cru
+ - rockchip,rv1126-pmucru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-clk, Michael Turquette, Stephen Boyd
Document dt-bindings for Rockchip RV1126 clock controller.
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
new file mode 100644
index 000000000000..cf4f11709125
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROCKCHIP RV1126 Family Clock Control Module Binding
+
+maintainers:
+ - Jagan Teki <jagan@edgeble.ai>
+ - Finley Xiao <finley.xiao@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The RV1126 clock controller generates the clock and also implements a
+ reset controller for SoC peripherals.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rv1126-cru
+ - rockchip,rv1126-pmucru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: xin24m
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the syscon managing the "general register files" (GRF),
+ if missing pll rates are not changeable, due to the missing pll
+ lock status.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ - |
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-clk, Michael Turquette, Stephen Boyd, Finley Xiao
Add clock controller support for RV1126 SoC.
Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.
This patch is trying to add minimal Clock-Architecture Diagram's
inferred from [1] authored by Finley Xiao.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1126.c | 1107 ++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 19 +
include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++++++
5 files changed, 1766 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rv1126.c
create mode 100644 include/dt-bindings/clock/rv1126-cru.h
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 3067bdb6e119..345a5d2a457c 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -23,6 +23,13 @@ config CLK_RV110X
help
Build the driver for RV110x Clock Driver.
+config CLK_RV1126
+ bool "Rockchip RV1126 clock controller support"
+ depends on ARM || COMPILE_TEST
+ default y
+ help
+ Build the driver for RV1126 Clock Driver.
+
config CLK_RK3036
bool "Rockchip RK3036 clock controller support"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 2b78f1247372..e8543876c056 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -17,6 +17,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
+obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
new file mode 100644
index 000000000000..40d8b635a00a
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rv1126-cru.h>
+#include "clk.h"
+
+#define RV1126_GMAC_CON 0x460
+#define RV1126_GRF_IOFUNC_CON1 0x10264
+#define RV1126_GRF_SOC_STATUS0 0x10
+
+#define RV1126_FRAC_MAX_PRATE 1200000000
+#define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
+
+enum rv1126_pmu_plls {
+ gpll,
+};
+
+enum rv1126_plls {
+ apll, dpll, cpll, hpll,
+};
+
+static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
+ RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
+ RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
+ RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
+ RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
+ RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RV1126_DIV_ACLK_CORE_MASK 0xf
+#define RV1126_DIV_ACLK_CORE_SHIFT 4
+#define RV1126_DIV_PCLK_DBG_MASK 0x7
+#define RV1126_DIV_PCLK_DBG_SHIFT 0
+
+#define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
+{ \
+ .reg = RV1126_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
+ RV1126_DIV_ACLK_CORE_SHIFT) | \
+ HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
+ RV1126_DIV_PCLK_DBG_SHIFT), \
+}
+
+#define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
+ RV1126_CPUCLK_RATE(1608000000, 1, 7),
+ RV1126_CPUCLK_RATE(1584000000, 1, 7),
+ RV1126_CPUCLK_RATE(1560000000, 1, 7),
+ RV1126_CPUCLK_RATE(1536000000, 1, 7),
+ RV1126_CPUCLK_RATE(1512000000, 1, 7),
+ RV1126_CPUCLK_RATE(1488000000, 1, 5),
+ RV1126_CPUCLK_RATE(1464000000, 1, 5),
+ RV1126_CPUCLK_RATE(1440000000, 1, 5),
+ RV1126_CPUCLK_RATE(1416000000, 1, 5),
+ RV1126_CPUCLK_RATE(1392000000, 1, 5),
+ RV1126_CPUCLK_RATE(1368000000, 1, 5),
+ RV1126_CPUCLK_RATE(1344000000, 1, 5),
+ RV1126_CPUCLK_RATE(1320000000, 1, 5),
+ RV1126_CPUCLK_RATE(1296000000, 1, 5),
+ RV1126_CPUCLK_RATE(1272000000, 1, 5),
+ RV1126_CPUCLK_RATE(1248000000, 1, 5),
+ RV1126_CPUCLK_RATE(1224000000, 1, 5),
+ RV1126_CPUCLK_RATE(1200000000, 1, 5),
+ RV1126_CPUCLK_RATE(1104000000, 1, 5),
+ RV1126_CPUCLK_RATE(1008000000, 1, 5),
+ RV1126_CPUCLK_RATE(912000000, 1, 5),
+ RV1126_CPUCLK_RATE(816000000, 1, 3),
+ RV1126_CPUCLK_RATE(696000000, 1, 3),
+ RV1126_CPUCLK_RATE(600000000, 1, 3),
+ RV1126_CPUCLK_RATE(408000000, 1, 1),
+ RV1126_CPUCLK_RATE(312000000, 1, 1),
+ RV1126_CPUCLK_RATE(216000000, 1, 1),
+ RV1126_CPUCLK_RATE(96000000, 1, 1),
+};
+
+static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
+ .core_reg[0] = RV1126_CLKSEL_CON(0),
+ .div_core_shift[0] = 0,
+ .div_core_mask[0] = 0x1f,
+ .num_cores = 1,
+ .mux_core_alt = 0,
+ .mux_core_main = 2,
+ .mux_core_shift = 6,
+ .mux_core_mask = 0x3,
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
+PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
+PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
+PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
+PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
+PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
+PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
+PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
+PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
+PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
+PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
+PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
+PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
+PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
+PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
+PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
+PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
+PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
+PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
+PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
+PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
+PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
+PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
+PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
+PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
+PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
+PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
+PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
+PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
+PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
+PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
+PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
+PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
+PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
+PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
+PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
+PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
+PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
+PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
+PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
+PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
+PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
+PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
+PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
+PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
+PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
+PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
+PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
+PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
+PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
+PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
+
+static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
+
+static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ 0, RV1126_PMU_PLL_CON(0),
+ RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
+};
+
+static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+ 0, RV1126_PLL_CON(0),
+ RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
+ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+ 0, RV1126_PLL_CON(8),
+ RV1126_MODE_CON, 2, 1, 0, NULL),
+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+ 0, RV1126_PLL_CON(16),
+ RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
+ [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
+ 0, RV1126_PLL_CON(24),
+ RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
+ MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
+ MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
+ MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
+ MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
+ MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
+ MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
+ MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
+ MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
+ MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
+ MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
+ MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
+ MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 2
+ */
+ /* PD_PMU */
+ COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
+
+ COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKSEL_CON(13), 0,
+ RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
+ &rv1126_rtc32k_fracmux),
+
+ COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
+ GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
+ MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
+
+ GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
+
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
+ RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(5), 0,
+ RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
+ &rv1126_uart1_fracmux),
+ GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
+ RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
+
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
+ RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
+ COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
+ RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
+
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
+ COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
+ RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
+
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
+ RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
+
+ GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
+ GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
+ GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
+ FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
+ FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
+ MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
+ MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
+
+ COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
+ GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
+ MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
+
+ GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
+
+ GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
+ GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
+
+ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 1
+ */
+ MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
+ RV1126_MODE_CON, 10, 2, MFLAGS),
+ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RV1126_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
+ RV1126_CLKGATE_CON(0), 12, GFLAGS),
+ GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
+ RV1126_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
+ RV1126_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(0), 8, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ /* PD_BUS */
+ COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 1, GFLAGS),
+ GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 12, GFLAGS),
+ COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 2, GFLAGS),
+ GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 13, GFLAGS),
+ /* aclk_dmac is controlled by sgrf_clkgat_con. */
+ SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
+ GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 6, GFLAGS),
+ GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 7, GFLAGS),
+ GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 14, GFLAGS),
+ GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 10, GFLAGS),
+
+ COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(4), 7, GFLAGS),
+ GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 14, GFLAGS),
+ GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
+ RV1126_CLKGATE_CON(4), 8, GFLAGS),
+ GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
+ RV1126_CLKGATE_CON(4), 9, GFLAGS),
+ GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
+ RV1126_CLKGATE_CON(4), 10, GFLAGS),
+
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 0, GFLAGS),
+ COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 1, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(11), 0,
+ RV1126_CLKGATE_CON(5), 2, GFLAGS,
+ &rv1126_uart0_fracmux),
+ GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
+ RV1126_CLKGATE_CON(5), 3, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 4, GFLAGS),
+ COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 5, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(13), 0,
+ RV1126_CLKGATE_CON(5), 6, GFLAGS,
+ &rv1126_uart2_fracmux),
+ GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
+ RV1126_CLKGATE_CON(5), 7, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 8, GFLAGS),
+ COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 9, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(15), 0,
+ RV1126_CLKGATE_CON(5), 10, GFLAGS,
+ &rv1126_uart3_fracmux),
+ GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
+ RV1126_CLKGATE_CON(5), 11, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 12, GFLAGS),
+ COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
+ DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(17), 0,
+ RV1126_CLKGATE_CON(5), 14, GFLAGS,
+ &rv1126_uart4_fracmux),
+ GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
+ RV1126_CLKGATE_CON(5), 15, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
+ DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(19), 0,
+ RV1126_CLKGATE_CON(6), 2, GFLAGS,
+ &rv1126_uart5_fracmux),
+ GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
+ RV1126_CLKGATE_CON(6), 3, GFLAGS),
+
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
+ RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 11, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
+ RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 13, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 14, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
+ RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
+ RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 1, GFLAGS),
+
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 3, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
+ RV1126_CLKGATE_CON(4), 6, GFLAGS),
+ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
+ RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 5, GFLAGS),
+
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 0, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 2, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 4, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 5, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 6, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 7, GFLAGS),
+
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+ RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(6), 5, GFLAGS),
+
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 7, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 8, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 10, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 11, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 12, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 13, GFLAGS),
+
+ GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 6, GFLAGS),
+
+ GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 11, GFLAGS),
+ GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 12, GFLAGS),
+ COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(7), 13, GFLAGS),
+
+ GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 8, GFLAGS),
+ COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(7), 9, GFLAGS),
+ /* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
+ SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
+ SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
+
+ GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(24), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
+ RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(24), 4, GFLAGS),
+ GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
+ RV1126_CLKGATE_CON(24), 5, GFLAGS),
+ GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(24), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
+ RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(24), 1, GFLAGS),
+ GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
+ RV1126_CLKGATE_CON(24), 2, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+ /* PD_AUDIO */
+ COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
+ RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(9), 0, GFLAGS),
+
+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(9), 4, GFLAGS),
+ COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(9), 5, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(28), 0,
+ RV1126_CLKGATE_CON(9), 6, GFLAGS,
+ &rv1126_i2s0_tx_fracmux),
+ GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
+ RV1126_CLKGATE_CON(9), 9, GFLAGS),
+ COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(9), 7, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(29), 0,
+ RV1126_CLKGATE_CON(9), 8, GFLAGS,
+ &rv1126_i2s0_rx_fracmux),
+ GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
+ RV1126_CLKGATE_CON(9), 10, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
+ RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
+ RV1126_CLKGATE_CON(9), 13, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
+ RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
+ RV1126_CLKGATE_CON(9), 14, GFLAGS),
+
+ GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 0, GFLAGS),
+ COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 1, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(32), 0,
+ RV1126_CLKGATE_CON(10), 2, GFLAGS,
+ &rv1126_i2s1_fracmux),
+ GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
+ RV1126_CLKGATE_CON(10), 3, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
+ RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
+ RV1126_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 5, GFLAGS),
+ COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 6, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(34), 0,
+ RV1126_CLKGATE_CON(10), 7, GFLAGS,
+ &rv1126_i2s2_fracmux),
+ GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
+ RV1126_CLKGATE_CON(10), 8, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
+ RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
+ RV1126_CLKGATE_CON(10), 9, GFLAGS),
+
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 10, GFLAGS),
+ COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 11, GFLAGS),
+
+ GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 12, GFLAGS),
+ COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 13, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(37), 0,
+ RV1126_CLKGATE_CON(10), 14, GFLAGS,
+ &rv1126_audpwm_fracmux),
+ GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
+ RV1126_CLKGATE_CON(10), 15, GFLAGS),
+
+ GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(11), 0, GFLAGS),
+ GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
+ RV1126_CLKGATE_CON(11), 2, GFLAGS),
+ GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
+ RV1126_CLKGATE_CON(11), 3, GFLAGS),
+ COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(11), 1, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 12
+ */
+ /* PD_PHP */
+ COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(17), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(17), 1, GFLAGS),
+ /* PD_SDCARD */
+ GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(17), 6, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
+ RV1126_CLKGATE_CON(18), 4, GFLAGS),
+ COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
+ DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
+ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
+
+ /* PD_SDIO */
+ GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(17), 8, GFLAGS),
+ GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
+ RV1126_CLKGATE_CON(18), 6, GFLAGS),
+ COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 7, GFLAGS),
+ MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
+
+ /* PD_NVM */
+ GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(18), 1, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 8, GFLAGS),
+ COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 9, GFLAGS),
+ GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 13, GFLAGS),
+ COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 14, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 10, GFLAGS),
+ GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 11, GFLAGS),
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 12, GFLAGS),
+ MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
+
+ /* PD_USB */
+ GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
+ RV1126_CLKGATE_CON(19), 0, GFLAGS),
+ GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(19), 1, GFLAGS),
+ GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 4, GFLAGS),
+ GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 5, GFLAGS),
+ COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
+ RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(19), 6, GFLAGS),
+ GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 7, GFLAGS),
+ GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
+ RV1126_CLKGATE_CON(19), 8, GFLAGS),
+ /* PD_GMAC */
+ GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
+ RV1126_CLKGATE_CON(20), 0, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
+ RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 1, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
+ RV1126_CLKGATE_CON(20), 4, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
+ RV1126_CLKGATE_CON(20), 5, GFLAGS),
+
+ COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 6, GFLAGS),
+ GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
+ RV1126_CLKGATE_CON(20), 12, GFLAGS),
+ MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 0, 1, MFLAGS),
+ GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
+ RV1126_CLKGATE_CON(20), 13, GFLAGS),
+ MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 5, 1, MFLAGS),
+ MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+ RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
+
+ GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 7, GFLAGS),
+
+ GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 9, GFLAGS),
+ FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
+ FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
+ MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
+ GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 8, GFLAGS),
+ FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
+ FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
+ MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 1, 1, MFLAGS),
+ MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+ RV1126_GMAC_CON, 4, 1, MFLAGS),
+
+ GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
+ RV1126_CLKGATE_CON(20), 10, GFLAGS),
+ COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 11, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 15
+ */
+ GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 8, GFLAGS),
+ GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 4, GFLAGS),
+ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 2, GFLAGS),
+ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 3, GFLAGS),
+ GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(19), 13, GFLAGS),
+ GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(19), 12, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RV1126_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 5, GFLAGS),
+ GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 4, GFLAGS),
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ /* PD_BUS */
+ GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 10, GFLAGS),
+ GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 3, GFLAGS),
+ GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 6, GFLAGS),
+ GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 7, GFLAGS),
+ GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 8, GFLAGS),
+ GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 9, GFLAGS),
+ GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(6), 15, GFLAGS),
+ GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(8), 4, GFLAGS),
+ GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 9, GFLAGS),
+ GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(7), 14, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+ /* PD_AUDIO */
+ GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(9), 2, GFLAGS),
+ GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(9), 3, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 12
+ */
+ /* PD_PHP */
+ GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 2, GFLAGS),
+ GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 3, GFLAGS),
+ GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 4, GFLAGS),
+ GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 5, GFLAGS),
+
+ /* PD_SDCARD */
+ GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 7, GFLAGS),
+
+ /* PD_SDIO */
+ GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 9, GFLAGS),
+
+ /* PD_NVM */
+ GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(18), 3, GFLAGS),
+
+ /* PD_USB */
+ GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(19), 2, GFLAGS),
+ GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(19), 3, GFLAGS),
+
+ /* PD_GMAC */
+ GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 2, GFLAGS),
+ GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 3, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 13
+ */
+ /* PD_DDR */
+ COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(21), 0, GFLAGS),
+ GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 15, GFLAGS),
+ GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 6, GFLAGS),
+ COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
+ CLK_DIVIDER_POWER_OF_TWO),
+ COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(21), 8, GFLAGS),
+ GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 1, GFLAGS),
+ GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 10, GFLAGS),
+ GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 2, GFLAGS),
+ GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 13, GFLAGS),
+ GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 4, GFLAGS),
+ GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 14, GFLAGS),
+ GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 9, GFLAGS),
+ GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 5, GFLAGS),
+ GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 3, GFLAGS),
+ GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 15, GFLAGS),
+ GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 7, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 15
+ */
+ GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 9, GFLAGS),
+ GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 10, GFLAGS),
+ GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 11, GFLAGS),
+ GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 12, GFLAGS),
+ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 0, GFLAGS),
+};
+
+static const char *const rv1126_cru_critical_clocks[] __initconst = {
+ "gpll",
+ "cpll",
+ "hpll",
+ "armclk",
+ "pclk_dbg",
+ "pclk_pdpmu",
+ "aclk_pdbus",
+ "hclk_pdbus",
+ "pclk_pdbus",
+ "aclk_pdphp",
+ "hclk_pdphp",
+ "clk_ddrphy",
+ "pclk_pdddr",
+ "pclk_pdtop",
+ "clk_usbhost_utmi_ohci",
+ "aclk_pdjpeg_niu",
+ "hclk_pdjpeg_niu",
+ "aclk_pdvdec_niu",
+ "hclk_pdvdec_niu",
+};
+
+static void __init rv1126_pmu_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru pmu region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip pmu clk init failed\n", __func__);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
+ ARRAY_SIZE(rv1126_pmu_pll_clks),
+ RV1126_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
+ ARRAY_SIZE(rv1126_clk_pmu_branches));
+
+ rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);
+
+static void __init rv1126_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126_pll_clks,
+ ARRAY_SIZE(rv1126_pll_clks),
+ RV1126_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
+ mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ &rv1126_cpuclk_data, rv1126_cpuclk_rates,
+ ARRAY_SIZE(rv1126_cpuclk_rates));
+
+ rockchip_clk_register_branches(ctx, rv1126_clk_branches,
+ ARRAY_SIZE(rv1126_clk_branches));
+
+ rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
+
+ rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
+ ARRAY_SIZE(rv1126_cru_critical_clocks));
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 93937fb1d368..ee01739e4a7c 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -79,6 +79,25 @@ struct clk;
#define RV1108_EMMC_CON0 0x1e8
#define RV1108_EMMC_CON1 0x1ec
+#define RV1126_PMU_MODE 0x0
+#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
+#define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
+#define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
+#define RV1126_PLL_CON(x) ((x) * 0x4)
+#define RV1126_MODE_CON 0x90
+#define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
+#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
+#define RV1126_GLB_SRST_FST 0x408
+#define RV1126_GLB_SRST_SND 0x40c
+#define RV1126_SDMMC_CON0 0x440
+#define RV1126_SDMMC_CON1 0x444
+#define RV1126_SDIO_CON0 0x448
+#define RV1126_SDIO_CON1 0x44c
+#define RV1126_EMMC_CON0 0x450
+#define RV1126_EMMC_CON1 0x454
+
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
diff --git a/include/dt-bindings/clock/rv1126-cru.h b/include/dt-bindings/clock/rv1126-cru.h
new file mode 100644
index 000000000000..cfba8226ded2
--- /dev/null
+++ b/include/dt-bindings/clock/rv1126-cru.h
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+
+/* pmucru-clocks indices */
+
+/* pll clocks */
+#define PLL_GPLL 1
+
+/* sclk (special clocks) */
+#define CLK_OSC0_DIV32K 2
+#define CLK_RTC32K 3
+#define CLK_WIFI_DIV 4
+#define CLK_WIFI_OSC0 5
+#define CLK_WIFI 6
+#define CLK_PMU 7
+#define SCLK_UART1_DIV 8
+#define SCLK_UART1_FRACDIV 9
+#define SCLK_UART1_MUX 10
+#define SCLK_UART1 11
+#define CLK_I2C0 12
+#define CLK_I2C2 13
+#define CLK_CAPTURE_PWM0 14
+#define CLK_PWM0 15
+#define CLK_CAPTURE_PWM1 16
+#define CLK_PWM1 17
+#define CLK_SPI0 18
+#define DBCLK_GPIO0 19
+#define CLK_PMUPVTM 20
+#define CLK_CORE_PMUPVTM 21
+#define CLK_REF12M 22
+#define CLK_USBPHY_OTG_REF 23
+#define CLK_USBPHY_HOST_REF 24
+#define CLK_REF24M 25
+#define CLK_MIPIDSIPHY_REF 26
+
+/* pclk */
+#define PCLK_PDPMU 30
+#define PCLK_PMU 31
+#define PCLK_UART1 32
+#define PCLK_I2C0 33
+#define PCLK_I2C2 34
+#define PCLK_PWM0 35
+#define PCLK_PWM1 36
+#define PCLK_SPI0 37
+#define PCLK_GPIO0 38
+#define PCLK_PMUSGRF 39
+#define PCLK_PMUGRF 40
+#define PCLK_PMUCRU 41
+#define PCLK_CHIPVEROTP 42
+#define PCLK_PDPMU_NIU 43
+#define PCLK_PMUPVTM 44
+#define PCLK_SCRKEYGEN 45
+
+#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
+
+/* cru-clocks indices */
+
+/* pll clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_HPLL 4
+
+/* sclk (special clocks) */
+#define ARMCLK 5
+#define USB480M 6
+#define CLK_CORE_CPUPVTM 7
+#define CLK_CPUPVTM 8
+#define CLK_SCR1 9
+#define CLK_SCR1_CORE 10
+#define CLK_SCR1_RTC 11
+#define CLK_SCR1_JTAG 12
+#define SCLK_UART0_DIV 13
+#define SCLK_UART0_FRAC 14
+#define SCLK_UART0_MUX 15
+#define SCLK_UART0 16
+#define SCLK_UART2_DIV 17
+#define SCLK_UART2_FRAC 18
+#define SCLK_UART2_MUX 19
+#define SCLK_UART2 20
+#define SCLK_UART3_DIV 21
+#define SCLK_UART3_FRAC 22
+#define SCLK_UART3_MUX 23
+#define SCLK_UART3 24
+#define SCLK_UART4_DIV 25
+#define SCLK_UART4_FRAC 26
+#define SCLK_UART4_MUX 27
+#define SCLK_UART4 28
+#define SCLK_UART5_DIV 29
+#define SCLK_UART5_FRAC 30
+#define SCLK_UART5_MUX 31
+#define SCLK_UART5 32
+#define CLK_I2C1 33
+#define CLK_I2C3 34
+#define CLK_I2C4 35
+#define CLK_I2C5 36
+#define CLK_SPI1 37
+#define CLK_CAPTURE_PWM2 38
+#define CLK_PWM2 39
+#define DBCLK_GPIO1 40
+#define DBCLK_GPIO2 41
+#define DBCLK_GPIO3 42
+#define DBCLK_GPIO4 43
+#define CLK_SARADC 44
+#define CLK_TIMER0 45
+#define CLK_TIMER1 46
+#define CLK_TIMER2 47
+#define CLK_TIMER3 48
+#define CLK_TIMER4 49
+#define CLK_TIMER5 50
+#define CLK_CAN 51
+#define CLK_NPU_TSADC 52
+#define CLK_NPU_TSADCPHY 53
+#define CLK_CPU_TSADC 54
+#define CLK_CPU_TSADCPHY 55
+#define CLK_CRYPTO_CORE 56
+#define CLK_CRYPTO_PKA 57
+#define MCLK_I2S0_TX_DIV 58
+#define MCLK_I2S0_TX_FRACDIV 59
+#define MCLK_I2S0_TX_MUX 60
+#define MCLK_I2S0_TX 61
+#define MCLK_I2S0_RX_DIV 62
+#define MCLK_I2S0_RX_FRACDIV 63
+#define MCLK_I2S0_RX_MUX 64
+#define MCLK_I2S0_RX 65
+#define MCLK_I2S0_TX_OUT2IO 66
+#define MCLK_I2S0_RX_OUT2IO 67
+#define MCLK_I2S1_DIV 68
+#define MCLK_I2S1_FRACDIV 69
+#define MCLK_I2S1_MUX 70
+#define MCLK_I2S1 71
+#define MCLK_I2S1_OUT2IO 72
+#define MCLK_I2S2_DIV 73
+#define MCLK_I2S2_FRACDIV 74
+#define MCLK_I2S2_MUX 75
+#define MCLK_I2S2 76
+#define MCLK_I2S2_OUT2IO 77
+#define MCLK_PDM 78
+#define SCLK_ADUPWM_DIV 79
+#define SCLK_AUDPWM_FRACDIV 80
+#define SCLK_AUDPWM_MUX 81
+#define SCLK_AUDPWM 82
+#define CLK_ACDCDIG_ADC 83
+#define CLK_ACDCDIG_DAC 84
+#define CLK_ACDCDIG_I2C 85
+#define CLK_VENC_CORE 86
+#define CLK_VDEC_CORE 87
+#define CLK_VDEC_CA 88
+#define CLK_VDEC_HEVC_CA 89
+#define CLK_RGA_CORE 90
+#define CLK_IEP_CORE 91
+#define CLK_ISP_DIV 92
+#define CLK_ISP_NP5 93
+#define CLK_ISP_NUX 94
+#define CLK_ISP 95
+#define CLK_CIF_OUT_DIV 96
+#define CLK_CIF_OUT_FRACDIV 97
+#define CLK_CIF_OUT_MUX 98
+#define CLK_CIF_OUT 99
+#define CLK_MIPICSI_OUT_DIV 100
+#define CLK_MIPICSI_OUT_FRACDIV 101
+#define CLK_MIPICSI_OUT_MUX 102
+#define CLK_MIPICSI_OUT 103
+#define CLK_ISPP_DIV 104
+#define CLK_ISPP_NP5 105
+#define CLK_ISPP_NUX 106
+#define CLK_ISPP 107
+#define CLK_SDMMC 108
+#define SCLK_SDMMC_DRV 109
+#define SCLK_SDMMC_SAMPLE 110
+#define CLK_SDIO 111
+#define SCLK_SDIO_DRV 112
+#define SCLK_SDIO_SAMPLE 113
+#define CLK_EMMC 114
+#define SCLK_EMMC_DRV 115
+#define SCLK_EMMC_SAMPLE 116
+#define CLK_NANDC 117
+#define SCLK_SFC 118
+#define CLK_USBHOST_UTMI_OHCI 119
+#define CLK_USBOTG_REF 120
+#define CLK_GMAC_DIV 121
+#define CLK_GMAC_RGMII_M0 122
+#define CLK_GMAC_SRC_M0 123
+#define CLK_GMAC_RGMII_M1 124
+#define CLK_GMAC_SRC_M1 125
+#define CLK_GMAC_SRC 126
+#define CLK_GMAC_REF 127
+#define CLK_GMAC_TX_SRC 128
+#define CLK_GMAC_TX_DIV5 129
+#define CLK_GMAC_TX_DIV50 130
+#define RGMII_MODE_CLK 131
+#define CLK_GMAC_RX_SRC 132
+#define CLK_GMAC_RX_DIV2 133
+#define CLK_GMAC_RX_DIV20 134
+#define RMII_MODE_CLK 135
+#define CLK_GMAC_TX_RX 136
+#define CLK_GMAC_PTPREF 137
+#define CLK_GMAC_ETHERNET_OUT 138
+#define CLK_DDRPHY 139
+#define CLK_DDR_MON 140
+#define TMCLK_DDR_MON 141
+#define CLK_NPU_DIV 142
+#define CLK_NPU_NP5 143
+#define CLK_CORE_NPU 144
+#define CLK_CORE_NPUPVTM 145
+#define CLK_NPUPVTM 146
+#define SCLK_DDRCLK 147
+#define CLK_OTP 148
+
+/* dclk */
+#define DCLK_DECOM 150
+#define DCLK_VOP_DIV 151
+#define DCLK_VOP_FRACDIV 152
+#define DCLK_VOP_MUX 153
+#define DCLK_VOP 154
+#define DCLK_CIF 155
+#define DCLK_CIFLITE 156
+
+/* aclk */
+#define ACLK_PDBUS 160
+#define ACLK_DMAC 161
+#define ACLK_DCF 162
+#define ACLK_SPINLOCK 163
+#define ACLK_DECOM 164
+#define ACLK_PDCRYPTO 165
+#define ACLK_CRYPTO 166
+#define ACLK_PDVEPU 167
+#define ACLK_VENC 168
+#define ACLK_PDVDEC 169
+#define ACLK_PDJPEG 170
+#define ACLK_VDEC 171
+#define ACLK_JPEG 172
+#define ACLK_PDVO 173
+#define ACLK_RGA 174
+#define ACLK_VOP 175
+#define ACLK_IEP 176
+#define ACLK_PDVI_DIV 177
+#define ACLK_PDVI_NP5 178
+#define ACLK_PDVI 179
+#define ACLK_ISP 180
+#define ACLK_CIF 181
+#define ACLK_CIFLITE 182
+#define ACLK_PDISPP_DIV 183
+#define ACLK_PDISPP_NP5 184
+#define ACLK_PDISPP 185
+#define ACLK_ISPP 186
+#define ACLK_PDPHP 187
+#define ACLK_PDUSB 188
+#define ACLK_USBOTG 189
+#define ACLK_PDGMAC 190
+#define ACLK_GMAC 191
+#define ACLK_PDNPU_DIV 192
+#define ACLK_PDNPU_NP5 193
+#define ACLK_PDNPU 194
+#define ACLK_NPU 195
+
+/* hclk */
+#define HCLK_PDCORE_NIU 200
+#define HCLK_PDUSB 201
+#define HCLK_PDCRYPTO 202
+#define HCLK_CRYPTO 203
+#define HCLK_PDAUDIO 204
+#define HCLK_I2S0 205
+#define HCLK_I2S1 206
+#define HCLK_I2S2 207
+#define HCLK_PDM 208
+#define HCLK_AUDPWM 209
+#define HCLK_PDVEPU 210
+#define HCLK_VENC 211
+#define HCLK_PDVDEC 212
+#define HCLK_PDJPEG 213
+#define HCLK_VDEC 214
+#define HCLK_JPEG 215
+#define HCLK_PDVO 216
+#define HCLK_RGA 217
+#define HCLK_VOP 218
+#define HCLK_IEP 219
+#define HCLK_PDVI 220
+#define HCLK_ISP 221
+#define HCLK_CIF 222
+#define HCLK_CIFLITE 223
+#define HCLK_PDISPP 224
+#define HCLK_ISPP 225
+#define HCLK_PDPHP 226
+#define HCLK_PDSDMMC 227
+#define HCLK_SDMMC 228
+#define HCLK_PDSDIO 229
+#define HCLK_SDIO 230
+#define HCLK_PDNVM 231
+#define HCLK_EMMC 232
+#define HCLK_NANDC 233
+#define HCLK_SFC 234
+#define HCLK_SFCXIP 235
+#define HCLK_PDBUS 236
+#define HCLK_USBHOST 237
+#define HCLK_USBHOST_ARB 238
+#define HCLK_PDNPU 239
+#define HCLK_NPU 240
+
+/* pclk */
+#define PCLK_CPUPVTM 245
+#define PCLK_PDBUS 246
+#define PCLK_DCF 247
+#define PCLK_WDT 248
+#define PCLK_MAILBOX 249
+#define PCLK_UART0 250
+#define PCLK_UART2 251
+#define PCLK_UART3 252
+#define PCLK_UART4 253
+#define PCLK_UART5 254
+#define PCLK_I2C1 255
+#define PCLK_I2C3 256
+#define PCLK_I2C4 257
+#define PCLK_I2C5 258
+#define PCLK_SPI1 259
+#define PCLK_PWM2 261
+#define PCLK_GPIO1 262
+#define PCLK_GPIO2 263
+#define PCLK_GPIO3 264
+#define PCLK_GPIO4 265
+#define PCLK_SARADC 266
+#define PCLK_TIMER 267
+#define PCLK_DECOM 268
+#define PCLK_CAN 269
+#define PCLK_NPU_TSADC 270
+#define PCLK_CPU_TSADC 271
+#define PCLK_ACDCDIG 272
+#define PCLK_PDVO 273
+#define PCLK_DSIHOST 274
+#define PCLK_PDVI 275
+#define PCLK_CSIHOST 276
+#define PCLK_PDGMAC 277
+#define PCLK_GMAC 278
+#define PCLK_PDDDR 279
+#define PCLK_DDR_MON 280
+#define PCLK_PDNPU 281
+#define PCLK_NPUPVTM 282
+#define PCLK_PDTOP 283
+#define PCLK_TOPCRU 284
+#define PCLK_TOPGRF 285
+#define PCLK_CPUEMADET 286
+#define PCLK_DDRPHY 287
+#define PCLK_DSIPHY 289
+#define PCLK_CSIPHY0 290
+#define PCLK_CSIPHY1 291
+#define PCLK_USBPHY_HOST 292
+#define PCLK_USBPHY_OTG 293
+#define PCLK_OTP 294
+
+#define CLK_NR_CLKS (PCLK_OTP + 1)
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_PDPMU_NIU_P 0
+#define SRST_PMU_SGRF_P 1
+#define SRST_PMU_SGRF_REMAP_P 2
+#define SRST_I2C0_P 3
+#define SRST_I2C0 4
+#define SRST_I2C2_P 7
+#define SRST_I2C2 8
+#define SRST_UART1_P 9
+#define SRST_UART1 10
+#define SRST_PWM0_P 11
+#define SRST_PWM0 12
+#define SRST_PWM1_P 13
+#define SRST_PWM1 14
+#define SRST_DDR_FAIL_SAFE 15
+
+/* pmu_cru_softrst_con1 */
+#define SRST_GPIO0_P 17
+#define SRST_GPIO0_DB 18
+#define SRST_SPI0_P 19
+#define SRST_SPI0 20
+#define SRST_PMUGRF_P 21
+#define SRST_CHIPVEROTP_P 22
+#define SRST_PMUPVTM 24
+#define SRST_PMUPVTM_P 25
+#define SRST_PMUCRU_P 30
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_NL2 12
+#define SRST_CORE_NIU_A 13
+#define SRST_DBG_DAPLITE_P 14
+#define SRST_DAPLITE_P 15
+
+/* cru_softrst_con1 */
+#define SRST_PDBUS_NIU1_A 16
+#define SRST_PDBUS_NIU1_H 17
+#define SRST_PDBUS_NIU1_P 18
+#define SRST_PDBUS_NIU2_A 19
+#define SRST_PDBUS_NIU2_H 20
+#define SRST_PDBUS_NIU3_A 21
+#define SRST_PDBUS_NIU3_H 22
+#define SRST_PDBUS_HOLD_NIU1_A 23
+#define SRST_DBG_NIU_P 24
+#define SRST_PDCORE_NIIU_H 25
+#define SRST_MUC_NIU 26
+#define SRST_DCF_A 29
+#define SRST_DCF_P 30
+#define SRST_SYSTEM_SRAM_A 31
+
+/* cru_softrst_con2 */
+#define SRST_I2C1_P 32
+#define SRST_I2C1 33
+#define SRST_I2C3_P 34
+#define SRST_I2C3 35
+#define SRST_I2C4_P 36
+#define SRST_I2C4 37
+#define SRST_I2C5_P 38
+#define SRST_I2C5 39
+#define SRST_SPI1_P 40
+#define SRST_SPI1 41
+#define SRST_MCU_CORE 42
+#define SRST_PWM2_P 44
+#define SRST_PWM2 45
+#define SRST_SPINLOCK_A 46
+
+/* cru_softrst_con3 */
+#define SRST_UART0_P 48
+#define SRST_UART0 49
+#define SRST_UART2_P 50
+#define SRST_UART2 51
+#define SRST_UART3_P 52
+#define SRST_UART3 53
+#define SRST_UART4_P 54
+#define SRST_UART4 55
+#define SRST_UART5_P 56
+#define SRST_UART5 57
+#define SRST_WDT_P 58
+#define SRST_SARADC_P 59
+#define SRST_GRF_P 61
+#define SRST_TIMER_P 62
+#define SRST_MAILBOX_P 63
+
+/* cru_softrst_con4 */
+#define SRST_TIMER0 64
+#define SRST_TIMER1 65
+#define SRST_TIMER2 66
+#define SRST_TIMER3 67
+#define SRST_TIMER4 68
+#define SRST_TIMER5 69
+#define SRST_INTMUX_P 70
+#define SRST_GPIO1_P 72
+#define SRST_GPIO1_DB 73
+#define SRST_GPIO2_P 74
+#define SRST_GPIO2_DB 75
+#define SRST_GPIO3_P 76
+#define SRST_GPIO3_DB 77
+#define SRST_GPIO4_P 78
+#define SRST_GPIO4_DB 79
+
+/* cru_softrst_con5 */
+#define SRST_CAN_P 80
+#define SRST_CAN 81
+#define SRST_DECOM_A 85
+#define SRST_DECOM_P 86
+#define SRST_DECOM_D 87
+#define SRST_PDCRYPTO_NIU_A 88
+#define SRST_PDCRYPTO_NIU_H 89
+#define SRST_CRYPTO_A 90
+#define SRST_CRYPTO_H 91
+#define SRST_CRYPTO_CORE 92
+#define SRST_CRYPTO_PKA 93
+#define SRST_SGRF_P 95
+
+/* cru_softrst_con6 */
+#define SRST_PDAUDIO_NIU_H 96
+#define SRST_PDAUDIO_NIU_P 97
+#define SRST_I2S0_H 98
+#define SRST_I2S0_TX_M 99
+#define SRST_I2S0_RX_M 100
+#define SRST_I2S1_H 101
+#define SRST_I2S1_M 102
+#define SRST_I2S2_H 103
+#define SRST_I2S2_M 104
+#define SRST_PDM_H 105
+#define SRST_PDM_M 106
+#define SRST_AUDPWM_H 107
+#define SRST_AUDPWM 108
+#define SRST_ACDCDIG_P 109
+#define SRST_ACDCDIG 110
+
+/* cru_softrst_con7 */
+#define SRST_PDVEPU_NIU_A 112
+#define SRST_PDVEPU_NIU_H 113
+#define SRST_VENC_A 114
+#define SRST_VENC_H 115
+#define SRST_VENC_CORE 116
+#define SRST_PDVDEC_NIU_A 117
+#define SRST_PDVDEC_NIU_H 118
+#define SRST_VDEC_A 119
+#define SRST_VDEC_H 120
+#define SRST_VDEC_CORE 121
+#define SRST_VDEC_CA 122
+#define SRST_VDEC_HEVC_CA 123
+#define SRST_PDJPEG_NIU_A 124
+#define SRST_PDJPEG_NIU_H 125
+#define SRST_JPEG_A 126
+#define SRST_JPEG_H 127
+
+/* cru_softrst_con8 */
+#define SRST_PDVO_NIU_A 128
+#define SRST_PDVO_NIU_H 129
+#define SRST_PDVO_NIU_P 130
+#define SRST_RGA_A 131
+#define SRST_RGA_H 132
+#define SRST_RGA_CORE 133
+#define SRST_VOP_A 134
+#define SRST_VOP_H 135
+#define SRST_VOP_D 136
+#define SRST_TXBYTEHS_DSIHOST 137
+#define SRST_DSIHOST_P 138
+#define SRST_IEP_A 139
+#define SRST_IEP_H 140
+#define SRST_IEP_CORE 141
+#define SRST_ISP_RX_P 142
+
+/* cru_softrst_con9 */
+#define SRST_PDVI_NIU_A 144
+#define SRST_PDVI_NIU_H 145
+#define SRST_PDVI_NIU_P 146
+#define SRST_ISP 147
+#define SRST_CIF_A 148
+#define SRST_CIF_H 149
+#define SRST_CIF_D 150
+#define SRST_CIF_P 151
+#define SRST_CIF_I 152
+#define SRST_CIF_RX_P 153
+#define SRST_PDISPP_NIU_A 154
+#define SRST_PDISPP_NIU_H 155
+#define SRST_ISPP_A 156
+#define SRST_ISPP_H 157
+#define SRST_ISPP 158
+#define SRST_CSIHOST_P 159
+
+/* cru_softrst_con10 */
+#define SRST_PDPHPMID_NIU_A 160
+#define SRST_PDPHPMID_NIU_H 161
+#define SRST_PDNVM_NIU_H 163
+#define SRST_SDMMC_H 164
+#define SRST_SDIO_H 165
+#define SRST_EMMC_H 166
+#define SRST_SFC_H 167
+#define SRST_SFCXIP_H 168
+#define SRST_SFC 169
+#define SRST_NANDC_H 170
+#define SRST_NANDC 171
+#define SRST_PDSDMMC_H 173
+#define SRST_PDSDIO_H 174
+
+/* cru_softrst_con11 */
+#define SRST_PDUSB_NIU_A 176
+#define SRST_PDUSB_NIU_H 177
+#define SRST_USBHOST_H 178
+#define SRST_USBHOST_ARB_H 179
+#define SRST_USBHOST_UTMI 180
+#define SRST_USBOTG_A 181
+#define SRST_USBPHY_OTG_P 182
+#define SRST_USBPHY_HOST_P 183
+#define SRST_USBPHYPOR_OTG 184
+#define SRST_USBPHYPOR_HOST 185
+#define SRST_PDGMAC_NIU_A 188
+#define SRST_PDGMAC_NIU_P 189
+#define SRST_GMAC_A 190
+
+/* cru_softrst_con12 */
+#define SRST_DDR_DFICTL_P 193
+#define SRST_DDR_MON_P 194
+#define SRST_DDR_STANDBY_P 195
+#define SRST_DDR_GRF_P 196
+#define SRST_DDR_MSCH_P 197
+#define SRST_DDR_SPLIT_A 198
+#define SRST_DDR_MSCH 199
+#define SRST_DDR_DFICTL 202
+#define SRST_DDR_STANDBY 203
+#define SRST_NPUMCU_NIU 205
+#define SRST_DDRPHY_P 206
+#define SRST_DDRPHY 207
+
+/* cru_softrst_con13 */
+#define SRST_PDNPU_NIU_A 208
+#define SRST_PDNPU_NIU_H 209
+#define SRST_PDNPU_NIU_P 210
+#define SRST_NPU_A 211
+#define SRST_NPU_H 212
+#define SRST_NPU 213
+#define SRST_NPUPVTM_P 214
+#define SRST_NPUPVTM 215
+#define SRST_NPU_TSADC_P 216
+#define SRST_NPU_TSADC 217
+#define SRST_NPU_TSADCPHY 218
+#define SRST_CIFLITE_A 220
+#define SRST_CIFLITE_H 221
+#define SRST_CIFLITE_D 222
+#define SRST_CIFLITE_RX_P 223
+
+/* cru_softrst_con14 */
+#define SRST_TOPNIU_P 224
+#define SRST_TOPCRU_P 225
+#define SRST_TOPGRF_P 226
+#define SRST_CPUEMADET_P 227
+#define SRST_CSIPHY0_P 228
+#define SRST_CSIPHY1_P 229
+#define SRST_DSIPHY_P 230
+#define SRST_CPU_TSADC_P 232
+#define SRST_CPU_TSADC 233
+#define SRST_CPU_TSADCPHY 234
+#define SRST_CPUPVTM_P 235
+#define SRST_CPUPVTM 236
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-clk, Michael Turquette, Stephen Boyd, Finley Xiao
Add clock controller support for RV1126 SoC.
Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.
This patch is trying to add minimal Clock-Architecture Diagram's
inferred from [1] authored by Finley Xiao.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1126.c | 1107 ++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 19 +
include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++++++
5 files changed, 1766 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rv1126.c
create mode 100644 include/dt-bindings/clock/rv1126-cru.h
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 3067bdb6e119..345a5d2a457c 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -23,6 +23,13 @@ config CLK_RV110X
help
Build the driver for RV110x Clock Driver.
+config CLK_RV1126
+ bool "Rockchip RV1126 clock controller support"
+ depends on ARM || COMPILE_TEST
+ default y
+ help
+ Build the driver for RV1126 Clock Driver.
+
config CLK_RK3036
bool "Rockchip RK3036 clock controller support"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 2b78f1247372..e8543876c056 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -17,6 +17,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
+obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
new file mode 100644
index 000000000000..40d8b635a00a
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rv1126-cru.h>
+#include "clk.h"
+
+#define RV1126_GMAC_CON 0x460
+#define RV1126_GRF_IOFUNC_CON1 0x10264
+#define RV1126_GRF_SOC_STATUS0 0x10
+
+#define RV1126_FRAC_MAX_PRATE 1200000000
+#define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
+
+enum rv1126_pmu_plls {
+ gpll,
+};
+
+enum rv1126_plls {
+ apll, dpll, cpll, hpll,
+};
+
+static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
+ RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
+ RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
+ RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
+ RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
+ RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RV1126_DIV_ACLK_CORE_MASK 0xf
+#define RV1126_DIV_ACLK_CORE_SHIFT 4
+#define RV1126_DIV_PCLK_DBG_MASK 0x7
+#define RV1126_DIV_PCLK_DBG_SHIFT 0
+
+#define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
+{ \
+ .reg = RV1126_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
+ RV1126_DIV_ACLK_CORE_SHIFT) | \
+ HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
+ RV1126_DIV_PCLK_DBG_SHIFT), \
+}
+
+#define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
+ RV1126_CPUCLK_RATE(1608000000, 1, 7),
+ RV1126_CPUCLK_RATE(1584000000, 1, 7),
+ RV1126_CPUCLK_RATE(1560000000, 1, 7),
+ RV1126_CPUCLK_RATE(1536000000, 1, 7),
+ RV1126_CPUCLK_RATE(1512000000, 1, 7),
+ RV1126_CPUCLK_RATE(1488000000, 1, 5),
+ RV1126_CPUCLK_RATE(1464000000, 1, 5),
+ RV1126_CPUCLK_RATE(1440000000, 1, 5),
+ RV1126_CPUCLK_RATE(1416000000, 1, 5),
+ RV1126_CPUCLK_RATE(1392000000, 1, 5),
+ RV1126_CPUCLK_RATE(1368000000, 1, 5),
+ RV1126_CPUCLK_RATE(1344000000, 1, 5),
+ RV1126_CPUCLK_RATE(1320000000, 1, 5),
+ RV1126_CPUCLK_RATE(1296000000, 1, 5),
+ RV1126_CPUCLK_RATE(1272000000, 1, 5),
+ RV1126_CPUCLK_RATE(1248000000, 1, 5),
+ RV1126_CPUCLK_RATE(1224000000, 1, 5),
+ RV1126_CPUCLK_RATE(1200000000, 1, 5),
+ RV1126_CPUCLK_RATE(1104000000, 1, 5),
+ RV1126_CPUCLK_RATE(1008000000, 1, 5),
+ RV1126_CPUCLK_RATE(912000000, 1, 5),
+ RV1126_CPUCLK_RATE(816000000, 1, 3),
+ RV1126_CPUCLK_RATE(696000000, 1, 3),
+ RV1126_CPUCLK_RATE(600000000, 1, 3),
+ RV1126_CPUCLK_RATE(408000000, 1, 1),
+ RV1126_CPUCLK_RATE(312000000, 1, 1),
+ RV1126_CPUCLK_RATE(216000000, 1, 1),
+ RV1126_CPUCLK_RATE(96000000, 1, 1),
+};
+
+static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
+ .core_reg[0] = RV1126_CLKSEL_CON(0),
+ .div_core_shift[0] = 0,
+ .div_core_mask[0] = 0x1f,
+ .num_cores = 1,
+ .mux_core_alt = 0,
+ .mux_core_main = 2,
+ .mux_core_shift = 6,
+ .mux_core_mask = 0x3,
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
+PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
+PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
+PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
+PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
+PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
+PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
+PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
+PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
+PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
+PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
+PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
+PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
+PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
+PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
+PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
+PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
+PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
+PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
+PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
+PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
+PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
+PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
+PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
+PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
+PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
+PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
+PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
+PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
+PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
+PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
+PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
+PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
+PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
+PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
+PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
+PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
+PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
+PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
+PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
+PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
+PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
+PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
+PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
+PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
+PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
+PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
+PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
+PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
+PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
+PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
+
+static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
+
+static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ 0, RV1126_PMU_PLL_CON(0),
+ RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
+};
+
+static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+ 0, RV1126_PLL_CON(0),
+ RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
+ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+ 0, RV1126_PLL_CON(8),
+ RV1126_MODE_CON, 2, 1, 0, NULL),
+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+ 0, RV1126_PLL_CON(16),
+ RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
+ [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
+ 0, RV1126_PLL_CON(24),
+ RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
+ MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
+ MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
+ MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
+ MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
+ MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
+ MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
+ MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
+ MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
+ MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
+ MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
+ MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
+ MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 2
+ */
+ /* PD_PMU */
+ COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
+
+ COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKSEL_CON(13), 0,
+ RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
+ &rv1126_rtc32k_fracmux),
+
+ COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
+ GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
+ MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
+
+ GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
+
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
+ RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(5), 0,
+ RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
+ &rv1126_uart1_fracmux),
+ GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
+ RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
+
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
+ RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
+ COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
+ RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
+
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
+ COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
+ RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
+
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
+ RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
+
+ GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
+ GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
+ GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
+ FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
+ FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
+ MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
+ MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
+
+ COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
+ GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
+ MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
+
+ GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
+
+ GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
+ GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
+
+ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 1
+ */
+ MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
+ RV1126_MODE_CON, 10, 2, MFLAGS),
+ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RV1126_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
+ RV1126_CLKGATE_CON(0), 12, GFLAGS),
+ GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
+ RV1126_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
+ RV1126_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(0), 8, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ /* PD_BUS */
+ COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 1, GFLAGS),
+ GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 12, GFLAGS),
+ COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 2, GFLAGS),
+ GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 13, GFLAGS),
+ /* aclk_dmac is controlled by sgrf_clkgat_con. */
+ SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
+ GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 6, GFLAGS),
+ GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 7, GFLAGS),
+ GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 14, GFLAGS),
+ GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 10, GFLAGS),
+
+ COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(4), 7, GFLAGS),
+ GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 14, GFLAGS),
+ GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
+ RV1126_CLKGATE_CON(4), 8, GFLAGS),
+ GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
+ RV1126_CLKGATE_CON(4), 9, GFLAGS),
+ GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
+ RV1126_CLKGATE_CON(4), 10, GFLAGS),
+
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 0, GFLAGS),
+ COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 1, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(11), 0,
+ RV1126_CLKGATE_CON(5), 2, GFLAGS,
+ &rv1126_uart0_fracmux),
+ GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
+ RV1126_CLKGATE_CON(5), 3, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 4, GFLAGS),
+ COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 5, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(13), 0,
+ RV1126_CLKGATE_CON(5), 6, GFLAGS,
+ &rv1126_uart2_fracmux),
+ GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
+ RV1126_CLKGATE_CON(5), 7, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 8, GFLAGS),
+ COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 9, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(15), 0,
+ RV1126_CLKGATE_CON(5), 10, GFLAGS,
+ &rv1126_uart3_fracmux),
+ GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
+ RV1126_CLKGATE_CON(5), 11, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 12, GFLAGS),
+ COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
+ DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(17), 0,
+ RV1126_CLKGATE_CON(5), 14, GFLAGS,
+ &rv1126_uart4_fracmux),
+ GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
+ RV1126_CLKGATE_CON(5), 15, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
+ DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(19), 0,
+ RV1126_CLKGATE_CON(6), 2, GFLAGS,
+ &rv1126_uart5_fracmux),
+ GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
+ RV1126_CLKGATE_CON(6), 3, GFLAGS),
+
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
+ RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 11, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
+ RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 13, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 14, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
+ RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
+ RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 1, GFLAGS),
+
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 3, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
+ RV1126_CLKGATE_CON(4), 6, GFLAGS),
+ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
+ RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 5, GFLAGS),
+
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 0, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 2, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 4, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 5, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 6, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 7, GFLAGS),
+
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+ RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(6), 5, GFLAGS),
+
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 7, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 8, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 10, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 11, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 12, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 13, GFLAGS),
+
+ GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 6, GFLAGS),
+
+ GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 11, GFLAGS),
+ GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 12, GFLAGS),
+ COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(7), 13, GFLAGS),
+
+ GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 8, GFLAGS),
+ COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(7), 9, GFLAGS),
+ /* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
+ SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
+ SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
+
+ GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(24), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
+ RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(24), 4, GFLAGS),
+ GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
+ RV1126_CLKGATE_CON(24), 5, GFLAGS),
+ GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(24), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
+ RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(24), 1, GFLAGS),
+ GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
+ RV1126_CLKGATE_CON(24), 2, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+ /* PD_AUDIO */
+ COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
+ RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(9), 0, GFLAGS),
+
+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(9), 4, GFLAGS),
+ COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(9), 5, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(28), 0,
+ RV1126_CLKGATE_CON(9), 6, GFLAGS,
+ &rv1126_i2s0_tx_fracmux),
+ GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
+ RV1126_CLKGATE_CON(9), 9, GFLAGS),
+ COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(9), 7, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(29), 0,
+ RV1126_CLKGATE_CON(9), 8, GFLAGS,
+ &rv1126_i2s0_rx_fracmux),
+ GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
+ RV1126_CLKGATE_CON(9), 10, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
+ RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
+ RV1126_CLKGATE_CON(9), 13, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
+ RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
+ RV1126_CLKGATE_CON(9), 14, GFLAGS),
+
+ GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 0, GFLAGS),
+ COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 1, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(32), 0,
+ RV1126_CLKGATE_CON(10), 2, GFLAGS,
+ &rv1126_i2s1_fracmux),
+ GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
+ RV1126_CLKGATE_CON(10), 3, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
+ RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
+ RV1126_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 5, GFLAGS),
+ COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 6, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(34), 0,
+ RV1126_CLKGATE_CON(10), 7, GFLAGS,
+ &rv1126_i2s2_fracmux),
+ GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
+ RV1126_CLKGATE_CON(10), 8, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
+ RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
+ RV1126_CLKGATE_CON(10), 9, GFLAGS),
+
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 10, GFLAGS),
+ COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 11, GFLAGS),
+
+ GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 12, GFLAGS),
+ COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 13, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(37), 0,
+ RV1126_CLKGATE_CON(10), 14, GFLAGS,
+ &rv1126_audpwm_fracmux),
+ GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
+ RV1126_CLKGATE_CON(10), 15, GFLAGS),
+
+ GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(11), 0, GFLAGS),
+ GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
+ RV1126_CLKGATE_CON(11), 2, GFLAGS),
+ GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
+ RV1126_CLKGATE_CON(11), 3, GFLAGS),
+ COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(11), 1, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 12
+ */
+ /* PD_PHP */
+ COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(17), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(17), 1, GFLAGS),
+ /* PD_SDCARD */
+ GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(17), 6, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
+ RV1126_CLKGATE_CON(18), 4, GFLAGS),
+ COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
+ DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
+ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
+
+ /* PD_SDIO */
+ GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(17), 8, GFLAGS),
+ GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
+ RV1126_CLKGATE_CON(18), 6, GFLAGS),
+ COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 7, GFLAGS),
+ MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
+
+ /* PD_NVM */
+ GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(18), 1, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 8, GFLAGS),
+ COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 9, GFLAGS),
+ GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 13, GFLAGS),
+ COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 14, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 10, GFLAGS),
+ GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 11, GFLAGS),
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 12, GFLAGS),
+ MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
+
+ /* PD_USB */
+ GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
+ RV1126_CLKGATE_CON(19), 0, GFLAGS),
+ GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(19), 1, GFLAGS),
+ GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 4, GFLAGS),
+ GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 5, GFLAGS),
+ COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
+ RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(19), 6, GFLAGS),
+ GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 7, GFLAGS),
+ GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
+ RV1126_CLKGATE_CON(19), 8, GFLAGS),
+ /* PD_GMAC */
+ GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
+ RV1126_CLKGATE_CON(20), 0, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
+ RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 1, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
+ RV1126_CLKGATE_CON(20), 4, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
+ RV1126_CLKGATE_CON(20), 5, GFLAGS),
+
+ COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 6, GFLAGS),
+ GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
+ RV1126_CLKGATE_CON(20), 12, GFLAGS),
+ MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 0, 1, MFLAGS),
+ GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
+ RV1126_CLKGATE_CON(20), 13, GFLAGS),
+ MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 5, 1, MFLAGS),
+ MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+ RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
+
+ GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 7, GFLAGS),
+
+ GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 9, GFLAGS),
+ FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
+ FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
+ MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
+ GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 8, GFLAGS),
+ FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
+ FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
+ MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 1, 1, MFLAGS),
+ MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+ RV1126_GMAC_CON, 4, 1, MFLAGS),
+
+ GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
+ RV1126_CLKGATE_CON(20), 10, GFLAGS),
+ COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 11, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 15
+ */
+ GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 8, GFLAGS),
+ GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 4, GFLAGS),
+ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 2, GFLAGS),
+ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 3, GFLAGS),
+ GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(19), 13, GFLAGS),
+ GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(19), 12, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RV1126_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 5, GFLAGS),
+ GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 4, GFLAGS),
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ /* PD_BUS */
+ GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 10, GFLAGS),
+ GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 3, GFLAGS),
+ GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 6, GFLAGS),
+ GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 7, GFLAGS),
+ GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 8, GFLAGS),
+ GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 9, GFLAGS),
+ GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(6), 15, GFLAGS),
+ GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(8), 4, GFLAGS),
+ GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 9, GFLAGS),
+ GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(7), 14, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+ /* PD_AUDIO */
+ GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(9), 2, GFLAGS),
+ GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(9), 3, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 12
+ */
+ /* PD_PHP */
+ GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 2, GFLAGS),
+ GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 3, GFLAGS),
+ GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 4, GFLAGS),
+ GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 5, GFLAGS),
+
+ /* PD_SDCARD */
+ GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 7, GFLAGS),
+
+ /* PD_SDIO */
+ GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 9, GFLAGS),
+
+ /* PD_NVM */
+ GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(18), 3, GFLAGS),
+
+ /* PD_USB */
+ GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(19), 2, GFLAGS),
+ GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(19), 3, GFLAGS),
+
+ /* PD_GMAC */
+ GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 2, GFLAGS),
+ GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 3, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 13
+ */
+ /* PD_DDR */
+ COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(21), 0, GFLAGS),
+ GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 15, GFLAGS),
+ GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 6, GFLAGS),
+ COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
+ CLK_DIVIDER_POWER_OF_TWO),
+ COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(21), 8, GFLAGS),
+ GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 1, GFLAGS),
+ GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 10, GFLAGS),
+ GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 2, GFLAGS),
+ GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 13, GFLAGS),
+ GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 4, GFLAGS),
+ GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 14, GFLAGS),
+ GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 9, GFLAGS),
+ GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 5, GFLAGS),
+ GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 3, GFLAGS),
+ GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 15, GFLAGS),
+ GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 7, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 15
+ */
+ GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 9, GFLAGS),
+ GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 10, GFLAGS),
+ GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 11, GFLAGS),
+ GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 12, GFLAGS),
+ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 0, GFLAGS),
+};
+
+static const char *const rv1126_cru_critical_clocks[] __initconst = {
+ "gpll",
+ "cpll",
+ "hpll",
+ "armclk",
+ "pclk_dbg",
+ "pclk_pdpmu",
+ "aclk_pdbus",
+ "hclk_pdbus",
+ "pclk_pdbus",
+ "aclk_pdphp",
+ "hclk_pdphp",
+ "clk_ddrphy",
+ "pclk_pdddr",
+ "pclk_pdtop",
+ "clk_usbhost_utmi_ohci",
+ "aclk_pdjpeg_niu",
+ "hclk_pdjpeg_niu",
+ "aclk_pdvdec_niu",
+ "hclk_pdvdec_niu",
+};
+
+static void __init rv1126_pmu_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru pmu region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip pmu clk init failed\n", __func__);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
+ ARRAY_SIZE(rv1126_pmu_pll_clks),
+ RV1126_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
+ ARRAY_SIZE(rv1126_clk_pmu_branches));
+
+ rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);
+
+static void __init rv1126_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126_pll_clks,
+ ARRAY_SIZE(rv1126_pll_clks),
+ RV1126_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
+ mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ &rv1126_cpuclk_data, rv1126_cpuclk_rates,
+ ARRAY_SIZE(rv1126_cpuclk_rates));
+
+ rockchip_clk_register_branches(ctx, rv1126_clk_branches,
+ ARRAY_SIZE(rv1126_clk_branches));
+
+ rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
+
+ rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
+ ARRAY_SIZE(rv1126_cru_critical_clocks));
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 93937fb1d368..ee01739e4a7c 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -79,6 +79,25 @@ struct clk;
#define RV1108_EMMC_CON0 0x1e8
#define RV1108_EMMC_CON1 0x1ec
+#define RV1126_PMU_MODE 0x0
+#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
+#define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
+#define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
+#define RV1126_PLL_CON(x) ((x) * 0x4)
+#define RV1126_MODE_CON 0x90
+#define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
+#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
+#define RV1126_GLB_SRST_FST 0x408
+#define RV1126_GLB_SRST_SND 0x40c
+#define RV1126_SDMMC_CON0 0x440
+#define RV1126_SDMMC_CON1 0x444
+#define RV1126_SDIO_CON0 0x448
+#define RV1126_SDIO_CON1 0x44c
+#define RV1126_EMMC_CON0 0x450
+#define RV1126_EMMC_CON1 0x454
+
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
diff --git a/include/dt-bindings/clock/rv1126-cru.h b/include/dt-bindings/clock/rv1126-cru.h
new file mode 100644
index 000000000000..cfba8226ded2
--- /dev/null
+++ b/include/dt-bindings/clock/rv1126-cru.h
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+
+/* pmucru-clocks indices */
+
+/* pll clocks */
+#define PLL_GPLL 1
+
+/* sclk (special clocks) */
+#define CLK_OSC0_DIV32K 2
+#define CLK_RTC32K 3
+#define CLK_WIFI_DIV 4
+#define CLK_WIFI_OSC0 5
+#define CLK_WIFI 6
+#define CLK_PMU 7
+#define SCLK_UART1_DIV 8
+#define SCLK_UART1_FRACDIV 9
+#define SCLK_UART1_MUX 10
+#define SCLK_UART1 11
+#define CLK_I2C0 12
+#define CLK_I2C2 13
+#define CLK_CAPTURE_PWM0 14
+#define CLK_PWM0 15
+#define CLK_CAPTURE_PWM1 16
+#define CLK_PWM1 17
+#define CLK_SPI0 18
+#define DBCLK_GPIO0 19
+#define CLK_PMUPVTM 20
+#define CLK_CORE_PMUPVTM 21
+#define CLK_REF12M 22
+#define CLK_USBPHY_OTG_REF 23
+#define CLK_USBPHY_HOST_REF 24
+#define CLK_REF24M 25
+#define CLK_MIPIDSIPHY_REF 26
+
+/* pclk */
+#define PCLK_PDPMU 30
+#define PCLK_PMU 31
+#define PCLK_UART1 32
+#define PCLK_I2C0 33
+#define PCLK_I2C2 34
+#define PCLK_PWM0 35
+#define PCLK_PWM1 36
+#define PCLK_SPI0 37
+#define PCLK_GPIO0 38
+#define PCLK_PMUSGRF 39
+#define PCLK_PMUGRF 40
+#define PCLK_PMUCRU 41
+#define PCLK_CHIPVEROTP 42
+#define PCLK_PDPMU_NIU 43
+#define PCLK_PMUPVTM 44
+#define PCLK_SCRKEYGEN 45
+
+#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
+
+/* cru-clocks indices */
+
+/* pll clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_HPLL 4
+
+/* sclk (special clocks) */
+#define ARMCLK 5
+#define USB480M 6
+#define CLK_CORE_CPUPVTM 7
+#define CLK_CPUPVTM 8
+#define CLK_SCR1 9
+#define CLK_SCR1_CORE 10
+#define CLK_SCR1_RTC 11
+#define CLK_SCR1_JTAG 12
+#define SCLK_UART0_DIV 13
+#define SCLK_UART0_FRAC 14
+#define SCLK_UART0_MUX 15
+#define SCLK_UART0 16
+#define SCLK_UART2_DIV 17
+#define SCLK_UART2_FRAC 18
+#define SCLK_UART2_MUX 19
+#define SCLK_UART2 20
+#define SCLK_UART3_DIV 21
+#define SCLK_UART3_FRAC 22
+#define SCLK_UART3_MUX 23
+#define SCLK_UART3 24
+#define SCLK_UART4_DIV 25
+#define SCLK_UART4_FRAC 26
+#define SCLK_UART4_MUX 27
+#define SCLK_UART4 28
+#define SCLK_UART5_DIV 29
+#define SCLK_UART5_FRAC 30
+#define SCLK_UART5_MUX 31
+#define SCLK_UART5 32
+#define CLK_I2C1 33
+#define CLK_I2C3 34
+#define CLK_I2C4 35
+#define CLK_I2C5 36
+#define CLK_SPI1 37
+#define CLK_CAPTURE_PWM2 38
+#define CLK_PWM2 39
+#define DBCLK_GPIO1 40
+#define DBCLK_GPIO2 41
+#define DBCLK_GPIO3 42
+#define DBCLK_GPIO4 43
+#define CLK_SARADC 44
+#define CLK_TIMER0 45
+#define CLK_TIMER1 46
+#define CLK_TIMER2 47
+#define CLK_TIMER3 48
+#define CLK_TIMER4 49
+#define CLK_TIMER5 50
+#define CLK_CAN 51
+#define CLK_NPU_TSADC 52
+#define CLK_NPU_TSADCPHY 53
+#define CLK_CPU_TSADC 54
+#define CLK_CPU_TSADCPHY 55
+#define CLK_CRYPTO_CORE 56
+#define CLK_CRYPTO_PKA 57
+#define MCLK_I2S0_TX_DIV 58
+#define MCLK_I2S0_TX_FRACDIV 59
+#define MCLK_I2S0_TX_MUX 60
+#define MCLK_I2S0_TX 61
+#define MCLK_I2S0_RX_DIV 62
+#define MCLK_I2S0_RX_FRACDIV 63
+#define MCLK_I2S0_RX_MUX 64
+#define MCLK_I2S0_RX 65
+#define MCLK_I2S0_TX_OUT2IO 66
+#define MCLK_I2S0_RX_OUT2IO 67
+#define MCLK_I2S1_DIV 68
+#define MCLK_I2S1_FRACDIV 69
+#define MCLK_I2S1_MUX 70
+#define MCLK_I2S1 71
+#define MCLK_I2S1_OUT2IO 72
+#define MCLK_I2S2_DIV 73
+#define MCLK_I2S2_FRACDIV 74
+#define MCLK_I2S2_MUX 75
+#define MCLK_I2S2 76
+#define MCLK_I2S2_OUT2IO 77
+#define MCLK_PDM 78
+#define SCLK_ADUPWM_DIV 79
+#define SCLK_AUDPWM_FRACDIV 80
+#define SCLK_AUDPWM_MUX 81
+#define SCLK_AUDPWM 82
+#define CLK_ACDCDIG_ADC 83
+#define CLK_ACDCDIG_DAC 84
+#define CLK_ACDCDIG_I2C 85
+#define CLK_VENC_CORE 86
+#define CLK_VDEC_CORE 87
+#define CLK_VDEC_CA 88
+#define CLK_VDEC_HEVC_CA 89
+#define CLK_RGA_CORE 90
+#define CLK_IEP_CORE 91
+#define CLK_ISP_DIV 92
+#define CLK_ISP_NP5 93
+#define CLK_ISP_NUX 94
+#define CLK_ISP 95
+#define CLK_CIF_OUT_DIV 96
+#define CLK_CIF_OUT_FRACDIV 97
+#define CLK_CIF_OUT_MUX 98
+#define CLK_CIF_OUT 99
+#define CLK_MIPICSI_OUT_DIV 100
+#define CLK_MIPICSI_OUT_FRACDIV 101
+#define CLK_MIPICSI_OUT_MUX 102
+#define CLK_MIPICSI_OUT 103
+#define CLK_ISPP_DIV 104
+#define CLK_ISPP_NP5 105
+#define CLK_ISPP_NUX 106
+#define CLK_ISPP 107
+#define CLK_SDMMC 108
+#define SCLK_SDMMC_DRV 109
+#define SCLK_SDMMC_SAMPLE 110
+#define CLK_SDIO 111
+#define SCLK_SDIO_DRV 112
+#define SCLK_SDIO_SAMPLE 113
+#define CLK_EMMC 114
+#define SCLK_EMMC_DRV 115
+#define SCLK_EMMC_SAMPLE 116
+#define CLK_NANDC 117
+#define SCLK_SFC 118
+#define CLK_USBHOST_UTMI_OHCI 119
+#define CLK_USBOTG_REF 120
+#define CLK_GMAC_DIV 121
+#define CLK_GMAC_RGMII_M0 122
+#define CLK_GMAC_SRC_M0 123
+#define CLK_GMAC_RGMII_M1 124
+#define CLK_GMAC_SRC_M1 125
+#define CLK_GMAC_SRC 126
+#define CLK_GMAC_REF 127
+#define CLK_GMAC_TX_SRC 128
+#define CLK_GMAC_TX_DIV5 129
+#define CLK_GMAC_TX_DIV50 130
+#define RGMII_MODE_CLK 131
+#define CLK_GMAC_RX_SRC 132
+#define CLK_GMAC_RX_DIV2 133
+#define CLK_GMAC_RX_DIV20 134
+#define RMII_MODE_CLK 135
+#define CLK_GMAC_TX_RX 136
+#define CLK_GMAC_PTPREF 137
+#define CLK_GMAC_ETHERNET_OUT 138
+#define CLK_DDRPHY 139
+#define CLK_DDR_MON 140
+#define TMCLK_DDR_MON 141
+#define CLK_NPU_DIV 142
+#define CLK_NPU_NP5 143
+#define CLK_CORE_NPU 144
+#define CLK_CORE_NPUPVTM 145
+#define CLK_NPUPVTM 146
+#define SCLK_DDRCLK 147
+#define CLK_OTP 148
+
+/* dclk */
+#define DCLK_DECOM 150
+#define DCLK_VOP_DIV 151
+#define DCLK_VOP_FRACDIV 152
+#define DCLK_VOP_MUX 153
+#define DCLK_VOP 154
+#define DCLK_CIF 155
+#define DCLK_CIFLITE 156
+
+/* aclk */
+#define ACLK_PDBUS 160
+#define ACLK_DMAC 161
+#define ACLK_DCF 162
+#define ACLK_SPINLOCK 163
+#define ACLK_DECOM 164
+#define ACLK_PDCRYPTO 165
+#define ACLK_CRYPTO 166
+#define ACLK_PDVEPU 167
+#define ACLK_VENC 168
+#define ACLK_PDVDEC 169
+#define ACLK_PDJPEG 170
+#define ACLK_VDEC 171
+#define ACLK_JPEG 172
+#define ACLK_PDVO 173
+#define ACLK_RGA 174
+#define ACLK_VOP 175
+#define ACLK_IEP 176
+#define ACLK_PDVI_DIV 177
+#define ACLK_PDVI_NP5 178
+#define ACLK_PDVI 179
+#define ACLK_ISP 180
+#define ACLK_CIF 181
+#define ACLK_CIFLITE 182
+#define ACLK_PDISPP_DIV 183
+#define ACLK_PDISPP_NP5 184
+#define ACLK_PDISPP 185
+#define ACLK_ISPP 186
+#define ACLK_PDPHP 187
+#define ACLK_PDUSB 188
+#define ACLK_USBOTG 189
+#define ACLK_PDGMAC 190
+#define ACLK_GMAC 191
+#define ACLK_PDNPU_DIV 192
+#define ACLK_PDNPU_NP5 193
+#define ACLK_PDNPU 194
+#define ACLK_NPU 195
+
+/* hclk */
+#define HCLK_PDCORE_NIU 200
+#define HCLK_PDUSB 201
+#define HCLK_PDCRYPTO 202
+#define HCLK_CRYPTO 203
+#define HCLK_PDAUDIO 204
+#define HCLK_I2S0 205
+#define HCLK_I2S1 206
+#define HCLK_I2S2 207
+#define HCLK_PDM 208
+#define HCLK_AUDPWM 209
+#define HCLK_PDVEPU 210
+#define HCLK_VENC 211
+#define HCLK_PDVDEC 212
+#define HCLK_PDJPEG 213
+#define HCLK_VDEC 214
+#define HCLK_JPEG 215
+#define HCLK_PDVO 216
+#define HCLK_RGA 217
+#define HCLK_VOP 218
+#define HCLK_IEP 219
+#define HCLK_PDVI 220
+#define HCLK_ISP 221
+#define HCLK_CIF 222
+#define HCLK_CIFLITE 223
+#define HCLK_PDISPP 224
+#define HCLK_ISPP 225
+#define HCLK_PDPHP 226
+#define HCLK_PDSDMMC 227
+#define HCLK_SDMMC 228
+#define HCLK_PDSDIO 229
+#define HCLK_SDIO 230
+#define HCLK_PDNVM 231
+#define HCLK_EMMC 232
+#define HCLK_NANDC 233
+#define HCLK_SFC 234
+#define HCLK_SFCXIP 235
+#define HCLK_PDBUS 236
+#define HCLK_USBHOST 237
+#define HCLK_USBHOST_ARB 238
+#define HCLK_PDNPU 239
+#define HCLK_NPU 240
+
+/* pclk */
+#define PCLK_CPUPVTM 245
+#define PCLK_PDBUS 246
+#define PCLK_DCF 247
+#define PCLK_WDT 248
+#define PCLK_MAILBOX 249
+#define PCLK_UART0 250
+#define PCLK_UART2 251
+#define PCLK_UART3 252
+#define PCLK_UART4 253
+#define PCLK_UART5 254
+#define PCLK_I2C1 255
+#define PCLK_I2C3 256
+#define PCLK_I2C4 257
+#define PCLK_I2C5 258
+#define PCLK_SPI1 259
+#define PCLK_PWM2 261
+#define PCLK_GPIO1 262
+#define PCLK_GPIO2 263
+#define PCLK_GPIO3 264
+#define PCLK_GPIO4 265
+#define PCLK_SARADC 266
+#define PCLK_TIMER 267
+#define PCLK_DECOM 268
+#define PCLK_CAN 269
+#define PCLK_NPU_TSADC 270
+#define PCLK_CPU_TSADC 271
+#define PCLK_ACDCDIG 272
+#define PCLK_PDVO 273
+#define PCLK_DSIHOST 274
+#define PCLK_PDVI 275
+#define PCLK_CSIHOST 276
+#define PCLK_PDGMAC 277
+#define PCLK_GMAC 278
+#define PCLK_PDDDR 279
+#define PCLK_DDR_MON 280
+#define PCLK_PDNPU 281
+#define PCLK_NPUPVTM 282
+#define PCLK_PDTOP 283
+#define PCLK_TOPCRU 284
+#define PCLK_TOPGRF 285
+#define PCLK_CPUEMADET 286
+#define PCLK_DDRPHY 287
+#define PCLK_DSIPHY 289
+#define PCLK_CSIPHY0 290
+#define PCLK_CSIPHY1 291
+#define PCLK_USBPHY_HOST 292
+#define PCLK_USBPHY_OTG 293
+#define PCLK_OTP 294
+
+#define CLK_NR_CLKS (PCLK_OTP + 1)
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_PDPMU_NIU_P 0
+#define SRST_PMU_SGRF_P 1
+#define SRST_PMU_SGRF_REMAP_P 2
+#define SRST_I2C0_P 3
+#define SRST_I2C0 4
+#define SRST_I2C2_P 7
+#define SRST_I2C2 8
+#define SRST_UART1_P 9
+#define SRST_UART1 10
+#define SRST_PWM0_P 11
+#define SRST_PWM0 12
+#define SRST_PWM1_P 13
+#define SRST_PWM1 14
+#define SRST_DDR_FAIL_SAFE 15
+
+/* pmu_cru_softrst_con1 */
+#define SRST_GPIO0_P 17
+#define SRST_GPIO0_DB 18
+#define SRST_SPI0_P 19
+#define SRST_SPI0 20
+#define SRST_PMUGRF_P 21
+#define SRST_CHIPVEROTP_P 22
+#define SRST_PMUPVTM 24
+#define SRST_PMUPVTM_P 25
+#define SRST_PMUCRU_P 30
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_NL2 12
+#define SRST_CORE_NIU_A 13
+#define SRST_DBG_DAPLITE_P 14
+#define SRST_DAPLITE_P 15
+
+/* cru_softrst_con1 */
+#define SRST_PDBUS_NIU1_A 16
+#define SRST_PDBUS_NIU1_H 17
+#define SRST_PDBUS_NIU1_P 18
+#define SRST_PDBUS_NIU2_A 19
+#define SRST_PDBUS_NIU2_H 20
+#define SRST_PDBUS_NIU3_A 21
+#define SRST_PDBUS_NIU3_H 22
+#define SRST_PDBUS_HOLD_NIU1_A 23
+#define SRST_DBG_NIU_P 24
+#define SRST_PDCORE_NIIU_H 25
+#define SRST_MUC_NIU 26
+#define SRST_DCF_A 29
+#define SRST_DCF_P 30
+#define SRST_SYSTEM_SRAM_A 31
+
+/* cru_softrst_con2 */
+#define SRST_I2C1_P 32
+#define SRST_I2C1 33
+#define SRST_I2C3_P 34
+#define SRST_I2C3 35
+#define SRST_I2C4_P 36
+#define SRST_I2C4 37
+#define SRST_I2C5_P 38
+#define SRST_I2C5 39
+#define SRST_SPI1_P 40
+#define SRST_SPI1 41
+#define SRST_MCU_CORE 42
+#define SRST_PWM2_P 44
+#define SRST_PWM2 45
+#define SRST_SPINLOCK_A 46
+
+/* cru_softrst_con3 */
+#define SRST_UART0_P 48
+#define SRST_UART0 49
+#define SRST_UART2_P 50
+#define SRST_UART2 51
+#define SRST_UART3_P 52
+#define SRST_UART3 53
+#define SRST_UART4_P 54
+#define SRST_UART4 55
+#define SRST_UART5_P 56
+#define SRST_UART5 57
+#define SRST_WDT_P 58
+#define SRST_SARADC_P 59
+#define SRST_GRF_P 61
+#define SRST_TIMER_P 62
+#define SRST_MAILBOX_P 63
+
+/* cru_softrst_con4 */
+#define SRST_TIMER0 64
+#define SRST_TIMER1 65
+#define SRST_TIMER2 66
+#define SRST_TIMER3 67
+#define SRST_TIMER4 68
+#define SRST_TIMER5 69
+#define SRST_INTMUX_P 70
+#define SRST_GPIO1_P 72
+#define SRST_GPIO1_DB 73
+#define SRST_GPIO2_P 74
+#define SRST_GPIO2_DB 75
+#define SRST_GPIO3_P 76
+#define SRST_GPIO3_DB 77
+#define SRST_GPIO4_P 78
+#define SRST_GPIO4_DB 79
+
+/* cru_softrst_con5 */
+#define SRST_CAN_P 80
+#define SRST_CAN 81
+#define SRST_DECOM_A 85
+#define SRST_DECOM_P 86
+#define SRST_DECOM_D 87
+#define SRST_PDCRYPTO_NIU_A 88
+#define SRST_PDCRYPTO_NIU_H 89
+#define SRST_CRYPTO_A 90
+#define SRST_CRYPTO_H 91
+#define SRST_CRYPTO_CORE 92
+#define SRST_CRYPTO_PKA 93
+#define SRST_SGRF_P 95
+
+/* cru_softrst_con6 */
+#define SRST_PDAUDIO_NIU_H 96
+#define SRST_PDAUDIO_NIU_P 97
+#define SRST_I2S0_H 98
+#define SRST_I2S0_TX_M 99
+#define SRST_I2S0_RX_M 100
+#define SRST_I2S1_H 101
+#define SRST_I2S1_M 102
+#define SRST_I2S2_H 103
+#define SRST_I2S2_M 104
+#define SRST_PDM_H 105
+#define SRST_PDM_M 106
+#define SRST_AUDPWM_H 107
+#define SRST_AUDPWM 108
+#define SRST_ACDCDIG_P 109
+#define SRST_ACDCDIG 110
+
+/* cru_softrst_con7 */
+#define SRST_PDVEPU_NIU_A 112
+#define SRST_PDVEPU_NIU_H 113
+#define SRST_VENC_A 114
+#define SRST_VENC_H 115
+#define SRST_VENC_CORE 116
+#define SRST_PDVDEC_NIU_A 117
+#define SRST_PDVDEC_NIU_H 118
+#define SRST_VDEC_A 119
+#define SRST_VDEC_H 120
+#define SRST_VDEC_CORE 121
+#define SRST_VDEC_CA 122
+#define SRST_VDEC_HEVC_CA 123
+#define SRST_PDJPEG_NIU_A 124
+#define SRST_PDJPEG_NIU_H 125
+#define SRST_JPEG_A 126
+#define SRST_JPEG_H 127
+
+/* cru_softrst_con8 */
+#define SRST_PDVO_NIU_A 128
+#define SRST_PDVO_NIU_H 129
+#define SRST_PDVO_NIU_P 130
+#define SRST_RGA_A 131
+#define SRST_RGA_H 132
+#define SRST_RGA_CORE 133
+#define SRST_VOP_A 134
+#define SRST_VOP_H 135
+#define SRST_VOP_D 136
+#define SRST_TXBYTEHS_DSIHOST 137
+#define SRST_DSIHOST_P 138
+#define SRST_IEP_A 139
+#define SRST_IEP_H 140
+#define SRST_IEP_CORE 141
+#define SRST_ISP_RX_P 142
+
+/* cru_softrst_con9 */
+#define SRST_PDVI_NIU_A 144
+#define SRST_PDVI_NIU_H 145
+#define SRST_PDVI_NIU_P 146
+#define SRST_ISP 147
+#define SRST_CIF_A 148
+#define SRST_CIF_H 149
+#define SRST_CIF_D 150
+#define SRST_CIF_P 151
+#define SRST_CIF_I 152
+#define SRST_CIF_RX_P 153
+#define SRST_PDISPP_NIU_A 154
+#define SRST_PDISPP_NIU_H 155
+#define SRST_ISPP_A 156
+#define SRST_ISPP_H 157
+#define SRST_ISPP 158
+#define SRST_CSIHOST_P 159
+
+/* cru_softrst_con10 */
+#define SRST_PDPHPMID_NIU_A 160
+#define SRST_PDPHPMID_NIU_H 161
+#define SRST_PDNVM_NIU_H 163
+#define SRST_SDMMC_H 164
+#define SRST_SDIO_H 165
+#define SRST_EMMC_H 166
+#define SRST_SFC_H 167
+#define SRST_SFCXIP_H 168
+#define SRST_SFC 169
+#define SRST_NANDC_H 170
+#define SRST_NANDC 171
+#define SRST_PDSDMMC_H 173
+#define SRST_PDSDIO_H 174
+
+/* cru_softrst_con11 */
+#define SRST_PDUSB_NIU_A 176
+#define SRST_PDUSB_NIU_H 177
+#define SRST_USBHOST_H 178
+#define SRST_USBHOST_ARB_H 179
+#define SRST_USBHOST_UTMI 180
+#define SRST_USBOTG_A 181
+#define SRST_USBPHY_OTG_P 182
+#define SRST_USBPHY_HOST_P 183
+#define SRST_USBPHYPOR_OTG 184
+#define SRST_USBPHYPOR_HOST 185
+#define SRST_PDGMAC_NIU_A 188
+#define SRST_PDGMAC_NIU_P 189
+#define SRST_GMAC_A 190
+
+/* cru_softrst_con12 */
+#define SRST_DDR_DFICTL_P 193
+#define SRST_DDR_MON_P 194
+#define SRST_DDR_STANDBY_P 195
+#define SRST_DDR_GRF_P 196
+#define SRST_DDR_MSCH_P 197
+#define SRST_DDR_SPLIT_A 198
+#define SRST_DDR_MSCH 199
+#define SRST_DDR_DFICTL 202
+#define SRST_DDR_STANDBY 203
+#define SRST_NPUMCU_NIU 205
+#define SRST_DDRPHY_P 206
+#define SRST_DDRPHY 207
+
+/* cru_softrst_con13 */
+#define SRST_PDNPU_NIU_A 208
+#define SRST_PDNPU_NIU_H 209
+#define SRST_PDNPU_NIU_P 210
+#define SRST_NPU_A 211
+#define SRST_NPU_H 212
+#define SRST_NPU 213
+#define SRST_NPUPVTM_P 214
+#define SRST_NPUPVTM 215
+#define SRST_NPU_TSADC_P 216
+#define SRST_NPU_TSADC 217
+#define SRST_NPU_TSADCPHY 218
+#define SRST_CIFLITE_A 220
+#define SRST_CIFLITE_H 221
+#define SRST_CIFLITE_D 222
+#define SRST_CIFLITE_RX_P 223
+
+/* cru_softrst_con14 */
+#define SRST_TOPNIU_P 224
+#define SRST_TOPCRU_P 225
+#define SRST_TOPGRF_P 226
+#define SRST_CPUEMADET_P 227
+#define SRST_CSIPHY0_P 228
+#define SRST_CSIPHY1_P 229
+#define SRST_DSIPHY_P 230
+#define SRST_CPU_TSADC_P 232
+#define SRST_CPU_TSADC 233
+#define SRST_CPU_TSADCPHY 234
+#define SRST_CPUPVTM_P 235
+#define SRST_CPUPVTM 236
+
+#endif
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-clk, Michael Turquette, Stephen Boyd, Finley Xiao
Add clock controller support for RV1126 SoC.
Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
and CRU_PMU blocks.
This patch is trying to add minimal Clock-Architecture Diagram's
inferred from [1] authored by Finley Xiao.
[1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rv1126.c | 1107 ++++++++++++++++++++++++
drivers/clk/rockchip/clk.h | 19 +
include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++++++
5 files changed, 1766 insertions(+)
create mode 100644 drivers/clk/rockchip/clk-rv1126.c
create mode 100644 include/dt-bindings/clock/rv1126-cru.h
diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig
index 3067bdb6e119..345a5d2a457c 100644
--- a/drivers/clk/rockchip/Kconfig
+++ b/drivers/clk/rockchip/Kconfig
@@ -23,6 +23,13 @@ config CLK_RV110X
help
Build the driver for RV110x Clock Driver.
+config CLK_RV1126
+ bool "Rockchip RV1126 clock controller support"
+ depends on ARM || COMPILE_TEST
+ default y
+ help
+ Build the driver for RV1126 Clock Driver.
+
config CLK_RK3036
bool "Rockchip RK3036 clock controller support"
depends on ARM || COMPILE_TEST
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 2b78f1247372..e8543876c056 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -17,6 +17,7 @@ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-$(CONFIG_CLK_PX30) += clk-px30.o
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
+obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c
new file mode 100644
index 000000000000..40d8b635a00a
--- /dev/null
+++ b/drivers/clk/rockchip/clk-rv1126.c
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+#include <dt-bindings/clock/rv1126-cru.h>
+#include "clk.h"
+
+#define RV1126_GMAC_CON 0x460
+#define RV1126_GRF_IOFUNC_CON1 0x10264
+#define RV1126_GRF_SOC_STATUS0 0x10
+
+#define RV1126_FRAC_MAX_PRATE 1200000000
+#define RV1126_CSIOUT_FRAC_MAX_PRATE 300000000
+
+enum rv1126_pmu_plls {
+ gpll,
+};
+
+enum rv1126_plls {
+ apll, dpll, cpll, hpll,
+};
+
+static struct rockchip_pll_rate_table rv1126_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1584000000, 1, 132, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1560000000, 1, 130, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1536000000, 1, 128, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 126, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1488000000, 1, 124, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1464000000, 1, 122, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1440000000, 1, 120, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1392000000, 1, 116, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1368000000, 1, 114, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1344000000, 1, 112, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1320000000, 1, 110, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1272000000, 1, 106, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1248000000, 1, 104, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(984000000, 1, 82, 2, 1, 1, 0),
+ RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
+ RK3036_PLL_RATE(936000000, 1, 78, 2, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(900000000, 1, 75, 2, 1, 1, 0),
+ RK3036_PLL_RATE(888000000, 1, 74, 2, 1, 1, 0),
+ RK3036_PLL_RATE(864000000, 1, 72, 2, 1, 1, 0),
+ RK3036_PLL_RATE(840000000, 1, 70, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
+ RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0),
+ RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0),
+ RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0),
+ RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+#define RV1126_DIV_ACLK_CORE_MASK 0xf
+#define RV1126_DIV_ACLK_CORE_SHIFT 4
+#define RV1126_DIV_PCLK_DBG_MASK 0x7
+#define RV1126_DIV_PCLK_DBG_SHIFT 0
+
+#define RV1126_CLKSEL1(_aclk_core, _pclk_dbg) \
+{ \
+ .reg = RV1126_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE(_aclk_core, RV1126_DIV_ACLK_CORE_MASK, \
+ RV1126_DIV_ACLK_CORE_SHIFT) | \
+ HIWORD_UPDATE(_pclk_dbg, RV1126_DIV_PCLK_DBG_MASK, \
+ RV1126_DIV_PCLK_DBG_SHIFT), \
+}
+
+#define RV1126_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RV1126_CLKSEL1(_aclk_core, _pclk_dbg), \
+ }, \
+}
+
+static struct rockchip_cpuclk_rate_table rv1126_cpuclk_rates[] __initdata = {
+ RV1126_CPUCLK_RATE(1608000000, 1, 7),
+ RV1126_CPUCLK_RATE(1584000000, 1, 7),
+ RV1126_CPUCLK_RATE(1560000000, 1, 7),
+ RV1126_CPUCLK_RATE(1536000000, 1, 7),
+ RV1126_CPUCLK_RATE(1512000000, 1, 7),
+ RV1126_CPUCLK_RATE(1488000000, 1, 5),
+ RV1126_CPUCLK_RATE(1464000000, 1, 5),
+ RV1126_CPUCLK_RATE(1440000000, 1, 5),
+ RV1126_CPUCLK_RATE(1416000000, 1, 5),
+ RV1126_CPUCLK_RATE(1392000000, 1, 5),
+ RV1126_CPUCLK_RATE(1368000000, 1, 5),
+ RV1126_CPUCLK_RATE(1344000000, 1, 5),
+ RV1126_CPUCLK_RATE(1320000000, 1, 5),
+ RV1126_CPUCLK_RATE(1296000000, 1, 5),
+ RV1126_CPUCLK_RATE(1272000000, 1, 5),
+ RV1126_CPUCLK_RATE(1248000000, 1, 5),
+ RV1126_CPUCLK_RATE(1224000000, 1, 5),
+ RV1126_CPUCLK_RATE(1200000000, 1, 5),
+ RV1126_CPUCLK_RATE(1104000000, 1, 5),
+ RV1126_CPUCLK_RATE(1008000000, 1, 5),
+ RV1126_CPUCLK_RATE(912000000, 1, 5),
+ RV1126_CPUCLK_RATE(816000000, 1, 3),
+ RV1126_CPUCLK_RATE(696000000, 1, 3),
+ RV1126_CPUCLK_RATE(600000000, 1, 3),
+ RV1126_CPUCLK_RATE(408000000, 1, 1),
+ RV1126_CPUCLK_RATE(312000000, 1, 1),
+ RV1126_CPUCLK_RATE(216000000, 1, 1),
+ RV1126_CPUCLK_RATE(96000000, 1, 1),
+};
+
+static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = {
+ .core_reg[0] = RV1126_CLKSEL_CON(0),
+ .div_core_shift[0] = 0,
+ .div_core_mask[0] = 0x1f,
+ .num_cores = 1,
+ .mux_core_alt = 0,
+ .mux_core_main = 2,
+ .mux_core_shift = 6,
+ .mux_core_mask = 0x3,
+};
+
+PNAME(mux_pll_p) = { "xin24m" };
+PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
+PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
+PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
+PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
+PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
+PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
+PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
+PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
+PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
+PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
+PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
+PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
+PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
+PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
+PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
+PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
+PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
+PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
+PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
+PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
+PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
+PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
+PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
+PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
+PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
+PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
+PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
+PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
+PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
+PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
+PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
+PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
+PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
+PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
+PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
+PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
+PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
+PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
+PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
+PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
+PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
+PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
+PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
+PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
+PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
+PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
+PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
+PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
+PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
+PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
+PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
+PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
+PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
+PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
+
+static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 };
+
+static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = {
+ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
+ 0, RV1126_PMU_PLL_CON(0),
+ RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates),
+};
+
+static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = {
+ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
+ 0, RV1126_PLL_CON(0),
+ RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates),
+ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
+ 0, RV1126_PLL_CON(8),
+ RV1126_MODE_CON, 2, 1, 0, NULL),
+ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
+ 0, RV1126_PLL_CON(16),
+ RV1126_MODE_CON, 4, 2, 0, rv1126_pll_rates),
+ [hpll] = PLL(pll_rk3328, PLL_HPLL, "hpll", mux_pll_p,
+ 0, RV1126_PLL_CON(24),
+ RV1126_MODE_CON, 6, 4, 0, rv1126_pll_rates),
+};
+
+#define MFLAGS CLK_MUX_HIWORD_MASK
+#define DFLAGS CLK_DIVIDER_HIWORD_MASK
+#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
+
+static struct rockchip_clk_branch rv1126_rtc32k_fracmux __initdata =
+ MUX(CLK_RTC32K, "clk_rtc32k", mux_rtc32k_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(0), 7, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart1_fracmux __initdata =
+ MUX(SCLK_UART1_MUX, "sclk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(4), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart0_fracmux __initdata =
+ MUX(SCLK_UART0_MUX, "sclk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(10), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart2_fracmux __initdata =
+ MUX(SCLK_UART2_MUX, "sclk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(12), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart3_fracmux __initdata =
+ MUX(SCLK_UART3_MUX, "sclk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(14), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart4_fracmux __initdata =
+ MUX(SCLK_UART4_MUX, "sclk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(16), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_uart5_fracmux __initdata =
+ MUX(SCLK_UART5_MUX, "sclk_uart5_mux", mux_uart5_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(18), 10, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s0_tx_fracmux __initdata =
+ MUX(MCLK_I2S0_TX_MUX, "mclk_i2s0_tx_mux", mux_i2s0_tx_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(30), 0, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s0_rx_fracmux __initdata =
+ MUX(MCLK_I2S0_RX_MUX, "mclk_i2s0_rx_mux", mux_i2s0_rx_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(30), 2, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s1_fracmux __initdata =
+ MUX(MCLK_I2S1_MUX, "mclk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(31), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_i2s2_fracmux __initdata =
+ MUX(MCLK_I2S2_MUX, "mclk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(33), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
+ MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
+
+static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 2
+ */
+ /* PD_PMU */
+ COMPOSITE_NOMUX(PCLK_PDPMU, "pclk_pdpmu", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKSEL_CON(1), 0, 5, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 0, GFLAGS),
+
+ COMPOSITE_FRACMUX(CLK_OSC0_DIV32K, "clk_osc0_div32k", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKSEL_CON(13), 0,
+ RV1126_PMU_CLKGATE_CON(2), 9, GFLAGS,
+ &rv1126_rtc32k_fracmux),
+
+ COMPOSITE_NOMUX(CLK_WIFI_DIV, "clk_wifi_div", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(12), 0, 6, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(2), 10, GFLAGS),
+ GATE(CLK_WIFI_OSC0, "clk_wifi_osc0", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 11, GFLAGS),
+ MUX(CLK_WIFI, "clk_wifi", mux_wifi_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(12), 8, 1, MFLAGS),
+
+ GATE(PCLK_PMU, "pclk_pmu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 1, GFLAGS),
+
+ GATE(PCLK_UART1, "pclk_uart1", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE(SCLK_UART1_DIV, "sclk_uart1_div", mux_gpll_usb480m_cpll_xin24m_p, 0,
+ RV1126_PMU_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 12, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART1_FRACDIV, "sclk_uart1_fracdiv", "sclk_uart1_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(5), 0,
+ RV1126_PMU_CLKGATE_CON(0), 13, GFLAGS,
+ &rv1126_uart1_fracmux),
+ GATE(SCLK_UART1, "sclk_uart1", "sclk_uart1_mux", 0,
+ RV1126_PMU_CLKGATE_CON(0), 14, GFLAGS),
+
+ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 5, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C0, "clk_i2c0", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 9, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C2, "clk_i2c2", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(0), 10, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 2, GFLAGS),
+ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 0, GFLAGS),
+ COMPOSITE(CLK_PWM0, "clk_pwm0", mux_xin24m_gpll_p, 0,
+ RV1126_PMU_CLKSEL_CON(6), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 1, GFLAGS),
+ GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 5, GFLAGS),
+ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 3, GFLAGS),
+ COMPOSITE(CLK_PWM1, "clk_pwm1", mux_xin24m_gpll_p, 0,
+ RV1126_PMU_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 4, GFLAGS),
+
+ GATE(PCLK_SPI0, "pclk_spi0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 11, GFLAGS),
+ COMPOSITE(CLK_SPI0, "clk_spi0", mux_gpll_xin24m_p, 0,
+ RV1126_PMU_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 12, GFLAGS),
+
+ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(1), 9, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_xin24m_32k_p, 0,
+ RV1126_PMU_CLKSEL_CON(8), 15, 1, MFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 10, GFLAGS),
+
+ GATE(PCLK_PMUPVTM, "pclk_pmupvtm", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(2), 6, GFLAGS),
+ GATE(CLK_PMUPVTM, "clk_pmupvtm", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(CLK_CORE_PMUPVTM, "clk_core_pmupvtm", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(2), 7, GFLAGS),
+
+ COMPOSITE_NOMUX(CLK_REF12M, "clk_ref12m", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(7), 8, 7, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 15, GFLAGS),
+ GATE(0, "xin_osc0_usbphyref_otg", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 6, GFLAGS),
+ GATE(0, "xin_osc0_usbphyref_host", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 7, GFLAGS),
+ FACTOR(0, "xin_osc0_div2_usbphyref_otg", "xin_osc0_usbphyref_otg", 0, 1, 2),
+ FACTOR(0, "xin_osc0_div2_usbphyref_host", "xin_osc0_usbphyref_host", 0, 1, 2),
+ MUX(CLK_USBPHY_OTG_REF, "clk_usbphy_otg_ref", mux_usbphy_otg_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 6, 1, MFLAGS),
+ MUX(CLK_USBPHY_HOST_REF, "clk_usbphy_host_ref", mux_usbphy_host_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 7, 1, MFLAGS),
+
+ COMPOSITE_NOMUX(CLK_REF24M, "clk_ref24m", "gpll", 0,
+ RV1126_PMU_CLKSEL_CON(7), 0, 6, DFLAGS,
+ RV1126_PMU_CLKGATE_CON(1), 14, GFLAGS),
+ GATE(0, "xin_osc0_mipiphyref", "xin24m", 0,
+ RV1126_PMU_CLKGATE_CON(1), 8, GFLAGS),
+ MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT,
+ RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS),
+
+ GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS),
+
+ GATE(PCLK_PMUSGRF, "pclk_pmusgrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 4, GFLAGS),
+ GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(1), 13, GFLAGS),
+ GATE(PCLK_PMUCRU, "pclk_pmucru", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(PCLK_CHIPVEROTP, "pclk_chipverotp", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(PCLK_PDPMU_NIU, "pclk_pdpmu_niu", "pclk_pdpmu", CLK_IGNORE_UNUSED,
+ RV1126_PMU_CLKGATE_CON(0), 2, GFLAGS),
+
+ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pdpmu", 0,
+ RV1126_PMU_CLKGATE_CON(0), 7, GFLAGS),
+};
+
+static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
+ /*
+ * Clock-Architecture Diagram 1
+ */
+ MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
+ RV1126_MODE_CON, 10, 2, MFLAGS),
+ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "pclk_dbg", "armclk", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RV1126_CLKGATE_CON(0), 6, GFLAGS),
+ GATE(CLK_CORE_CPUPVTM, "clk_core_cpupvtm", "armclk", 0,
+ RV1126_CLKGATE_CON(0), 12, GFLAGS),
+ GATE(PCLK_CPUPVTM, "pclk_cpupvtm", "pclk_dbg", 0,
+ RV1126_CLKGATE_CON(0), 10, GFLAGS),
+ GATE(CLK_CPUPVTM, "clk_cpupvtm", "xin24m", 0,
+ RV1126_CLKGATE_CON(0), 11, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDCORE_NIU, "hclk_pdcore_niu", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(0), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(0), 8, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ /* PD_BUS */
+ COMPOSITE(0, "aclk_pdbus_pre", mux_gpll_cpll_dpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(2), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 0, GFLAGS),
+ GATE(ACLK_PDBUS, "aclk_pdbus", "aclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 11, GFLAGS),
+ COMPOSITE(0, "hclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(2), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 1, GFLAGS),
+ GATE(HCLK_PDBUS, "hclk_pdbus", "hclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 12, GFLAGS),
+ COMPOSITE(0, "pclk_pdbus_pre", mux_hclk_pclk_pdbus_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(2), 2, GFLAGS),
+ GATE(PCLK_PDBUS, "pclk_pdbus", "pclk_pdbus_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 13, GFLAGS),
+ /* aclk_dmac is controlled by sgrf_clkgat_con. */
+ SGRF_GATE(ACLK_DMAC, "aclk_dmac", "hclk_pdbus"),
+ GATE(ACLK_DCF, "aclk_dcf", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 6, GFLAGS),
+ GATE(PCLK_DCF, "pclk_dcf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 7, GFLAGS),
+ GATE(PCLK_WDT, "pclk_wdt", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 14, GFLAGS),
+ GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 10, GFLAGS),
+
+ COMPOSITE(CLK_SCR1, "clk_scr1", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(3), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(4), 7, GFLAGS),
+ GATE(0, "clk_scr1_niu", "clk_scr1", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 14, GFLAGS),
+ GATE(CLK_SCR1_CORE, "clk_scr1_core", "clk_scr1", 0,
+ RV1126_CLKGATE_CON(4), 8, GFLAGS),
+ GATE(CLK_SCR1_RTC, "clk_scr1_rtc", "xin24m", 0,
+ RV1126_CLKGATE_CON(4), 9, GFLAGS),
+ GATE(CLK_SCR1_JTAG, "clk_scr1_jtag", "clk_scr1_jtag_io", 0,
+ RV1126_CLKGATE_CON(4), 10, GFLAGS),
+
+ GATE(PCLK_UART0, "pclk_uart0", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 0, GFLAGS),
+ COMPOSITE(SCLK_UART0_DIV, "sclk_uart0_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(10), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 1, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART0_FRAC, "sclk_uart0_frac", "sclk_uart0_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(11), 0,
+ RV1126_CLKGATE_CON(5), 2, GFLAGS,
+ &rv1126_uart0_fracmux),
+ GATE(SCLK_UART0, "sclk_uart0", "sclk_uart0_mux", 0,
+ RV1126_CLKGATE_CON(5), 3, GFLAGS),
+ GATE(PCLK_UART2, "pclk_uart2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 4, GFLAGS),
+ COMPOSITE(SCLK_UART2_DIV, "sclk_uart2_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(12), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 5, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART2_FRAC, "sclk_uart2_frac", "sclk_uart2_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(13), 0,
+ RV1126_CLKGATE_CON(5), 6, GFLAGS,
+ &rv1126_uart2_fracmux),
+ GATE(SCLK_UART2, "sclk_uart2", "sclk_uart2_mux", 0,
+ RV1126_CLKGATE_CON(5), 7, GFLAGS),
+ GATE(PCLK_UART3, "pclk_uart3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 8, GFLAGS),
+ COMPOSITE(SCLK_UART3_DIV, "sclk_uart3_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(14), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(5), 9, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART3_FRAC, "sclk_uart3_frac", "sclk_uart3_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(15), 0,
+ RV1126_CLKGATE_CON(5), 10, GFLAGS,
+ &rv1126_uart3_fracmux),
+ GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
+ RV1126_CLKGATE_CON(5), 11, GFLAGS),
+ GATE(PCLK_UART4, "pclk_uart4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(5), 12, GFLAGS),
+ COMPOSITE(SCLK_UART4_DIV, "sclk_uart4_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(16), 8, 2, MFLAGS, 0, 7,
+ DFLAGS, RV1126_CLKGATE_CON(5), 13, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART4_FRAC, "sclk_uart4_frac", "sclk_uart4_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(17), 0,
+ RV1126_CLKGATE_CON(5), 14, GFLAGS,
+ &rv1126_uart4_fracmux),
+ GATE(SCLK_UART4, "sclk_uart4", "sclk_uart4_mux", 0,
+ RV1126_CLKGATE_CON(5), 15, GFLAGS),
+ GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE(SCLK_UART5_DIV, "sclk_uart5_div", mux_gpll_cpll_usb480m_xin24m_p, 0,
+ RV1126_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7,
+ DFLAGS, RV1126_CLKGATE_CON(6), 1, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_UART5_FRAC, "sclk_uart5_frac", "sclk_uart5_div", CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(19), 0,
+ RV1126_CLKGATE_CON(6), 2, GFLAGS,
+ &rv1126_uart5_fracmux),
+ GATE(SCLK_UART5, "sclk_uart5", "sclk_uart5_mux", 0,
+ RV1126_CLKGATE_CON(6), 3, GFLAGS),
+
+ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 10, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C1, "clk_i2c1", "gpll", 0,
+ RV1126_CLKSEL_CON(5), 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 11, GFLAGS),
+ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 12, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C3, "clk_i2c3", "gpll", 0,
+ RV1126_CLKSEL_CON(5), 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 13, GFLAGS),
+ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(3), 14, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C4, "clk_i2c4", "gpll", 0,
+ RV1126_CLKSEL_CON(6), 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(3), 15, GFLAGS),
+ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_I2C5, "clk_i2c5", "gpll", 0,
+ RV1126_CLKSEL_CON(6), 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 1, GFLAGS),
+
+ GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 2, GFLAGS),
+ COMPOSITE(CLK_SPI1, "clk_spi1", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 3, GFLAGS),
+
+ GATE(CLK_CAPTURE_PWM2, "clk_capture_pwm2", "xin24m", 0,
+ RV1126_CLKGATE_CON(4), 6, GFLAGS),
+ GATE(PCLK_PWM2, "pclk_pwm2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(4), 4, GFLAGS),
+ COMPOSITE(CLK_PWM2, "clk_pwm2", mux_xin24m_gpll_p, 0,
+ RV1126_CLKSEL_CON(9), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(4), 5, GFLAGS),
+
+ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 0, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO1, "dbclk_gpio1", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(21), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 1, GFLAGS),
+ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 2, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(22), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 3, GFLAGS),
+ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 4, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(23), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 5, GFLAGS),
+ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 6, GFLAGS),
+ COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", mux_xin24m_32k_p, 0,
+ RV1126_CLKSEL_CON(24), 15, 1, MFLAGS,
+ RV1126_CLKGATE_CON(7), 7, GFLAGS),
+
+ GATE(PCLK_SARADC, "pclk_saradc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 4, GFLAGS),
+ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
+ RV1126_CLKSEL_CON(20), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(6), 5, GFLAGS),
+
+ GATE(PCLK_TIMER, "pclk_timer", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 7, GFLAGS),
+ GATE(CLK_TIMER0, "clk_timer0", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 8, GFLAGS),
+ GATE(CLK_TIMER1, "clk_timer1", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 9, GFLAGS),
+ GATE(CLK_TIMER2, "clk_timer2", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 10, GFLAGS),
+ GATE(CLK_TIMER3, "clk_timer3", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 11, GFLAGS),
+ GATE(CLK_TIMER4, "clk_timer4", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 12, GFLAGS),
+ GATE(CLK_TIMER5, "clk_timer5", "xin24m", 0,
+ RV1126_CLKGATE_CON(6), 13, GFLAGS),
+
+ GATE(ACLK_SPINLOCK, "aclk_spinlock", "hclk_pdbus", 0,
+ RV1126_CLKGATE_CON(6), 6, GFLAGS),
+
+ GATE(ACLK_DECOM, "aclk_decom", "aclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 11, GFLAGS),
+ GATE(PCLK_DECOM, "pclk_decom", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 12, GFLAGS),
+ COMPOSITE(DCLK_DECOM, "dclk_decom", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(7), 13, GFLAGS),
+
+ GATE(PCLK_CAN, "pclk_can", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(7), 8, GFLAGS),
+ COMPOSITE(CLK_CAN, "clk_can", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(7), 9, GFLAGS),
+ /* pclk_otp and clk_otp are controlled by sgrf_clkgat_con. */
+ SGRF_GATE(CLK_OTP, "clk_otp", "xin24m"),
+ SGRF_GATE(PCLK_OTP, "pclk_otp", "pclk_pdbus"),
+
+ GATE(PCLK_NPU_TSADC, "pclk_npu_tsadc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(24), 3, GFLAGS),
+ COMPOSITE_NOMUX(CLK_NPU_TSADC, "clk_npu_tsadc", "xin24m", 0,
+ RV1126_CLKSEL_CON(71), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(24), 4, GFLAGS),
+ GATE(CLK_NPU_TSADCPHY, "clk_npu_tsadcphy", "clk_npu_tsadc", 0,
+ RV1126_CLKGATE_CON(24), 5, GFLAGS),
+ GATE(PCLK_CPU_TSADC, "pclk_cpu_tsadc", "pclk_pdbus", 0,
+ RV1126_CLKGATE_CON(24), 0, GFLAGS),
+ COMPOSITE_NOMUX(CLK_CPU_TSADC, "clk_cpu_tsadc", "xin24m", 0,
+ RV1126_CLKSEL_CON(70), 0, 11, DFLAGS,
+ RV1126_CLKGATE_CON(24), 1, GFLAGS),
+ GATE(CLK_CPU_TSADCPHY, "clk_cpu_tsadcphy", "clk_cpu_tsadc", 0,
+ RV1126_CLKGATE_CON(24), 2, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+ /* PD_AUDIO */
+ COMPOSITE_NOMUX(HCLK_PDAUDIO, "hclk_pdaudio", "gpll", 0,
+ RV1126_CLKSEL_CON(26), 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(9), 0, GFLAGS),
+
+ GATE(HCLK_I2S0, "hclk_i2s0", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(9), 4, GFLAGS),
+ COMPOSITE(MCLK_I2S0_TX_DIV, "mclk_i2s0_tx_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(27), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(9), 5, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S0_TX_FRACDIV, "mclk_i2s0_tx_fracdiv", "mclk_i2s0_tx_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(28), 0,
+ RV1126_CLKGATE_CON(9), 6, GFLAGS,
+ &rv1126_i2s0_tx_fracmux),
+ GATE(MCLK_I2S0_TX, "mclk_i2s0_tx", "mclk_i2s0_tx_mux", 0,
+ RV1126_CLKGATE_CON(9), 9, GFLAGS),
+ COMPOSITE(MCLK_I2S0_RX_DIV, "mclk_i2s0_rx_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RV1126_CLKGATE_CON(9), 7, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S0_RX_FRACDIV, "mclk_i2s0_rx_fracdiv", "mclk_i2s0_rx_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(29), 0,
+ RV1126_CLKGATE_CON(9), 8, GFLAGS,
+ &rv1126_i2s0_rx_fracmux),
+ GATE(MCLK_I2S0_RX, "mclk_i2s0_rx", "mclk_i2s0_rx_mux", 0,
+ RV1126_CLKGATE_CON(9), 10, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S0_TX_OUT2IO, "mclk_i2s0_tx_out2io", mux_i2s0_tx_out2io_p, 0,
+ RV1126_CLKSEL_CON(30), 6, 1, MFLAGS,
+ RV1126_CLKGATE_CON(9), 13, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S0_RX_OUT2IO, "mclk_i2s0_rx_out2io", mux_i2s0_rx_out2io_p, 0,
+ RV1126_CLKSEL_CON(30), 8, 1, MFLAGS,
+ RV1126_CLKGATE_CON(9), 14, GFLAGS),
+
+ GATE(HCLK_I2S1, "hclk_i2s1", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 0, GFLAGS),
+ COMPOSITE(MCLK_I2S1_DIV, "mclk_i2s1_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 1, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S1_FRACDIV, "mclk_i2s1_fracdiv", "mclk_i2s1_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(32), 0,
+ RV1126_CLKGATE_CON(10), 2, GFLAGS,
+ &rv1126_i2s1_fracmux),
+ GATE(MCLK_I2S1, "mclk_i2s1", "mclk_i2s1_mux", 0,
+ RV1126_CLKGATE_CON(10), 3, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S1_OUT2IO, "mclk_i2s1_out2io", mux_i2s1_out2io_p, 0,
+ RV1126_CLKSEL_CON(31), 12, 1, MFLAGS,
+ RV1126_CLKGATE_CON(10), 4, GFLAGS),
+ GATE(HCLK_I2S2, "hclk_i2s2", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 5, GFLAGS),
+ COMPOSITE(MCLK_I2S2_DIV, "mclk_i2s2_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(33), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 6, GFLAGS),
+ COMPOSITE_FRACMUX(MCLK_I2S2_FRACDIV, "mclk_i2s2_fracdiv", "mclk_i2s2_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(34), 0,
+ RV1126_CLKGATE_CON(10), 7, GFLAGS,
+ &rv1126_i2s2_fracmux),
+ GATE(MCLK_I2S2, "mclk_i2s2", "mclk_i2s2_mux", 0,
+ RV1126_CLKGATE_CON(10), 8, GFLAGS),
+ COMPOSITE_NODIV(MCLK_I2S2_OUT2IO, "mclk_i2s2_out2io", mux_i2s2_out2io_p, 0,
+ RV1126_CLKSEL_CON(33), 10, 1, MFLAGS,
+ RV1126_CLKGATE_CON(10), 9, GFLAGS),
+
+ GATE(HCLK_PDM, "hclk_pdm", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 10, GFLAGS),
+ COMPOSITE(MCLK_PDM, "mclk_pdm", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(35), 8, 2, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 11, GFLAGS),
+
+ GATE(HCLK_AUDPWM, "hclk_audpwm", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(10), 12, GFLAGS),
+ COMPOSITE(SCLK_ADUPWM_DIV, "sclk_audpwm_div", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(10), 13, GFLAGS),
+ COMPOSITE_FRACMUX(SCLK_AUDPWM_FRACDIV, "sclk_audpwm_fracdiv", "sclk_audpwm_div",
+ CLK_SET_RATE_PARENT,
+ RV1126_CLKSEL_CON(37), 0,
+ RV1126_CLKGATE_CON(10), 14, GFLAGS,
+ &rv1126_audpwm_fracmux),
+ GATE(SCLK_AUDPWM, "sclk_audpwm", "mclk_audpwm_mux", 0,
+ RV1126_CLKGATE_CON(10), 15, GFLAGS),
+
+ GATE(PCLK_ACDCDIG, "pclk_acdcdig", "hclk_pdaudio", 0,
+ RV1126_CLKGATE_CON(11), 0, GFLAGS),
+ GATE(CLK_ACDCDIG_ADC, "clk_acdcdig_adc", "mclk_i2s0_rx", 0,
+ RV1126_CLKGATE_CON(11), 2, GFLAGS),
+ GATE(CLK_ACDCDIG_DAC, "clk_acdcdig_dac", "mclk_i2s0_tx", 0,
+ RV1126_CLKGATE_CON(11), 3, GFLAGS),
+ COMPOSITE(CLK_ACDCDIG_I2C, "clk_acdcdig_i2c", mux_gpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
+ RV1126_CLKGATE_CON(11), 1, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 12
+ */
+ /* PD_PHP */
+ COMPOSITE(ACLK_PDPHP, "aclk_pdphp", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(53), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(17), 0, GFLAGS),
+ COMPOSITE_NOMUX(HCLK_PDPHP, "hclk_pdphp", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(53), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(17), 1, GFLAGS),
+ /* PD_SDCARD */
+ GATE(HCLK_PDSDMMC, "hclk_pdsdmmc", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(17), 6, GFLAGS),
+ GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_pdsdmmc", 0,
+ RV1126_CLKGATE_CON(18), 4, GFLAGS),
+ COMPOSITE(CLK_SDMMC, "clk_sdmmc", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(55), 14, 2, MFLAGS, 0, 8,
+ DFLAGS, RV1126_CLKGATE_CON(18), 5, GFLAGS),
+ MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RV1126_SDMMC_CON0, 1),
+ MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RV1126_SDMMC_CON1, 1),
+
+ /* PD_SDIO */
+ GATE(HCLK_PDSDIO, "hclk_pdsdio", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(17), 8, GFLAGS),
+ GATE(HCLK_SDIO, "hclk_sdio", "hclk_pdsdio", 0,
+ RV1126_CLKGATE_CON(18), 6, GFLAGS),
+ COMPOSITE(CLK_SDIO, "clk_sdio", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(56), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 7, GFLAGS),
+ MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RV1126_SDIO_CON0, 1),
+ MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RV1126_SDIO_CON1, 1),
+
+ /* PD_NVM */
+ GATE(HCLK_PDNVM, "hclk_pdnvm", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(18), 1, GFLAGS),
+ GATE(HCLK_EMMC, "hclk_emmc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 8, GFLAGS),
+ COMPOSITE(CLK_EMMC, "clk_emmc", mux_gpll_cpll_xin24m_p, 0,
+ RV1126_CLKSEL_CON(57), 14, 2, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 9, GFLAGS),
+ GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 13, GFLAGS),
+ COMPOSITE(CLK_NANDC, "clk_nandc", mux_gpll_cpll_p, 0,
+ RV1126_CLKSEL_CON(59), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 14, GFLAGS),
+ GATE(HCLK_SFC, "hclk_sfc", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 10, GFLAGS),
+ GATE(HCLK_SFCXIP, "hclk_sfcxip", "hclk_pdnvm", 0,
+ RV1126_CLKGATE_CON(18), 11, GFLAGS),
+ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(58), 15, 1, MFLAGS, 0, 8, DFLAGS,
+ RV1126_CLKGATE_CON(18), 12, GFLAGS),
+ MMC(SCLK_EMMC_DRV, "emmc_drv", "clk_emmc", RV1126_EMMC_CON0, 1),
+ MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "clk_emmc", RV1126_EMMC_CON1, 1),
+
+ /* PD_USB */
+ GATE(ACLK_PDUSB, "aclk_pdusb", "aclk_pdphp", 0,
+ RV1126_CLKGATE_CON(19), 0, GFLAGS),
+ GATE(HCLK_PDUSB, "hclk_pdusb", "hclk_pdphp", 0,
+ RV1126_CLKGATE_CON(19), 1, GFLAGS),
+ GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 4, GFLAGS),
+ GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 5, GFLAGS),
+ COMPOSITE(CLK_USBHOST_UTMI_OHCI, "clk_usbhost_utmi_ohci", mux_usb480m_gpll_p, 0,
+ RV1126_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(19), 6, GFLAGS),
+ GATE(ACLK_USBOTG, "aclk_usbotg", "aclk_pdusb", 0,
+ RV1126_CLKGATE_CON(19), 7, GFLAGS),
+ GATE(CLK_USBOTG_REF, "clk_usbotg_ref", "xin24m", 0,
+ RV1126_CLKGATE_CON(19), 8, GFLAGS),
+ /* PD_GMAC */
+ GATE(ACLK_PDGMAC, "aclk_pdgmac", "aclk_pdphp", 0,
+ RV1126_CLKGATE_CON(20), 0, GFLAGS),
+ COMPOSITE_NOMUX(PCLK_PDGMAC, "pclk_pdgmac", "aclk_pdgmac", 0,
+ RV1126_CLKSEL_CON(63), 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 1, GFLAGS),
+ GATE(ACLK_GMAC, "aclk_gmac", "aclk_pdgmac", 0,
+ RV1126_CLKGATE_CON(20), 4, GFLAGS),
+ GATE(PCLK_GMAC, "pclk_gmac", "pclk_pdgmac", 0,
+ RV1126_CLKGATE_CON(20), 5, GFLAGS),
+
+ COMPOSITE(CLK_GMAC_DIV, "clk_gmac_div", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 6, GFLAGS),
+ GATE(CLK_GMAC_RGMII_M0, "clk_gmac_rgmii_m0", "clk_gmac_rgmii_clkin_m0", 0,
+ RV1126_CLKGATE_CON(20), 12, GFLAGS),
+ MUX(CLK_GMAC_SRC_M0, "clk_gmac_src_m0", clk_gmac_src_m0_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 0, 1, MFLAGS),
+ GATE(CLK_GMAC_RGMII_M1, "clk_gmac_rgmii_m1", "clk_gmac_rgmii_clkin_m1", 0,
+ RV1126_CLKGATE_CON(20), 13, GFLAGS),
+ MUX(CLK_GMAC_SRC_M1, "clk_gmac_src_m1", clk_gmac_src_m1_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 5, 1, MFLAGS),
+ MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+ RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
+
+ GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 7, GFLAGS),
+
+ GATE(CLK_GMAC_TX_SRC, "clk_gmac_tx_src", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 9, GFLAGS),
+ FACTOR(CLK_GMAC_TX_DIV5, "clk_gmac_tx_div5", "clk_gmac_tx_src", 0, 1, 5),
+ FACTOR(CLK_GMAC_TX_DIV50, "clk_gmac_tx_div50", "clk_gmac_tx_src", 0, 1, 50),
+ MUXTBL(RGMII_MODE_CLK, "rgmii_mode_clk", mux_rgmii_clk_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 2, 2, MFLAGS, rgmii_mux_idx),
+ GATE(CLK_GMAC_RX_SRC, "clk_gmac_rx_src", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 8, GFLAGS),
+ FACTOR(CLK_GMAC_RX_DIV2, "clk_gmac_rx_div2", "clk_gmac_rx_src", 0, 1, 2),
+ FACTOR(CLK_GMAC_RX_DIV20, "clk_gmac_rx_div20", "clk_gmac_rx_src", 0, 1, 20),
+ MUX(RMII_MODE_CLK, "rmii_mode_clk", mux_rmii_clk_p, CLK_SET_RATE_PARENT,
+ RV1126_GMAC_CON, 1, 1, MFLAGS),
+ MUX(CLK_GMAC_TX_RX, "clk_gmac_tx_rx", mux_gmac_tx_rx_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+ RV1126_GMAC_CON, 4, 1, MFLAGS),
+
+ GATE(CLK_GMAC_PTPREF, "clk_gmac_ptpref", "xin24m", 0,
+ RV1126_CLKGATE_CON(20), 10, GFLAGS),
+ COMPOSITE(CLK_GMAC_ETHERNET_OUT, "clk_gmac_ethernet_out2io", mux_cpll_gpll_p, 0,
+ RV1126_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(20), 11, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 15
+ */
+ GATE(PCLK_PDTOP, "pclk_pdtop", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 8, GFLAGS),
+ GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 4, GFLAGS),
+ GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 2, GFLAGS),
+ GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(23), 3, GFLAGS),
+ GATE(PCLK_USBPHY_HOST, "pclk_usbphy_host", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(19), 13, GFLAGS),
+ GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0,
+ RV1126_CLKGATE_CON(19), 12, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 3
+ */
+ /* PD_CORE */
+ COMPOSITE_NOMUX(0, "aclk_core", "armclk", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
+ RV1126_CLKGATE_CON(0), 2, GFLAGS),
+ GATE(0, "pclk_dbg_daplite", "pclk_dbg", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 5, GFLAGS),
+ GATE(0, "clk_a7_jtag", "clk_jtag_ori", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 9, GFLAGS),
+ GATE(0, "aclk_core_niu", "aclk_core", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 3, GFLAGS),
+ GATE(0, "pclk_dbg_niu", "pclk_dbg", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(0), 4, GFLAGS),
+ /*
+ * Clock-Architecture Diagram 4
+ */
+ /* PD_BUS */
+ GATE(0, "aclk_pdbus_hold_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 10, GFLAGS),
+ GATE(0, "aclk_pdbus_niu1", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 3, GFLAGS),
+ GATE(0, "hclk_pdbus_niu1", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 4, GFLAGS),
+ GATE(0, "pclk_pdbus_niu1", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 5, GFLAGS),
+ GATE(0, "aclk_pdbus_niu2", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 6, GFLAGS),
+ GATE(0, "hclk_pdbus_niu2", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 7, GFLAGS),
+ GATE(0, "aclk_pdbus_niu3", "aclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 8, GFLAGS),
+ GATE(0, "hclk_pdbus_niu3", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(2), 9, GFLAGS),
+ GATE(0, "pclk_grf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(6), 15, GFLAGS),
+ GATE(0, "pclk_sgrf", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(8), 4, GFLAGS),
+ GATE(0, "aclk_sysram", "hclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(3), 9, GFLAGS),
+ GATE(0, "pclk_intmux", "pclk_pdbus", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(7), 14, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 6
+ */
+ /* PD_AUDIO */
+ GATE(0, "hclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(9), 2, GFLAGS),
+ GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(9), 3, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 12
+ */
+ /* PD_PHP */
+ GATE(0, "aclk_pdphpmid", "aclk_pdphp", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 2, GFLAGS),
+ GATE(0, "hclk_pdphpmid", "hclk_pdphp", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 3, GFLAGS),
+ GATE(0, "aclk_pdphpmid_niu", "aclk_pdphpmid", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 4, GFLAGS),
+ GATE(0, "hclk_pdphpmid_niu", "hclk_pdphpmid", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 5, GFLAGS),
+
+ /* PD_SDCARD */
+ GATE(0, "hclk_pdsdmmc_niu", "hclk_pdsdmmc", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 7, GFLAGS),
+
+ /* PD_SDIO */
+ GATE(0, "hclk_pdsdio_niu", "hclk_pdsdio", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(17), 9, GFLAGS),
+
+ /* PD_NVM */
+ GATE(0, "hclk_pdnvm_niu", "hclk_pdnvm", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(18), 3, GFLAGS),
+
+ /* PD_USB */
+ GATE(0, "aclk_pdusb_niu", "aclk_pdusb", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(19), 2, GFLAGS),
+ GATE(0, "hclk_pdusb_niu", "hclk_pdusb", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(19), 3, GFLAGS),
+
+ /* PD_GMAC */
+ GATE(0, "aclk_pdgmac_niu", "aclk_pdgmac", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 2, GFLAGS),
+ GATE(0, "pclk_pdgmac_niu", "pclk_pdgmac", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 3, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 13
+ */
+ /* PD_DDR */
+ COMPOSITE_NOMUX(0, "pclk_pdddr_pre", "gpll", CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 0, 5, DFLAGS,
+ RV1126_CLKGATE_CON(21), 0, GFLAGS),
+ GATE(PCLK_PDDDR, "pclk_pdddr", "pclk_pdddr_pre", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 15, GFLAGS),
+ GATE(0, "pclk_ddr_msch", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 6, GFLAGS),
+ COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS |
+ CLK_DIVIDER_POWER_OF_TWO),
+ COMPOSITE(CLK_DDRPHY, "clk_ddrphy", mux_dpll_gpll_p, CLK_IGNORE_UNUSED,
+ RV1126_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RV1126_CLKGATE_CON(21), 8, GFLAGS),
+ GATE(0, "clk1x_phy", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 1, GFLAGS),
+ GATE(0, "clk_ddr_msch", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 10, GFLAGS),
+ GATE(0, "pclk_ddr_dfictl", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 2, GFLAGS),
+ GATE(0, "clk_ddr_dfictl", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 13, GFLAGS),
+ GATE(0, "pclk_ddr_standby", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 4, GFLAGS),
+ GATE(0, "clk_ddr_standby", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 14, GFLAGS),
+ GATE(0, "aclk_ddr_split", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 9, GFLAGS),
+ GATE(0, "pclk_ddr_grf", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 5, GFLAGS),
+ GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_pdddr", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 3, GFLAGS),
+ GATE(CLK_DDR_MON, "clk_ddr_mon", "clk_ddrphy", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(20), 15, GFLAGS),
+ GATE(TMCLK_DDR_MON, "tmclk_ddr_mon", "xin24m", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(21), 7, GFLAGS),
+
+ /*
+ * Clock-Architecture Diagram 15
+ */
+ GATE(0, "pclk_topniu", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 9, GFLAGS),
+ GATE(PCLK_TOPCRU, "pclk_topcru", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 10, GFLAGS),
+ GATE(PCLK_TOPGRF, "pclk_topgrf", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 11, GFLAGS),
+ GATE(PCLK_CPUEMADET, "pclk_cpuemadet", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 12, GFLAGS),
+ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_pdtop", CLK_IGNORE_UNUSED,
+ RV1126_CLKGATE_CON(23), 0, GFLAGS),
+};
+
+static const char *const rv1126_cru_critical_clocks[] __initconst = {
+ "gpll",
+ "cpll",
+ "hpll",
+ "armclk",
+ "pclk_dbg",
+ "pclk_pdpmu",
+ "aclk_pdbus",
+ "hclk_pdbus",
+ "pclk_pdbus",
+ "aclk_pdphp",
+ "hclk_pdphp",
+ "clk_ddrphy",
+ "pclk_pdddr",
+ "pclk_pdtop",
+ "clk_usbhost_utmi_ohci",
+ "aclk_pdjpeg_niu",
+ "hclk_pdjpeg_niu",
+ "aclk_pdvdec_niu",
+ "hclk_pdvdec_niu",
+};
+
+static void __init rv1126_pmu_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru pmu region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip pmu clk init failed\n", __func__);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126_pmu_pll_clks,
+ ARRAY_SIZE(rv1126_pmu_pll_clks),
+ RV1126_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_branches(ctx, rv1126_clk_pmu_branches,
+ ARRAY_SIZE(rv1126_clk_pmu_branches));
+
+ rockchip_register_softrst(np, 2, reg_base + RV1126_PMU_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1126_cru_pmu, "rockchip,rv1126-pmucru", rv1126_pmu_clk_init);
+
+static void __init rv1126_clk_init(struct device_node *np)
+{
+ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
+
+ rockchip_clk_register_plls(ctx, rv1126_pll_clks,
+ ARRAY_SIZE(rv1126_pll_clks),
+ RV1126_GRF_SOC_STATUS0);
+
+ rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
+ mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ &rv1126_cpuclk_data, rv1126_cpuclk_rates,
+ ARRAY_SIZE(rv1126_cpuclk_rates));
+
+ rockchip_clk_register_branches(ctx, rv1126_clk_branches,
+ ARRAY_SIZE(rv1126_clk_branches));
+
+ rockchip_register_softrst(np, 15, reg_base + RV1126_SOFTRST_CON(0),
+ ROCKCHIP_SOFTRST_HIWORD_MASK);
+
+ rockchip_register_restart_notifier(ctx, RV1126_GLB_SRST_FST, NULL);
+
+ rockchip_clk_protect_critical(rv1126_cru_critical_clocks,
+ ARRAY_SIZE(rv1126_cru_critical_clocks));
+
+ rockchip_clk_of_add_provider(np, ctx);
+}
+
+CLK_OF_DECLARE(rv1126_cru, "rockchip,rv1126-cru", rv1126_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 93937fb1d368..ee01739e4a7c 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -79,6 +79,25 @@ struct clk;
#define RV1108_EMMC_CON0 0x1e8
#define RV1108_EMMC_CON1 0x1ec
+#define RV1126_PMU_MODE 0x0
+#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
+#define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
+#define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
+#define RV1126_PLL_CON(x) ((x) * 0x4)
+#define RV1126_MODE_CON 0x90
+#define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
+#define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
+#define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
+#define RV1126_GLB_SRST_FST 0x408
+#define RV1126_GLB_SRST_SND 0x40c
+#define RV1126_SDMMC_CON0 0x440
+#define RV1126_SDMMC_CON1 0x444
+#define RV1126_SDIO_CON0 0x448
+#define RV1126_SDIO_CON1 0x44c
+#define RV1126_EMMC_CON0 0x450
+#define RV1126_EMMC_CON1 0x454
+
#define RK2928_PLL_CON(x) ((x) * 0x4)
#define RK2928_MODE_CON 0x40
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
diff --git a/include/dt-bindings/clock/rv1126-cru.h b/include/dt-bindings/clock/rv1126-cru.h
new file mode 100644
index 000000000000..cfba8226ded2
--- /dev/null
+++ b/include/dt-bindings/clock/rv1126-cru.h
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+
+/* pmucru-clocks indices */
+
+/* pll clocks */
+#define PLL_GPLL 1
+
+/* sclk (special clocks) */
+#define CLK_OSC0_DIV32K 2
+#define CLK_RTC32K 3
+#define CLK_WIFI_DIV 4
+#define CLK_WIFI_OSC0 5
+#define CLK_WIFI 6
+#define CLK_PMU 7
+#define SCLK_UART1_DIV 8
+#define SCLK_UART1_FRACDIV 9
+#define SCLK_UART1_MUX 10
+#define SCLK_UART1 11
+#define CLK_I2C0 12
+#define CLK_I2C2 13
+#define CLK_CAPTURE_PWM0 14
+#define CLK_PWM0 15
+#define CLK_CAPTURE_PWM1 16
+#define CLK_PWM1 17
+#define CLK_SPI0 18
+#define DBCLK_GPIO0 19
+#define CLK_PMUPVTM 20
+#define CLK_CORE_PMUPVTM 21
+#define CLK_REF12M 22
+#define CLK_USBPHY_OTG_REF 23
+#define CLK_USBPHY_HOST_REF 24
+#define CLK_REF24M 25
+#define CLK_MIPIDSIPHY_REF 26
+
+/* pclk */
+#define PCLK_PDPMU 30
+#define PCLK_PMU 31
+#define PCLK_UART1 32
+#define PCLK_I2C0 33
+#define PCLK_I2C2 34
+#define PCLK_PWM0 35
+#define PCLK_PWM1 36
+#define PCLK_SPI0 37
+#define PCLK_GPIO0 38
+#define PCLK_PMUSGRF 39
+#define PCLK_PMUGRF 40
+#define PCLK_PMUCRU 41
+#define PCLK_CHIPVEROTP 42
+#define PCLK_PDPMU_NIU 43
+#define PCLK_PMUPVTM 44
+#define PCLK_SCRKEYGEN 45
+
+#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
+
+/* cru-clocks indices */
+
+/* pll clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_HPLL 4
+
+/* sclk (special clocks) */
+#define ARMCLK 5
+#define USB480M 6
+#define CLK_CORE_CPUPVTM 7
+#define CLK_CPUPVTM 8
+#define CLK_SCR1 9
+#define CLK_SCR1_CORE 10
+#define CLK_SCR1_RTC 11
+#define CLK_SCR1_JTAG 12
+#define SCLK_UART0_DIV 13
+#define SCLK_UART0_FRAC 14
+#define SCLK_UART0_MUX 15
+#define SCLK_UART0 16
+#define SCLK_UART2_DIV 17
+#define SCLK_UART2_FRAC 18
+#define SCLK_UART2_MUX 19
+#define SCLK_UART2 20
+#define SCLK_UART3_DIV 21
+#define SCLK_UART3_FRAC 22
+#define SCLK_UART3_MUX 23
+#define SCLK_UART3 24
+#define SCLK_UART4_DIV 25
+#define SCLK_UART4_FRAC 26
+#define SCLK_UART4_MUX 27
+#define SCLK_UART4 28
+#define SCLK_UART5_DIV 29
+#define SCLK_UART5_FRAC 30
+#define SCLK_UART5_MUX 31
+#define SCLK_UART5 32
+#define CLK_I2C1 33
+#define CLK_I2C3 34
+#define CLK_I2C4 35
+#define CLK_I2C5 36
+#define CLK_SPI1 37
+#define CLK_CAPTURE_PWM2 38
+#define CLK_PWM2 39
+#define DBCLK_GPIO1 40
+#define DBCLK_GPIO2 41
+#define DBCLK_GPIO3 42
+#define DBCLK_GPIO4 43
+#define CLK_SARADC 44
+#define CLK_TIMER0 45
+#define CLK_TIMER1 46
+#define CLK_TIMER2 47
+#define CLK_TIMER3 48
+#define CLK_TIMER4 49
+#define CLK_TIMER5 50
+#define CLK_CAN 51
+#define CLK_NPU_TSADC 52
+#define CLK_NPU_TSADCPHY 53
+#define CLK_CPU_TSADC 54
+#define CLK_CPU_TSADCPHY 55
+#define CLK_CRYPTO_CORE 56
+#define CLK_CRYPTO_PKA 57
+#define MCLK_I2S0_TX_DIV 58
+#define MCLK_I2S0_TX_FRACDIV 59
+#define MCLK_I2S0_TX_MUX 60
+#define MCLK_I2S0_TX 61
+#define MCLK_I2S0_RX_DIV 62
+#define MCLK_I2S0_RX_FRACDIV 63
+#define MCLK_I2S0_RX_MUX 64
+#define MCLK_I2S0_RX 65
+#define MCLK_I2S0_TX_OUT2IO 66
+#define MCLK_I2S0_RX_OUT2IO 67
+#define MCLK_I2S1_DIV 68
+#define MCLK_I2S1_FRACDIV 69
+#define MCLK_I2S1_MUX 70
+#define MCLK_I2S1 71
+#define MCLK_I2S1_OUT2IO 72
+#define MCLK_I2S2_DIV 73
+#define MCLK_I2S2_FRACDIV 74
+#define MCLK_I2S2_MUX 75
+#define MCLK_I2S2 76
+#define MCLK_I2S2_OUT2IO 77
+#define MCLK_PDM 78
+#define SCLK_ADUPWM_DIV 79
+#define SCLK_AUDPWM_FRACDIV 80
+#define SCLK_AUDPWM_MUX 81
+#define SCLK_AUDPWM 82
+#define CLK_ACDCDIG_ADC 83
+#define CLK_ACDCDIG_DAC 84
+#define CLK_ACDCDIG_I2C 85
+#define CLK_VENC_CORE 86
+#define CLK_VDEC_CORE 87
+#define CLK_VDEC_CA 88
+#define CLK_VDEC_HEVC_CA 89
+#define CLK_RGA_CORE 90
+#define CLK_IEP_CORE 91
+#define CLK_ISP_DIV 92
+#define CLK_ISP_NP5 93
+#define CLK_ISP_NUX 94
+#define CLK_ISP 95
+#define CLK_CIF_OUT_DIV 96
+#define CLK_CIF_OUT_FRACDIV 97
+#define CLK_CIF_OUT_MUX 98
+#define CLK_CIF_OUT 99
+#define CLK_MIPICSI_OUT_DIV 100
+#define CLK_MIPICSI_OUT_FRACDIV 101
+#define CLK_MIPICSI_OUT_MUX 102
+#define CLK_MIPICSI_OUT 103
+#define CLK_ISPP_DIV 104
+#define CLK_ISPP_NP5 105
+#define CLK_ISPP_NUX 106
+#define CLK_ISPP 107
+#define CLK_SDMMC 108
+#define SCLK_SDMMC_DRV 109
+#define SCLK_SDMMC_SAMPLE 110
+#define CLK_SDIO 111
+#define SCLK_SDIO_DRV 112
+#define SCLK_SDIO_SAMPLE 113
+#define CLK_EMMC 114
+#define SCLK_EMMC_DRV 115
+#define SCLK_EMMC_SAMPLE 116
+#define CLK_NANDC 117
+#define SCLK_SFC 118
+#define CLK_USBHOST_UTMI_OHCI 119
+#define CLK_USBOTG_REF 120
+#define CLK_GMAC_DIV 121
+#define CLK_GMAC_RGMII_M0 122
+#define CLK_GMAC_SRC_M0 123
+#define CLK_GMAC_RGMII_M1 124
+#define CLK_GMAC_SRC_M1 125
+#define CLK_GMAC_SRC 126
+#define CLK_GMAC_REF 127
+#define CLK_GMAC_TX_SRC 128
+#define CLK_GMAC_TX_DIV5 129
+#define CLK_GMAC_TX_DIV50 130
+#define RGMII_MODE_CLK 131
+#define CLK_GMAC_RX_SRC 132
+#define CLK_GMAC_RX_DIV2 133
+#define CLK_GMAC_RX_DIV20 134
+#define RMII_MODE_CLK 135
+#define CLK_GMAC_TX_RX 136
+#define CLK_GMAC_PTPREF 137
+#define CLK_GMAC_ETHERNET_OUT 138
+#define CLK_DDRPHY 139
+#define CLK_DDR_MON 140
+#define TMCLK_DDR_MON 141
+#define CLK_NPU_DIV 142
+#define CLK_NPU_NP5 143
+#define CLK_CORE_NPU 144
+#define CLK_CORE_NPUPVTM 145
+#define CLK_NPUPVTM 146
+#define SCLK_DDRCLK 147
+#define CLK_OTP 148
+
+/* dclk */
+#define DCLK_DECOM 150
+#define DCLK_VOP_DIV 151
+#define DCLK_VOP_FRACDIV 152
+#define DCLK_VOP_MUX 153
+#define DCLK_VOP 154
+#define DCLK_CIF 155
+#define DCLK_CIFLITE 156
+
+/* aclk */
+#define ACLK_PDBUS 160
+#define ACLK_DMAC 161
+#define ACLK_DCF 162
+#define ACLK_SPINLOCK 163
+#define ACLK_DECOM 164
+#define ACLK_PDCRYPTO 165
+#define ACLK_CRYPTO 166
+#define ACLK_PDVEPU 167
+#define ACLK_VENC 168
+#define ACLK_PDVDEC 169
+#define ACLK_PDJPEG 170
+#define ACLK_VDEC 171
+#define ACLK_JPEG 172
+#define ACLK_PDVO 173
+#define ACLK_RGA 174
+#define ACLK_VOP 175
+#define ACLK_IEP 176
+#define ACLK_PDVI_DIV 177
+#define ACLK_PDVI_NP5 178
+#define ACLK_PDVI 179
+#define ACLK_ISP 180
+#define ACLK_CIF 181
+#define ACLK_CIFLITE 182
+#define ACLK_PDISPP_DIV 183
+#define ACLK_PDISPP_NP5 184
+#define ACLK_PDISPP 185
+#define ACLK_ISPP 186
+#define ACLK_PDPHP 187
+#define ACLK_PDUSB 188
+#define ACLK_USBOTG 189
+#define ACLK_PDGMAC 190
+#define ACLK_GMAC 191
+#define ACLK_PDNPU_DIV 192
+#define ACLK_PDNPU_NP5 193
+#define ACLK_PDNPU 194
+#define ACLK_NPU 195
+
+/* hclk */
+#define HCLK_PDCORE_NIU 200
+#define HCLK_PDUSB 201
+#define HCLK_PDCRYPTO 202
+#define HCLK_CRYPTO 203
+#define HCLK_PDAUDIO 204
+#define HCLK_I2S0 205
+#define HCLK_I2S1 206
+#define HCLK_I2S2 207
+#define HCLK_PDM 208
+#define HCLK_AUDPWM 209
+#define HCLK_PDVEPU 210
+#define HCLK_VENC 211
+#define HCLK_PDVDEC 212
+#define HCLK_PDJPEG 213
+#define HCLK_VDEC 214
+#define HCLK_JPEG 215
+#define HCLK_PDVO 216
+#define HCLK_RGA 217
+#define HCLK_VOP 218
+#define HCLK_IEP 219
+#define HCLK_PDVI 220
+#define HCLK_ISP 221
+#define HCLK_CIF 222
+#define HCLK_CIFLITE 223
+#define HCLK_PDISPP 224
+#define HCLK_ISPP 225
+#define HCLK_PDPHP 226
+#define HCLK_PDSDMMC 227
+#define HCLK_SDMMC 228
+#define HCLK_PDSDIO 229
+#define HCLK_SDIO 230
+#define HCLK_PDNVM 231
+#define HCLK_EMMC 232
+#define HCLK_NANDC 233
+#define HCLK_SFC 234
+#define HCLK_SFCXIP 235
+#define HCLK_PDBUS 236
+#define HCLK_USBHOST 237
+#define HCLK_USBHOST_ARB 238
+#define HCLK_PDNPU 239
+#define HCLK_NPU 240
+
+/* pclk */
+#define PCLK_CPUPVTM 245
+#define PCLK_PDBUS 246
+#define PCLK_DCF 247
+#define PCLK_WDT 248
+#define PCLK_MAILBOX 249
+#define PCLK_UART0 250
+#define PCLK_UART2 251
+#define PCLK_UART3 252
+#define PCLK_UART4 253
+#define PCLK_UART5 254
+#define PCLK_I2C1 255
+#define PCLK_I2C3 256
+#define PCLK_I2C4 257
+#define PCLK_I2C5 258
+#define PCLK_SPI1 259
+#define PCLK_PWM2 261
+#define PCLK_GPIO1 262
+#define PCLK_GPIO2 263
+#define PCLK_GPIO3 264
+#define PCLK_GPIO4 265
+#define PCLK_SARADC 266
+#define PCLK_TIMER 267
+#define PCLK_DECOM 268
+#define PCLK_CAN 269
+#define PCLK_NPU_TSADC 270
+#define PCLK_CPU_TSADC 271
+#define PCLK_ACDCDIG 272
+#define PCLK_PDVO 273
+#define PCLK_DSIHOST 274
+#define PCLK_PDVI 275
+#define PCLK_CSIHOST 276
+#define PCLK_PDGMAC 277
+#define PCLK_GMAC 278
+#define PCLK_PDDDR 279
+#define PCLK_DDR_MON 280
+#define PCLK_PDNPU 281
+#define PCLK_NPUPVTM 282
+#define PCLK_PDTOP 283
+#define PCLK_TOPCRU 284
+#define PCLK_TOPGRF 285
+#define PCLK_CPUEMADET 286
+#define PCLK_DDRPHY 287
+#define PCLK_DSIPHY 289
+#define PCLK_CSIPHY0 290
+#define PCLK_CSIPHY1 291
+#define PCLK_USBPHY_HOST 292
+#define PCLK_USBPHY_OTG 293
+#define PCLK_OTP 294
+
+#define CLK_NR_CLKS (PCLK_OTP + 1)
+
+/* pmu soft-reset indices */
+
+/* pmu_cru_softrst_con0 */
+#define SRST_PDPMU_NIU_P 0
+#define SRST_PMU_SGRF_P 1
+#define SRST_PMU_SGRF_REMAP_P 2
+#define SRST_I2C0_P 3
+#define SRST_I2C0 4
+#define SRST_I2C2_P 7
+#define SRST_I2C2 8
+#define SRST_UART1_P 9
+#define SRST_UART1 10
+#define SRST_PWM0_P 11
+#define SRST_PWM0 12
+#define SRST_PWM1_P 13
+#define SRST_PWM1 14
+#define SRST_DDR_FAIL_SAFE 15
+
+/* pmu_cru_softrst_con1 */
+#define SRST_GPIO0_P 17
+#define SRST_GPIO0_DB 18
+#define SRST_SPI0_P 19
+#define SRST_SPI0 20
+#define SRST_PMUGRF_P 21
+#define SRST_CHIPVEROTP_P 22
+#define SRST_PMUPVTM 24
+#define SRST_PMUPVTM_P 25
+#define SRST_PMUCRU_P 30
+
+/* soft-reset indices */
+
+/* cru_softrst_con0 */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_NL2 12
+#define SRST_CORE_NIU_A 13
+#define SRST_DBG_DAPLITE_P 14
+#define SRST_DAPLITE_P 15
+
+/* cru_softrst_con1 */
+#define SRST_PDBUS_NIU1_A 16
+#define SRST_PDBUS_NIU1_H 17
+#define SRST_PDBUS_NIU1_P 18
+#define SRST_PDBUS_NIU2_A 19
+#define SRST_PDBUS_NIU2_H 20
+#define SRST_PDBUS_NIU3_A 21
+#define SRST_PDBUS_NIU3_H 22
+#define SRST_PDBUS_HOLD_NIU1_A 23
+#define SRST_DBG_NIU_P 24
+#define SRST_PDCORE_NIIU_H 25
+#define SRST_MUC_NIU 26
+#define SRST_DCF_A 29
+#define SRST_DCF_P 30
+#define SRST_SYSTEM_SRAM_A 31
+
+/* cru_softrst_con2 */
+#define SRST_I2C1_P 32
+#define SRST_I2C1 33
+#define SRST_I2C3_P 34
+#define SRST_I2C3 35
+#define SRST_I2C4_P 36
+#define SRST_I2C4 37
+#define SRST_I2C5_P 38
+#define SRST_I2C5 39
+#define SRST_SPI1_P 40
+#define SRST_SPI1 41
+#define SRST_MCU_CORE 42
+#define SRST_PWM2_P 44
+#define SRST_PWM2 45
+#define SRST_SPINLOCK_A 46
+
+/* cru_softrst_con3 */
+#define SRST_UART0_P 48
+#define SRST_UART0 49
+#define SRST_UART2_P 50
+#define SRST_UART2 51
+#define SRST_UART3_P 52
+#define SRST_UART3 53
+#define SRST_UART4_P 54
+#define SRST_UART4 55
+#define SRST_UART5_P 56
+#define SRST_UART5 57
+#define SRST_WDT_P 58
+#define SRST_SARADC_P 59
+#define SRST_GRF_P 61
+#define SRST_TIMER_P 62
+#define SRST_MAILBOX_P 63
+
+/* cru_softrst_con4 */
+#define SRST_TIMER0 64
+#define SRST_TIMER1 65
+#define SRST_TIMER2 66
+#define SRST_TIMER3 67
+#define SRST_TIMER4 68
+#define SRST_TIMER5 69
+#define SRST_INTMUX_P 70
+#define SRST_GPIO1_P 72
+#define SRST_GPIO1_DB 73
+#define SRST_GPIO2_P 74
+#define SRST_GPIO2_DB 75
+#define SRST_GPIO3_P 76
+#define SRST_GPIO3_DB 77
+#define SRST_GPIO4_P 78
+#define SRST_GPIO4_DB 79
+
+/* cru_softrst_con5 */
+#define SRST_CAN_P 80
+#define SRST_CAN 81
+#define SRST_DECOM_A 85
+#define SRST_DECOM_P 86
+#define SRST_DECOM_D 87
+#define SRST_PDCRYPTO_NIU_A 88
+#define SRST_PDCRYPTO_NIU_H 89
+#define SRST_CRYPTO_A 90
+#define SRST_CRYPTO_H 91
+#define SRST_CRYPTO_CORE 92
+#define SRST_CRYPTO_PKA 93
+#define SRST_SGRF_P 95
+
+/* cru_softrst_con6 */
+#define SRST_PDAUDIO_NIU_H 96
+#define SRST_PDAUDIO_NIU_P 97
+#define SRST_I2S0_H 98
+#define SRST_I2S0_TX_M 99
+#define SRST_I2S0_RX_M 100
+#define SRST_I2S1_H 101
+#define SRST_I2S1_M 102
+#define SRST_I2S2_H 103
+#define SRST_I2S2_M 104
+#define SRST_PDM_H 105
+#define SRST_PDM_M 106
+#define SRST_AUDPWM_H 107
+#define SRST_AUDPWM 108
+#define SRST_ACDCDIG_P 109
+#define SRST_ACDCDIG 110
+
+/* cru_softrst_con7 */
+#define SRST_PDVEPU_NIU_A 112
+#define SRST_PDVEPU_NIU_H 113
+#define SRST_VENC_A 114
+#define SRST_VENC_H 115
+#define SRST_VENC_CORE 116
+#define SRST_PDVDEC_NIU_A 117
+#define SRST_PDVDEC_NIU_H 118
+#define SRST_VDEC_A 119
+#define SRST_VDEC_H 120
+#define SRST_VDEC_CORE 121
+#define SRST_VDEC_CA 122
+#define SRST_VDEC_HEVC_CA 123
+#define SRST_PDJPEG_NIU_A 124
+#define SRST_PDJPEG_NIU_H 125
+#define SRST_JPEG_A 126
+#define SRST_JPEG_H 127
+
+/* cru_softrst_con8 */
+#define SRST_PDVO_NIU_A 128
+#define SRST_PDVO_NIU_H 129
+#define SRST_PDVO_NIU_P 130
+#define SRST_RGA_A 131
+#define SRST_RGA_H 132
+#define SRST_RGA_CORE 133
+#define SRST_VOP_A 134
+#define SRST_VOP_H 135
+#define SRST_VOP_D 136
+#define SRST_TXBYTEHS_DSIHOST 137
+#define SRST_DSIHOST_P 138
+#define SRST_IEP_A 139
+#define SRST_IEP_H 140
+#define SRST_IEP_CORE 141
+#define SRST_ISP_RX_P 142
+
+/* cru_softrst_con9 */
+#define SRST_PDVI_NIU_A 144
+#define SRST_PDVI_NIU_H 145
+#define SRST_PDVI_NIU_P 146
+#define SRST_ISP 147
+#define SRST_CIF_A 148
+#define SRST_CIF_H 149
+#define SRST_CIF_D 150
+#define SRST_CIF_P 151
+#define SRST_CIF_I 152
+#define SRST_CIF_RX_P 153
+#define SRST_PDISPP_NIU_A 154
+#define SRST_PDISPP_NIU_H 155
+#define SRST_ISPP_A 156
+#define SRST_ISPP_H 157
+#define SRST_ISPP 158
+#define SRST_CSIHOST_P 159
+
+/* cru_softrst_con10 */
+#define SRST_PDPHPMID_NIU_A 160
+#define SRST_PDPHPMID_NIU_H 161
+#define SRST_PDNVM_NIU_H 163
+#define SRST_SDMMC_H 164
+#define SRST_SDIO_H 165
+#define SRST_EMMC_H 166
+#define SRST_SFC_H 167
+#define SRST_SFCXIP_H 168
+#define SRST_SFC 169
+#define SRST_NANDC_H 170
+#define SRST_NANDC 171
+#define SRST_PDSDMMC_H 173
+#define SRST_PDSDIO_H 174
+
+/* cru_softrst_con11 */
+#define SRST_PDUSB_NIU_A 176
+#define SRST_PDUSB_NIU_H 177
+#define SRST_USBHOST_H 178
+#define SRST_USBHOST_ARB_H 179
+#define SRST_USBHOST_UTMI 180
+#define SRST_USBOTG_A 181
+#define SRST_USBPHY_OTG_P 182
+#define SRST_USBPHY_HOST_P 183
+#define SRST_USBPHYPOR_OTG 184
+#define SRST_USBPHYPOR_HOST 185
+#define SRST_PDGMAC_NIU_A 188
+#define SRST_PDGMAC_NIU_P 189
+#define SRST_GMAC_A 190
+
+/* cru_softrst_con12 */
+#define SRST_DDR_DFICTL_P 193
+#define SRST_DDR_MON_P 194
+#define SRST_DDR_STANDBY_P 195
+#define SRST_DDR_GRF_P 196
+#define SRST_DDR_MSCH_P 197
+#define SRST_DDR_SPLIT_A 198
+#define SRST_DDR_MSCH 199
+#define SRST_DDR_DFICTL 202
+#define SRST_DDR_STANDBY 203
+#define SRST_NPUMCU_NIU 205
+#define SRST_DDRPHY_P 206
+#define SRST_DDRPHY 207
+
+/* cru_softrst_con13 */
+#define SRST_PDNPU_NIU_A 208
+#define SRST_PDNPU_NIU_H 209
+#define SRST_PDNPU_NIU_P 210
+#define SRST_NPU_A 211
+#define SRST_NPU_H 212
+#define SRST_NPU 213
+#define SRST_NPUPVTM_P 214
+#define SRST_NPUPVTM 215
+#define SRST_NPU_TSADC_P 216
+#define SRST_NPU_TSADC 217
+#define SRST_NPU_TSADCPHY 218
+#define SRST_CIFLITE_A 220
+#define SRST_CIFLITE_H 221
+#define SRST_CIFLITE_D 222
+#define SRST_CIFLITE_RX_P 223
+
+/* cru_softrst_con14 */
+#define SRST_TOPNIU_P 224
+#define SRST_TOPCRU_P 225
+#define SRST_TOPGRF_P 226
+#define SRST_CPUEMADET_P 227
+#define SRST_CSIPHY0_P 228
+#define SRST_CSIPHY1_P 229
+#define SRST_DSIPHY_P 230
+#define SRST_CPU_TSADC_P 232
+#define SRST_CPU_TSADC 233
+#define SRST_CPU_TSADCPHY 234
+#define SRST_CPUPVTM_P 235
+#define SRST_CPUPVTM 236
+
+#endif
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-mmc, Ulf Hansson
Add a compatible string for Rockchip RV1126 SoC.
Cc: linux-mmc@vger.kernel.org
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
index 54fb59820d2b..8d888b435817 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
@@ -39,6 +39,7 @@ properties:
- rockchip,rk3399-dw-mshc
- rockchip,rk3568-dw-mshc
- rockchip,rv1108-dw-mshc
+ - rockchip,rv1126-dw-mshc
- const: rockchip,rk3288-dw-mshc
reg:
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-mmc, Ulf Hansson
Add a compatible string for Rockchip RV1126 SoC.
Cc: linux-mmc@vger.kernel.org
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
index 54fb59820d2b..8d888b435817 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
@@ -39,6 +39,7 @@ properties:
- rockchip,rk3399-dw-mshc
- rockchip,rk3568-dw-mshc
- rockchip,rv1108-dw-mshc
+ - rockchip,rv1126-dw-mshc
- const: rockchip,rk3288-dw-mshc
reg:
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-mmc, Ulf Hansson
Add a compatible string for Rockchip RV1126 SoC.
Cc: linux-mmc@vger.kernel.org
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
index 54fb59820d2b..8d888b435817 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
@@ -39,6 +39,7 @@ properties:
- rockchip,rk3399-dw-mshc
- rockchip,rk3568-dw-mshc
- rockchip,rv1108-dw-mshc
+ - rockchip,rv1126-dw-mshc
- const: rockchip,rk3288-dw-mshc
reg:
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-serial, Greg Kroah-Hartman
Document compatible string for Rockchip RV1126 SoC.
Cc: linux-serial@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 12137fe80acf..4f47d4e4dd94 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -34,6 +34,7 @@ properties:
- rockchip,rk3399-uart
- rockchip,rk3568-uart
- rockchip,rv1108-uart
+ - rockchip,rv1126-uart
- const: snps,dw-apb-uart
- items:
- enum:
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-serial, Greg Kroah-Hartman
Document compatible string for Rockchip RV1126 SoC.
Cc: linux-serial@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 12137fe80acf..4f47d4e4dd94 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -34,6 +34,7 @@ properties:
- rockchip,rk3399-uart
- rockchip,rk3568-uart
- rockchip,rv1108-uart
+ - rockchip,rv1126-uart
- const: snps,dw-apb-uart
- items:
- enum:
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
linux-serial, Greg Kroah-Hartman
Document compatible string for Rockchip RV1126 SoC.
Cc: linux-serial@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
index 12137fe80acf..4f47d4e4dd94 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml
@@ -34,6 +34,7 @@ properties:
- rockchip,rk3399-uart
- rockchip,rk3568-uart
- rockchip,rv1108-uart
+ - rockchip,rv1126-uart
- const: snps,dw-apb-uart
- items:
- enum:
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, linux-i2c
Document compatible string for Rockchip RV1126 SoC.
Cc: linux-i2c@vger.kernel.org
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
index 5339dd4fc370..f350b7a0b991 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
@@ -37,6 +37,7 @@ properties:
- rockchip,rk3308-i2c
- rockchip,rk3328-i2c
- rockchip,rk3568-i2c
+ - rockchip,rv1126-i2c
- const: rockchip,rk3399-i2c
reg:
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, linux-i2c
Document compatible string for Rockchip RV1126 SoC.
Cc: linux-i2c@vger.kernel.org
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
index 5339dd4fc370..f350b7a0b991 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
@@ -37,6 +37,7 @@ properties:
- rockchip,rk3308-i2c
- rockchip,rk3328-i2c
- rockchip,rk3568-i2c
+ - rockchip,rv1126-i2c
- const: rockchip,rk3399-i2c
reg:
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, linux-i2c
Document compatible string for Rockchip RV1126 SoC.
Cc: linux-i2c@vger.kernel.org
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
index 5339dd4fc370..f350b7a0b991 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
@@ -37,6 +37,7 @@ properties:
- rockchip,rk3308-i2c
- rockchip,rk3328-i2c
- rockchip,rk3568-i2c
+ - rockchip,rv1126-i2c
- const: rockchip,rk3399-i2c
reg:
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document compatible string for Rockchip RV1126 grf.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 75a2b8bb25fb..dd7090d668f5 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -45,6 +45,7 @@ properties:
- rockchip,rk3568-pmugrf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
+ - rockchip,rv1126-grf
- const: syscon
- const: simple-mfd
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document compatible string for Rockchip RV1126 grf.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 75a2b8bb25fb..dd7090d668f5 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -45,6 +45,7 @@ properties:
- rockchip,rk3568-pmugrf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
+ - rockchip,rv1126-grf
- const: syscon
- const: simple-mfd
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document compatible string for Rockchip RV1126 grf.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 75a2b8bb25fb..dd7090d668f5 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -45,6 +45,7 @@ properties:
- rockchip,rk3568-pmugrf
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
+ - rockchip,rv1126-grf
- const: syscon
- const: simple-mfd
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document compatible string for Rockchip RV1126 pmugrf.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index dd7090d668f5..521fbcb8eeb9 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -46,6 +46,7 @@ properties:
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
- rockchip,rv1126-grf
+ - rockchip,rv1126-pmugrf
- const: syscon
- const: simple-mfd
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document compatible string for Rockchip RV1126 pmugrf.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index dd7090d668f5..521fbcb8eeb9 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -46,6 +46,7 @@ properties:
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
- rockchip,rv1126-grf
+ - rockchip,rv1126-pmugrf
- const: syscon
- const: simple-mfd
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Document compatible string for Rockchip RV1126 pmugrf.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index dd7090d668f5..521fbcb8eeb9 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -46,6 +46,7 @@ properties:
- rockchip,rv1108-grf
- rockchip,rv1108-pmugrf
- rockchip,rv1126-grf
+ - rockchip,rv1126-pmugrf
- const: syscon
- const: simple-mfd
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Lee Jones
Document dt-bindings for Rockchip RV1126 QoS registers.
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index fb784045013f..32cd2ebccaf2 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -59,6 +59,7 @@ properties:
- rockchip,rk3368-qos
- rockchip,rk3399-qos
- rockchip,rk3568-qos
+ - rockchip,rv1126-qos
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Lee Jones
Document dt-bindings for Rockchip RV1126 QoS registers.
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index fb784045013f..32cd2ebccaf2 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -59,6 +59,7 @@ properties:
- rockchip,rk3368-qos
- rockchip,rk3399-qos
- rockchip,rk3568-qos
+ - rockchip,rv1126-qos
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Lee Jones
Document dt-bindings for Rockchip RV1126 QoS registers.
Cc: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index fb784045013f..32cd2ebccaf2 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -59,6 +59,7 @@ properties:
- rockchip,rk3368-qos
- rockchip,rk3399-qos
- rockchip,rk3568-qos
+ - rockchip,rv1126-qos
- samsung,exynos3-sysreg
- samsung,exynos4-sysreg
- samsung,exynos5-sysreg
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 17/22] ARM: dts: rockchip: Add Rockchip RV1126 SoC
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
Jon Lin, Sugar Zhang
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
MAINTAINERS | 2 +-
arch/arm/boot/dts/rockchip-pinconf.dtsi | 115 ++++++
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 ++++++++++++++
arch/arm/boot/dts/rv1126.dtsi | 500 ++++++++++++++++++++++++
4 files changed, 918 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rockchip-pinconf.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index f679152bdbad..124247f95787 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2646,7 +2646,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
-F: arch/arm/boot/dts/rv1108*
+F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*
diff --git a/arch/arm/boot/dts/rockchip-pinconf.dtsi b/arch/arm/boot/dts/rockchip-pinconf.dtsi
new file mode 100644
index 000000000000..c11819929348
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip-pinconf.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+&pinctrl {
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+ bias-pull-down;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+ bias-pull-down;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_smt: pcfg-pull-up-smt {
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_smt: pcfg-pull-down-smt {
+ bias-pull-down;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+ bias-disable;
+ drive-strength = <0>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 000000000000..93e2885e8708
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clko */
+ <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c0_sda */
+ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ /* i2c1_scl */
+ <1 RK_PD3 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c1_sda */
+ <1 RK_PD2 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ /* i2c2_scl */
+ <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c2_sda */
+ <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <3 RK_PA4 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m0 */
+ <3 RK_PA5 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <2 RK_PD4 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m1 */
+ <2 RK_PD5 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <1 RK_PD6 3 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m2 */
+ <1 RK_PD7 3 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PA0 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PA1 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m0 */
+ <2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <3 RK_PB0 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m1 */
+ <3 RK_PB1 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <1 RK_PD0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m2 */
+ <1 RK_PD1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_pwr: sdmmc0-pwr {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_pwr: sdmmc1-pwr {
+ rockchip,pins =
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <1 RK_PC2 1 &pcfg_pull_up>,
+ /* uart0_tx */
+ <1 RK_PC3 1 &pcfg_pull_up>;
+ };
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn_gpio: uart0-rts-pin {
+ rockchip,pins =
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+ uart2 {
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA3 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA2 1 &pcfg_pull_up>;
+ };
+ };
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PC7 4 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PC6 4 &pcfg_pull_up>;
+ };
+ };
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PA5 4 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
new file mode 100644
index 000000000000..8340734b9a18
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/clock/rv1126-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rv1126-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1126";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu2: cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu3: cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ grf: syscon@fe000000 {
+ compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
+ reg = <0xfe000000 0x20000>;
+ };
+
+ pmugrf: syscon@fe020000 {
+ compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
+ reg = <0xfe020000 0x1000>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rv1126-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ qos_emmc: qos@fe860000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860000 0x20>;
+ };
+
+ qos_nandc: qos@fe860080 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860080 0x20>;
+ };
+
+ qos_sfc: qos@fe860200 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860200 0x20>;
+ };
+
+ qos_sdio: qos@fe86c000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe86c000 0x20>;
+ };
+
+ gic: interrupt-controller@feff0000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xfeff1000 0x1000>,
+ <0xfeff2000 0x2000>,
+ <0xfeff4000 0x2000>,
+ <0xfeff6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pmu: power-management@ff3e0000 {
+ compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
+ reg = <0xff3e0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rv1126-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RV1126_PD_NVM {
+ reg = <RV1126_PD_NVM>;
+ clocks = <&cru HCLK_EMMC>,
+ <&cru CLK_EMMC>,
+ <&cru HCLK_NANDC>,
+ <&cru CLK_NANDC>,
+ <&cru HCLK_SFC>,
+ <&cru HCLK_SFCXIP>,
+ <&cru SCLK_SFC>;
+ pm_qos = <&qos_emmc>,
+ <&qos_nandc>,
+ <&qos_sfc>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RV1126_PD_SDIO {
+ reg = <RV1126_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru CLK_SDIO>;
+ pm_qos = <&qos_sdio>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ i2c0: i2c@ff3f0000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff3f0000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ff400000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff400000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dmac: dma-controller@ff4e0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff4e0000 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+
+ uart1: serial@ff410000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff410000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 7>, <&dmac 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ i2c1: i2c@ff510000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff510000 0x1000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ff520000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff520000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ff530000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff530000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ff540000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff540000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@ff560000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff560000 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 5>, <&dmac 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff570000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff570000 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 9>, <&dmac 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff580000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff580000 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 11>, <&dmac 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff590000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff590000 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 13>, <&dmac 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff5a0000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff5a0000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ dmas = <&dmac 15>, <&dmac 14>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ saradc: saradc@ff5e0000 {
+ compatible = "rockchip,rk3399-saradc";
+ reg = <0xff5e0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC_P>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ timer: timer@ff660000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0xff660000 0x20>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ emmc: mmc@ffc50000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc50000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_NVM>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc60000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc60000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdio: mmc@ffc70000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc70000 0x4000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_SDIO>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1126-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@ff460000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff460000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff620000 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff630000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@ff640000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff640000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio4@ff650000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff650000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rv1126-pinctrl.dtsi"
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 17/22] ARM: dts: rockchip: Add Rockchip RV1126 SoC
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
Jon Lin, Sugar Zhang
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
MAINTAINERS | 2 +-
arch/arm/boot/dts/rockchip-pinconf.dtsi | 115 ++++++
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 ++++++++++++++
arch/arm/boot/dts/rv1126.dtsi | 500 ++++++++++++++++++++++++
4 files changed, 918 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rockchip-pinconf.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index f679152bdbad..124247f95787 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2646,7 +2646,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
-F: arch/arm/boot/dts/rv1108*
+F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*
diff --git a/arch/arm/boot/dts/rockchip-pinconf.dtsi b/arch/arm/boot/dts/rockchip-pinconf.dtsi
new file mode 100644
index 000000000000..c11819929348
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip-pinconf.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+&pinctrl {
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+ bias-pull-down;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+ bias-pull-down;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_smt: pcfg-pull-up-smt {
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_smt: pcfg-pull-down-smt {
+ bias-pull-down;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+ bias-disable;
+ drive-strength = <0>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 000000000000..93e2885e8708
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clko */
+ <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c0_sda */
+ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ /* i2c1_scl */
+ <1 RK_PD3 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c1_sda */
+ <1 RK_PD2 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ /* i2c2_scl */
+ <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c2_sda */
+ <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <3 RK_PA4 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m0 */
+ <3 RK_PA5 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <2 RK_PD4 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m1 */
+ <2 RK_PD5 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <1 RK_PD6 3 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m2 */
+ <1 RK_PD7 3 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PA0 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PA1 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m0 */
+ <2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <3 RK_PB0 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m1 */
+ <3 RK_PB1 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <1 RK_PD0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m2 */
+ <1 RK_PD1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_pwr: sdmmc0-pwr {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_pwr: sdmmc1-pwr {
+ rockchip,pins =
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <1 RK_PC2 1 &pcfg_pull_up>,
+ /* uart0_tx */
+ <1 RK_PC3 1 &pcfg_pull_up>;
+ };
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn_gpio: uart0-rts-pin {
+ rockchip,pins =
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+ uart2 {
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA3 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA2 1 &pcfg_pull_up>;
+ };
+ };
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PC7 4 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PC6 4 &pcfg_pull_up>;
+ };
+ };
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PA5 4 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
new file mode 100644
index 000000000000..8340734b9a18
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/clock/rv1126-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rv1126-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1126";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu2: cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu3: cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ grf: syscon@fe000000 {
+ compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
+ reg = <0xfe000000 0x20000>;
+ };
+
+ pmugrf: syscon@fe020000 {
+ compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
+ reg = <0xfe020000 0x1000>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rv1126-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ qos_emmc: qos@fe860000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860000 0x20>;
+ };
+
+ qos_nandc: qos@fe860080 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860080 0x20>;
+ };
+
+ qos_sfc: qos@fe860200 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860200 0x20>;
+ };
+
+ qos_sdio: qos@fe86c000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe86c000 0x20>;
+ };
+
+ gic: interrupt-controller@feff0000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xfeff1000 0x1000>,
+ <0xfeff2000 0x2000>,
+ <0xfeff4000 0x2000>,
+ <0xfeff6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pmu: power-management@ff3e0000 {
+ compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
+ reg = <0xff3e0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rv1126-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RV1126_PD_NVM {
+ reg = <RV1126_PD_NVM>;
+ clocks = <&cru HCLK_EMMC>,
+ <&cru CLK_EMMC>,
+ <&cru HCLK_NANDC>,
+ <&cru CLK_NANDC>,
+ <&cru HCLK_SFC>,
+ <&cru HCLK_SFCXIP>,
+ <&cru SCLK_SFC>;
+ pm_qos = <&qos_emmc>,
+ <&qos_nandc>,
+ <&qos_sfc>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RV1126_PD_SDIO {
+ reg = <RV1126_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru CLK_SDIO>;
+ pm_qos = <&qos_sdio>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ i2c0: i2c@ff3f0000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff3f0000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ff400000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff400000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dmac: dma-controller@ff4e0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff4e0000 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+
+ uart1: serial@ff410000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff410000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 7>, <&dmac 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ i2c1: i2c@ff510000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff510000 0x1000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ff520000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff520000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ff530000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff530000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ff540000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff540000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@ff560000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff560000 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 5>, <&dmac 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff570000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff570000 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 9>, <&dmac 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff580000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff580000 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 11>, <&dmac 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff590000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff590000 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 13>, <&dmac 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff5a0000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff5a0000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ dmas = <&dmac 15>, <&dmac 14>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ saradc: saradc@ff5e0000 {
+ compatible = "rockchip,rk3399-saradc";
+ reg = <0xff5e0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC_P>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ timer: timer@ff660000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0xff660000 0x20>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ emmc: mmc@ffc50000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc50000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_NVM>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc60000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc60000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdio: mmc@ffc70000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc70000 0x4000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_SDIO>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1126-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@ff460000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff460000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff620000 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff630000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@ff640000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff640000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio4@ff650000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff650000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rv1126-pinctrl.dtsi"
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 17/22] ARM: dts: rockchip: Add Rockchip RV1126 SoC
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
Jon Lin, Sugar Zhang
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
MAINTAINERS | 2 +-
arch/arm/boot/dts/rockchip-pinconf.dtsi | 115 ++++++
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 302 ++++++++++++++
arch/arm/boot/dts/rv1126.dtsi | 500 ++++++++++++++++++++++++
4 files changed, 918 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rockchip-pinconf.dtsi
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index f679152bdbad..124247f95787 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2646,7 +2646,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
-F: arch/arm/boot/dts/rv1108*
+F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*
diff --git a/arch/arm/boot/dts/rockchip-pinconf.dtsi b/arch/arm/boot/dts/rockchip-pinconf.dtsi
new file mode 100644
index 000000000000..c11819929348
--- /dev/null
+++ b/arch/arm/boot/dts/rockchip-pinconf.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ */
+&pinctrl {
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+ bias-pull-down;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+ bias-pull-down;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_smt: pcfg-pull-up-smt {
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_smt: pcfg-pull-down-smt {
+ bias-pull-down;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+ bias-disable;
+ drive-strength = <0>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 000000000000..93e2885e8708
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clko */
+ <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c0_sda */
+ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ /* i2c1_scl */
+ <1 RK_PD3 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c1_sda */
+ <1 RK_PD2 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins =
+ /* i2c2_scl */
+ <0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c2_sda */
+ <0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <3 RK_PA4 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m0 */
+ <3 RK_PA5 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <2 RK_PD4 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m1 */
+ <2 RK_PD5 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <1 RK_PD6 3 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c3_sda_m2 */
+ <1 RK_PD7 3 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PA0 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PA1 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c4_sda_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <2 RK_PA5 7 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m0 */
+ <2 RK_PB3 7 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <3 RK_PB0 5 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m1 */
+ <3 RK_PB1 5 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <1 RK_PD0 4 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c5_sda_m2 */
+ <1 RK_PD1 4 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_pwr: sdmmc0-pwr {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_pwr: sdmmc1-pwr {
+ rockchip,pins =
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <1 RK_PC2 1 &pcfg_pull_up>,
+ /* uart0_tx */
+ <1 RK_PC3 1 &pcfg_pull_up>;
+ };
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn_gpio: uart0-rts-pin {
+ rockchip,pins =
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+ uart2 {
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA3 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA2 1 &pcfg_pull_up>;
+ };
+ };
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PC7 4 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PC6 4 &pcfg_pull_up>;
+ };
+ };
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PA5 4 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
new file mode 100644
index 000000000000..8340734b9a18
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -0,0 +1,500 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/clock/rv1126-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rv1126-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1126";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu2: cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu3: cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ grf: syscon@fe000000 {
+ compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
+ reg = <0xfe000000 0x20000>;
+ };
+
+ pmugrf: syscon@fe020000 {
+ compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
+ reg = <0xfe020000 0x1000>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rv1126-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ qos_emmc: qos@fe860000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860000 0x20>;
+ };
+
+ qos_nandc: qos@fe860080 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860080 0x20>;
+ };
+
+ qos_sfc: qos@fe860200 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860200 0x20>;
+ };
+
+ qos_sdio: qos@fe86c000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe86c000 0x20>;
+ };
+
+ gic: interrupt-controller@feff0000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xfeff1000 0x1000>,
+ <0xfeff2000 0x2000>,
+ <0xfeff4000 0x2000>,
+ <0xfeff6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pmu: power-management@ff3e0000 {
+ compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
+ reg = <0xff3e0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rv1126-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RV1126_PD_NVM {
+ reg = <RV1126_PD_NVM>;
+ clocks = <&cru HCLK_EMMC>,
+ <&cru CLK_EMMC>,
+ <&cru HCLK_NANDC>,
+ <&cru CLK_NANDC>,
+ <&cru HCLK_SFC>,
+ <&cru HCLK_SFCXIP>,
+ <&cru SCLK_SFC>;
+ pm_qos = <&qos_emmc>,
+ <&qos_nandc>,
+ <&qos_sfc>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RV1126_PD_SDIO {
+ reg = <RV1126_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru CLK_SDIO>;
+ pm_qos = <&qos_sdio>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ i2c0: i2c@ff3f0000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff3f0000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ff400000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff400000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dmac: dma-controller@ff4e0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff4e0000 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+
+ uart1: serial@ff410000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff410000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 7>, <&dmac 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ i2c1: i2c@ff510000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff510000 0x1000>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ff520000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff520000 0x1000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ff530000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff530000 0x1000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ff540000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff540000 0x1000>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@ff560000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff560000 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 5>, <&dmac 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff570000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff570000 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 9>, <&dmac 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff580000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff580000 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 11>, <&dmac 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff590000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff590000 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 13>, <&dmac 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff5a0000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff5a0000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ dmas = <&dmac 15>, <&dmac 14>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ saradc: saradc@ff5e0000 {
+ compatible = "rockchip,rk3399-saradc";
+ reg = <0xff5e0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC_P>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ timer: timer@ff660000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0xff660000 0x20>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ emmc: mmc@ffc50000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc50000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_NVM>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc60000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc60000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdio: mmc@ffc70000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc70000 0x4000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_SDIO>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1126-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@ff460000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff460000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff620000 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff630000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@ff640000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff640000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio4@ff650000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff650000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rv1126-pinctrl.dtsi"
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edgeble AI is an Artificial Intelligence company with a focus
on deploying Neural Acceleration principles at the Edge.
Add vendor prefix for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 0496773a3c4d..d2b8ef2e1ea5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -356,6 +356,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
+ "^edgeble,.*":
+ description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edgeble AI is an Artificial Intelligence company with a focus
on deploying Neural Acceleration principles at the Edge.
Add vendor prefix for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 0496773a3c4d..d2b8ef2e1ea5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -356,6 +356,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
+ "^edgeble,.*":
+ description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edgeble AI is an Artificial Intelligence company with a focus
on deploying Neural Acceleration principles at the Edge.
Add vendor prefix for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 0496773a3c4d..d2b8ef2e1ea5 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -356,6 +356,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
+ "^edgeble,.*":
+ description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
Edge Compute Module 0 Carrier board is an industrial form factor
evaluation board from Edgeble AI.
Edge Compute Module 0 needs to mount on top of this evaluation board
for creating complete Edge Compute Module 0 Carrier board.
Add dt-bindings for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index cf9eb1e8326a..2a4b7f2d018f 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -65,6 +65,12 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
+ - description: Edgeble AI Edge Compute Module 0 SoM based boards
+ items:
+ - const: edgeble,edge-compute-module-0-carrier # Edgeble AI Edge Compute Module 0 Carrier
+ - const: edgeble,edge-compute-module-0 # Edgeble AI Edge Compute Module 0 SoM
+ - const: rockchip,rv1126
+
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
Edge Compute Module 0 Carrier board is an industrial form factor
evaluation board from Edgeble AI.
Edge Compute Module 0 needs to mount on top of this evaluation board
for creating complete Edge Compute Module 0 Carrier board.
Add dt-bindings for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index cf9eb1e8326a..2a4b7f2d018f 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -65,6 +65,12 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
+ - description: Edgeble AI Edge Compute Module 0 SoM based boards
+ items:
+ - const: edgeble,edge-compute-module-0-carrier # Edgeble AI Edge Compute Module 0 Carrier
+ - const: edgeble,edge-compute-module-0 # Edgeble AI Edge Compute Module 0 SoM
+ - const: rockchip,rv1126
+
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
Edge Compute Module 0 Carrier board is an industrial form factor
evaluation board from Edgeble AI.
Edge Compute Module 0 needs to mount on top of this evaluation board
for creating complete Edge Compute Module 0 Carrier board.
Add dt-bindings for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index cf9eb1e8326a..2a4b7f2d018f 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -65,6 +65,12 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
+ - description: Edgeble AI Edge Compute Module 0 SoM based boards
+ items:
+ - const: edgeble,edge-compute-module-0-carrier # Edgeble AI Edge Compute Module 0 Carrier
+ - const: edgeble,edge-compute-module-0 # Edgeble AI Edge Compute Module 0 SoM
+ - const: rockchip,rv1126
+
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 20/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 16GB eMMC
- Fn-link 8223A-SR WiFi/BT
Edge Compute Module 0 needs to mount on top of Edgeble AI Carrier
boards for creating complete platform solutions.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../dts/rv1126-edge-compute-module-0.dtsi | 329 ++++++++++++++++++
1 file changed, 329 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
diff --git a/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi b/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
new file mode 100644
index 000000000000..c98232dd2521
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,edge-compute-module-0", "rockchip,rv1126";
+
+ aliases {
+ mmc0 = &emmc;
+ };
+
+ vcc5v0_sys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccio_flash: vccio-flash {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_vol_sel>;
+ regulator-name = "vccio_flash";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_flash>;
+ rockchip,default-sample-phase = <90>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_buck5>;
+ vcc6-supply = <&vcc_buck5>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_npu_vepu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu_vepu";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_arm";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc3v3_sys";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_buck5: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-name = "vcc_buck5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2200000>;
+ };
+ };
+
+ vcc_0v8: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc_0v8";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd0v8_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc0v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_dovdd: LDO_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_dovdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_dvdd: LDO_REG6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc_dvdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_avdd: LDO_REG7 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc_avdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_5v0: SWITCH_REG1 {
+ regulator-name = "vcc_5v0";
+ };
+
+ vcc_3v3: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ flash {
+ flash_vol_sel: flash-vol-sel {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio0-supply = <&vcc1v8_pmu>;
+ pmuio1-supply = <&vcc3v3_sys>;
+ vccio1-supply = <&vccio_flash>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_1v8>;
+ vccio4-supply = <&vcc_dovdd>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_dovdd>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 20/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 16GB eMMC
- Fn-link 8223A-SR WiFi/BT
Edge Compute Module 0 needs to mount on top of Edgeble AI Carrier
boards for creating complete platform solutions.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../dts/rv1126-edge-compute-module-0.dtsi | 329 ++++++++++++++++++
1 file changed, 329 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
diff --git a/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi b/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
new file mode 100644
index 000000000000..c98232dd2521
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,edge-compute-module-0", "rockchip,rv1126";
+
+ aliases {
+ mmc0 = &emmc;
+ };
+
+ vcc5v0_sys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccio_flash: vccio-flash {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_vol_sel>;
+ regulator-name = "vccio_flash";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_flash>;
+ rockchip,default-sample-phase = <90>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_buck5>;
+ vcc6-supply = <&vcc_buck5>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_npu_vepu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu_vepu";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_arm";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc3v3_sys";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_buck5: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-name = "vcc_buck5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2200000>;
+ };
+ };
+
+ vcc_0v8: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc_0v8";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd0v8_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc0v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_dovdd: LDO_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_dovdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_dvdd: LDO_REG6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc_dvdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_avdd: LDO_REG7 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc_avdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_5v0: SWITCH_REG1 {
+ regulator-name = "vcc_5v0";
+ };
+
+ vcc_3v3: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ flash {
+ flash_vol_sel: flash-vol-sel {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio0-supply = <&vcc1v8_pmu>;
+ pmuio1-supply = <&vcc3v3_sys>;
+ vccio1-supply = <&vccio_flash>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_1v8>;
+ vccio4-supply = <&vcc_dovdd>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_dovdd>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 20/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 16GB eMMC
- Fn-link 8223A-SR WiFi/BT
Edge Compute Module 0 needs to mount on top of Edgeble AI Carrier
boards for creating complete platform solutions.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
.../dts/rv1126-edge-compute-module-0.dtsi | 329 ++++++++++++++++++
1 file changed, 329 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
diff --git a/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi b/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
new file mode 100644
index 000000000000..c98232dd2521
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edge-compute-module-0.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,edge-compute-module-0", "rockchip,rv1126";
+
+ aliases {
+ mmc0 = &emmc;
+ };
+
+ vcc5v0_sys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccio_flash: vccio-flash {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_vol_sel>;
+ regulator-name = "vccio_flash";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_flash>;
+ rockchip,default-sample-phase = <90>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_buck5>;
+ vcc6-supply = <&vcc_buck5>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_npu_vepu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu_vepu";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_arm";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc3v3_sys";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_buck5: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-name = "vcc_buck5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2200000>;
+ };
+ };
+
+ vcc_0v8: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc_0v8";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd0v8_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc0v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_dovdd: LDO_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_dovdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_dvdd: LDO_REG6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc_dvdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_avdd: LDO_REG7 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc_avdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_5v0: SWITCH_REG1 {
+ regulator-name = "vcc_5v0";
+ };
+
+ vcc_3v3: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ flash {
+ flash_vol_sel: flash-vol-sel {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio0-supply = <&vcc1v8_pmu>;
+ pmuio1-supply = <&vcc3v3_sys>;
+ vccio1-supply = <&vccio_flash>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_1v8>;
+ vccio4-supply = <&vcc_dovdd>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_dovdd>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 21/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Edge Compute Module 0 needs to mount on top of this Carrier board for
creating Edge Compute Module 0 Carrier platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/boot/dts/Makefile | 1 +
.../rv1126-edge-compute-module-0-carrier.dts | 38 +++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5112f493f494..6a0ba434c1cf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1097,6 +1097,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
+ rv1126-edge-compute-module-0-carrier.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts b/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
new file mode 100644
index 000000000000..b3b6f70c1a9b
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edge-compute-module-0.dtsi"
+
+/ {
+ model = "Edgeble AI Edge Compute Module 0 Carrier board";
+ compatible = "edgeble,edge-compute-module-0-carrier",
+ "edgeble,edge-compute-module-0", "rockchip,rv1126";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 21/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Edge Compute Module 0 needs to mount on top of this Carrier board for
creating Edge Compute Module 0 Carrier platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/boot/dts/Makefile | 1 +
.../rv1126-edge-compute-module-0-carrier.dts | 38 +++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5112f493f494..6a0ba434c1cf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1097,6 +1097,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
+ rv1126-edge-compute-module-0-carrier.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts b/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
new file mode 100644
index 000000000000..b3b6f70c1a9b
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edge-compute-module-0.dtsi"
+
+/ {
+ model = "Edgeble AI Edge Compute Module 0 Carrier board";
+ compatible = "edgeble,edge-compute-module-0-carrier",
+ "edgeble,edge-compute-module-0", "rockchip,rv1126";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 21/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Edge Compute Module 0 needs to mount on top of this Carrier board for
creating Edge Compute Module 0 Carrier platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/boot/dts/Makefile | 1 +
.../rv1126-edge-compute-module-0-carrier.dts | 38 +++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5112f493f494..6a0ba434c1cf 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1097,6 +1097,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
+ rv1126-edge-compute-module-0-carrier.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts b/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
new file mode 100644
index 000000000000..b3b6f70c1a9b
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edge-compute-module-0-carrier.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edge-compute-module-0.dtsi"
+
+/ {
+ model = "Edgeble AI Edge Compute Module 0 Carrier board";
+ compatible = "edgeble,edge-compute-module-0-carrier",
+ "edgeble,edge-compute-module-0", "rockchip,rv1126";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 22/22] ARM: configs: Add RV1126 ECM0 fragment config
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:43 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/configs/rv1126-ecm0.config | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 arch/arm/configs/rv1126-ecm0.config
diff --git a/arch/arm/configs/rv1126-ecm0.config b/arch/arm/configs/rv1126-ecm0.config
new file mode 100644
index 000000000000..8219c2d4d794
--- /dev/null
+++ b/arch/arm/configs/rv1126-ecm0.config
@@ -0,0 +1,3 @@
+CONFIG_RTC_DRV_RK808=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_ROCKCHIP_SARADC=y
--
2.25.1
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 22/22] ARM: configs: Add RV1126 ECM0 fragment config
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/configs/rv1126-ecm0.config | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 arch/arm/configs/rv1126-ecm0.config
diff --git a/arch/arm/configs/rv1126-ecm0.config b/arch/arm/configs/rv1126-ecm0.config
new file mode 100644
index 000000000000..8219c2d4d794
--- /dev/null
+++ b/arch/arm/configs/rv1126-ecm0.config
@@ -0,0 +1,3 @@
+CONFIG_RTC_DRV_RK808=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_ROCKCHIP_SARADC=y
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 144+ messages in thread
* [PATCH 22/22] ARM: configs: Add RV1126 ECM0 fragment config
@ 2022-07-23 20:43 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-23 20:43 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
arch/arm/configs/rv1126-ecm0.config | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 arch/arm/configs/rv1126-ecm0.config
diff --git a/arch/arm/configs/rv1126-ecm0.config b/arch/arm/configs/rv1126-ecm0.config
new file mode 100644
index 000000000000..8219c2d4d794
--- /dev/null
+++ b/arch/arm/configs/rv1126-ecm0.config
@@ -0,0 +1,3 @@
+CONFIG_RTC_DRV_RK808=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_ROCKCHIP_SARADC=y
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 144+ messages in thread
* Re: [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:57 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:57 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 power-controller.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller
@ 2022-07-23 20:57 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:57 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 power-controller.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller
@ 2022-07-23 20:57 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:57 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 power-controller.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../devicetree/bindings/power/rockchip,power-controller.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:58 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:58 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 23/07/2022 22:43, Jagan Teki wrote:
> Add power-domain header for RV1126 SoC from description in TRM.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 include/dt-bindings/power/rv1126-power.h
>
> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> new file mode 100644
> index 000000000000..f15930ff06f7
> --- /dev/null
> +++ b/include/dt-bindings/power/rv1126-power.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
Dual license and a blank line, please.
> +#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
> +#define __DT_BINDINGS_POWER_RV1126_POWER_H__
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-23 20:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:58 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 23/07/2022 22:43, Jagan Teki wrote:
> Add power-domain header for RV1126 SoC from description in TRM.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 include/dt-bindings/power/rv1126-power.h
>
> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> new file mode 100644
> index 000000000000..f15930ff06f7
> --- /dev/null
> +++ b/include/dt-bindings/power/rv1126-power.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
Dual license and a blank line, please.
> +#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
> +#define __DT_BINDINGS_POWER_RV1126_POWER_H__
> +
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-23 20:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:58 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 23/07/2022 22:43, Jagan Teki wrote:
> Add power-domain header for RV1126 SoC from description in TRM.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 include/dt-bindings/power/rv1126-power.h
>
> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> new file mode 100644
> index 000000000000..f15930ff06f7
> --- /dev/null
> +++ b/include/dt-bindings/power/rv1126-power.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
Dual license and a blank line, please.
> +#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
> +#define __DT_BINDINGS_POWER_RV1126_POWER_H__
> +
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:59 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:59 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 PMU IO domains.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../bindings/power/rockchip-io-domain.yaml | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains
@ 2022-07-23 20:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:59 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 PMU IO domains.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../bindings/power/rockchip-io-domain.yaml | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains
@ 2022-07-23 20:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:59 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 PMU IO domains.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../bindings/power/rockchip-io-domain.yaml | 30 +++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 20:59 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:59 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, linux-gpio, Linus Walleij
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 SoC pinctrl support.
>
> Cc: linux-gpio@vger.kernel.org
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
@ 2022-07-23 20:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:59 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, linux-gpio, Linus Walleij
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 SoC pinctrl support.
>
> Cc: linux-gpio@vger.kernel.org
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl
@ 2022-07-23 20:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 20:59 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, linux-gpio, Linus Walleij
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for RV1126 SoC pinctrl support.
>
> Cc: linux-gpio@vger.kernel.org
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 +
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-23 21:01 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 21:01 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, linux-clk,
Michael Turquette, Stephen Boyd
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 clock controller.
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
> new file mode 100644
> index 000000000000..cf4f11709125
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ROCKCHIP RV1126 Family Clock Control Module Binding
s/Binding//
> +
> +maintainers:
> + - Jagan Teki <jagan@edgeble.ai>
> + - Finley Xiao <finley.xiao@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +description: |
You can skip '|'. No formatting in text.
> + The RV1126 clock controller generates the clock and also implements a
> + reset controller for SoC peripherals.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rv1126-cru
> + - rockchip,rv1126-pmucru
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: xin24m
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the "general register files" (GRF),
> + if missing pll rates are not changeable, due to the missing pll
> + lock status.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pmucru: clock-controller@ff480000 {
> + compatible = "rockchip,rv1126-pmucru";
> + reg = <0xff480000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> + - |
> + cru: clock-controller@ff490000 {
> + compatible = "rockchip,rv1126-cru";
> + reg = <0xff490000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
I would keep just one example - they are the same, except compatible.
Less code to manage or to fix later...
With all the changes:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU
@ 2022-07-23 21:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 21:01 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, linux-clk,
Michael Turquette, Stephen Boyd
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 clock controller.
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
> new file mode 100644
> index 000000000000..cf4f11709125
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ROCKCHIP RV1126 Family Clock Control Module Binding
s/Binding//
> +
> +maintainers:
> + - Jagan Teki <jagan@edgeble.ai>
> + - Finley Xiao <finley.xiao@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +description: |
You can skip '|'. No formatting in text.
> + The RV1126 clock controller generates the clock and also implements a
> + reset controller for SoC peripherals.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rv1126-cru
> + - rockchip,rv1126-pmucru
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: xin24m
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the "general register files" (GRF),
> + if missing pll rates are not changeable, due to the missing pll
> + lock status.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pmucru: clock-controller@ff480000 {
> + compatible = "rockchip,rv1126-pmucru";
> + reg = <0xff480000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> + - |
> + cru: clock-controller@ff490000 {
> + compatible = "rockchip,rv1126-cru";
> + reg = <0xff490000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
I would keep just one example - they are the same, except compatible.
Less code to manage or to fix later...
With all the changes:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU
@ 2022-07-23 21:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-23 21:01 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: linux-arm-kernel, linux-rockchip, devicetree, linux-clk,
Michael Turquette, Stephen Boyd
On 23/07/2022 22:43, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 clock controller.
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> .../bindings/clock/rockchip,rv1126-cru.yaml | 70 +++++++++++++++++++
> 1 file changed, 70 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
> new file mode 100644
> index 000000000000..cf4f11709125
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,rv1126-cru.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rv1126-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ROCKCHIP RV1126 Family Clock Control Module Binding
s/Binding//
> +
> +maintainers:
> + - Jagan Teki <jagan@edgeble.ai>
> + - Finley Xiao <finley.xiao@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> +
> +description: |
You can skip '|'. No formatting in text.
> + The RV1126 clock controller generates the clock and also implements a
> + reset controller for SoC peripherals.
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rv1126-cru
> + - rockchip,rv1126-pmucru
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: xin24m
> +
> + rockchip,grf:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the syscon managing the "general register files" (GRF),
> + if missing pll rates are not changeable, due to the missing pll
> + lock status.
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pmucru: clock-controller@ff480000 {
> + compatible = "rockchip,rv1126-pmucru";
> + reg = <0xff480000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> + - |
> + cru: clock-controller@ff490000 {
> + compatible = "rockchip,rv1126-cru";
> + reg = <0xff490000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
I would keep just one example - they are the same, except compatible.
Less code to manage or to fix later...
With all the changes:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 1:31 ` kernel test robot
-1 siblings, 0 replies; 144+ messages in thread
From: kernel test robot @ 2022-07-25 1:31 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: llvm, kbuild-all, linux-arm-kernel, linux-rockchip, devicetree,
Jagan Teki, linux-clk, Michael Turquette, Stephen Boyd,
Finley Xiao
Hi Jagan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on rockchip/for-next]
[also build test WARNING on robh/for-next linusw-pinctrl/devel clk/clk-next lee-mfd/for-mfd-next soc/for-next linus/master v5.19-rc8 next-20220722]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jagan-Teki/ARM-Add-Rockchip-RV1126-support/20220724-044645
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm64-randconfig-r034-20220724 (https://download.01.org/0day-ci/archive/20220725/202207250930.PM0gI4EI-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 12fbd2d377e396ad61bce56d71c98a1eb1bebfa9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/bf47ecd1af07018e35b815e7a40172dce3fffdb6
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jagan-Teki/ARM-Add-Rockchip-RV1126-support/20220724-044645
git checkout bf47ecd1af07018e35b815e7a40172dce3fffdb6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/clk/rockchip/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/rockchip/clk-rv1126.c:176:7: warning: unused variable 'mux_cpll_hpll_gpll_p' [-Wunused-const-variable]
PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:177:7: warning: unused variable 'mux_cpll_gpll_hpll_p' [-Wunused-const-variable]
PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:178:7: warning: unused variable 'mux_dclk_vop_p' [-Wunused-const-variable]
PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
^
>> drivers/clk/rockchip/clk-rv1126.c:179:7: warning: unused variable 'mux_aclk_pdvi_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:180:7: warning: unused variable 'mux_gpll_cpll_hpll_p' [-Wunused-const-variable]
PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:181:7: warning: unused variable 'mux_clk_isp_p' [-Wunused-const-variable]
PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:182:7: warning: unused variable 'mux_gpll_usb480m_p' [-Wunused-const-variable]
PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
^
>> drivers/clk/rockchip/clk-rv1126.c:183:7: warning: unused variable 'mux_cif_out2io_p' [-Wunused-const-variable]
PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
^
>> drivers/clk/rockchip/clk-rv1126.c:184:7: warning: unused variable 'mux_mipicsi_out2io_p' [-Wunused-const-variable]
PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
^
>> drivers/clk/rockchip/clk-rv1126.c:185:7: warning: unused variable 'mux_aclk_pdispp_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
^
>> drivers/clk/rockchip/clk-rv1126.c:186:7: warning: unused variable 'mux_clk_ispp_p' [-Wunused-const-variable]
PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
^
>> drivers/clk/rockchip/clk-rv1126.c:195:7: warning: unused variable 'mux_gpll_cpll_apll_hpll_p' [-Wunused-const-variable]
PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:196:7: warning: unused variable 'mux_aclk_pdnpu_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:197:7: warning: unused variable 'mux_clk_npu_p' [-Wunused-const-variable]
PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
^
14 warnings generated.
vim +/mux_cpll_hpll_gpll_p +176 drivers/clk/rockchip/clk-rv1126.c
142
143 PNAME(mux_pll_p) = { "xin24m" };
144 PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
145 PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
146 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
147 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
148 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
149 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
150 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
151 PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
152 PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
153 PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
154 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
155 PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
156 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
157 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
158 PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
159 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
160 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
161 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
162 PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
163 PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
164 PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
165 PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
166 PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
167 PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
168 PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
169 PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
170 PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
171 PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
172 PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
173 PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
174 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
175 PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
> 176 PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
> 177 PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
> 178 PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
> 179 PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
> 180 PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
> 181 PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
> 182 PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
> 183 PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
> 184 PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
> 185 PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
> 186 PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
187 PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
188 PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
189 PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
190 PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
191 PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
192 PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
193 PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
194 PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
> 195 PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
> 196 PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
> 197 PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
198
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
@ 2022-07-25 1:31 ` kernel test robot
0 siblings, 0 replies; 144+ messages in thread
From: kernel test robot @ 2022-07-25 1:31 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: llvm, kbuild-all, linux-arm-kernel, linux-rockchip, devicetree,
Jagan Teki, linux-clk, Michael Turquette, Stephen Boyd,
Finley Xiao
Hi Jagan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on rockchip/for-next]
[also build test WARNING on robh/for-next linusw-pinctrl/devel clk/clk-next lee-mfd/for-mfd-next soc/for-next linus/master v5.19-rc8 next-20220722]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jagan-Teki/ARM-Add-Rockchip-RV1126-support/20220724-044645
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm64-randconfig-r034-20220724 (https://download.01.org/0day-ci/archive/20220725/202207250930.PM0gI4EI-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 12fbd2d377e396ad61bce56d71c98a1eb1bebfa9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/bf47ecd1af07018e35b815e7a40172dce3fffdb6
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jagan-Teki/ARM-Add-Rockchip-RV1126-support/20220724-044645
git checkout bf47ecd1af07018e35b815e7a40172dce3fffdb6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/clk/rockchip/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/rockchip/clk-rv1126.c:176:7: warning: unused variable 'mux_cpll_hpll_gpll_p' [-Wunused-const-variable]
PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:177:7: warning: unused variable 'mux_cpll_gpll_hpll_p' [-Wunused-const-variable]
PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:178:7: warning: unused variable 'mux_dclk_vop_p' [-Wunused-const-variable]
PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
^
>> drivers/clk/rockchip/clk-rv1126.c:179:7: warning: unused variable 'mux_aclk_pdvi_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:180:7: warning: unused variable 'mux_gpll_cpll_hpll_p' [-Wunused-const-variable]
PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:181:7: warning: unused variable 'mux_clk_isp_p' [-Wunused-const-variable]
PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:182:7: warning: unused variable 'mux_gpll_usb480m_p' [-Wunused-const-variable]
PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
^
>> drivers/clk/rockchip/clk-rv1126.c:183:7: warning: unused variable 'mux_cif_out2io_p' [-Wunused-const-variable]
PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
^
>> drivers/clk/rockchip/clk-rv1126.c:184:7: warning: unused variable 'mux_mipicsi_out2io_p' [-Wunused-const-variable]
PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
^
>> drivers/clk/rockchip/clk-rv1126.c:185:7: warning: unused variable 'mux_aclk_pdispp_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
^
>> drivers/clk/rockchip/clk-rv1126.c:186:7: warning: unused variable 'mux_clk_ispp_p' [-Wunused-const-variable]
PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
^
>> drivers/clk/rockchip/clk-rv1126.c:195:7: warning: unused variable 'mux_gpll_cpll_apll_hpll_p' [-Wunused-const-variable]
PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:196:7: warning: unused variable 'mux_aclk_pdnpu_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:197:7: warning: unused variable 'mux_clk_npu_p' [-Wunused-const-variable]
PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
^
14 warnings generated.
vim +/mux_cpll_hpll_gpll_p +176 drivers/clk/rockchip/clk-rv1126.c
142
143 PNAME(mux_pll_p) = { "xin24m" };
144 PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
145 PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
146 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
147 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
148 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
149 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
150 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
151 PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
152 PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
153 PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
154 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
155 PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
156 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
157 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
158 PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
159 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
160 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
161 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
162 PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
163 PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
164 PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
165 PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
166 PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
167 PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
168 PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
169 PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
170 PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
171 PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
172 PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
173 PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
174 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
175 PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
> 176 PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
> 177 PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
> 178 PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
> 179 PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
> 180 PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
> 181 PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
> 182 PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
> 183 PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
> 184 PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
> 185 PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
> 186 PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
187 PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
188 PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
189 PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
190 PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
191 PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
192 PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
193 PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
194 PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
> 195 PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
> 196 PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
> 197 PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
198
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
@ 2022-07-25 1:31 ` kernel test robot
0 siblings, 0 replies; 144+ messages in thread
From: kernel test robot @ 2022-07-25 1:31 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang
Cc: llvm, kbuild-all, linux-arm-kernel, linux-rockchip, devicetree,
Jagan Teki, linux-clk, Michael Turquette, Stephen Boyd,
Finley Xiao
Hi Jagan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on rockchip/for-next]
[also build test WARNING on robh/for-next linusw-pinctrl/devel clk/clk-next lee-mfd/for-mfd-next soc/for-next linus/master v5.19-rc8 next-20220722]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Jagan-Teki/ARM-Add-Rockchip-RV1126-support/20220724-044645
base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: arm64-randconfig-r034-20220724 (https://download.01.org/0day-ci/archive/20220725/202207250930.PM0gI4EI-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 12fbd2d377e396ad61bce56d71c98a1eb1bebfa9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/bf47ecd1af07018e35b815e7a40172dce3fffdb6
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jagan-Teki/ARM-Add-Rockchip-RV1126-support/20220724-044645
git checkout bf47ecd1af07018e35b815e7a40172dce3fffdb6
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/clk/rockchip/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/rockchip/clk-rv1126.c:176:7: warning: unused variable 'mux_cpll_hpll_gpll_p' [-Wunused-const-variable]
PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:177:7: warning: unused variable 'mux_cpll_gpll_hpll_p' [-Wunused-const-variable]
PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:178:7: warning: unused variable 'mux_dclk_vop_p' [-Wunused-const-variable]
PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
^
>> drivers/clk/rockchip/clk-rv1126.c:179:7: warning: unused variable 'mux_aclk_pdvi_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:180:7: warning: unused variable 'mux_gpll_cpll_hpll_p' [-Wunused-const-variable]
PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:181:7: warning: unused variable 'mux_clk_isp_p' [-Wunused-const-variable]
PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:182:7: warning: unused variable 'mux_gpll_usb480m_p' [-Wunused-const-variable]
PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
^
>> drivers/clk/rockchip/clk-rv1126.c:183:7: warning: unused variable 'mux_cif_out2io_p' [-Wunused-const-variable]
PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
^
>> drivers/clk/rockchip/clk-rv1126.c:184:7: warning: unused variable 'mux_mipicsi_out2io_p' [-Wunused-const-variable]
PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
^
>> drivers/clk/rockchip/clk-rv1126.c:185:7: warning: unused variable 'mux_aclk_pdispp_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
^
>> drivers/clk/rockchip/clk-rv1126.c:186:7: warning: unused variable 'mux_clk_ispp_p' [-Wunused-const-variable]
PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
^
>> drivers/clk/rockchip/clk-rv1126.c:195:7: warning: unused variable 'mux_gpll_cpll_apll_hpll_p' [-Wunused-const-variable]
PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
^
>> drivers/clk/rockchip/clk-rv1126.c:196:7: warning: unused variable 'mux_aclk_pdnpu_p' [-Wunused-const-variable]
PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
^
>> drivers/clk/rockchip/clk-rv1126.c:197:7: warning: unused variable 'mux_clk_npu_p' [-Wunused-const-variable]
PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
^
14 warnings generated.
vim +/mux_cpll_hpll_gpll_p +176 drivers/clk/rockchip/clk-rv1126.c
142
143 PNAME(mux_pll_p) = { "xin24m" };
144 PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" };
145 PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" };
146 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
147 PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" };
148 PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" };
149 PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" };
150 PNAME(mux_xin24m_32k_p) = { "xin24m", "clk_rtc32k" };
151 PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" };
152 PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" };
153 PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" };
154 PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" };
155 PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" };
156 PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" };
157 PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
158 PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" };
159 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
160 PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" };
161 PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" };
162 PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" };
163 PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" };
164 PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" };
165 PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" };
166 PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" };
167 PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" };
168 PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" };
169 PNAME(mux_i2s0_rx_out2io_p) = { "mclk_i2s0_rx", "xin12m" };
170 PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xin12m" };
171 PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" };
172 PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" };
173 PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
174 PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
175 PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
> 176 PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" };
> 177 PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" };
> 178 PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
> 179 PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" };
> 180 PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" };
> 181 PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" };
> 182 PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" };
> 183 PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" };
> 184 PNAME(mux_mipicsi_out2io_p) = { "xin24m", "clk_mipicsi_out2io_div", "clk_mipicsi_out2io_fracdiv" };
> 185 PNAME(mux_aclk_pdispp_p) = { "aclk_pdispp_div", "aclk_pdispp_npu" };
> 186 PNAME(mux_clk_ispp_p) = { "clk_ispp_div", "clk_ispp_npu" };
187 PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
188 PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
189 PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
190 PNAME(mux_clk_gmac_src_p) = { "clk_gmac_src_m0", "clk_gmac_src_m1" };
191 PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_tx_src", "clk_gmac_tx_src"};
192 PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" };
193 PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" };
194 PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" };
> 195 PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" };
> 196 PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" };
> 197 PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" };
198
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:25 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:25 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-clk,
Michael Turquette, Stephen Boyd, Finley Xiao
On Sun, Jul 24, 2022 at 02:13:23AM +0530, Jagan Teki wrote:
> Add clock controller support for RV1126 SoC.
>
> Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
> and CRU_PMU blocks.
>
> This patch is trying to add minimal Clock-Architecture Diagram's
> inferred from [1] authored by Finley Xiao.
>
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> drivers/clk/rockchip/Kconfig | 7 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk-rv1126.c | 1107 ++++++++++++++++++++++++
> drivers/clk/rockchip/clk.h | 19 +
> include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++++++
This goes with the binding patch.
> 5 files changed, 1766 insertions(+)
> create mode 100644 drivers/clk/rockchip/clk-rv1126.c
> create mode 100644 include/dt-bindings/clock/rv1126-cru.h
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
@ 2022-07-25 23:25 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:25 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-clk,
Michael Turquette, Stephen Boyd, Finley Xiao
On Sun, Jul 24, 2022 at 02:13:23AM +0530, Jagan Teki wrote:
> Add clock controller support for RV1126 SoC.
>
> Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
> and CRU_PMU blocks.
>
> This patch is trying to add minimal Clock-Architecture Diagram's
> inferred from [1] authored by Finley Xiao.
>
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> drivers/clk/rockchip/Kconfig | 7 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk-rv1126.c | 1107 ++++++++++++++++++++++++
> drivers/clk/rockchip/clk.h | 19 +
> include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++++++
This goes with the binding patch.
> 5 files changed, 1766 insertions(+)
> create mode 100644 drivers/clk/rockchip/clk-rv1126.c
> create mode 100644 include/dt-bindings/clock/rv1126-cru.h
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 10/22] clk: rockchip: Add RV1126 clock controller
@ 2022-07-25 23:25 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:25 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-clk,
Michael Turquette, Stephen Boyd, Finley Xiao
On Sun, Jul 24, 2022 at 02:13:23AM +0530, Jagan Teki wrote:
> Add clock controller support for RV1126 SoC.
>
> Clock & Reset Unit (CRU) in RV1126 support clocks for CRU
> and CRU_PMU blocks.
>
> This patch is trying to add minimal Clock-Architecture Diagram's
> inferred from [1] authored by Finley Xiao.
>
> [1] https://github.com/rockchip-linux/kernel/blob/develop-4.19/drivers/clk/rockchip/clk-rv1126.c
>
> Cc: linux-clk@vger.kernel.org
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> drivers/clk/rockchip/Kconfig | 7 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk-rv1126.c | 1107 ++++++++++++++++++++++++
> drivers/clk/rockchip/clk.h | 19 +
> include/dt-bindings/clock/rv1126-cru.h | 632 ++++++++++++++
This goes with the binding patch.
> 5 files changed, 1766 insertions(+)
> create mode 100644 drivers/clk/rockchip/clk-rv1126.c
> create mode 100644 include/dt-bindings/clock/rv1126-cru.h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:25 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:25 UTC (permalink / raw)
To: Jagan Teki
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
Kever Yang, Heiko Stuebner, linux-rockchip, devicetree,
linux-mmc
On Sun, 24 Jul 2022 02:13:24 +0530, Jagan Teki wrote:
> Add a compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-mmc@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
@ 2022-07-25 23:25 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:25 UTC (permalink / raw)
To: Jagan Teki
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
Kever Yang, Heiko Stuebner, linux-rockchip, devicetree,
linux-mmc
On Sun, 24 Jul 2022 02:13:24 +0530, Jagan Teki wrote:
> Add a compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-mmc@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
@ 2022-07-25 23:25 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:25 UTC (permalink / raw)
To: Jagan Teki
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel,
Kever Yang, Heiko Stuebner, linux-rockchip, devicetree,
linux-mmc
On Sun, 24 Jul 2022 02:13:24 +0530, Jagan Teki wrote:
> Add a compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-mmc@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:26 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Rob Herring, linux-arm-kernel, Kever Yang, linux-serial,
Heiko Stuebner, linux-rockchip, Krzysztof Kozlowski,
Greg Kroah-Hartman, devicetree
On Sun, 24 Jul 2022 02:13:25 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-serial@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Rob Herring, linux-arm-kernel, Kever Yang, linux-serial,
Heiko Stuebner, linux-rockchip, Krzysztof Kozlowski,
Greg Kroah-Hartman, devicetree
On Sun, 24 Jul 2022 02:13:25 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-serial@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: Document Rockchip RV1126
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Rob Herring, linux-arm-kernel, Kever Yang, linux-serial,
Heiko Stuebner, linux-rockchip, Krzysztof Kozlowski,
Greg Kroah-Hartman, devicetree
On Sun, 24 Jul 2022 02:13:25 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-serial@vger.kernel.org
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:26 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, Rob Herring, linux-rockchip, Kever Yang,
devicetree, linux-arm-kernel, linux-i2c, Heiko Stuebner
On Sun, 24 Jul 2022 02:13:26 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, Rob Herring, linux-rockchip, Kever Yang,
devicetree, linux-arm-kernel, linux-i2c, Heiko Stuebner
On Sun, 24 Jul 2022 02:13:26 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, Rob Herring, linux-rockchip, Kever Yang,
devicetree, linux-arm-kernel, linux-i2c, Heiko Stuebner
On Sun, 24 Jul 2022 02:13:26 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:26 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: devicetree, linux-rockchip, Rob Herring, Heiko Stuebner,
Krzysztof Kozlowski, linux-arm-kernel, Kever Yang
On Sun, 24 Jul 2022 02:13:27 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 grf.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: devicetree, linux-rockchip, Rob Herring, Heiko Stuebner,
Krzysztof Kozlowski, linux-arm-kernel, Kever Yang
On Sun, 24 Jul 2022 02:13:27 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 grf.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: devicetree, linux-rockchip, Rob Herring, Heiko Stuebner,
Krzysztof Kozlowski, linux-arm-kernel, Kever Yang
On Sun, 24 Jul 2022 02:13:27 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 grf.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:26 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, Kever Yang, Rob Herring, devicetree,
Heiko Stuebner, linux-arm-kernel, linux-rockchip
On Sun, 24 Jul 2022 02:13:28 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 pmugrf.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, Kever Yang, Rob Herring, devicetree,
Heiko Stuebner, linux-arm-kernel, linux-rockchip
On Sun, 24 Jul 2022 02:13:28 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 pmugrf.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, Kever Yang, Rob Herring, devicetree,
Heiko Stuebner, linux-arm-kernel, linux-rockchip
On Sun, 24 Jul 2022 02:13:28 +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 pmugrf.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:26 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: linux-rockchip, Rob Herring, linux-arm-kernel,
Krzysztof Kozlowski, Heiko Stuebner, Lee Jones, Kever Yang,
devicetree
On Sun, 24 Jul 2022 02:13:29 +0530, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 QoS registers.
>
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: linux-rockchip, Rob Herring, linux-arm-kernel,
Krzysztof Kozlowski, Heiko Stuebner, Lee Jones, Kever Yang,
devicetree
On Sun, 24 Jul 2022 02:13:29 +0530, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 QoS registers.
>
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
@ 2022-07-25 23:26 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:26 UTC (permalink / raw)
To: Jagan Teki
Cc: linux-rockchip, Rob Herring, linux-arm-kernel,
Krzysztof Kozlowski, Heiko Stuebner, Lee Jones, Kever Yang,
devicetree
On Sun, 24 Jul 2022 02:13:29 +0530, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 QoS registers.
>
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:27 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, linux-rockchip, Rob Herring, Kever Yang,
devicetree, Krzysztof Kozlowski, linux-arm-kernel
On Sun, 24 Jul 2022 02:13:31 +0530, Jagan Teki wrote:
> Edgeble AI is an Artificial Intelligence company with a focus
> on deploying Neural Acceleration principles at the Edge.
>
> Add vendor prefix for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
@ 2022-07-25 23:27 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, linux-rockchip, Rob Herring, Kever Yang,
devicetree, Krzysztof Kozlowski, linux-arm-kernel
On Sun, 24 Jul 2022 02:13:31 +0530, Jagan Teki wrote:
> Edgeble AI is an Artificial Intelligence company with a focus
> on deploying Neural Acceleration principles at the Edge.
>
> Add vendor prefix for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
@ 2022-07-25 23:27 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, linux-rockchip, Rob Herring, Kever Yang,
devicetree, Krzysztof Kozlowski, linux-arm-kernel
On Sun, 24 Jul 2022 02:13:31 +0530, Jagan Teki wrote:
> Edgeble AI is an Artificial Intelligence company with a focus
> on deploying Neural Acceleration principles at the Edge.
>
> Add vendor prefix for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-25 23:27 ` Rob Herring
-1 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Krzysztof Kozlowski, Kever Yang, devicetree,
Rob Herring, linux-arm-kernel, linux-rockchip
On Sun, 24 Jul 2022 02:13:32 +0530, Jagan Teki wrote:
> Edge Compute Module 0 is a 96boards SoM-CB compute module based
> on Rockchip RV1126 from Edgeble AI.
>
> Edge Compute Module 0 Carrier board is an industrial form factor
> evaluation board from Edgeble AI.
>
> Edge Compute Module 0 needs to mount on top of this evaluation board
> for creating complete Edge Compute Module 0 Carrier board.
>
> Add dt-bindings for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
@ 2022-07-25 23:27 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Krzysztof Kozlowski, Kever Yang, devicetree,
Rob Herring, linux-arm-kernel, linux-rockchip
On Sun, 24 Jul 2022 02:13:32 +0530, Jagan Teki wrote:
> Edge Compute Module 0 is a 96boards SoM-CB compute module based
> on Rockchip RV1126 from Edgeble AI.
>
> Edge Compute Module 0 Carrier board is an industrial form factor
> evaluation board from Edgeble AI.
>
> Edge Compute Module 0 needs to mount on top of this evaluation board
> for creating complete Edge Compute Module 0 Carrier board.
>
> Add dt-bindings for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier
@ 2022-07-25 23:27 ` Rob Herring
0 siblings, 0 replies; 144+ messages in thread
From: Rob Herring @ 2022-07-25 23:27 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Krzysztof Kozlowski, Kever Yang, devicetree,
Rob Herring, linux-arm-kernel, linux-rockchip
On Sun, 24 Jul 2022 02:13:32 +0530, Jagan Teki wrote:
> Edge Compute Module 0 is a 96boards SoM-CB compute module based
> on Rockchip RV1126 from Edgeble AI.
>
> Edge Compute Module 0 Carrier board is an industrial form factor
> evaluation board from Edgeble AI.
>
> Edge Compute Module 0 needs to mount on top of this evaluation board
> for creating complete Edge Compute Module 0 Carrier board.
>
> Add dt-bindings for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-23 20:58 ` Krzysztof Kozlowski
(?)
@ 2022-07-26 13:44 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-26 13:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 23/07/2022 22:43, Jagan Teki wrote:
> > Add power-domain header for RV1126 SoC from description in TRM.
> >
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> > ---
> > include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 include/dt-bindings/power/rv1126-power.h
> >
> > diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> > new file mode 100644
> > index 000000000000..f15930ff06f7
> > --- /dev/null
> > +++ b/include/dt-bindings/power/rv1126-power.h
> > @@ -0,0 +1,34 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> Dual license and a blank line, please.
Yes, all rockchip power includes (at least here) are GPL-2.0 what is
the issue with it?
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-26 13:44 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-26 13:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 23/07/2022 22:43, Jagan Teki wrote:
> > Add power-domain header for RV1126 SoC from description in TRM.
> >
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> > ---
> > include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 include/dt-bindings/power/rv1126-power.h
> >
> > diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> > new file mode 100644
> > index 000000000000..f15930ff06f7
> > --- /dev/null
> > +++ b/include/dt-bindings/power/rv1126-power.h
> > @@ -0,0 +1,34 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> Dual license and a blank line, please.
Yes, all rockchip power includes (at least here) are GPL-2.0 what is
the issue with it?
Thanks,
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-26 13:44 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-26 13:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 23/07/2022 22:43, Jagan Teki wrote:
> > Add power-domain header for RV1126 SoC from description in TRM.
> >
> > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> > ---
> > include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> > create mode 100644 include/dt-bindings/power/rv1126-power.h
> >
> > diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> > new file mode 100644
> > index 000000000000..f15930ff06f7
> > --- /dev/null
> > +++ b/include/dt-bindings/power/rv1126-power.h
> > @@ -0,0 +1,34 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
>
> Dual license and a blank line, please.
Yes, all rockchip power includes (at least here) are GPL-2.0 what is
the issue with it?
Thanks,
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-26 13:44 ` Jagan Teki
(?)
@ 2022-07-26 13:52 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-26 13:52 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 26/07/2022 15:44, Jagan Teki wrote:
> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 23/07/2022 22:43, Jagan Teki wrote:
>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>
>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>> ---
>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>> 1 file changed, 34 insertions(+)
>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>
>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>> new file mode 100644
>>> index 000000000000..f15930ff06f7
>>> --- /dev/null
>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>> @@ -0,0 +1,34 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>
>> Dual license and a blank line, please.
>
> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> the issue with it?
The headers are part of bindings and all bindings should be dual
licensed, so they can be used in other projects.
Of course if copyright holder does not agree to release it on BSD, then
it would be fine as exception. Also would be fine from us not to accept
such bindings. :)
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-26 13:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-26 13:52 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 26/07/2022 15:44, Jagan Teki wrote:
> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 23/07/2022 22:43, Jagan Teki wrote:
>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>
>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>> ---
>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>> 1 file changed, 34 insertions(+)
>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>
>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>> new file mode 100644
>>> index 000000000000..f15930ff06f7
>>> --- /dev/null
>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>> @@ -0,0 +1,34 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>
>> Dual license and a blank line, please.
>
> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> the issue with it?
The headers are part of bindings and all bindings should be dual
licensed, so they can be used in other projects.
Of course if copyright holder does not agree to release it on BSD, then
it would be fine as exception. Also would be fine from us not to accept
such bindings. :)
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-26 13:52 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-26 13:52 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 26/07/2022 15:44, Jagan Teki wrote:
> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 23/07/2022 22:43, Jagan Teki wrote:
>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>
>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>> ---
>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>> 1 file changed, 34 insertions(+)
>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>
>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>> new file mode 100644
>>> index 000000000000..f15930ff06f7
>>> --- /dev/null
>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>> @@ -0,0 +1,34 @@
>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>
>> Dual license and a blank line, please.
>
> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> the issue with it?
The headers are part of bindings and all bindings should be dual
licensed, so they can be used in other projects.
Of course if copyright holder does not agree to release it on BSD, then
it would be fine as exception. Also would be fine from us not to accept
such bindings. :)
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-26 15:00 ` Ulf Hansson
-1 siblings, 0 replies; 144+ messages in thread
From: Ulf Hansson @ 2022-07-26 15:00 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-mmc
On Sat, 23 Jul 2022 at 22:44, Jagan Teki <jagan@edgeble.ai> wrote:
>
> Add a compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-mmc@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> index 54fb59820d2b..8d888b435817 100644
> --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> @@ -39,6 +39,7 @@ properties:
> - rockchip,rk3399-dw-mshc
> - rockchip,rk3568-dw-mshc
> - rockchip,rv1108-dw-mshc
> + - rockchip,rv1126-dw-mshc
> - const: rockchip,rk3288-dw-mshc
>
> reg:
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
@ 2022-07-26 15:00 ` Ulf Hansson
0 siblings, 0 replies; 144+ messages in thread
From: Ulf Hansson @ 2022-07-26 15:00 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-mmc
On Sat, 23 Jul 2022 at 22:44, Jagan Teki <jagan@edgeble.ai> wrote:
>
> Add a compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-mmc@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> index 54fb59820d2b..8d888b435817 100644
> --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> @@ -39,6 +39,7 @@ properties:
> - rockchip,rk3399-dw-mshc
> - rockchip,rk3568-dw-mshc
> - rockchip,rv1108-dw-mshc
> + - rockchip,rv1126-dw-mshc
> - const: rockchip,rk3288-dw-mshc
>
> reg:
> --
> 2.25.1
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126
@ 2022-07-26 15:00 ` Ulf Hansson
0 siblings, 0 replies; 144+ messages in thread
From: Ulf Hansson @ 2022-07-26 15:00 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-mmc
On Sat, 23 Jul 2022 at 22:44, Jagan Teki <jagan@edgeble.ai> wrote:
>
> Add a compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-mmc@vger.kernel.org
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> index 54fb59820d2b..8d888b435817 100644
> --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
> @@ -39,6 +39,7 @@ properties:
> - rockchip,rk3399-dw-mshc
> - rockchip,rk3568-dw-mshc
> - rockchip,rv1108-dw-mshc
> + - rockchip,rv1126-dw-mshc
> - const: rockchip,rk3288-dw-mshc
>
> reg:
> --
> 2.25.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-07-26 21:10 ` Wolfram Sang
-1 siblings, 0 replies; 144+ messages in thread
From: Wolfram Sang @ 2022-07-26 21:10 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-i2c
[-- Attachment #1: Type: text/plain, Size: 235 bytes --]
On Sun, Jul 24, 2022 at 02:13:26AM +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Applied to for-next, thanks!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
@ 2022-07-26 21:10 ` Wolfram Sang
0 siblings, 0 replies; 144+ messages in thread
From: Wolfram Sang @ 2022-07-26 21:10 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-i2c
[-- Attachment #1.1: Type: text/plain, Size: 235 bytes --]
On Sun, Jul 24, 2022 at 02:13:26AM +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Applied to for-next, thanks!
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 170 bytes --]
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: Document Rockchip RV1126
@ 2022-07-26 21:10 ` Wolfram Sang
0 siblings, 0 replies; 144+ messages in thread
From: Wolfram Sang @ 2022-07-26 21:10 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, linux-i2c
[-- Attachment #1.1: Type: text/plain, Size: 235 bytes --]
On Sun, Jul 24, 2022 at 02:13:26AM +0530, Jagan Teki wrote:
> Document compatible string for Rockchip RV1126 SoC.
>
> Cc: linux-i2c@vger.kernel.org
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Applied to for-next, thanks!
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-26 13:52 ` Krzysztof Kozlowski
(?)
@ 2022-07-27 6:52 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 6:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 15:44, Jagan Teki wrote:
> > On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 23/07/2022 22:43, Jagan Teki wrote:
> >>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>
> >>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>> ---
> >>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>> 1 file changed, 34 insertions(+)
> >>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>
> >>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>> new file mode 100644
> >>> index 000000000000..f15930ff06f7
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>> @@ -0,0 +1,34 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>
> >> Dual license and a blank line, please.
> >
> > Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> > the issue with it?
>
> The headers are part of bindings and all bindings should be dual
> licensed, so they can be used in other projects.
>
> Of course if copyright holder does not agree to release it on BSD, then
> it would be fine as exception. Also would be fine from us not to accept
> such bindings. :)
I don't hold anything here to use dual-licensing. The only thing I'm
wondering here is none of the rockchip power includes (which are
merged) are using dual-licensing they simply have GPL-2.0 which is
used in BSP. Let me know what you suggest?
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 6:52 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 6:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 15:44, Jagan Teki wrote:
> > On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 23/07/2022 22:43, Jagan Teki wrote:
> >>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>
> >>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>> ---
> >>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>> 1 file changed, 34 insertions(+)
> >>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>
> >>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>> new file mode 100644
> >>> index 000000000000..f15930ff06f7
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>> @@ -0,0 +1,34 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>
> >> Dual license and a blank line, please.
> >
> > Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> > the issue with it?
>
> The headers are part of bindings and all bindings should be dual
> licensed, so they can be used in other projects.
>
> Of course if copyright holder does not agree to release it on BSD, then
> it would be fine as exception. Also would be fine from us not to accept
> such bindings. :)
I don't hold anything here to use dual-licensing. The only thing I'm
wondering here is none of the rockchip power includes (which are
merged) are using dual-licensing they simply have GPL-2.0 which is
used in BSP. Let me know what you suggest?
Thanks,
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 6:52 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 6:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 26/07/2022 15:44, Jagan Teki wrote:
> > On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 23/07/2022 22:43, Jagan Teki wrote:
> >>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>
> >>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>> ---
> >>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>> 1 file changed, 34 insertions(+)
> >>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>
> >>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>> new file mode 100644
> >>> index 000000000000..f15930ff06f7
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>> @@ -0,0 +1,34 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>
> >> Dual license and a blank line, please.
> >
> > Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> > the issue with it?
>
> The headers are part of bindings and all bindings should be dual
> licensed, so they can be used in other projects.
>
> Of course if copyright holder does not agree to release it on BSD, then
> it would be fine as exception. Also would be fine from us not to accept
> such bindings. :)
I don't hold anything here to use dual-licensing. The only thing I'm
wondering here is none of the rockchip power includes (which are
merged) are using dual-licensing they simply have GPL-2.0 which is
used in BSP. Let me know what you suggest?
Thanks,
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-27 6:52 ` Jagan Teki
(?)
@ 2022-07-27 7:01 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 7:01 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 27/07/2022 08:52, Jagan Teki wrote:
> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 15:44, Jagan Teki wrote:
>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 23/07/2022 22:43, Jagan Teki wrote:
>>>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>>>
>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>>>> ---
>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>>>> 1 file changed, 34 insertions(+)
>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>>>
>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>>>> new file mode 100644
>>>>> index 000000000000..f15930ff06f7
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>>>> @@ -0,0 +1,34 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>
>>>> Dual license and a blank line, please.
>>>
>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
>>> the issue with it?
>>
>> The headers are part of bindings and all bindings should be dual
>> licensed, so they can be used in other projects.
>>
>> Of course if copyright holder does not agree to release it on BSD, then
>> it would be fine as exception. Also would be fine from us not to accept
>> such bindings. :)
>
> I don't hold anything here to use dual-licensing. The only thing I'm
> wondering here is none of the rockchip power includes (which are
> merged) are using dual-licensing they simply have GPL-2.0 which is
> used in BSP. Let me know what you suggest?
Hm, I think you asked this above and I answered that dual license should
be used. Maybe we misunderstand each other?
Do you include in this header any work which cannot be licensed on BSD
(e.g. is derivative of existing GPL-2 work)?
What other (independent) includes are doing, it's not relevant really.
If they were accepted as single license, then it's a past mistake.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 7:01 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 27/07/2022 08:52, Jagan Teki wrote:
> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 15:44, Jagan Teki wrote:
>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 23/07/2022 22:43, Jagan Teki wrote:
>>>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>>>
>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>>>> ---
>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>>>> 1 file changed, 34 insertions(+)
>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>>>
>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>>>> new file mode 100644
>>>>> index 000000000000..f15930ff06f7
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>>>> @@ -0,0 +1,34 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>
>>>> Dual license and a blank line, please.
>>>
>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
>>> the issue with it?
>>
>> The headers are part of bindings and all bindings should be dual
>> licensed, so they can be used in other projects.
>>
>> Of course if copyright holder does not agree to release it on BSD, then
>> it would be fine as exception. Also would be fine from us not to accept
>> such bindings. :)
>
> I don't hold anything here to use dual-licensing. The only thing I'm
> wondering here is none of the rockchip power includes (which are
> merged) are using dual-licensing they simply have GPL-2.0 which is
> used in BSP. Let me know what you suggest?
Hm, I think you asked this above and I answered that dual license should
be used. Maybe we misunderstand each other?
Do you include in this header any work which cannot be licensed on BSD
(e.g. is derivative of existing GPL-2 work)?
What other (independent) includes are doing, it's not relevant really.
If they were accepted as single license, then it's a past mistake.
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:01 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 7:01 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 27/07/2022 08:52, Jagan Teki wrote:
> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 26/07/2022 15:44, Jagan Teki wrote:
>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 23/07/2022 22:43, Jagan Teki wrote:
>>>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>>>
>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>>>> ---
>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>>>> 1 file changed, 34 insertions(+)
>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>>>
>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>>>> new file mode 100644
>>>>> index 000000000000..f15930ff06f7
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>>>> @@ -0,0 +1,34 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>
>>>> Dual license and a blank line, please.
>>>
>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
>>> the issue with it?
>>
>> The headers are part of bindings and all bindings should be dual
>> licensed, so they can be used in other projects.
>>
>> Of course if copyright holder does not agree to release it on BSD, then
>> it would be fine as exception. Also would be fine from us not to accept
>> such bindings. :)
>
> I don't hold anything here to use dual-licensing. The only thing I'm
> wondering here is none of the rockchip power includes (which are
> merged) are using dual-licensing they simply have GPL-2.0 which is
> used in BSP. Let me know what you suggest?
Hm, I think you asked this above and I answered that dual license should
be used. Maybe we misunderstand each other?
Do you include in this header any work which cannot be licensed on BSD
(e.g. is derivative of existing GPL-2 work)?
What other (independent) includes are doing, it's not relevant really.
If they were accepted as single license, then it's a past mistake.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-27 7:01 ` Krzysztof Kozlowski
(?)
@ 2022-07-27 7:09 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 7:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 08:52, Jagan Teki wrote:
> > On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 15:44, Jagan Teki wrote:
> >>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 23/07/2022 22:43, Jagan Teki wrote:
> >>>>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>>>
> >>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>>>> ---
> >>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>>>> 1 file changed, 34 insertions(+)
> >>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>>>
> >>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>>>> new file mode 100644
> >>>>> index 000000000000..f15930ff06f7
> >>>>> --- /dev/null
> >>>>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>>>> @@ -0,0 +1,34 @@
> >>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>
> >>>> Dual license and a blank line, please.
> >>>
> >>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> >>> the issue with it?
> >>
> >> The headers are part of bindings and all bindings should be dual
> >> licensed, so they can be used in other projects.
> >>
> >> Of course if copyright holder does not agree to release it on BSD, then
> >> it would be fine as exception. Also would be fine from us not to accept
> >> such bindings. :)
> >
> > I don't hold anything here to use dual-licensing. The only thing I'm
> > wondering here is none of the rockchip power includes (which are
> > merged) are using dual-licensing they simply have GPL-2.0 which is
> > used in BSP. Let me know what you suggest?
>
> Hm, I think you asked this above and I answered that dual license should
> be used. Maybe we misunderstand each other?
Sorry, I'm asking again as I'm liable to change the license here or not.
>
> Do you include in this header any work which cannot be licensed on BSD
> (e.g. is derivative of existing GPL-2 work)?
Yes, it is from BSP
https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:09 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 7:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 08:52, Jagan Teki wrote:
> > On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 15:44, Jagan Teki wrote:
> >>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 23/07/2022 22:43, Jagan Teki wrote:
> >>>>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>>>
> >>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>>>> ---
> >>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>>>> 1 file changed, 34 insertions(+)
> >>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>>>
> >>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>>>> new file mode 100644
> >>>>> index 000000000000..f15930ff06f7
> >>>>> --- /dev/null
> >>>>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>>>> @@ -0,0 +1,34 @@
> >>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>
> >>>> Dual license and a blank line, please.
> >>>
> >>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> >>> the issue with it?
> >>
> >> The headers are part of bindings and all bindings should be dual
> >> licensed, so they can be used in other projects.
> >>
> >> Of course if copyright holder does not agree to release it on BSD, then
> >> it would be fine as exception. Also would be fine from us not to accept
> >> such bindings. :)
> >
> > I don't hold anything here to use dual-licensing. The only thing I'm
> > wondering here is none of the rockchip power includes (which are
> > merged) are using dual-licensing they simply have GPL-2.0 which is
> > used in BSP. Let me know what you suggest?
>
> Hm, I think you asked this above and I answered that dual license should
> be used. Maybe we misunderstand each other?
Sorry, I'm asking again as I'm liable to change the license here or not.
>
> Do you include in this header any work which cannot be licensed on BSD
> (e.g. is derivative of existing GPL-2 work)?
Yes, it is from BSP
https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
Thanks,
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:09 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 7:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 08:52, Jagan Teki wrote:
> > On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 26/07/2022 15:44, Jagan Teki wrote:
> >>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 23/07/2022 22:43, Jagan Teki wrote:
> >>>>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>>>
> >>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>>>> ---
> >>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>>>> 1 file changed, 34 insertions(+)
> >>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>>>
> >>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>>>> new file mode 100644
> >>>>> index 000000000000..f15930ff06f7
> >>>>> --- /dev/null
> >>>>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>>>> @@ -0,0 +1,34 @@
> >>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>
> >>>> Dual license and a blank line, please.
> >>>
> >>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> >>> the issue with it?
> >>
> >> The headers are part of bindings and all bindings should be dual
> >> licensed, so they can be used in other projects.
> >>
> >> Of course if copyright holder does not agree to release it on BSD, then
> >> it would be fine as exception. Also would be fine from us not to accept
> >> such bindings. :)
> >
> > I don't hold anything here to use dual-licensing. The only thing I'm
> > wondering here is none of the rockchip power includes (which are
> > merged) are using dual-licensing they simply have GPL-2.0 which is
> > used in BSP. Let me know what you suggest?
>
> Hm, I think you asked this above and I answered that dual license should
> be used. Maybe we misunderstand each other?
Sorry, I'm asking again as I'm liable to change the license here or not.
>
> Do you include in this header any work which cannot be licensed on BSD
> (e.g. is derivative of existing GPL-2 work)?
Yes, it is from BSP
https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
Thanks,
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-27 7:09 ` Jagan Teki
(?)
@ 2022-07-27 7:15 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 7:15 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 27/07/2022 09:09, Jagan Teki wrote:
> On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 27/07/2022 08:52, Jagan Teki wrote:
>>> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 26/07/2022 15:44, Jagan Teki wrote:
>>>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
>>>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>>>
>>>>>> On 23/07/2022 22:43, Jagan Teki wrote:
>>>>>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>>>>>
>>>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>>>>>> ---
>>>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>>>>>> 1 file changed, 34 insertions(+)
>>>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>>>>>
>>>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..f15930ff06f7
>>>>>>> --- /dev/null
>>>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>>>>>> @@ -0,0 +1,34 @@
>>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>>>
>>>>>> Dual license and a blank line, please.
>>>>>
>>>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
>>>>> the issue with it?
>>>>
>>>> The headers are part of bindings and all bindings should be dual
>>>> licensed, so they can be used in other projects.
>>>>
>>>> Of course if copyright holder does not agree to release it on BSD, then
>>>> it would be fine as exception. Also would be fine from us not to accept
>>>> such bindings. :)
>>>
>>> I don't hold anything here to use dual-licensing. The only thing I'm
>>> wondering here is none of the rockchip power includes (which are
>>> merged) are using dual-licensing they simply have GPL-2.0 which is
>>> used in BSP. Let me know what you suggest?
>>
>> Hm, I think you asked this above and I answered that dual license should
>> be used. Maybe we misunderstand each other?
>
> Sorry, I'm asking again as I'm liable to change the license here or not.
>
>>
>> Do you include in this header any work which cannot be licensed on BSD
>> (e.g. is derivative of existing GPL-2 work)?
>
> Yes, it is from BSP
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
Eh... if you don't have permission to relicense it and you copied the
IDs (although one would say it is not really copyrightable work), then
let it be GPL-2.0. In the future just write the IDs by yourself (not as
derivative work) and dual-license the header.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 7:15 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 27/07/2022 09:09, Jagan Teki wrote:
> On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 27/07/2022 08:52, Jagan Teki wrote:
>>> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 26/07/2022 15:44, Jagan Teki wrote:
>>>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
>>>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>>>
>>>>>> On 23/07/2022 22:43, Jagan Teki wrote:
>>>>>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>>>>>
>>>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>>>>>> ---
>>>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>>>>>> 1 file changed, 34 insertions(+)
>>>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>>>>>
>>>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..f15930ff06f7
>>>>>>> --- /dev/null
>>>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>>>>>> @@ -0,0 +1,34 @@
>>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>>>
>>>>>> Dual license and a blank line, please.
>>>>>
>>>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
>>>>> the issue with it?
>>>>
>>>> The headers are part of bindings and all bindings should be dual
>>>> licensed, so they can be used in other projects.
>>>>
>>>> Of course if copyright holder does not agree to release it on BSD, then
>>>> it would be fine as exception. Also would be fine from us not to accept
>>>> such bindings. :)
>>>
>>> I don't hold anything here to use dual-licensing. The only thing I'm
>>> wondering here is none of the rockchip power includes (which are
>>> merged) are using dual-licensing they simply have GPL-2.0 which is
>>> used in BSP. Let me know what you suggest?
>>
>> Hm, I think you asked this above and I answered that dual license should
>> be used. Maybe we misunderstand each other?
>
> Sorry, I'm asking again as I'm liable to change the license here or not.
>
>>
>> Do you include in this header any work which cannot be licensed on BSD
>> (e.g. is derivative of existing GPL-2 work)?
>
> Yes, it is from BSP
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
Eh... if you don't have permission to relicense it and you copied the
IDs (although one would say it is not really copyrightable work), then
let it be GPL-2.0. In the future just write the IDs by yourself (not as
derivative work) and dual-license the header.
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:15 ` Krzysztof Kozlowski
0 siblings, 0 replies; 144+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-27 7:15 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On 27/07/2022 09:09, Jagan Teki wrote:
> On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 27/07/2022 08:52, Jagan Teki wrote:
>>> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 26/07/2022 15:44, Jagan Teki wrote:
>>>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
>>>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>>>
>>>>>> On 23/07/2022 22:43, Jagan Teki wrote:
>>>>>>> Add power-domain header for RV1126 SoC from description in TRM.
>>>>>>>
>>>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>>>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
>>>>>>> ---
>>>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
>>>>>>> 1 file changed, 34 insertions(+)
>>>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
>>>>>>>
>>>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..f15930ff06f7
>>>>>>> --- /dev/null
>>>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
>>>>>>> @@ -0,0 +1,34 @@
>>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
>>>>>>
>>>>>> Dual license and a blank line, please.
>>>>>
>>>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
>>>>> the issue with it?
>>>>
>>>> The headers are part of bindings and all bindings should be dual
>>>> licensed, so they can be used in other projects.
>>>>
>>>> Of course if copyright holder does not agree to release it on BSD, then
>>>> it would be fine as exception. Also would be fine from us not to accept
>>>> such bindings. :)
>>>
>>> I don't hold anything here to use dual-licensing. The only thing I'm
>>> wondering here is none of the rockchip power includes (which are
>>> merged) are using dual-licensing they simply have GPL-2.0 which is
>>> used in BSP. Let me know what you suggest?
>>
>> Hm, I think you asked this above and I answered that dual license should
>> be used. Maybe we misunderstand each other?
>
> Sorry, I'm asking again as I'm liable to change the license here or not.
>
>>
>> Do you include in this header any work which cannot be licensed on BSD
>> (e.g. is derivative of existing GPL-2 work)?
>
> Yes, it is from BSP
> https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
Eh... if you don't have permission to relicense it and you copied the
IDs (although one would say it is not really copyrightable work), then
let it be GPL-2.0. In the future just write the IDs by yourself (not as
derivative work) and dual-license the header.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
2022-07-27 7:15 ` Krzysztof Kozlowski
(?)
@ 2022-07-27 7:31 ` Jagan Teki
-1 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 7:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Wed, 27 Jul 2022 at 12:46, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 09:09, Jagan Teki wrote:
> > On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 27/07/2022 08:52, Jagan Teki wrote:
> >>> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 26/07/2022 15:44, Jagan Teki wrote:
> >>>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> >>>>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>>>
> >>>>>> On 23/07/2022 22:43, Jagan Teki wrote:
> >>>>>>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>>>>>
> >>>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>>>>>> ---
> >>>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>>>>>> 1 file changed, 34 insertions(+)
> >>>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>>>>>
> >>>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>>>>>> new file mode 100644
> >>>>>>> index 000000000000..f15930ff06f7
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>>>>>> @@ -0,0 +1,34 @@
> >>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>>>
> >>>>>> Dual license and a blank line, please.
> >>>>>
> >>>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> >>>>> the issue with it?
> >>>>
> >>>> The headers are part of bindings and all bindings should be dual
> >>>> licensed, so they can be used in other projects.
> >>>>
> >>>> Of course if copyright holder does not agree to release it on BSD, then
> >>>> it would be fine as exception. Also would be fine from us not to accept
> >>>> such bindings. :)
> >>>
> >>> I don't hold anything here to use dual-licensing. The only thing I'm
> >>> wondering here is none of the rockchip power includes (which are
> >>> merged) are using dual-licensing they simply have GPL-2.0 which is
> >>> used in BSP. Let me know what you suggest?
> >>
> >> Hm, I think you asked this above and I answered that dual license should
> >> be used. Maybe we misunderstand each other?
> >
> > Sorry, I'm asking again as I'm liable to change the license here or not.
> >
> >>
> >> Do you include in this header any work which cannot be licensed on BSD
> >> (e.g. is derivative of existing GPL-2 work)?
> >
> > Yes, it is from BSP
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
>
> Eh... if you don't have permission to relicense it and you copied the
> IDs (although one would say it is not really copyrightable work), then
> let it be GPL-2.0. In the future just write the IDs by yourself (not as
> derivative work) and dual-license the header.
Yes, I usually follow the dual-license if I wrote new ones in bindings.
Thanks for the details.
Jagan.
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:31 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 7:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Wed, 27 Jul 2022 at 12:46, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 09:09, Jagan Teki wrote:
> > On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 27/07/2022 08:52, Jagan Teki wrote:
> >>> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 26/07/2022 15:44, Jagan Teki wrote:
> >>>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> >>>>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>>>
> >>>>>> On 23/07/2022 22:43, Jagan Teki wrote:
> >>>>>>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>>>>>
> >>>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>>>>>> ---
> >>>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>>>>>> 1 file changed, 34 insertions(+)
> >>>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>>>>>
> >>>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>>>>>> new file mode 100644
> >>>>>>> index 000000000000..f15930ff06f7
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>>>>>> @@ -0,0 +1,34 @@
> >>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>>>
> >>>>>> Dual license and a blank line, please.
> >>>>>
> >>>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> >>>>> the issue with it?
> >>>>
> >>>> The headers are part of bindings and all bindings should be dual
> >>>> licensed, so they can be used in other projects.
> >>>>
> >>>> Of course if copyright holder does not agree to release it on BSD, then
> >>>> it would be fine as exception. Also would be fine from us not to accept
> >>>> such bindings. :)
> >>>
> >>> I don't hold anything here to use dual-licensing. The only thing I'm
> >>> wondering here is none of the rockchip power includes (which are
> >>> merged) are using dual-licensing they simply have GPL-2.0 which is
> >>> used in BSP. Let me know what you suggest?
> >>
> >> Hm, I think you asked this above and I answered that dual license should
> >> be used. Maybe we misunderstand each other?
> >
> > Sorry, I'm asking again as I'm liable to change the license here or not.
> >
> >>
> >> Do you include in this header any work which cannot be licensed on BSD
> >> (e.g. is derivative of existing GPL-2 work)?
> >
> > Yes, it is from BSP
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
>
> Eh... if you don't have permission to relicense it and you copied the
> IDs (although one would say it is not really copyrightable work), then
> let it be GPL-2.0. In the future just write the IDs by yourself (not as
> derivative work) and dual-license the header.
Yes, I usually follow the dual-license if I wrote new ones in bindings.
Thanks for the details.
Jagan.
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126
@ 2022-07-27 7:31 ` Jagan Teki
0 siblings, 0 replies; 144+ messages in thread
From: Jagan Teki @ 2022-07-27 7:31 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Elaine Zhang
On Wed, 27 Jul 2022 at 12:46, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 27/07/2022 09:09, Jagan Teki wrote:
> > On Wed, 27 Jul 2022 at 12:31, Krzysztof Kozlowski
> > <krzysztof.kozlowski@linaro.org> wrote:
> >>
> >> On 27/07/2022 08:52, Jagan Teki wrote:
> >>> On Tue, 26 Jul 2022 at 19:22, Krzysztof Kozlowski
> >>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>
> >>>> On 26/07/2022 15:44, Jagan Teki wrote:
> >>>>> On Sun, 24 Jul 2022 at 02:28, Krzysztof Kozlowski
> >>>>> <krzysztof.kozlowski@linaro.org> wrote:
> >>>>>>
> >>>>>> On 23/07/2022 22:43, Jagan Teki wrote:
> >>>>>>> Add power-domain header for RV1126 SoC from description in TRM.
> >>>>>>>
> >>>>>>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> >>>>>>> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> >>>>>>> ---
> >>>>>>> include/dt-bindings/power/rv1126-power.h | 34 ++++++++++++++++++++++++
> >>>>>>> 1 file changed, 34 insertions(+)
> >>>>>>> create mode 100644 include/dt-bindings/power/rv1126-power.h
> >>>>>>>
> >>>>>>> diff --git a/include/dt-bindings/power/rv1126-power.h b/include/dt-bindings/power/rv1126-power.h
> >>>>>>> new file mode 100644
> >>>>>>> index 000000000000..f15930ff06f7
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/include/dt-bindings/power/rv1126-power.h
> >>>>>>> @@ -0,0 +1,34 @@
> >>>>>>> +/* SPDX-License-Identifier: GPL-2.0 */
> >>>>>>
> >>>>>> Dual license and a blank line, please.
> >>>>>
> >>>>> Yes, all rockchip power includes (at least here) are GPL-2.0 what is
> >>>>> the issue with it?
> >>>>
> >>>> The headers are part of bindings and all bindings should be dual
> >>>> licensed, so they can be used in other projects.
> >>>>
> >>>> Of course if copyright holder does not agree to release it on BSD, then
> >>>> it would be fine as exception. Also would be fine from us not to accept
> >>>> such bindings. :)
> >>>
> >>> I don't hold anything here to use dual-licensing. The only thing I'm
> >>> wondering here is none of the rockchip power includes (which are
> >>> merged) are using dual-licensing they simply have GPL-2.0 which is
> >>> used in BSP. Let me know what you suggest?
> >>
> >> Hm, I think you asked this above and I answered that dual license should
> >> be used. Maybe we misunderstand each other?
> >
> > Sorry, I'm asking again as I'm liable to change the license here or not.
> >
> >>
> >> Do you include in this header any work which cannot be licensed on BSD
> >> (e.g. is derivative of existing GPL-2 work)?
> >
> > Yes, it is from BSP
> > https://github.com/rockchip-linux/kernel/blob/develop-4.19/include/dt-bindings/power/rv1126-power.h
>
> Eh... if you don't have permission to relicense it and you copied the
> IDs (although one would say it is not really copyrightable work), then
> let it be GPL-2.0. In the future just write the IDs by yourself (not as
> derivative work) and dual-license the header.
Yes, I usually follow the dual-license if I wrote new ones in bindings.
Thanks for the details.
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
2022-07-23 20:43 ` Jagan Teki
(?)
@ 2022-08-08 15:24 ` Lee Jones
-1 siblings, 0 replies; 144+ messages in thread
From: Lee Jones @ 2022-08-08 15:24 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Lee Jones
On Sun, 24 Jul 2022, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 QoS registers.
>
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
DEPRECATED: Please use lee@kernel.org
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
@ 2022-08-08 15:24 ` Lee Jones
0 siblings, 0 replies; 144+ messages in thread
From: Lee Jones @ 2022-08-08 15:24 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Lee Jones
On Sun, 24 Jul 2022, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 QoS registers.
>
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
DEPRECATED: Please use lee@kernel.org
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 144+ messages in thread
* Re: [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register
@ 2022-08-08 15:24 ` Lee Jones
0 siblings, 0 replies; 144+ messages in thread
From: Lee Jones @ 2022-08-08 15:24 UTC (permalink / raw)
To: Jagan Teki
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Kever Yang,
linux-arm-kernel, linux-rockchip, devicetree, Lee Jones
On Sun, 24 Jul 2022, Jagan Teki wrote:
> Document dt-bindings for Rockchip RV1126 QoS registers.
>
> Cc: Lee Jones <lee.jones@linaro.org>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
DEPRECATED: Please use lee@kernel.org
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 144+ messages in thread
end of thread, other threads:[~2022-08-08 15:25 UTC | newest]
Thread overview: 144+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-23 20:43 [PATCH 00/22] ARM: Add Rockchip RV1126 support Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 01/22] dt-bindings: power: rockchip: Document RV1126 power-controller Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:57 ` Krzysztof Kozlowski
2022-07-23 20:57 ` Krzysztof Kozlowski
2022-07-23 20:57 ` Krzysztof Kozlowski
2022-07-23 20:43 ` [PATCH 02/22] dt-bindings: power: Add power-domain header for RV1126 Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:58 ` Krzysztof Kozlowski
2022-07-23 20:58 ` Krzysztof Kozlowski
2022-07-23 20:58 ` Krzysztof Kozlowski
2022-07-26 13:44 ` Jagan Teki
2022-07-26 13:44 ` Jagan Teki
2022-07-26 13:44 ` Jagan Teki
2022-07-26 13:52 ` Krzysztof Kozlowski
2022-07-26 13:52 ` Krzysztof Kozlowski
2022-07-26 13:52 ` Krzysztof Kozlowski
2022-07-27 6:52 ` Jagan Teki
2022-07-27 6:52 ` Jagan Teki
2022-07-27 6:52 ` Jagan Teki
2022-07-27 7:01 ` Krzysztof Kozlowski
2022-07-27 7:01 ` Krzysztof Kozlowski
2022-07-27 7:01 ` Krzysztof Kozlowski
2022-07-27 7:09 ` Jagan Teki
2022-07-27 7:09 ` Jagan Teki
2022-07-27 7:09 ` Jagan Teki
2022-07-27 7:15 ` Krzysztof Kozlowski
2022-07-27 7:15 ` Krzysztof Kozlowski
2022-07-27 7:15 ` Krzysztof Kozlowski
2022-07-27 7:31 ` Jagan Teki
2022-07-27 7:31 ` Jagan Teki
2022-07-27 7:31 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 03/22] soc: rockchip: power-domain: Add RV1126 power domains Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 04/22] dt-bindings: power: rockchip: Document RV1126 PMU IO domains Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:59 ` Krzysztof Kozlowski
2022-07-23 20:59 ` Krzysztof Kozlowski
2022-07-23 20:59 ` Krzysztof Kozlowski
2022-07-23 20:43 ` [PATCH 05/22] soc: rockchip: io-domain: Add RV1126 " Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 06/22] dt-bindings: pinctrl: rockchip: Document RV1126 pinctrl Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:59 ` Krzysztof Kozlowski
2022-07-23 20:59 ` Krzysztof Kozlowski
2022-07-23 20:59 ` Krzysztof Kozlowski
2022-07-23 20:43 ` [PATCH 07/22] pinctrl: rockchip: Add RV1126 pinctrl support Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 08/22] clk: rockchip: Add MUXTBL variant Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 09/22] dt-bindings: clock: rockchip: Document RV1126 CRU Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 21:01 ` Krzysztof Kozlowski
2022-07-23 21:01 ` Krzysztof Kozlowski
2022-07-23 21:01 ` Krzysztof Kozlowski
2022-07-23 20:43 ` [PATCH 10/22] clk: rockchip: Add RV1126 clock controller Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 1:31 ` kernel test robot
2022-07-25 1:31 ` kernel test robot
2022-07-25 1:31 ` kernel test robot
2022-07-25 23:25 ` Rob Herring
2022-07-25 23:25 ` Rob Herring
2022-07-25 23:25 ` Rob Herring
2022-07-23 20:43 ` [PATCH 11/22] dt-bindings: mmc: rockchip-dw-mshc: Document Rockchip RV1126 Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:25 ` Rob Herring
2022-07-25 23:25 ` Rob Herring
2022-07-25 23:25 ` Rob Herring
2022-07-26 15:00 ` Ulf Hansson
2022-07-26 15:00 ` Ulf Hansson
2022-07-26 15:00 ` Ulf Hansson
2022-07-23 20:43 ` [PATCH 12/22] dt-bindings: serial: snps-dw-apb-uart: " Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-23 20:43 ` [PATCH 13/22] dt-bindings: i2c: i2c-rk3x: " Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-26 21:10 ` Wolfram Sang
2022-07-26 21:10 ` Wolfram Sang
2022-07-26 21:10 ` Wolfram Sang
2022-07-23 20:43 ` [PATCH 14/22] dt-bindings: soc: rockchip: Document RV1126 grf Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-23 20:43 ` [PATCH 15/22] dt-bindings: soc: rockchip: Document RV1126 pmugrf Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-23 20:43 ` [PATCH 16/22] dt-bindings: mfd: syscon: Add Rockchip RV1126 QoS register Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-07-25 23:26 ` Rob Herring
2022-08-08 15:24 ` Lee Jones
2022-08-08 15:24 ` Lee Jones
2022-08-08 15:24 ` Lee Jones
2022-07-23 20:43 ` [PATCH 17/22] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 18/22] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:27 ` Rob Herring
2022-07-25 23:27 ` Rob Herring
2022-07-25 23:27 ` Rob Herring
2022-07-23 20:43 ` [PATCH 19/22] dt-bindings: arm: rockchip: Add Edgeble AI Edge Compute Module 0 Carrier Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-25 23:27 ` Rob Herring
2022-07-25 23:27 ` Rob Herring
2022-07-25 23:27 ` Rob Herring
2022-07-23 20:43 ` [PATCH 20/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 21/22] ARM: dts: rockchip: rv1126: Add Edgeble AI Edge Compute Module 0 Carrier Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` [PATCH 22/22] ARM: configs: Add RV1126 ECM0 fragment config Jagan Teki
2022-07-23 20:43 ` Jagan Teki
2022-07-23 20:43 ` Jagan Teki
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.