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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
To: robh+dt@kernel.org
Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org,
	chaotian.jing@mediatek.com, ulf.hansson@linaro.org,
	matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com,
	hsinyi@chromium.org, nfraprado@collabora.com,
	allen-kh.cheng@mediatek.com, fparent@baylibre.com,
	sam.shih@mediatek.com, sean.wang@mediatek.com,
	long.cheng@mediatek.com, wenbin.mei@mediatek.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org,
	~postmarketos/upstreaming@lists.sr.ht
Subject: [PATCH 4/8] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
Date: Fri, 29 Jul 2022 12:44:36 +0200	[thread overview]
Message-ID: <20220729104441.39177-5-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com>

The UART nodes had a dummy clock for early bringup, as it is
expected that these are left on by the bootloader: now that
the pericfg clock controller is supported, we can replace
them with the real clocks.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 9166d481a366..559fec1ee123 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -312,7 +312,8 @@ uart0: serial@11002000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x400>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 
@@ -321,7 +322,8 @@ uart1: serial@11003000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11003000 0 0x400>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 
@@ -330,7 +332,8 @@ uart2: serial@11004000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11004000 0 0x400>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 
@@ -339,7 +342,8 @@ uart3: serial@11005000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11005000 0 0x400>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 	};
-- 
2.35.1


WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: robh+dt@kernel.org
Cc: krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org,
	chaotian.jing@mediatek.com, ulf.hansson@linaro.org,
	matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com,
	hsinyi@chromium.org, nfraprado@collabora.com,
	allen-kh.cheng@mediatek.com, fparent@baylibre.com,
	sam.shih@mediatek.com, sean.wang@mediatek.com,
	long.cheng@mediatek.com, wenbin.mei@mediatek.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, phone-devel@vger.kernel.org,
	~postmarketos/upstreaming@lists.sr.ht
Subject: [PATCH 4/8] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg
Date: Fri, 29 Jul 2022 12:44:36 +0200	[thread overview]
Message-ID: <20220729104441.39177-5-angelogioacchino.delregno@collabora.com> (raw)
In-Reply-To: <20220729104441.39177-1-angelogioacchino.delregno@collabora.com>

The UART nodes had a dummy clock for early bringup, as it is
expected that these are left on by the bootloader: now that
the pericfg clock controller is supported, we can replace
them with the real clocks.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
index 9166d481a366..559fec1ee123 100644
--- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi
@@ -312,7 +312,8 @@ uart0: serial@11002000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11002000 0 0x400>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 
@@ -321,7 +322,8 @@ uart1: serial@11003000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11003000 0 0x400>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 
@@ -330,7 +332,8 @@ uart2: serial@11004000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11004000 0 0x400>;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 
@@ -339,7 +342,8 @@ uart3: serial@11005000 {
 				     "mediatek,mt6577-uart";
 			reg = <0 0x11005000 0 0x400>;
 			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
-			clocks = <&clk26m>;
+			clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
+			clock-names = "baud", "bus";
 			status = "disabled";
 		};
 	};
-- 
2.35.1


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  parent reply	other threads:[~2022-07-29 10:45 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-29 10:44 [PATCH 0/8] MT6795 Devicetrees and Sony Xperia M5 AngeloGioacchino Del Regno
2022-07-29 10:44 ` AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 1/8] dt-bindings: dma: mediatek,uart-dma: Add binding for MT6795 SoC AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-08-02  7:34   ` Krzysztof Kozlowski
2022-08-02  7:34     ` Krzysztof Kozlowski
2022-09-04 17:26   ` Vinod Koul
2022-09-04 17:26     ` Vinod Koul
2022-07-29 10:44 ` [PATCH 2/8] dt-bindings: mmc: Add compatible for MT6795 Helio X10 SoC AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-07-29 23:05   ` Rob Herring
2022-07-29 23:05     ` Rob Herring
2022-08-15 18:28   ` Ulf Hansson
2022-08-15 18:28     ` Ulf Hansson
2022-07-29 10:44 ` [PATCH 3/8] arm64: dts: mediatek: mt6795: Add topckgen, infra, peri clocks/resets AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-07-29 10:44 ` AngeloGioacchino Del Regno [this message]
2022-07-29 10:44   ` [PATCH 4/8] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 5/8] arm64: dts: mediatek: mt6795: Add support for APDMA and wire up UART DMAs AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 6/8] arm64: dts: mediatek: mt6795: Add support for eMMC/SD/SDIO controllers AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 7/7] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-07-29 12:00   ` Konrad Dybcio
2022-07-29 12:00     ` Konrad Dybcio
2022-10-27  9:28     ` AngeloGioacchino Del Regno
2022-10-27  9:28       ` AngeloGioacchino Del Regno
2022-10-27  9:40       ` Konrad Dybcio
2022-10-27  9:40         ` Konrad Dybcio
2022-10-27 10:01         ` AngeloGioacchino Del Regno
2022-10-27 10:01           ` AngeloGioacchino Del Regno
2022-07-29 10:44 ` [PATCH 7/8] dt-bindings: arm: mediatek: Add compatible for MT6795 Sony Xperia M5 AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno
2022-07-29 23:05   ` Rob Herring
2022-07-29 23:05     ` Rob Herring
2022-07-29 10:44 ` [PATCH 8/8] arm64: dts: mediatek: Add support for MT6795 Sony Xperia M5 smartphone AngeloGioacchino Del Regno
2022-07-29 10:44   ` AngeloGioacchino Del Regno

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