From: Naveen Mamindlapalli <naveenm@marvell.com>
To: <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
<pabeni@redhat.com>, <richardcochran@gmail.com>,
<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sgoutham@marvell.com>
Cc: Naveen Mamindlapalli <naveenm@marvell.com>
Subject: [net-next PATCH v2 4/4] octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly
Date: Sat, 30 Jul 2022 17:27:58 +0530 [thread overview]
Message-ID: <20220730115758.16787-5-naveenm@marvell.com> (raw)
In-Reply-To: <20220730115758.16787-1-naveenm@marvell.com>
Since the reset value of PTP_SEC_ROLLOVER is incorrect on
CNF10KB silicon, the ptp timestamps are inaccurate. This
patch initializes the PTP_SEC_ROLLOVER register properly
for the CNF10KB silicon.
Signed-off-by: Naveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: Sunil Kovvuri Goutham <sgoutham@marvell.com>
---
drivers/net/ethernet/marvell/octeontx2/af/ptp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
index 01f7dbad6b92..3411e2e47d46 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c
@@ -52,12 +52,18 @@
#define PTP_CLOCK_COMP 0xF18ULL
#define PTP_TIMESTAMP 0xF20ULL
#define PTP_CLOCK_SEC 0xFD0ULL
+#define PTP_SEC_ROLLOVER 0xFD8ULL
#define CYCLE_MULT 1000
static struct ptp *first_ptp_block;
static const struct pci_device_id ptp_id_table[];
+static bool is_ptp_dev_cnf10kb(struct ptp *ptp)
+{
+ return (ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_B_PTP) ? true : false;
+}
+
static bool is_ptp_dev_cn10k(struct ptp *ptp)
{
return (ptp->pdev->device == PCI_DEVID_CN10K_PTP) ? true : false;
@@ -290,6 +296,10 @@ void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts)
/* sclk is in MHz */
ptp->clock_rate = sclk * 1000000;
+ /* Program the seconds rollover value to 1 second */
+ if (is_ptp_dev_cnf10kb(ptp))
+ writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER);
+
/* Enable PTP clock */
clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);
--
2.16.5
next prev parent reply other threads:[~2022-07-30 11:58 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-30 11:57 [net-next PATCH v2 0/4] Add PTP support for CN10K silicon Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 1/4] octeontx2-af: return correct ptp timestamp " Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 2/4] octeontx2-pf: Add support for ptp 1-step mode on " Naveen Mamindlapalli
2022-07-30 11:57 ` [net-next PATCH v2 3/4] octeontx2-af: Add PTP PPS Errata workaround " Naveen Mamindlapalli
2022-07-30 11:57 ` Naveen Mamindlapalli [this message]
2022-08-02 19:14 ` [net-next PATCH v2 0/4] Add PTP support for " Jakub Kicinski
2022-08-03 4:44 ` Jakub Kicinski
2022-08-04 3:08 ` Richard Cochran
2022-08-04 16:06 ` Jakub Kicinski
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