From: jassisinghbrar@gmail.com
To: robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, sudeep.holla@arm.com
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Jassi Brar <jaswinder.singh@linaro.org>
Subject: [PATCH] arm64: dts: juno: Add missing MHU secure-irq
Date: Mon, 1 Aug 2022 09:10:05 -0500 [thread overview]
Message-ID: <20220801141005.599258-1-jassisinghbrar@gmail.com> (raw)
From: Jassi Brar <jaswinder.singh@linaro.org>
The MHU secure interrupt exists physically but is missing in the DT node.
Specify the interrupt in DT node to fix a warning on Arm Juno board:
mhu@2b1f0000: interrupts: [[0, 36, 4], [0, 35, 4]] is too short
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 446c8f476eec0..fa3710c7c26c4 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -26,7 +26,8 @@ mailbox: mhu@2b1f0000 {
compatible = "arm,mhu", "arm,primecell";
reg = <0x0 0x2b1f0000 0x0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
clocks = <&soc_refclk100mhz>;
clock-names = "apb_pclk";
--
2.25.1
next reply other threads:[~2022-08-01 14:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-01 14:10 jassisinghbrar [this message]
2022-08-15 14:24 ` [PATCH] arm64: dts: juno: Add missing MHU secure-irq Sudeep Holla
-- strict thread matches above, loose matches on Subject: below --
2022-07-30 14:23 jassisinghbrar
2022-08-01 10:33 ` Sudeep Holla
2022-08-01 10:38 ` Sudeep Holla
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