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* [PATCH 1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type
@ 2022-08-02 10:15 Biju Das
  2022-08-02 10:15 ` [PATCH 2/3] arm64: dts: renesas: r9a07g054: " Biju Das
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Biju Das @ 2022-08-02 10:15 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the interrupt type of SCI{Rx,TX} is edge triggered.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 47785ba08faf..f0860cdb57a7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -400,8 +400,8 @@ sci0: serial@1004d000 {
 			compatible = "renesas,r9a07g044-sci", "renesas,sci";
 			reg = <0 0x1004d000 0 0x400>;
 			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
@@ -415,8 +415,8 @@ sci1: serial@1004d400 {
 			compatible = "renesas,r9a07g044-sci", "renesas,sci";
 			reg = <0 0x1004d400 0 0x400>;
 			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 2/3] arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt type
  2022-08-02 10:15 [PATCH 1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type Biju Das
@ 2022-08-02 10:15 ` Biju Das
  2022-08-18 11:42   ` Geert Uytterhoeven
  2022-08-02 10:15 ` [PATCH 3/3] arm64: dts: renesas: r9a07g043: " Biju Das
  2022-08-18 11:41 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: " Geert Uytterhoeven
  2 siblings, 1 reply; 6+ messages in thread
From: Biju Das @ 2022-08-02 10:15 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021),
the interrupt type of SCI{Rx,TX} is edge triggered.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index bfb7e67b95a1..8f8bfe43b4df 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -405,8 +405,8 @@ sci0: serial@1004d000 {
 			compatible = "renesas,r9a07g054-sci", "renesas,sci";
 			reg = <0 0x1004d000 0 0x400>;
 			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
@@ -420,8 +420,8 @@ sci1: serial@1004d400 {
 			compatible = "renesas,r9a07g054-sci", "renesas,sci";
 			reg = <0 0x1004d400 0 0x400>;
 			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 3/3] arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt type
  2022-08-02 10:15 [PATCH 1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type Biju Das
  2022-08-02 10:15 ` [PATCH 2/3] arm64: dts: renesas: r9a07g054: " Biju Das
@ 2022-08-02 10:15 ` Biju Das
  2022-08-18 11:43   ` Geert Uytterhoeven
  2022-08-18 11:41 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: " Geert Uytterhoeven
  2 siblings, 1 reply; 6+ messages in thread
From: Biju Das @ 2022-08-02 10:15 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski
  Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
	devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad

As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
the interrupt type of SCI{Rx,TX} is edge triggered.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index d1b567d1b6e1..ff6aab388eb7 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -340,8 +340,8 @@ sci0: serial@1004d000 {
 			compatible = "renesas,r9a07g043-sci", "renesas,sci";
 			reg = <0 0x1004d000 0 0x400>;
 			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
@@ -355,8 +355,8 @@ sci1: serial@1004d400 {
 			compatible = "renesas,r9a07g043-sci", "renesas,sci";
 			reg = <0 0x1004d400 0 0x400>;
 			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi", "tei";
 			clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type
  2022-08-02 10:15 [PATCH 1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type Biju Das
  2022-08-02 10:15 ` [PATCH 2/3] arm64: dts: renesas: r9a07g054: " Biju Das
  2022-08-02 10:15 ` [PATCH 3/3] arm64: dts: renesas: r9a07g043: " Biju Das
@ 2022-08-18 11:41 ` Geert Uytterhoeven
  2 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-08-18 11:41 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

On Tue, Aug 2, 2022 at 12:15 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
> the interrupt type of SCI{Rx,TX} is edge triggered.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Fixes: f9a2adcc9e908907 ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/3] arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt type
  2022-08-02 10:15 ` [PATCH 2/3] arm64: dts: renesas: r9a07g054: " Biju Das
@ 2022-08-18 11:42   ` Geert Uytterhoeven
  0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-08-18 11:42 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

On Tue, Aug 2, 2022 at 12:15 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021),
> the interrupt type of SCI{Rx,TX} is edge triggered.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 3/3] arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt type
  2022-08-02 10:15 ` [PATCH 3/3] arm64: dts: renesas: r9a07g043: " Biju Das
@ 2022-08-18 11:43   ` Geert Uytterhoeven
  0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2022-08-18 11:43 UTC (permalink / raw)
  To: Biju Das
  Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Chris Paterson, Biju Das, Prabhakar Mahadev Lad

On Tue, Aug 2, 2022 at 12:15 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022),
> the interrupt type of SCI{Rx,TX} is edge triggered.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for
RZ/G2UL SoC")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2022-08-18 11:43 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-02 10:15 [PATCH 1/3] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt type Biju Das
2022-08-02 10:15 ` [PATCH 2/3] arm64: dts: renesas: r9a07g054: " Biju Das
2022-08-18 11:42   ` Geert Uytterhoeven
2022-08-02 10:15 ` [PATCH 3/3] arm64: dts: renesas: r9a07g043: " Biju Das
2022-08-18 11:43   ` Geert Uytterhoeven
2022-08-18 11:41 ` [PATCH 1/3] arm64: dts: renesas: r9a07g044: " Geert Uytterhoeven

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