* [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
Add GSC support for XeHP SDV and DG2 platforms.
The series includes changes for the mei driver:
- add ability to use polling instead of interrupts
- add ability to use extended timeouts
- setup extended operational memory for GSC
The series includes changes for the i915 driver:
- allocate extended operational memory for GSC
- GSC on XeHP SDV offsets and definitions
This patch set should be merged via gfx tree as
the auxiliary device belongs there.
Greg, your ACK is required for the drives/misc/mei code base,
please review the patches.
V2: rebase over merged DG1 series and DG2 enablement patch,
fix commit messages
V3: rebase over latest tip
V4: add missed changelog in pxp dbugfs patch
V5: rebase over latest tip
fix changelog in pxp dbugfs patch
put HAX patch last to the ease of merging
reorder patches in the series
V6: change prefix from 'drm/i915/gsc:' to 'mei' in patch:
mei: add slow_fw flag to the mei auxiliary device
Address following checkpatch warnings:
CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
FILE: drivers/misc/mei/mkhi.h:54:
+ uint32_t flags;
-:51: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'cldev->bus->pxp_mode != MEI_DEV_PXP_INIT'
#51: FILE: drivers/misc/mei/bus-fixup.c:257:
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ (cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
Remove some spurious code formatting changes in:
drm/i915/gsc: allocate extended operational memory in LMEM
V7: Add new patch to add kdoc for mei_aux_device structure.
Rename slow_fw to slow_firmware flag.
Use drm_dbg/err() functions instead of dev_dbg/err() in i195
codebase.
Alexander Usyskin (4):
drm/i915/gsc: add slow_firmware flag to the gsc device definition
drm/i915/gsc: add GSC XeHP SDV platform definition
mei: gsc: wait for reset thread on stop
mei: extend timeouts on slow devices.
Daniele Ceraolo Spurio (1):
HAX: drm/i915: force INTEL_MEI_GSC on for CI
Tomas Winkler (7):
mei: add kdoc for struct mei_aux_device
mei: add slow_firmware flag to the mei auxiliary device
mei: gsc: use polling instead of interrupts
mei: mkhi: add memory ready command
mei: gsc: setup gsc extended operational memory
mei: debugfs: add pxp mode to devstate in debugfs
drm/i915/gsc: allocate extended operational memory in LMEM
Vitaly Lubart (3):
drm/i915/gsc: skip irq initialization if using polling
mei: bus: export common mkhi definitions into a separate header
mei: gsc: add transition to PXP mode in resume flow
drivers/gpu/drm/i915/Kconfig.debug | 1 +
drivers/gpu/drm/i915/gt/intel_gsc.c | 118 +++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
drivers/misc/mei/bus-fixup.c | 104 ++++++++++++++++--------
drivers/misc/mei/client.c | 14 ++--
drivers/misc/mei/debugfs.c | 17 ++++
drivers/misc/mei/gsc-me.c | 77 +++++++++++++++---
drivers/misc/mei/hbm.c | 12 +--
drivers/misc/mei/hw-me-regs.h | 7 ++
drivers/misc/mei/hw-me.c | 116 ++++++++++++++++++++++-----
drivers/misc/mei/hw-me.h | 14 +++-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 ++
drivers/misc/mei/init.c | 21 ++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 26 ++++++
drivers/misc/mei/mkhi.h | 57 ++++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
include/linux/mei_aux.h | 12 +++
19 files changed, 519 insertions(+), 91 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
--
2.37.1
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
Add GSC support for XeHP SDV and DG2 platforms.
The series includes changes for the mei driver:
- add ability to use polling instead of interrupts
- add ability to use extended timeouts
- setup extended operational memory for GSC
The series includes changes for the i915 driver:
- allocate extended operational memory for GSC
- GSC on XeHP SDV offsets and definitions
This patch set should be merged via gfx tree as
the auxiliary device belongs there.
Greg, your ACK is required for the drives/misc/mei code base,
please review the patches.
V2: rebase over merged DG1 series and DG2 enablement patch,
fix commit messages
V3: rebase over latest tip
V4: add missed changelog in pxp dbugfs patch
V5: rebase over latest tip
fix changelog in pxp dbugfs patch
put HAX patch last to the ease of merging
reorder patches in the series
V6: change prefix from 'drm/i915/gsc:' to 'mei' in patch:
mei: add slow_fw flag to the mei auxiliary device
Address following checkpatch warnings:
CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
FILE: drivers/misc/mei/mkhi.h:54:
+ uint32_t flags;
-:51: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'cldev->bus->pxp_mode != MEI_DEV_PXP_INIT'
#51: FILE: drivers/misc/mei/bus-fixup.c:257:
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ (cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
Remove some spurious code formatting changes in:
drm/i915/gsc: allocate extended operational memory in LMEM
V7: Add new patch to add kdoc for mei_aux_device structure.
Rename slow_fw to slow_firmware flag.
Use drm_dbg/err() functions instead of dev_dbg/err() in i195
codebase.
Alexander Usyskin (4):
drm/i915/gsc: add slow_firmware flag to the gsc device definition
drm/i915/gsc: add GSC XeHP SDV platform definition
mei: gsc: wait for reset thread on stop
mei: extend timeouts on slow devices.
Daniele Ceraolo Spurio (1):
HAX: drm/i915: force INTEL_MEI_GSC on for CI
Tomas Winkler (7):
mei: add kdoc for struct mei_aux_device
mei: add slow_firmware flag to the mei auxiliary device
mei: gsc: use polling instead of interrupts
mei: mkhi: add memory ready command
mei: gsc: setup gsc extended operational memory
mei: debugfs: add pxp mode to devstate in debugfs
drm/i915/gsc: allocate extended operational memory in LMEM
Vitaly Lubart (3):
drm/i915/gsc: skip irq initialization if using polling
mei: bus: export common mkhi definitions into a separate header
mei: gsc: add transition to PXP mode in resume flow
drivers/gpu/drm/i915/Kconfig.debug | 1 +
drivers/gpu/drm/i915/gt/intel_gsc.c | 118 +++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
drivers/misc/mei/bus-fixup.c | 104 ++++++++++++++++--------
drivers/misc/mei/client.c | 14 ++--
drivers/misc/mei/debugfs.c | 17 ++++
drivers/misc/mei/gsc-me.c | 77 +++++++++++++++---
drivers/misc/mei/hbm.c | 12 +--
drivers/misc/mei/hw-me-regs.h | 7 ++
drivers/misc/mei/hw-me.c | 116 ++++++++++++++++++++++-----
drivers/misc/mei/hw-me.h | 14 +++-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 ++
drivers/misc/mei/init.c | 21 ++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 26 ++++++
drivers/misc/mei/mkhi.h | 57 ++++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
include/linux/mei_aux.h | 12 +++
19 files changed, 519 insertions(+), 91 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
--
2.37.1
^ permalink raw reply [flat|nested] 80+ messages in thread
* [PATCH v7 01/15] drm/i915/gsc: skip irq initialization if using polling
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
From: Vitaly Lubart <vitaly.lubart@intel.com>
Some platforms require the host to poll on the
GSC registers instead of relaying on the interrupts.
For those platforms, irq initialization should be skipped
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 0e494028b81d..e0236ff1d072 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -40,6 +40,7 @@ struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+ bool use_polling;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -117,6 +118,10 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
}
+ /* skip irq initialization */
+ if (def->use_polling)
+ goto add_device;
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
@@ -129,6 +134,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
goto fail;
}
+add_device:
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
goto fail;
@@ -182,10 +188,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
return;
}
- if (gt->gsc.intf[intf_id].irq < 0) {
- drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set");
+ if (gt->gsc.intf[intf_id].irq < 0)
return;
- }
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
if (ret)
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 01/15] drm/i915/gsc: skip irq initialization if using polling
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Some platforms require the host to poll on the
GSC registers instead of relaying on the interrupts.
For those platforms, irq initialization should be skipped
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 0e494028b81d..e0236ff1d072 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -40,6 +40,7 @@ struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
+ bool use_polling;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -117,6 +118,10 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
}
+ /* skip irq initialization */
+ if (def->use_polling)
+ goto add_device;
+
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
@@ -129,6 +134,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
goto fail;
}
+add_device:
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
if (!adev)
goto fail;
@@ -182,10 +188,8 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
return;
}
- if (gt->gsc.intf[intf_id].irq < 0) {
- drm_err_ratelimited(>->i915->drm, "GSC irq: irq not set");
+ if (gt->gsc.intf[intf_id].irq < 0)
return;
- }
ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);
if (ret)
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 02/15] mei: add kdoc for struct mei_aux_device
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
struct mei_aux_device is an interface structure
requires proper documenation.
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
include/linux/mei_aux.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a0cb587006d5 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -7,6 +7,12 @@
#include <linux/auxiliary_bus.h>
+/**
+ * struct mei_aux_device - mei auxiliary device
+ * @aux_dev: - auxiliary device object
+ * @irq: interrupt driving the mei auxiliary device
+ * @bar: mmio resource bar reserved to mei auxiliary device
+ */
struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 02/15] mei: add kdoc for struct mei_aux_device
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
struct mei_aux_device is an interface structure
requires proper documenation.
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
include/linux/mei_aux.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 587f25128848..a0cb587006d5 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -7,6 +7,12 @@
#include <linux/auxiliary_bus.h>
+/**
+ * struct mei_aux_device - mei auxiliary device
+ * @aux_dev: - auxiliary device object
+ * @irq: interrupt driving the mei auxiliary device
+ * @bar: mmio resource bar reserved to mei auxiliary device
+ */
struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 03/15] mei: add slow_firmware flag to the mei auxiliary device
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
Add slow_firmware flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
include/linux/mei_aux.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index a0cb587006d5..4894d8bf4159 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -12,11 +12,14 @@
* @aux_dev: - auxiliary device object
* @irq: interrupt driving the mei auxiliary device
* @bar: mmio resource bar reserved to mei auxiliary device
+ * @slow_firmware: The device has slow underlying firmware.
+ * Such firmware will require to use larger operation timeouts.
*/
struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ bool slow_firmware;
};
#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 03/15] mei: add slow_firmware flag to the mei auxiliary device
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
Add slow_firmware flag to the mei auxiliary device info
to inform the mei driver about slow underlying firmware.
Such firmware will require to use larger operation timeouts.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
include/linux/mei_aux.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index a0cb587006d5..4894d8bf4159 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -12,11 +12,14 @@
* @aux_dev: - auxiliary device object
* @irq: interrupt driving the mei auxiliary device
* @bar: mmio resource bar reserved to mei auxiliary device
+ * @slow_firmware: The device has slow underlying firmware.
+ * Such firmware will require to use larger operation timeouts.
*/
struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ bool slow_firmware;
};
#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 04/15] drm/i915/gsc: add slow_firmware flag to the gsc device definition
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
From: Alexander Usyskin <alexander.usyskin@intel.com>
Add slow_firmware flag to the gsc device definition
and pass it to mei auxiliary device, this instructs
the driver to use longer operation timeouts.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e0236ff1d072..73498c2574c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -41,6 +41,7 @@ struct gsc_def {
unsigned long bar;
size_t bar_size;
bool use_polling;
+ bool slow_firmware;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -145,6 +146,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
adev->bar.end = adev->bar.start + def->bar_size - 1;
adev->bar.flags = IORESOURCE_MEM;
adev->bar.desc = IORES_DESC_NONE;
+ adev->slow_firmware = def->slow_firmware;
aux_dev = &adev->aux_dev;
aux_dev->name = def->name;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 04/15] drm/i915/gsc: add slow_firmware flag to the gsc device definition
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Add slow_firmware flag to the gsc device definition
and pass it to mei auxiliary device, this instructs
the driver to use longer operation timeouts.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e0236ff1d072..73498c2574c8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -41,6 +41,7 @@ struct gsc_def {
unsigned long bar;
size_t bar_size;
bool use_polling;
+ bool slow_firmware;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -145,6 +146,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
adev->bar.end = adev->bar.start + def->bar_size - 1;
adev->bar.flags = IORESOURCE_MEM;
adev->bar.desc = IORES_DESC_NONE;
+ adev->slow_firmware = def->slow_firmware;
aux_dev = &adev->aux_dev;
aux_dev->name = def->name;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 05/15] drm/i915/gsc: add GSC XeHP SDV platform definition
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Define GSC on XeHP SDV (Intel(R) dGPU without display)
XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 73498c2574c8..e1040c8f2fd3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
+static const struct gsc_def gsc_def_xehpsdv[] = {
+ {
+ /* HECI1 not enabled on the device. */
+ },
+ {
+ .name = "mei-gscfi",
+ .bar = DG1_GSC_HECI2_BASE,
+ .bar_size = GSC_BAR_LENGTH,
+ .use_polling = true,
+ .slow_firmware = true,
+ }
+};
+
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (IS_DG1(i915)) {
def = &gsc_def_dg1[intf_id];
+ } else if (IS_XEHPSDV(i915)) {
+ def = &gsc_def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = &gsc_def_dg2[intf_id];
} else {
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 05/15] drm/i915/gsc: add GSC XeHP SDV platform definition
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Define GSC on XeHP SDV (Intel(R) dGPU without display)
XeHP SDV uses the same hardware settings as DG1, but uses polling
instead of interrupts and runs the firmware in slow pace due to
hardware limitations.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index 73498c2574c8..e1040c8f2fd3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
}
};
+static const struct gsc_def gsc_def_xehpsdv[] = {
+ {
+ /* HECI1 not enabled on the device. */
+ },
+ {
+ .name = "mei-gscfi",
+ .bar = DG1_GSC_HECI2_BASE,
+ .bar_size = GSC_BAR_LENGTH,
+ .use_polling = true,
+ .slow_firmware = true,
+ }
+};
+
static const struct gsc_def gsc_def_dg2[] = {
{
.name = "mei-gsc",
@@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (IS_DG1(i915)) {
def = &gsc_def_dg1[intf_id];
+ } else if (IS_XEHPSDV(i915)) {
+ def = &gsc_def_xehpsdv[intf_id];
} else if (IS_DG2(i915)) {
def = &gsc_def_dg2[intf_id];
} else {
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 06/15] mei: gsc: use polling instead of interrupts
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, James Ausmus
A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
a gsc register when gsc is sending an interrupt. The work-around is
to disable interrupts and to use polling instead.
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------
drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++---
drivers/misc/mei/hw-me.h | 12 ++++++++
3 files changed, 105 insertions(+), 13 deletions(-)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8145e9b62b6..2caba3a9ac35 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -13,6 +13,7 @@
#include <linux/ktime.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
+#include <linux/kthread.h>
#include "mei_dev.h"
#include "hw-me.h"
@@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
- ret = devm_request_threaded_irq(device, hw->irq,
- mei_me_irq_quick_handler,
- mei_me_irq_thread_handler,
- IRQF_ONESHOT, KBUILD_MODNAME, dev);
- if (ret) {
- dev_err(device, "irq register failed %d\n", ret);
- goto err;
+ /* use polling */
+ if (mei_me_hw_use_polling(hw)) {
+ mei_disable_interrupts(dev);
+ mei_clear_interrupts(dev);
+ init_waitqueue_head(&hw->wait_active);
+ hw->is_active = true; /* start in active mode for initialization */
+ hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
+ "kmegscirqd/%s", dev_name(device));
+ if (IS_ERR(hw->polling_thread)) {
+ ret = PTR_ERR(hw->polling_thread);
+ dev_err(device, "unable to create kernel thread: %d\n", ret);
+ goto err;
+ }
+ } else {
+ ret = devm_request_threaded_irq(device, hw->irq,
+ mei_me_irq_quick_handler,
+ mei_me_irq_thread_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
+ if (ret) {
+ dev_err(device, "irq register failed %d\n", ret);
+ goto err;
+ }
}
pm_runtime_get_noresume(device);
@@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
register_err:
mei_stop(dev);
- devm_free_irq(device, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(device, hw->irq, dev);
err:
dev_err(device, "probe failed: %d\n", ret);
@@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *aux_dev)
mei_stop(dev);
+ hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ kthread_stop(hw->polling_thread);
+
mei_deregister(dev);
pm_runtime_disable(&aux_dev->dev);
mei_disable_interrupts(dev);
- devm_free_irq(&aux_dev->dev, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(&aux_dev->dev, hw->irq, dev);
}
static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
@@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
if (mei_write_is_idle(dev)) {
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_ON;
+
+ if (mei_me_hw_use_polling(hw))
+ hw->is_active = false;
ret = 0;
} else {
ret = -EAGAIN;
@@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_OFF;
+ if (mei_me_hw_use_polling(hw)) {
+ hw->is_active = true;
+ wake_up(&hw->wait_active);
+ }
+
mutex_unlock(&dev->device_lock);
irq_ret = mei_me_irq_thread_handler(1, dev);
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index befa491e3344..46559517a902 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
+#include <linux/delay.h>
#include "mei_dev.h"
#include "hbm.h"
@@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
*/
static void mei_me_intr_enable(struct mei_device *dev)
{
- u32 hcsr = mei_hcsr_read(dev);
+ u32 hcsr;
+
+ if (mei_me_hw_use_polling(to_me_hw(dev)))
+ return;
- hcsr |= H_CSR_IE_MASK;
+ hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
mei_hcsr_set(dev, hcsr);
}
@@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ return;
+
synchronize_irq(hw->irq);
}
@@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *dev)
{
u32 hcsr = mei_hcsr_read(dev);
- hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
+ if (!mei_me_hw_use_polling(to_me_hw(dev)))
+ hcsr |= H_CSR_IE_MASK;
+
+ hcsr |= H_IG | H_RDY;
mei_hcsr_set(dev, hcsr);
}
@@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
- if (!intr_enable)
+ if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
hcsr &= ~H_CSR_IE_MASK;
dev->recvd_hw_ready = false;
@@ -1331,6 +1341,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
}
EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
+#define MEI_POLLING_TIMEOUT_ACTIVE 100
+#define MEI_POLLING_TIMEOUT_IDLE 500
+
+int mei_me_polling_thread(void *_dev)
+{
+ struct mei_device *dev = _dev;
+ irqreturn_t irq_ret;
+ long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+
+ dev_dbg(dev->dev, "kernel thread is running\n");
+ while (!kthread_should_stop()) {
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 hcsr;
+
+ wait_event_timeout(hw->wait_active,
+ hw->is_active || kthread_should_stop(),
+ msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
+
+ if (kthread_should_stop())
+ break;
+
+ hcsr = mei_hcsr_read(dev);
+ if (me_intr_src(hcsr)) {
+ polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+ irq_ret = mei_me_irq_thread_handler(1, dev);
+ if (irq_ret != IRQ_HANDLED)
+ dev_err(dev->dev, "irq_ret %d\n", irq_ret);
+ } else {
+ polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_IDLE);
+ }
+
+ schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mei_me_polling_thread);
+
static const struct mei_hw_ops mei_me_hw_ops = {
.trc_status = mei_me_trc_status,
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index a071c645e905..ca09274ac299 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -51,6 +51,8 @@ struct mei_cfg {
* @d0i3_supported: di03 support
* @hbuf_depth: depth of hardware host/write buffer in slots
* @read_fws: read FW status register handler
+ * @wait_active: the polling thread activity wait queue
+ * @is_active: the device is active
*/
struct mei_me_hw {
const struct mei_cfg *cfg;
@@ -60,10 +62,19 @@ struct mei_me_hw {
bool d0i3_supported;
u8 hbuf_depth;
int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
+ /* polling */
+ struct task_struct *polling_thread;
+ wait_queue_head_t wait_active;
+ bool is_active;
};
#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
+static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
+{
+ return hw->irq < 0;
+}
+
/**
* enum mei_cfg_idx - indices to platform specific configurations.
*
@@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev);
irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
+int mei_me_polling_thread(void *_dev);
#endif /* _MEI_INTERFACE_H_ */
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 06/15] mei: gsc: use polling instead of interrupts
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
a gsc register when gsc is sending an interrupt. The work-around is
to disable interrupts and to use polling instead.
Cc: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------
drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++---
drivers/misc/mei/hw-me.h | 12 ++++++++
3 files changed, 105 insertions(+), 13 deletions(-)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index c8145e9b62b6..2caba3a9ac35 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -13,6 +13,7 @@
#include <linux/ktime.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
+#include <linux/kthread.h>
#include "mei_dev.h"
#include "hw-me.h"
@@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
- ret = devm_request_threaded_irq(device, hw->irq,
- mei_me_irq_quick_handler,
- mei_me_irq_thread_handler,
- IRQF_ONESHOT, KBUILD_MODNAME, dev);
- if (ret) {
- dev_err(device, "irq register failed %d\n", ret);
- goto err;
+ /* use polling */
+ if (mei_me_hw_use_polling(hw)) {
+ mei_disable_interrupts(dev);
+ mei_clear_interrupts(dev);
+ init_waitqueue_head(&hw->wait_active);
+ hw->is_active = true; /* start in active mode for initialization */
+ hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
+ "kmegscirqd/%s", dev_name(device));
+ if (IS_ERR(hw->polling_thread)) {
+ ret = PTR_ERR(hw->polling_thread);
+ dev_err(device, "unable to create kernel thread: %d\n", ret);
+ goto err;
+ }
+ } else {
+ ret = devm_request_threaded_irq(device, hw->irq,
+ mei_me_irq_quick_handler,
+ mei_me_irq_thread_handler,
+ IRQF_ONESHOT, KBUILD_MODNAME, dev);
+ if (ret) {
+ dev_err(device, "irq register failed %d\n", ret);
+ goto err;
+ }
}
pm_runtime_get_noresume(device);
@@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
register_err:
mei_stop(dev);
- devm_free_irq(device, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(device, hw->irq, dev);
err:
dev_err(device, "probe failed: %d\n", ret);
@@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *aux_dev)
mei_stop(dev);
+ hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ kthread_stop(hw->polling_thread);
+
mei_deregister(dev);
pm_runtime_disable(&aux_dev->dev);
mei_disable_interrupts(dev);
- devm_free_irq(&aux_dev->dev, hw->irq, dev);
+ if (!mei_me_hw_use_polling(hw))
+ devm_free_irq(&aux_dev->dev, hw->irq, dev);
}
static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
@@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
if (mei_write_is_idle(dev)) {
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_ON;
+
+ if (mei_me_hw_use_polling(hw))
+ hw->is_active = false;
ret = 0;
} else {
ret = -EAGAIN;
@@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
hw = to_me_hw(dev);
hw->pg_state = MEI_PG_OFF;
+ if (mei_me_hw_use_polling(hw)) {
+ hw->is_active = true;
+ wake_up(&hw->wait_active);
+ }
+
mutex_unlock(&dev->device_lock);
irq_ret = mei_me_irq_thread_handler(1, dev);
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index befa491e3344..46559517a902 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
#include <linux/sizes.h>
+#include <linux/delay.h>
#include "mei_dev.h"
#include "hbm.h"
@@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
*/
static void mei_me_intr_enable(struct mei_device *dev)
{
- u32 hcsr = mei_hcsr_read(dev);
+ u32 hcsr;
+
+ if (mei_me_hw_use_polling(to_me_hw(dev)))
+ return;
- hcsr |= H_CSR_IE_MASK;
+ hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
mei_hcsr_set(dev, hcsr);
}
@@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
+ if (mei_me_hw_use_polling(hw))
+ return;
+
synchronize_irq(hw->irq);
}
@@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *dev)
{
u32 hcsr = mei_hcsr_read(dev);
- hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
+ if (!mei_me_hw_use_polling(to_me_hw(dev)))
+ hcsr |= H_CSR_IE_MASK;
+
+ hcsr |= H_IG | H_RDY;
mei_hcsr_set(dev, hcsr);
}
@@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
- if (!intr_enable)
+ if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
hcsr &= ~H_CSR_IE_MASK;
dev->recvd_hw_ready = false;
@@ -1331,6 +1341,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
}
EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
+#define MEI_POLLING_TIMEOUT_ACTIVE 100
+#define MEI_POLLING_TIMEOUT_IDLE 500
+
+int mei_me_polling_thread(void *_dev)
+{
+ struct mei_device *dev = _dev;
+ irqreturn_t irq_ret;
+ long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+
+ dev_dbg(dev->dev, "kernel thread is running\n");
+ while (!kthread_should_stop()) {
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 hcsr;
+
+ wait_event_timeout(hw->wait_active,
+ hw->is_active || kthread_should_stop(),
+ msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
+
+ if (kthread_should_stop())
+ break;
+
+ hcsr = mei_hcsr_read(dev);
+ if (me_intr_src(hcsr)) {
+ polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
+ irq_ret = mei_me_irq_thread_handler(1, dev);
+ if (irq_ret != IRQ_HANDLED)
+ dev_err(dev->dev, "irq_ret %d\n", irq_ret);
+ } else {
+ polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_ACTIVE,
+ MEI_POLLING_TIMEOUT_IDLE);
+ }
+
+ schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mei_me_polling_thread);
+
static const struct mei_hw_ops mei_me_hw_ops = {
.trc_status = mei_me_trc_status,
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index a071c645e905..ca09274ac299 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -51,6 +51,8 @@ struct mei_cfg {
* @d0i3_supported: di03 support
* @hbuf_depth: depth of hardware host/write buffer in slots
* @read_fws: read FW status register handler
+ * @wait_active: the polling thread activity wait queue
+ * @is_active: the device is active
*/
struct mei_me_hw {
const struct mei_cfg *cfg;
@@ -60,10 +62,19 @@ struct mei_me_hw {
bool d0i3_supported;
u8 hbuf_depth;
int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
+ /* polling */
+ struct task_struct *polling_thread;
+ wait_queue_head_t wait_active;
+ bool is_active;
};
#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
+static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
+{
+ return hw->irq < 0;
+}
+
/**
* enum mei_cfg_idx - indices to platform specific configurations.
*
@@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev);
irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
+int mei_me_polling_thread(void *_dev);
#endif /* _MEI_INTERFACE_H_ */
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 07/15] mei: gsc: wait for reset thread on stop
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Wait for reset work to complete before initiating
stop reset flow sequence.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index eb052005ca86..5bb6ba662cc0 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
mei_clear_interrupts(dev);
mei_synchronize_irq(dev);
+ /* to catch HW-initiated reset */
+ mei_cancel_work(dev);
mutex_lock(&dev->device_lock);
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 07/15] mei: gsc: wait for reset thread on stop
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Wait for reset work to complete before initiating
stop reset flow sequence.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index eb052005ca86..5bb6ba662cc0 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
mei_clear_interrupts(dev);
mei_synchronize_irq(dev);
+ /* to catch HW-initiated reset */
+ mei_cancel_work(dev);
mutex_lock(&dev->device_lock);
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 08/15] mei: extend timeouts on slow devices.
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Parametrize operational timeouts in order
to support slow firmware on some graphic devices.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/bus-fixup.c | 3 +--
drivers/misc/mei/client.c | 14 +++++++-------
drivers/misc/mei/gsc-me.c | 2 +-
drivers/misc/mei/hbm.c | 12 ++++++------
drivers/misc/mei/hw-me.c | 30 ++++++++++++++++--------------
drivers/misc/mei/hw-me.h | 2 +-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 +++++
drivers/misc/mei/init.c | 19 ++++++++++++++++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 16 ++++++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
12 files changed, 74 insertions(+), 35 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..24e91a9ea558 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)
sizeof(struct mkhi_fw_ver))
#define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
static int mei_fwver(struct mei_cl_device *cldev)
{
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
ret = 0;
bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
- MKHI_RCV_TIMEOUT);
+ cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
* Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..e7a16d9b2241 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
cl->state == MEI_FILE_DISCONNECT_REPLY ||
cl->state == MEI_FILE_DISCONNECTED,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
rets = cl->status;
@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_client *me_cl,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!mei_cl_is_connected(cl)) {
@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
cl->notify_en == request ||
cl->status ||
!mei_cl_is_connected(cl),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->notify_en != request && !cl->status)
@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const struct file *fp,
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!cl->dma_mapped && !cl->status)
@@ -2415,7 +2415,7 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct file *fp)
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
!cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->dma_mapped && !cl->status)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 2caba3a9ac35..bfa6154b93e2 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -48,7 +48,7 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
device = &aux_dev->dev;
- dev = mei_me_dev_init(device, cfg);
+ dev = mei_me_dev_init(device, cfg, adev->slow_firmware);
if (!dev) {
ret = -ENOMEM;
goto err;
diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c
index cf2b8261da14..708765056af2 100644
--- a/drivers/misc/mei/hbm.c
+++ b/drivers/misc/mei/hbm.c
@@ -232,7 +232,7 @@ int mei_hbm_start_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
ret = wait_event_timeout(dev->wait_hbm_start,
dev->hbm_state != MEI_HBM_STARTING,
- mei_secs_to_jiffies(MEI_HBM_TIMEOUT));
+ dev->timeouts.hbm);
mutex_lock(&dev->device_lock);
if (ret == 0 && (dev->hbm_state <= MEI_HBM_STARTING)) {
@@ -275,7 +275,7 @@ int mei_hbm_start_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_STARTING;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -316,7 +316,7 @@ static int mei_hbm_dma_setup_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_DR_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -351,7 +351,7 @@ static int mei_hbm_capabilities_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_CAP_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -385,7 +385,7 @@ static int mei_hbm_enum_clients_req(struct mei_device *dev)
return ret;
}
dev->hbm_state = MEI_HBM_ENUM_CLIENTS;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -751,7 +751,7 @@ static int mei_hbm_prop_req(struct mei_device *dev, unsigned long start_idx)
return ret;
}
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 46559517a902..6a8e8f3cea7e 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -445,7 +445,7 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_hw_ready,
dev->recvd_hw_ready,
- mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
+ dev->timeouts.hw_ready);
mutex_lock(&dev->device_lock);
if (!dev->recvd_hw_ready) {
dev_err(dev->dev, "wait hw ready failed\n");
@@ -707,7 +707,6 @@ static void mei_me_pg_unset(struct mei_device *dev)
static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
dev->pg_event = MEI_PG_EVENT_WAIT;
@@ -718,7 +717,8 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
@@ -744,7 +744,6 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
@@ -756,7 +755,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
reply:
@@ -772,7 +772,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
@@ -887,8 +888,6 @@ static u32 mei_me_d0i3_unset(struct mei_device *dev)
static int mei_me_d0i3_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
- unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
u32 reg;
@@ -910,7 +909,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
@@ -930,7 +930,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.d0i3);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev)
static int mei_me_d0i3_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
int ret;
u32 reg;
@@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -1686,11 +1687,12 @@ EXPORT_SYMBOL_GPL(mei_me_get_cfg);
*
* @parent: device associated with physical device (pci/platform)
* @cfg: per device generation config
+ * @slow_fw: configure longer timeouts as FW is slow
*
* Return: The mei_device pointer on success, NULL on failure.
*/
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg)
+ const struct mei_cfg *cfg, bool slow_fw)
{
struct mei_device *dev;
struct mei_me_hw *hw;
@@ -1705,7 +1707,7 @@ struct mei_device *mei_me_dev_init(struct device *parent,
for (i = 0; i < DMA_DSCR_NUM; i++)
dev->dr_dscr[i].size = cfg->dma_size[i];
- mei_device_init(dev, parent, &mei_me_hw_ops);
+ mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
hw->cfg = cfg;
dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index ca09274ac299..0e9d90808bcf 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -131,7 +131,7 @@ enum mei_cfg_idx {
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg);
+ const struct mei_cfg *cfg, bool slow_fw);
int mei_me_pg_enter_sync(struct mei_device *dev);
int mei_me_pg_exit_sync(struct mei_device *dev);
diff --git a/drivers/misc/mei/hw-txe.c b/drivers/misc/mei/hw-txe.c
index 00652c137cc7..fccfa806bd63 100644
--- a/drivers/misc/mei/hw-txe.c
+++ b/drivers/misc/mei/hw-txe.c
@@ -1201,7 +1201,7 @@ struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
if (!dev)
return NULL;
- mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
+ mei_device_init(dev, &pdev->dev, false, &mei_txe_hw_ops);
hw = to_txe_hw(dev);
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index b46077b17114..9381e5c13b4f 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -16,11 +16,16 @@
#define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */
#define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */
+#define MEI_CL_CONNECT_TIMEOUT_SLOW 30 /* HPS: Client Connect Timeout, slow FW */
#define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout */
#define MEI_PGI_TIMEOUT 1 /* PG Isolation time response 1 sec */
#define MEI_D0I3_TIMEOUT 5 /* D0i3 set/unset max response time */
#define MEI_HBM_TIMEOUT 1 /* 1 second */
+#define MEI_HBM_TIMEOUT_SLOW 5 /* 5 second, slow FW */
+
+#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
+#define MKHI_RCV_TIMEOUT_SLOW 10000 /* receive timeout in msec, slow FW */
/*
* FW page size for DMA allocations
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 5bb6ba662cc0..ce030a882d0c 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -359,14 +359,16 @@ bool mei_write_is_idle(struct mei_device *dev)
EXPORT_SYMBOL_GPL(mei_write_is_idle);
/**
- * mei_device_init -- initialize mei_device structure
+ * mei_device_init - initialize mei_device structure
*
* @dev: the mei device
* @device: the device structure
+ * @slow_fw: configure longer timeouts as FW is slow
* @hw_ops: hw operations
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops)
{
/* setup our list array */
@@ -404,6 +406,21 @@ void mei_device_init(struct mei_device *dev,
dev->pg_event = MEI_PG_EVENT_IDLE;
dev->ops = hw_ops;
dev->dev = device;
+
+ dev->timeouts.hw_ready = mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT);
+ dev->timeouts.connect = MEI_CONNECT_TIMEOUT;
+ dev->timeouts.client_init = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->timeouts.pgi = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
+ dev->timeouts.d0i3 = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
+ if (slow_fw) {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT_SLOW);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT_SLOW);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT_SLOW);
+ } else {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT);
+ }
}
EXPORT_SYMBOL_GPL(mei_device_init);
diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c
index 786f7c8f7f61..261939b945ef 100644
--- a/drivers/misc/mei/main.c
+++ b/drivers/misc/mei/main.c
@@ -571,7 +571,7 @@ static int mei_ioctl_connect_vtag(struct file *file,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
}
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 694f866f87ef..16f59b3a45fc 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -415,6 +415,17 @@ struct mei_fw_version {
#define MEI_MAX_FW_VER_BLOCKS 3
+struct mei_dev_timeouts {
+ unsigned long hw_ready; /* Timeout on ready message, in jiffies */
+ int connect; /* HPS: at least 2 seconds, in seconds */
+ unsigned long cl_connect; /* HPS: Client Connect Timeout, in jiffies */
+ int client_init; /* HPS: Clients Enumeration Timeout, in seconds */
+ unsigned long pgi; /* PG Isolation time response, in jiffies */
+ unsigned int d0i3; /* D0i3 set/unset max response time, in jiffies */
+ unsigned long hbm; /* HBM operation timeout, in jiffies */
+ unsigned long mkhi_recv; /* receive timeout, in jiffies */
+};
+
/**
* struct mei_device - MEI private device struct
*
@@ -480,6 +491,8 @@ struct mei_fw_version {
* @allow_fixed_address: allow user space to connect a fixed client
* @override_fixed_address: force allow fixed address behavior
*
+ * @timeouts: actual timeout values
+ *
* @reset_work : work item for the device reset
* @bus_rescan_work : work item for the bus rescan
*
@@ -568,6 +581,8 @@ struct mei_device {
bool allow_fixed_address;
bool override_fixed_address;
+ struct mei_dev_timeouts timeouts;
+
struct work_struct reset_work;
struct work_struct bus_rescan_work;
@@ -632,6 +647,7 @@ static inline u32 mei_slots2data(int slots)
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops);
int mei_reset(struct mei_device *dev);
int mei_start(struct mei_device *dev);
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 5435604327a7..b5af4e79bd52 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -203,7 +203,7 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
/* allocates and initializes the mei dev structure */
- dev = mei_me_dev_init(&pdev->dev, cfg);
+ dev = mei_me_dev_init(&pdev->dev, cfg, false);
if (!dev) {
err = -ENOMEM;
goto end;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 08/15] mei: extend timeouts on slow devices.
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Alexander Usyskin <alexander.usyskin@intel.com>
Parametrize operational timeouts in order
to support slow firmware on some graphic devices.
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/misc/mei/bus-fixup.c | 3 +--
drivers/misc/mei/client.c | 14 +++++++-------
drivers/misc/mei/gsc-me.c | 2 +-
drivers/misc/mei/hbm.c | 12 ++++++------
drivers/misc/mei/hw-me.c | 30 ++++++++++++++++--------------
drivers/misc/mei/hw-me.h | 2 +-
drivers/misc/mei/hw-txe.c | 2 +-
drivers/misc/mei/hw.h | 5 +++++
drivers/misc/mei/init.c | 19 ++++++++++++++++++-
drivers/misc/mei/main.c | 2 +-
drivers/misc/mei/mei_dev.h | 16 ++++++++++++++++
drivers/misc/mei/pci-me.c | 2 +-
12 files changed, 74 insertions(+), 35 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 59506ba6fc48..24e91a9ea558 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -164,7 +164,6 @@ static int mei_osver(struct mei_cl_device *cldev)
sizeof(struct mkhi_fw_ver))
#define MKHI_FWVER_LEN(__num) (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fw_ver_block) * (__num))
-#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
static int mei_fwver(struct mei_cl_device *cldev)
{
char buf[MKHI_FWVER_BUF_LEN];
@@ -187,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev)
ret = 0;
bytes_recv = __mei_cl_recv(cldev->cl, buf, sizeof(buf), NULL, 0,
- MKHI_RCV_TIMEOUT);
+ cldev->bus->timeouts.mkhi_recv);
if (bytes_recv < 0 || (size_t)bytes_recv < MKHI_FWVER_LEN(1)) {
/*
* Should be at least one version block,
diff --git a/drivers/misc/mei/client.c b/drivers/misc/mei/client.c
index 31264ab2eb13..e7a16d9b2241 100644
--- a/drivers/misc/mei/client.c
+++ b/drivers/misc/mei/client.c
@@ -870,7 +870,7 @@ static int mei_cl_send_disconnect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
@@ -945,7 +945,7 @@ static int __mei_cl_disconnect(struct mei_cl *cl)
wait_event_timeout(cl->wait,
cl->state == MEI_FILE_DISCONNECT_REPLY ||
cl->state == MEI_FILE_DISCONNECTED,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
rets = cl->status;
@@ -1065,7 +1065,7 @@ static int mei_cl_send_connect(struct mei_cl *cl, struct mei_cl_cb *cb)
}
list_move_tail(&cb->list, &dev->ctrl_rd_list);
- cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cl->timer_count = dev->timeouts.connect;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -1164,7 +1164,7 @@ int mei_cl_connect(struct mei_cl *cl, struct mei_me_client *me_cl,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!mei_cl_is_connected(cl)) {
@@ -1562,7 +1562,7 @@ int mei_cl_notify_request(struct mei_cl *cl,
cl->notify_en == request ||
cl->status ||
!mei_cl_is_connected(cl),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->notify_en != request && !cl->status)
@@ -2336,7 +2336,7 @@ int mei_cl_dma_alloc_and_map(struct mei_cl *cl, const struct file *fp,
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (!cl->dma_mapped && !cl->status)
@@ -2415,7 +2415,7 @@ int mei_cl_dma_unmap(struct mei_cl *cl, const struct file *fp)
mutex_unlock(&dev->device_lock);
wait_event_timeout(cl->wait,
!cl->dma_mapped || cl->status,
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
if (cl->dma_mapped && !cl->status)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 2caba3a9ac35..bfa6154b93e2 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -48,7 +48,7 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
device = &aux_dev->dev;
- dev = mei_me_dev_init(device, cfg);
+ dev = mei_me_dev_init(device, cfg, adev->slow_firmware);
if (!dev) {
ret = -ENOMEM;
goto err;
diff --git a/drivers/misc/mei/hbm.c b/drivers/misc/mei/hbm.c
index cf2b8261da14..708765056af2 100644
--- a/drivers/misc/mei/hbm.c
+++ b/drivers/misc/mei/hbm.c
@@ -232,7 +232,7 @@ int mei_hbm_start_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
ret = wait_event_timeout(dev->wait_hbm_start,
dev->hbm_state != MEI_HBM_STARTING,
- mei_secs_to_jiffies(MEI_HBM_TIMEOUT));
+ dev->timeouts.hbm);
mutex_lock(&dev->device_lock);
if (ret == 0 && (dev->hbm_state <= MEI_HBM_STARTING)) {
@@ -275,7 +275,7 @@ int mei_hbm_start_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_STARTING;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -316,7 +316,7 @@ static int mei_hbm_dma_setup_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_DR_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -351,7 +351,7 @@ static int mei_hbm_capabilities_req(struct mei_device *dev)
}
dev->hbm_state = MEI_HBM_CAP_SETUP;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -385,7 +385,7 @@ static int mei_hbm_enum_clients_req(struct mei_device *dev)
return ret;
}
dev->hbm_state = MEI_HBM_ENUM_CLIENTS;
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
}
@@ -751,7 +751,7 @@ static int mei_hbm_prop_req(struct mei_device *dev, unsigned long start_idx)
return ret;
}
- dev->init_clients_timer = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->init_clients_timer = dev->timeouts.client_init;
mei_schedule_stall_timer(dev);
return 0;
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 46559517a902..6a8e8f3cea7e 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -445,7 +445,7 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_hw_ready,
dev->recvd_hw_ready,
- mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT));
+ dev->timeouts.hw_ready);
mutex_lock(&dev->device_lock);
if (!dev->recvd_hw_ready) {
dev_err(dev->dev, "wait hw ready failed\n");
@@ -707,7 +707,6 @@ static void mei_me_pg_unset(struct mei_device *dev)
static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
dev->pg_event = MEI_PG_EVENT_WAIT;
@@ -718,7 +717,8 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
@@ -744,7 +744,6 @@ static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
@@ -756,7 +755,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
reply:
@@ -772,7 +772,8 @@ static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
@@ -887,8 +888,6 @@ static u32 mei_me_d0i3_unset(struct mei_device *dev)
static int mei_me_d0i3_enter_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long d0i3_timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
- unsigned long pgi_timeout = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
int ret;
u32 reg;
@@ -910,7 +909,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_RECEIVED, pgi_timeout);
+ dev->pg_event == MEI_PG_EVENT_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
@@ -930,7 +930,8 @@ static int mei_me_d0i3_enter_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, d0i3_timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.d0i3);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev)
static int mei_me_d0i3_exit_sync(struct mei_device *dev)
{
struct mei_me_hw *hw = to_me_hw(dev);
- unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
int ret;
u32 reg;
@@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *dev)
mutex_unlock(&dev->device_lock);
wait_event_timeout(dev->wait_pg,
- dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
+ dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
+ dev->timeouts.pgi);
mutex_lock(&dev->device_lock);
if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
@@ -1686,11 +1687,12 @@ EXPORT_SYMBOL_GPL(mei_me_get_cfg);
*
* @parent: device associated with physical device (pci/platform)
* @cfg: per device generation config
+ * @slow_fw: configure longer timeouts as FW is slow
*
* Return: The mei_device pointer on success, NULL on failure.
*/
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg)
+ const struct mei_cfg *cfg, bool slow_fw)
{
struct mei_device *dev;
struct mei_me_hw *hw;
@@ -1705,7 +1707,7 @@ struct mei_device *mei_me_dev_init(struct device *parent,
for (i = 0; i < DMA_DSCR_NUM; i++)
dev->dr_dscr[i].size = cfg->dma_size[i];
- mei_device_init(dev, parent, &mei_me_hw_ops);
+ mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
hw->cfg = cfg;
dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
index ca09274ac299..0e9d90808bcf 100644
--- a/drivers/misc/mei/hw-me.h
+++ b/drivers/misc/mei/hw-me.h
@@ -131,7 +131,7 @@ enum mei_cfg_idx {
const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
struct mei_device *mei_me_dev_init(struct device *parent,
- const struct mei_cfg *cfg);
+ const struct mei_cfg *cfg, bool slow_fw);
int mei_me_pg_enter_sync(struct mei_device *dev);
int mei_me_pg_exit_sync(struct mei_device *dev);
diff --git a/drivers/misc/mei/hw-txe.c b/drivers/misc/mei/hw-txe.c
index 00652c137cc7..fccfa806bd63 100644
--- a/drivers/misc/mei/hw-txe.c
+++ b/drivers/misc/mei/hw-txe.c
@@ -1201,7 +1201,7 @@ struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
if (!dev)
return NULL;
- mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
+ mei_device_init(dev, &pdev->dev, false, &mei_txe_hw_ops);
hw = to_txe_hw(dev);
diff --git a/drivers/misc/mei/hw.h b/drivers/misc/mei/hw.h
index b46077b17114..9381e5c13b4f 100644
--- a/drivers/misc/mei/hw.h
+++ b/drivers/misc/mei/hw.h
@@ -16,11 +16,16 @@
#define MEI_CONNECT_TIMEOUT 3 /* HPS: at least 2 seconds */
#define MEI_CL_CONNECT_TIMEOUT 15 /* HPS: Client Connect Timeout */
+#define MEI_CL_CONNECT_TIMEOUT_SLOW 30 /* HPS: Client Connect Timeout, slow FW */
#define MEI_CLIENTS_INIT_TIMEOUT 15 /* HPS: Clients Enumeration Timeout */
#define MEI_PGI_TIMEOUT 1 /* PG Isolation time response 1 sec */
#define MEI_D0I3_TIMEOUT 5 /* D0i3 set/unset max response time */
#define MEI_HBM_TIMEOUT 1 /* 1 second */
+#define MEI_HBM_TIMEOUT_SLOW 5 /* 5 second, slow FW */
+
+#define MKHI_RCV_TIMEOUT 500 /* receive timeout in msec */
+#define MKHI_RCV_TIMEOUT_SLOW 10000 /* receive timeout in msec, slow FW */
/*
* FW page size for DMA allocations
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 5bb6ba662cc0..ce030a882d0c 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -359,14 +359,16 @@ bool mei_write_is_idle(struct mei_device *dev)
EXPORT_SYMBOL_GPL(mei_write_is_idle);
/**
- * mei_device_init -- initialize mei_device structure
+ * mei_device_init - initialize mei_device structure
*
* @dev: the mei device
* @device: the device structure
+ * @slow_fw: configure longer timeouts as FW is slow
* @hw_ops: hw operations
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops)
{
/* setup our list array */
@@ -404,6 +406,21 @@ void mei_device_init(struct mei_device *dev,
dev->pg_event = MEI_PG_EVENT_IDLE;
dev->ops = hw_ops;
dev->dev = device;
+
+ dev->timeouts.hw_ready = mei_secs_to_jiffies(MEI_HW_READY_TIMEOUT);
+ dev->timeouts.connect = MEI_CONNECT_TIMEOUT;
+ dev->timeouts.client_init = MEI_CLIENTS_INIT_TIMEOUT;
+ dev->timeouts.pgi = mei_secs_to_jiffies(MEI_PGI_TIMEOUT);
+ dev->timeouts.d0i3 = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
+ if (slow_fw) {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT_SLOW);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT_SLOW);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT_SLOW);
+ } else {
+ dev->timeouts.cl_connect = mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT);
+ dev->timeouts.hbm = mei_secs_to_jiffies(MEI_HBM_TIMEOUT);
+ dev->timeouts.mkhi_recv = msecs_to_jiffies(MKHI_RCV_TIMEOUT);
+ }
}
EXPORT_SYMBOL_GPL(mei_device_init);
diff --git a/drivers/misc/mei/main.c b/drivers/misc/mei/main.c
index 786f7c8f7f61..261939b945ef 100644
--- a/drivers/misc/mei/main.c
+++ b/drivers/misc/mei/main.c
@@ -571,7 +571,7 @@ static int mei_ioctl_connect_vtag(struct file *file,
cl->state == MEI_FILE_DISCONNECTED ||
cl->state == MEI_FILE_DISCONNECT_REQUIRED ||
cl->state == MEI_FILE_DISCONNECT_REPLY),
- mei_secs_to_jiffies(MEI_CL_CONNECT_TIMEOUT));
+ dev->timeouts.cl_connect);
mutex_lock(&dev->device_lock);
}
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 694f866f87ef..16f59b3a45fc 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -415,6 +415,17 @@ struct mei_fw_version {
#define MEI_MAX_FW_VER_BLOCKS 3
+struct mei_dev_timeouts {
+ unsigned long hw_ready; /* Timeout on ready message, in jiffies */
+ int connect; /* HPS: at least 2 seconds, in seconds */
+ unsigned long cl_connect; /* HPS: Client Connect Timeout, in jiffies */
+ int client_init; /* HPS: Clients Enumeration Timeout, in seconds */
+ unsigned long pgi; /* PG Isolation time response, in jiffies */
+ unsigned int d0i3; /* D0i3 set/unset max response time, in jiffies */
+ unsigned long hbm; /* HBM operation timeout, in jiffies */
+ unsigned long mkhi_recv; /* receive timeout, in jiffies */
+};
+
/**
* struct mei_device - MEI private device struct
*
@@ -480,6 +491,8 @@ struct mei_fw_version {
* @allow_fixed_address: allow user space to connect a fixed client
* @override_fixed_address: force allow fixed address behavior
*
+ * @timeouts: actual timeout values
+ *
* @reset_work : work item for the device reset
* @bus_rescan_work : work item for the bus rescan
*
@@ -568,6 +581,8 @@ struct mei_device {
bool allow_fixed_address;
bool override_fixed_address;
+ struct mei_dev_timeouts timeouts;
+
struct work_struct reset_work;
struct work_struct bus_rescan_work;
@@ -632,6 +647,7 @@ static inline u32 mei_slots2data(int slots)
*/
void mei_device_init(struct mei_device *dev,
struct device *device,
+ bool slow_fw,
const struct mei_hw_ops *hw_ops);
int mei_reset(struct mei_device *dev);
int mei_start(struct mei_device *dev);
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index 5435604327a7..b5af4e79bd52 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -203,7 +203,7 @@ static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
}
/* allocates and initializes the mei dev structure */
- dev = mei_me_dev_init(&pdev->dev, cfg);
+ dev = mei_me_dev_init(&pdev->dev, cfg, false);
if (!dev) {
err = -ENOMEM;
goto end;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 31 +------------------------
drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 30 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 24e91a9ea558..811c94ebf250 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
#include "mei_dev.h"
#include "client.h"
+#include "mkhi.h"
#define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -89,20 +90,6 @@ struct mei_os_ver {
u8 reserved2;
} __packed;
-#define MKHI_FEATURE_PTT 0x10
-
-struct mkhi_rule_id {
- __le16 rule_type;
- u8 feature_id;
- u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
- struct mkhi_rule_id id;
- u8 len;
- u8 data[];
-} __packed;
-
struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +102,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
} __packed;
-#define MKHI_FWCAPS_GROUP_ID 0x3
-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
- u8 group_id;
- u8 command;
- u8 reserved;
- u8 result;
-} __packed;
-
-struct mkhi_msg {
- struct mkhi_msg_hdr hdr;
- u8 data[];
-} __packed;
-
#define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index 000000000000..27a9b476904e
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include "mei_dev.h"
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+#define MCHI_GROUP_ID 0xA
+
+struct mkhi_rule_id {
+ __le16 rule_type;
+ u8 feature_id;
+ u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+ struct mkhi_rule_id id;
+ u8 len;
+ u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+ u8 group_id;
+ u8 command;
+ u8 reserved;
+ u8 result;
+} __packed;
+
+struct mkhi_msg {
+ struct mkhi_msg_hdr hdr;
+ u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Exported common mkhi definitions from bus-fixup.c into a separate
header file mkhi.h for other driver usage.
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 31 +------------------------
drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 30 deletions(-)
create mode 100644 drivers/misc/mei/mkhi.h
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 24e91a9ea558..811c94ebf250 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -15,6 +15,7 @@
#include "mei_dev.h"
#include "client.h"
+#include "mkhi.h"
#define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
@@ -89,20 +90,6 @@ struct mei_os_ver {
u8 reserved2;
} __packed;
-#define MKHI_FEATURE_PTT 0x10
-
-struct mkhi_rule_id {
- __le16 rule_type;
- u8 feature_id;
- u8 reserved;
-} __packed;
-
-struct mkhi_fwcaps {
- struct mkhi_rule_id id;
- u8 len;
- u8 data[];
-} __packed;
-
struct mkhi_fw_ver_block {
u16 minor;
u8 major;
@@ -115,22 +102,6 @@ struct mkhi_fw_ver {
struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
} __packed;
-#define MKHI_FWCAPS_GROUP_ID 0x3
-#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
-#define MKHI_GEN_GROUP_ID 0xFF
-#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
-struct mkhi_msg_hdr {
- u8 group_id;
- u8 command;
- u8 reserved;
- u8 result;
-} __packed;
-
-struct mkhi_msg {
- struct mkhi_msg_hdr hdr;
- u8 data[];
-} __packed;
-
#define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
sizeof(struct mkhi_fwcaps) + \
sizeof(struct mei_os_ver))
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
new file mode 100644
index 000000000000..27a9b476904e
--- /dev/null
+++ b/drivers/misc/mei/mkhi.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ */
+
+#ifndef _MEI_MKHI_H_
+#define _MEI_MKHI_H_
+
+#include "mei_dev.h"
+
+#define MKHI_FEATURE_PTT 0x10
+
+#define MKHI_FWCAPS_GROUP_ID 0x3
+#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
+#define MKHI_GEN_GROUP_ID 0xFF
+#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
+
+#define MCHI_GROUP_ID 0xA
+
+struct mkhi_rule_id {
+ __le16 rule_type;
+ u8 feature_id;
+ u8 reserved;
+} __packed;
+
+struct mkhi_fwcaps {
+ struct mkhi_rule_id id;
+ u8 len;
+ u8 data[];
+} __packed;
+
+struct mkhi_msg_hdr {
+ u8 group_id;
+ u8 command;
+ u8 reserved;
+ u8 result;
+} __packed;
+
+struct mkhi_msg {
+ struct mkhi_msg_hdr hdr;
+ u8 data[];
+} __packed;
+
+#endif /* _MEI_MKHI_H_ */
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 10/15] mei: mkhi: add memory ready command
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
Add GSC memory ready command.
The command indicates to the firmware that extend operation
memory was setup and the firmware may enter PXP mode.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/mkhi.h | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index 27a9b476904e..056b76e73d40 100644
--- a/drivers/misc/mei/mkhi.h
+++ b/drivers/misc/mei/mkhi.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
* Intel Management Engine Interface (Intel MEI) Linux driver
*/
@@ -18,6 +18,13 @@
#define MCHI_GROUP_ID 0xA
+#define MKHI_GROUP_ID_GFX 0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1
+
struct mkhi_rule_id {
__le16 rule_type;
u8 feature_id;
@@ -42,4 +49,9 @@ struct mkhi_msg {
u8 data[];
} __packed;
+struct mkhi_gfx_mem_ready {
+ struct mkhi_msg_hdr hdr;
+ u32 flags;
+} __packed;
+
#endif /* _MEI_MKHI_H_ */
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 10/15] mei: mkhi: add memory ready command
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
Add GSC memory ready command.
The command indicates to the firmware that extend operation
memory was setup and the firmware may enter PXP mode.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/mkhi.h | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
index 27a9b476904e..056b76e73d40 100644
--- a/drivers/misc/mei/mkhi.h
+++ b/drivers/misc/mei/mkhi.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
* Intel Management Engine Interface (Intel MEI) Linux driver
*/
@@ -18,6 +18,13 @@
#define MCHI_GROUP_ID 0xA
+#define MKHI_GROUP_ID_GFX 0x30
+#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0
+#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1
+
+/* Allow transition to PXP mode without approval */
+#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1
+
struct mkhi_rule_id {
__le16 rule_type;
u8 feature_id;
@@ -42,4 +49,9 @@ struct mkhi_msg {
u8 data[];
} __packed;
+struct mkhi_gfx_mem_ready {
+ struct mkhi_msg_hdr hdr;
+ u32 flags;
+} __packed;
+
#endif /* _MEI_MKHI_H_ */
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
1. Retrieve extended operational memory physical pointers from the
auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
ready command.
4. Disable PXP device if GSC is not in PXP mode.
V7:
1. Add kdoc to mei_aux
2. rename pxp_isready() to pxp_is_ready()
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++-
drivers/misc/mei/gsc-me.c | 16 ++++++++
drivers/misc/mei/hw-me-regs.h | 7 ++++
drivers/misc/mei/hw-me.c | 28 +++++++++++++-
drivers/misc/mei/mei_dev.h | 10 +++++
include/linux/mei_aux.h | 3 ++
6 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 811c94ebf250..b350cc8d500c 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
return ret;
}
+static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
+{
+ struct mkhi_gfx_mem_ready req = {0};
+ unsigned int mode = MEI_CL_IO_TX_INTERNAL;
+
+ req.hdr.group_id = MKHI_GROUP_ID_GFX;
+ req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
+ req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
+
+ dev_dbg(&cldev->dev, "Sending memory ready command\n");
+ return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode);
+}
+
static void mei_mkhi_fix(struct mei_cl_device *cldev)
{
int ret;
@@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
dev_err(&cldev->dev, "FW version command failed %d\n", ret);
mei_cldev_disable(cldev);
}
+
+static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
+{
+ int ret;
+
+ /* No need to enable the client if nothing is needed from it */
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
+ return;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret)
+ return;
+
+ if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
+ ret = mei_gfx_memory_ready(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "memory ready command failed %d\n", ret);
+ else
+ dev_dbg(&cldev->dev, "memory ready command sent\n");
+ /* we go to reset after that */
+ cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
+ goto out;
+ }
+
+ ret = mei_fwver(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "FW version command failed %d\n",
+ ret);
+out:
+ mei_cldev_disable(cldev);
+}
+
/**
* mei_wd - wd client on the bus, change protocol version
* as the API has changed.
@@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev)
cldev->do_match = 1;
}
+/**
+ * pxp_is_ready - enable bus client if pxp is ready
+ *
+ * @cldev: me clients device
+ */
+static void pxp_is_ready(struct mei_cl_device *cldev)
+{
+ struct mei_device *bus = cldev->bus;
+
+ switch (bus->pxp_mode) {
+ case MEI_DEV_PXP_READY:
+ case MEI_DEV_PXP_DEFAULT:
+ cldev->do_match = 1;
+ break;
+ default:
+ cldev->do_match = 0;
+ break;
+ }
+}
+
#define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
static struct mei_fixup {
@@ -486,10 +552,10 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
- MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
+ MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
- MEI_FIXUP(MEI_UUID_PAVP, whitelist),
+ MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready),
};
/**
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index bfa6154b93e2..6b22726aed55 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
return 0;
}
+static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)
+{
+ u32 low = lower_32_bits(mem->start);
+ u32 hi = upper_32_bits(mem->start);
+ u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
+
+ iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
+ iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
+ iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
+}
+
static int mei_gsc_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
/* use polling */
if (mei_me_hw_use_polling(hw)) {
mei_disable_interrupts(dev);
diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 15e8e2b322b1..8049f288f74c 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -127,6 +127,8 @@
# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
#define PCI_CFG_HFS_4 0x64
#define PCI_CFG_HFS_5 0x68
+# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
+# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
#define PCI_CFG_HFS_6 0x6C
/* MEI registers */
@@ -143,6 +145,11 @@
/* H_D0I3C - D0I3 Control */
#define H_D0I3C 0x800
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
+#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
+#define GSC_EXT_OP_MEM_VALID BIT(31)
+
/* register bits of H_CSR (Host Control Status register) */
/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
#define H_CBD 0xFF000000
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 6a8e8f3cea7e..c86d6018bc20 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *dev)
return (mecsr & ME_RST_HRA) == ME_RST_HRA;
}
+/**
+ * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
+ *
+ * @dev: the device structure
+ */
+static void mei_gsc_pxp_check(struct mei_device *dev)
+{
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 fwsts5 = 0;
+
+ if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
+ return;
+
+ hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
+ trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
+ if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
+ dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
+ dev->pxp_mode = MEI_DEV_PXP_READY;
+ } else {
+ dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
+ }
+}
+
/**
* mei_me_hw_ready_wait - wait until the me(hw) has turned ready
* or timeout is reached
@@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
return -ETIME;
}
+ mei_gsc_pxp_check(dev);
+
mei_me_hw_reset_release(dev);
dev->recvd_hw_ready = false;
return 0;
@@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
/* check if ME wants a reset */
if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
- dev_warn(dev->dev, "FW not ready: resetting.\n");
+ dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
+ dev->dev_state, dev->pxp_mode);
if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
dev->dev_state == MEI_DEV_POWER_DOWN)
mei_cl_all_disconnect(dev);
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 16f59b3a45fc..7c508bca9a00 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -62,6 +62,14 @@ enum mei_dev_state {
MEI_DEV_POWER_UP
};
+/* MEI PXP mode state */
+enum mei_dev_pxp_mode {
+ MEI_DEV_PXP_DEFAULT = 0,
+ MEI_DEV_PXP_INIT = 1,
+ MEI_DEV_PXP_SETUP = 2,
+ MEI_DEV_PXP_READY = 3,
+};
+
const char *mei_dev_state_str(int state);
enum mei_file_transaction_states {
@@ -454,6 +462,7 @@ struct mei_dev_timeouts {
* @reset_count : number of consecutive resets
* @dev_state : device state
* @hbm_state : state of host bus message protocol
+ * @pxp_mode : PXP device mode
* @init_clients_timer : HBM init handshake timeout
*
* @pg_event : power gating event
@@ -537,6 +546,7 @@ struct mei_device {
unsigned long reset_count;
enum mei_dev_state dev_state;
enum mei_hbm_state hbm_state;
+ enum mei_dev_pxp_mode pxp_mode;
u16 init_clients_timer;
/*
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 4894d8bf4159..506912ad363b 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -12,6 +12,8 @@
* @aux_dev: - auxiliary device object
* @irq: interrupt driving the mei auxiliary device
* @bar: mmio resource bar reserved to mei auxiliary device
+ * @ext_op_mem: resource for extend operational memory
+ * used in graphics PXP mode.
* @slow_firmware: The device has slow underlying firmware.
* Such firmware will require to use larger operation timeouts.
*/
@@ -19,6 +21,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ struct resource ext_op_mem;
bool slow_firmware;
};
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
1. Retrieve extended operational memory physical pointers from the
auxiliary device info.
2. Setup memory registers.
3. Notify firmware that the memory is ready by sending the memory
ready command.
4. Disable PXP device if GSC is not in PXP mode.
V7:
1. Add kdoc to mei_aux
2. rename pxp_isready() to pxp_is_ready()
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++-
drivers/misc/mei/gsc-me.c | 16 ++++++++
drivers/misc/mei/hw-me-regs.h | 7 ++++
drivers/misc/mei/hw-me.c | 28 +++++++++++++-
drivers/misc/mei/mei_dev.h | 10 +++++
include/linux/mei_aux.h | 3 ++
6 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
index 811c94ebf250..b350cc8d500c 100644
--- a/drivers/misc/mei/bus-fixup.c
+++ b/drivers/misc/mei/bus-fixup.c
@@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
return ret;
}
+static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
+{
+ struct mkhi_gfx_mem_ready req = {0};
+ unsigned int mode = MEI_CL_IO_TX_INTERNAL;
+
+ req.hdr.group_id = MKHI_GROUP_ID_GFX;
+ req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
+ req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
+
+ dev_dbg(&cldev->dev, "Sending memory ready command\n");
+ return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode);
+}
+
static void mei_mkhi_fix(struct mei_cl_device *cldev)
{
int ret;
@@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
dev_err(&cldev->dev, "FW version command failed %d\n", ret);
mei_cldev_disable(cldev);
}
+
+static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
+{
+ int ret;
+
+ /* No need to enable the client if nothing is needed from it */
+ if (!cldev->bus->fw_f_fw_ver_supported &&
+ cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
+ return;
+
+ ret = mei_cldev_enable(cldev);
+ if (ret)
+ return;
+
+ if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
+ ret = mei_gfx_memory_ready(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "memory ready command failed %d\n", ret);
+ else
+ dev_dbg(&cldev->dev, "memory ready command sent\n");
+ /* we go to reset after that */
+ cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
+ goto out;
+ }
+
+ ret = mei_fwver(cldev);
+ if (ret < 0)
+ dev_err(&cldev->dev, "FW version command failed %d\n",
+ ret);
+out:
+ mei_cldev_disable(cldev);
+}
+
/**
* mei_wd - wd client on the bus, change protocol version
* as the API has changed.
@@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev)
cldev->do_match = 1;
}
+/**
+ * pxp_is_ready - enable bus client if pxp is ready
+ *
+ * @cldev: me clients device
+ */
+static void pxp_is_ready(struct mei_cl_device *cldev)
+{
+ struct mei_device *bus = cldev->bus;
+
+ switch (bus->pxp_mode) {
+ case MEI_DEV_PXP_READY:
+ case MEI_DEV_PXP_DEFAULT:
+ cldev->do_match = 1;
+ break;
+ default:
+ cldev->do_match = 0;
+ break;
+ }
+}
+
#define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
static struct mei_fixup {
@@ -486,10 +552,10 @@ static struct mei_fixup {
MEI_FIXUP(MEI_UUID_WD, mei_wd),
MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
- MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
+ MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
MEI_FIXUP(MEI_UUID_HDCP, whitelist),
MEI_FIXUP(MEI_UUID_ANY, vt_support),
- MEI_FIXUP(MEI_UUID_PAVP, whitelist),
+ MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready),
};
/**
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index bfa6154b93e2..6b22726aed55 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
return 0;
}
+static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)
+{
+ u32 low = lower_32_bits(mem->start);
+ u32 hi = upper_32_bits(mem->start);
+ u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
+
+ iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
+ iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
+ iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
+}
+
static int mei_gsc_probe(struct auxiliary_device *aux_dev,
const struct auxiliary_device_id *aux_dev_id)
{
@@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
dev_set_drvdata(device, dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
/* use polling */
if (mei_me_hw_use_polling(hw)) {
mei_disable_interrupts(dev);
diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
index 15e8e2b322b1..8049f288f74c 100644
--- a/drivers/misc/mei/hw-me-regs.h
+++ b/drivers/misc/mei/hw-me-regs.h
@@ -127,6 +127,8 @@
# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
#define PCI_CFG_HFS_4 0x64
#define PCI_CFG_HFS_5 0x68
+# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
+# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
#define PCI_CFG_HFS_6 0x6C
/* MEI registers */
@@ -143,6 +145,11 @@
/* H_D0I3C - D0I3 Control */
#define H_D0I3C 0x800
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
+#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
+#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
+#define GSC_EXT_OP_MEM_VALID BIT(31)
+
/* register bits of H_CSR (Host Control Status register) */
/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
#define H_CBD 0xFF000000
diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
index 6a8e8f3cea7e..c86d6018bc20 100644
--- a/drivers/misc/mei/hw-me.c
+++ b/drivers/misc/mei/hw-me.c
@@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *dev)
return (mecsr & ME_RST_HRA) == ME_RST_HRA;
}
+/**
+ * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
+ *
+ * @dev: the device structure
+ */
+static void mei_gsc_pxp_check(struct mei_device *dev)
+{
+ struct mei_me_hw *hw = to_me_hw(dev);
+ u32 fwsts5 = 0;
+
+ if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
+ return;
+
+ hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
+ trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
+ if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
+ dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
+ dev->pxp_mode = MEI_DEV_PXP_READY;
+ } else {
+ dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
+ }
+}
+
/**
* mei_me_hw_ready_wait - wait until the me(hw) has turned ready
* or timeout is reached
@@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
return -ETIME;
}
+ mei_gsc_pxp_check(dev);
+
mei_me_hw_reset_release(dev);
dev->recvd_hw_ready = false;
return 0;
@@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
/* check if ME wants a reset */
if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
- dev_warn(dev->dev, "FW not ready: resetting.\n");
+ dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
+ dev->dev_state, dev->pxp_mode);
if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
dev->dev_state == MEI_DEV_POWER_DOWN)
mei_cl_all_disconnect(dev);
diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
index 16f59b3a45fc..7c508bca9a00 100644
--- a/drivers/misc/mei/mei_dev.h
+++ b/drivers/misc/mei/mei_dev.h
@@ -62,6 +62,14 @@ enum mei_dev_state {
MEI_DEV_POWER_UP
};
+/* MEI PXP mode state */
+enum mei_dev_pxp_mode {
+ MEI_DEV_PXP_DEFAULT = 0,
+ MEI_DEV_PXP_INIT = 1,
+ MEI_DEV_PXP_SETUP = 2,
+ MEI_DEV_PXP_READY = 3,
+};
+
const char *mei_dev_state_str(int state);
enum mei_file_transaction_states {
@@ -454,6 +462,7 @@ struct mei_dev_timeouts {
* @reset_count : number of consecutive resets
* @dev_state : device state
* @hbm_state : state of host bus message protocol
+ * @pxp_mode : PXP device mode
* @init_clients_timer : HBM init handshake timeout
*
* @pg_event : power gating event
@@ -537,6 +546,7 @@ struct mei_device {
unsigned long reset_count;
enum mei_dev_state dev_state;
enum mei_hbm_state hbm_state;
+ enum mei_dev_pxp_mode pxp_mode;
u16 init_clients_timer;
/*
diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
index 4894d8bf4159..506912ad363b 100644
--- a/include/linux/mei_aux.h
+++ b/include/linux/mei_aux.h
@@ -12,6 +12,8 @@
* @aux_dev: - auxiliary device object
* @irq: interrupt driving the mei auxiliary device
* @bar: mmio resource bar reserved to mei auxiliary device
+ * @ext_op_mem: resource for extend operational memory
+ * used in graphics PXP mode.
* @slow_firmware: The device has slow underlying firmware.
* Such firmware will require to use larger operation timeouts.
*/
@@ -19,6 +21,7 @@ struct mei_aux_device {
struct auxiliary_device aux_dev;
int irq;
struct resource bar;
+ struct resource ext_op_mem;
bool slow_firmware;
};
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 12/15] mei: gsc: add transition to PXP mode in resume flow
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
From: Vitaly Lubart <vitaly.lubart@intel.com>
Added transition to PXP mode in resume flow.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 6b22726aed55..75765e4df4ed 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
static int __maybe_unused mei_gsc_pm_resume(struct device *device)
{
struct mei_device *dev = dev_get_drvdata(device);
+ struct auxiliary_device *aux_dev;
+ struct mei_aux_device *adev;
int err;
+ struct mei_me_hw *hw;
if (!dev)
return -ENODEV;
+ hw = to_me_hw(dev);
+ aux_dev = to_auxiliary_dev(device);
+ adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
err = mei_restart(dev);
if (err)
return err;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 12/15] mei: gsc: add transition to PXP mode in resume flow
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Vitaly Lubart <vitaly.lubart@intel.com>
Added transition to PXP mode in resume flow.
CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/gsc-me.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
index 6b22726aed55..75765e4df4ed 100644
--- a/drivers/misc/mei/gsc-me.c
+++ b/drivers/misc/mei/gsc-me.c
@@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
static int __maybe_unused mei_gsc_pm_resume(struct device *device)
{
struct mei_device *dev = dev_get_drvdata(device);
+ struct auxiliary_device *aux_dev;
+ struct mei_aux_device *adev;
int err;
+ struct mei_me_hw *hw;
if (!dev)
return -ENODEV;
+ hw = to_me_hw(dev);
+ aux_dev = to_auxiliary_dev(device);
+ adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
+ if (adev->ext_op_mem.start) {
+ mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
+ dev->pxp_mode = MEI_DEV_PXP_INIT;
+ }
+
err = mei_restart(dev);
if (err)
return err;
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 13/15] mei: debugfs: add pxp mode to devstate in debugfs
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart
Add pxp mode devstate to debugfs to monitor pxp state machine progress.
This is useful to debug issues in scenarios in which the pxp state
needs to be re-initialized, like during power transitions such as
suspend/resume. With this debugfs the state could be monitored
to ensure that pxp is in the ready state.
CC: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/debugfs.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index 1ce61e9e24fc..4074fec866a6 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
+static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
+{
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
+ switch (state) {
+ MEI_PXP_MODE(DEFAULT);
+ MEI_PXP_MODE(INIT);
+ MEI_PXP_MODE(SETUP);
+ MEI_PXP_MODE(READY);
+ default:
+ return "unknown";
+ }
+#undef MEI_PXP_MODE
+}
+
static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
{
struct mei_device *dev = m->private;
@@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
seq_printf(m, "pg: %s, %s\n",
mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
mei_pg_state_str(mei_pg_state(dev)));
+
+ seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
+
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 13/15] mei: debugfs: add pxp mode to devstate in debugfs
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
Add pxp mode devstate to debugfs to monitor pxp state machine progress.
This is useful to debug issues in scenarios in which the pxp state
needs to be re-initialized, like during power transitions such as
suspend/resume. With this debugfs the state could be monitored
to ensure that pxp is in the ready state.
CC: Vitaly Lubart <vitaly.lubart@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/misc/mei/debugfs.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
index 1ce61e9e24fc..4074fec866a6 100644
--- a/drivers/misc/mei/debugfs.c
+++ b/drivers/misc/mei/debugfs.c
@@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
+static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
+{
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
+ switch (state) {
+ MEI_PXP_MODE(DEFAULT);
+ MEI_PXP_MODE(INIT);
+ MEI_PXP_MODE(SETUP);
+ MEI_PXP_MODE(READY);
+ default:
+ return "unknown";
+ }
+#undef MEI_PXP_MODE
+}
+
static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
{
struct mei_device *dev = m->private;
@@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
seq_printf(m, "pg: %s, %s\n",
mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
mei_pg_state_str(mei_pg_state(dev)));
+
+ seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
+
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Alan Previn, Daniele Ceraolo Spurio
GSC requires more operational memory than available on chip.
Reserve 4M of LMEM for GSC operation. The memory is provided to the
GSC as struct resource to the auxiliary data of the child device.
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
2 files changed, 87 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e1040c8f2fd3..162bea57fbb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
#include <linux/mei_aux.h>
#include "i915_drv.h"
#include "i915_reg.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_gsc.h"
#include "gt/intel_gt.h"
@@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
}
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
+{
+ struct intel_gt *gt = gsc_to_gt(gsc);
+ struct drm_i915_gem_object *obj;
+ void *vaddr;
+ int err;
+
+ obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
+ goto out_put;
+ }
+
+ vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ drm_err(>->i915->drm, "Failed to map gsc memory\n");
+ goto out_unpin;
+ }
+
+ memset(vaddr, 0, obj->base.size);
+
+ i915_gem_object_unpin_map(obj);
+
+ intf->gem_obj = obj;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
+
+ if (!obj)
+ return;
+
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+
+ i915_gem_object_put(obj);
+}
+
struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
bool use_polling;
bool slow_firmware;
+ size_t lmem_size;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+ .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -90,26 +148,32 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
}
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+ struct intel_gsc *gsc, unsigned int intf_id)
{
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(&intf->adev->aux_dev);
auxiliary_device_uninit(&intf->adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+ gsc_ext_om_destroy(intf);
}
-static void gsc_init_one(struct drm_i915_private *i915,
- struct intel_gsc_intf *intf,
+static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
unsigned int intf_id)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct mei_aux_device *adev;
struct auxiliary_device *aux_dev;
const struct gsc_def *def;
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
int ret;
intf->irq = -1;
@@ -141,7 +205,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
- return;
+ goto fail;
}
ret = gsc_irq_init(intf->irq);
@@ -155,6 +219,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (!adev)
goto fail;
+ if (def->lmem_size) {
+ drm_dbg(&i915->drm, "setting up GSC lmem\n");
+
+ if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
+ drm_err(&i915->drm, "setting up gsc extended operational memory failed\n");
+ kfree(adev);
+ goto fail;
+ }
+
+ adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
+ adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
+ }
+
adev->irq = intf->irq;
adev->bar.parent = &pdev->resource[0];
adev->bar.start = def->bar + pdev->resource[0].start;
@@ -188,7 +265,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
fail:
- gsc_destroy_one(intf);
+ gsc_destroy_one(i915, gsc, intf->id);
}
static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
@@ -229,7 +306,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_init_one(i915, &gsc->intf[i], i);
+ gsc_init_one(i915, gsc, i);
}
void intel_gsc_fini(struct intel_gsc *gsc)
@@ -241,5 +318,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_destroy_one(&gsc->intf[i]);
+ gsc_destroy_one(gt->i915, gsc, i);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
index 68582f912b21..fcac1775e9c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.h
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
@@ -20,11 +20,14 @@ struct mei_aux_device;
/**
* struct intel_gsc - graphics security controller
+ *
+ * @gem_obj: scratch memory GSC operations
* @intf : gsc interface
*/
struct intel_gsc {
struct intel_gsc_intf {
struct mei_aux_device *adev;
+ struct drm_i915_gem_object *gem_obj;
int irq;
unsigned int id;
} intf[INTEL_GSC_NUM_INTERFACES];
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Alan Previn, intel-gfx, Alexander Usyskin, linux-kernel,
Rodrigo Vivi, Tomas Winkler, Vitaly Lubart
GSC requires more operational memory than available on chip.
Reserve 4M of LMEM for GSC operation. The memory is provided to the
GSC as struct resource to the auxiliary data of the child device.
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
2 files changed, 87 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
index e1040c8f2fd3..162bea57fbb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.c
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
@@ -7,6 +7,7 @@
#include <linux/mei_aux.h>
#include "i915_drv.h"
#include "i915_reg.h"
+#include "gem/i915_gem_region.h"
#include "gt/intel_gsc.h"
#include "gt/intel_gt.h"
@@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
return irq_set_chip_data(irq, NULL);
}
+static int
+gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
+{
+ struct intel_gt *gt = gsc_to_gt(gsc);
+ struct drm_i915_gem_object *obj;
+ void *vaddr;
+ int err;
+
+ obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
+ if (IS_ERR(obj)) {
+ drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
+ return PTR_ERR(obj);
+ }
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
+ goto out_put;
+ }
+
+ vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ drm_err(>->i915->drm, "Failed to map gsc memory\n");
+ goto out_unpin;
+ }
+
+ memset(vaddr, 0, obj->base.size);
+
+ i915_gem_object_unpin_map(obj);
+
+ intf->gem_obj = obj;
+
+ return 0;
+
+out_unpin:
+ i915_gem_object_unpin_pages(obj);
+out_put:
+ i915_gem_object_put(obj);
+ return err;
+}
+
+static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
+{
+ struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
+
+ if (!obj)
+ return;
+
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+
+ i915_gem_object_put(obj);
+}
+
struct gsc_def {
const char *name;
unsigned long bar;
size_t bar_size;
bool use_polling;
bool slow_firmware;
+ size_t lmem_size;
};
/* gsc resources and definitions (HECI1 and HECI2) */
@@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
.name = "mei-gsc",
.bar = DG2_GSC_HECI1_BASE,
.bar_size = GSC_BAR_LENGTH,
+ .lmem_size = SZ_4M,
},
{
.name = "mei-gscfi",
@@ -90,26 +148,32 @@ static void gsc_release_dev(struct device *dev)
kfree(adev);
}
-static void gsc_destroy_one(struct intel_gsc_intf *intf)
+static void gsc_destroy_one(struct drm_i915_private *i915,
+ struct intel_gsc *gsc, unsigned int intf_id)
{
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
+
if (intf->adev) {
auxiliary_device_delete(&intf->adev->aux_dev);
auxiliary_device_uninit(&intf->adev->aux_dev);
intf->adev = NULL;
}
+
if (intf->irq >= 0)
irq_free_desc(intf->irq);
intf->irq = -1;
+
+ gsc_ext_om_destroy(intf);
}
-static void gsc_init_one(struct drm_i915_private *i915,
- struct intel_gsc_intf *intf,
+static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
unsigned int intf_id)
{
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
struct mei_aux_device *adev;
struct auxiliary_device *aux_dev;
const struct gsc_def *def;
+ struct intel_gsc_intf *intf = &gsc->intf[intf_id];
int ret;
intf->irq = -1;
@@ -141,7 +205,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
intf->irq = irq_alloc_desc(0);
if (intf->irq < 0) {
drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
- return;
+ goto fail;
}
ret = gsc_irq_init(intf->irq);
@@ -155,6 +219,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
if (!adev)
goto fail;
+ if (def->lmem_size) {
+ drm_dbg(&i915->drm, "setting up GSC lmem\n");
+
+ if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
+ drm_err(&i915->drm, "setting up gsc extended operational memory failed\n");
+ kfree(adev);
+ goto fail;
+ }
+
+ adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
+ adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
+ }
+
adev->irq = intf->irq;
adev->bar.parent = &pdev->resource[0];
adev->bar.start = def->bar + pdev->resource[0].start;
@@ -188,7 +265,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
return;
fail:
- gsc_destroy_one(intf);
+ gsc_destroy_one(i915, gsc, intf->id);
}
static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
@@ -229,7 +306,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_init_one(i915, &gsc->intf[i], i);
+ gsc_init_one(i915, gsc, i);
}
void intel_gsc_fini(struct intel_gsc *gsc)
@@ -241,5 +318,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
return;
for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
- gsc_destroy_one(&gsc->intf[i]);
+ gsc_destroy_one(gt->i915, gsc, i);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
index 68582f912b21..fcac1775e9c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_gsc.h
+++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
@@ -20,11 +20,14 @@ struct mei_aux_device;
/**
* struct intel_gsc - graphics security controller
+ *
+ * @gem_obj: scratch memory GSC operations
* @intf : gsc interface
*/
struct intel_gsc {
struct intel_gsc_intf {
struct mei_aux_device *adev;
+ struct drm_i915_gem_object *gem_obj;
int irq;
unsigned int id;
} intf[INTEL_GSC_NUM_INTERFACES];
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [PATCH v7 15/15] HAX: drm/i915: force INTEL_MEI_GSC on for CI
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-08-06 12:26 ` Tomas Winkler
-1 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Tomas Winkler, Alexander Usyskin,
Vitaly Lubart, Daniele Ceraolo Spurio
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
After the new config option is merged we'll enable it by default in the
CI config, but for now just force it on via the i915 Kconfig so we can
get pre-merge CI results for it.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/Kconfig.debug | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..be4ef485d6c1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -48,6 +48,7 @@ config DRM_I915_DEBUG
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
+ select INTEL_MEI_GSC
select BROKEN # for prototype uAPI
default n
help
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] [PATCH v7 15/15] HAX: drm/i915: force INTEL_MEI_GSC on for CI
@ 2022-08-06 12:26 ` Tomas Winkler
0 siblings, 0 replies; 80+ messages in thread
From: Tomas Winkler @ 2022-08-06 12:26 UTC (permalink / raw)
To: Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi,
Tomas Winkler, Vitaly Lubart
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
After the new config option is merged we'll enable it by default in the
CI config, but for now just force it on via the i915 Kconfig so we can
get pre-merge CI results for it.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
---
drivers/gpu/drm/i915/Kconfig.debug | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..be4ef485d6c1 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -48,6 +48,7 @@ config DRM_I915_DEBUG
select DRM_I915_DEBUG_RUNTIME_PM
select DRM_I915_SW_FENCE_DEBUG_OBJECTS
select DRM_I915_SELFTEST
+ select INTEL_MEI_GSC
select BROKEN # for prototype uAPI
default n
help
--
2.37.1
^ permalink raw reply related [flat|nested] 80+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GSC support for XeHP SDV and DG2 (rev2)
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
` (15 preceding siblings ...)
(?)
@ 2022-08-06 12:59 ` Patchwork
-1 siblings, 0 replies; 80+ messages in thread
From: Patchwork @ 2022-08-06 12:59 UTC (permalink / raw)
To: Tomas Winkler; +Cc: intel-gfx
== Series Details ==
Series: GSC support for XeHP SDV and DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/106638/
State : warning
== Summary ==
Error: dim checkpatch failed
89f677f46f19 drm/i915/gsc: skip irq initialization if using polling
1661cc7ae3df mei: add kdoc for struct mei_aux_device
3789e46cd42c mei: add slow_firmware flag to the mei auxiliary device
7b6fdec93267 drm/i915/gsc: add slow_firmware flag to the gsc device definition
5063a20d2e82 drm/i915/gsc: add GSC XeHP SDV platform definition
c7992c5b15b4 mei: gsc: use polling instead of interrupts
8ac7b6c40f09 mei: gsc: wait for reset thread on stop
b7e494f4f9f9 mei: extend timeouts on slow devices.
35a2640b531a mei: bus: export common mkhi definitions into a separate header
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in <module>
import git
ModuleNotFoundError: No module named 'git'
-:71: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#71:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 94 lines checked
aa0afd915622 mei: mkhi: add memory ready command
505596c3b2b8 mei: gsc: setup gsc extended operational memory
89764c42af56 mei: gsc: add transition to PXP mode in resume flow
6b322648552f mei: debugfs: add pxp mode to devstate in debugfs
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#26: FILE: drivers/misc/mei/debugfs.c:91:
+#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
total: 1 errors, 0 warnings, 0 checks, 29 lines checked
53fabdce7eac drm/i915/gsc: allocate extended operational memory in LMEM
7bb7c17ab324 HAX: drm/i915: force INTEL_MEI_GSC on for CI
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for GSC support for XeHP SDV and DG2 (rev2)
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
` (16 preceding siblings ...)
(?)
@ 2022-08-06 12:59 ` Patchwork
-1 siblings, 0 replies; 80+ messages in thread
From: Patchwork @ 2022-08-06 12:59 UTC (permalink / raw)
To: Tomas Winkler; +Cc: intel-gfx
== Series Details ==
Series: GSC support for XeHP SDV and DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/106638/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for GSC support for XeHP SDV and DG2 (rev2)
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
` (17 preceding siblings ...)
(?)
@ 2022-08-06 13:22 ` Patchwork
-1 siblings, 0 replies; 80+ messages in thread
From: Patchwork @ 2022-08-06 13:22 UTC (permalink / raw)
To: Tomas Winkler; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6365 bytes --]
== Series Details ==
Series: GSC support for XeHP SDV and DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/106638/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11971 -> Patchwork_106638v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/index.html
Participating hosts (43 -> 41)
------------------------------
Missing (2): fi-glk-dsi fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_106638v2:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gtt:
- {bat-dg2-10}: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-dg2-10/igt@i915_selftest@live@gtt.html
Known issues
------------
Here are the changes found in Patchwork_106638v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/fi-pnv-d510/igt@i915_selftest@live@gem.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rplp-1}: [DMESG-WARN][3] ([i915#2867]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-rplp-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_module_load@reload:
- {bat-dg2-10}: [DMESG-WARN][5] -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-dg2-10/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-dg2-10/igt@i915_module_load@reload.html
* igt@i915_selftest@live@gem_contexts:
- {bat-dg2-8}: [INCOMPLETE][7] ([i915#6523]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][9] ([i915#4957]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- bat-dg1-6: [DMESG-FAIL][11] ([i915#4494] / [i915#4957]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][13] ([i915#4528]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/fi-pnv-d510/igt@i915_selftest@live@requests.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][15] ([i915#6367]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/bat-rpls-1/igt@i915_selftest@live@slpc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/bat-rpls-1/igt@i915_selftest@live@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6523]: https://gitlab.freedesktop.org/drm/intel/issues/6523
[i915#6531]: https://gitlab.freedesktop.org/drm/intel/issues/6531
Build changes
-------------
* Linux: CI_DRM_11971 -> Patchwork_106638v2
CI-20190529: 20190529
CI_DRM_11971: 2bdae66c9988dd0f07633629c0a85383cfc05940 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6614: fbb4a4058b8f4119a079b2fda5c94aaacd850a78 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106638v2: 2bdae66c9988dd0f07633629c0a85383cfc05940 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7cc941f23908 HAX: drm/i915: force INTEL_MEI_GSC on for CI
19d03248de66 drm/i915/gsc: allocate extended operational memory in LMEM
f4f9c475e2bf mei: debugfs: add pxp mode to devstate in debugfs
10243c95c610 mei: gsc: add transition to PXP mode in resume flow
55178e2905c1 mei: gsc: setup gsc extended operational memory
10bca444892b mei: mkhi: add memory ready command
7513b9c9a52e mei: bus: export common mkhi definitions into a separate header
343ffbb1cbcc mei: extend timeouts on slow devices.
a053fcda4210 mei: gsc: wait for reset thread on stop
9e7e39336754 mei: gsc: use polling instead of interrupts
0143b9c0238a drm/i915/gsc: add GSC XeHP SDV platform definition
da235c716118 drm/i915/gsc: add slow_firmware flag to the gsc device definition
d6abe17ce846 mei: add slow_firmware flag to the mei auxiliary device
3bacaf87d8a5 mei: add kdoc for struct mei_aux_device
fd96f7eb5ecc drm/i915/gsc: skip irq initialization if using polling
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/index.html
[-- Attachment #2: Type: text/html, Size: 6796 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for GSC support for XeHP SDV and DG2 (rev2)
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
` (18 preceding siblings ...)
(?)
@ 2022-08-06 14:49 ` Patchwork
-1 siblings, 0 replies; 80+ messages in thread
From: Patchwork @ 2022-08-06 14:49 UTC (permalink / raw)
To: Tomas Winkler; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 46927 bytes --]
== Series Details ==
Series: GSC support for XeHP SDV and DG2 (rev2)
URL : https://patchwork.freedesktop.org/series/106638/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11971_full -> Patchwork_106638v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_106638v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_106638v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_106638v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-kbl7/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl1/igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled.html
Known issues
------------
Here are the changes found in Patchwork_106638v2_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [FAIL][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk6/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk6/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk1/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk3/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk3/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk3/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk9/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk9/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk5/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk9/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk8/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk7/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk7/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk7/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk2/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk2/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk2/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk2/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk3/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk5/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk8/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk9/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk9/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk9/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-skl: NOTRUN -> [DMESG-WARN][53] ([i915#4991])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@gem_create@create-massive.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][54] -> [SKIP][55] ([i915#4525]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb4/igt@gem_exec_balancer@parallel-bb-first.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][56] -> [FAIL][57] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [PASS][58] -> [FAIL][59] ([i915#2842]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk7/igt@gem_exec_fair@basic-throttle@rcs0.html
- shard-kbl: [PASS][60] -> [FAIL][61] ([i915#2842])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-kbl7/igt@gem_exec_fair@basic-throttle@rcs0.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#4613])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@random:
- shard-kbl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#4613]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl4/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#4613]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_spin_batch@spin-each:
- shard-skl: [PASS][65] -> [FAIL][66] ([i915#2898])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl9/igt@gem_spin_batch@spin-each.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl2/igt@gem_spin_batch@spin-each.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3323])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][68] ([i915#3318])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl7/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@allowed-single:
- shard-apl: [PASS][69] -> [DMESG-WARN][70] ([i915#5566] / [i915#716])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl3/igt@gen9_exec_parse@allowed-single.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl: [PASS][71] -> [FAIL][72] ([i915#2521])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [SKIP][73] ([fdo#109271]) +154 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3886]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +6 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl4/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271]) +51 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@kms_ccs@pipe-b-random-ccs-data-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3886]) +3 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl1/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@dp-hpd:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [fdo#111827]) +12 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@kms_chamelium@dp-hpd.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +8 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl4/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@hdmi-mode-timings:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@kms_chamelium@hdmi-mode-timings.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][81] ([i915#1319])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl7/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1:
- shard-skl: [PASS][82] -> [INCOMPLETE][83] ([i915#4939])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl4/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@kms_cursor_crc@cursor-suspend@pipe-c-edp-1.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][84] -> [FAIL][85] ([i915#79])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1:
- shard-glk: [PASS][86] -> [FAIL][87] ([i915#2122])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][88] -> [FAIL][89] ([i915#79])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [PASS][90] -> [FAIL][91] ([i915#2122])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl7/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
- shard-iclb: [PASS][92] -> [SKIP][93] ([i915#3555]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][94] ([i915#2672] / [i915#3555])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][95] ([i915#3555])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][96] ([i915#2672]) +4 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
- shard-skl: [PASS][97] -> [DMESG-WARN][98] ([i915#1982])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][99] ([i915#265])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: NOTRUN -> [FAIL][100] ([fdo#108145] / [i915#265]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][101] ([fdo#108145] / [i915#265])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][102] -> [SKIP][103] ([i915#5235]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb3/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#658]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl7/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-apl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#658])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#658])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][107] -> [SKIP][108] ([fdo#109441]) +2 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-tglb: [PASS][109] -> [SKIP][110] ([i915#5519])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [PASS][111] -> [DMESG-WARN][112] ([i915#180]) +4 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
- shard-kbl: [PASS][113] -> [DMESG-WARN][114] ([i915#180]) +4 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-kbl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#2437])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl4/igt@kms_writeback@writeback-check-output.html
* igt@perf@non-zero-reason:
- shard-skl: NOTRUN -> [TIMEOUT][116] ([i915#6473])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@perf@non-zero-reason.html
* igt@sysfs_clients@fair-0:
- shard-kbl: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#2994]) +2 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl7/igt@sysfs_clients@fair-0.html
* igt@tools_test@sysfs_l3_parity:
- shard-kbl: NOTRUN -> [SKIP][118] ([fdo#109271]) +135 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl4/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@feature_discovery@psr1:
- {shard-rkl}: [SKIP][119] ([i915#658]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@feature_discovery@psr1.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@feature_discovery@psr1.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [INCOMPLETE][121] ([i915#180]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl3/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-tglb: [DMESG-WARN][123] ([i915#2411] / [i915#2867]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglb2/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglb5/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][125] ([i915#4525]) -> [PASS][126] +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][127] ([i915#2842]) -> [PASS][128] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][129] ([i915#2842]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [FAIL][131] -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-snb7/igt@gem_ppgtt@blt-vs-render-ctxn.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-snb5/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][133] ([i915#6258]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-1/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@i915_pm_sseu@full-enable:
- shard-skl: [FAIL][135] ([i915#3524]) -> [PASS][136]
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl9/igt@i915_pm_sseu@full-enable.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl2/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@live@gt_pm:
- {shard-tglu}: [DMESG-FAIL][137] ([i915#3987]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglu-3/igt@i915_selftest@live@gt_pm.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglu-6/igt@i915_selftest@live@gt_pm.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: [FAIL][139] ([i915#2521]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- {shard-tglu}: [INCOMPLETE][141] -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglu-6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglu-2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][143] ([i915#1845] / [i915#4098]) -> [PASS][144] +15 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-5/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size:
- shard-iclb: [FAIL][145] ([i915#5072]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb3/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][147] ([i915#2346]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled:
- {shard-rkl}: [SKIP][149] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][150] +4 similar issues
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-5/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-kbl: [FAIL][151] ([i915#79]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-kbl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][153] ([i915#79]) -> [PASS][154] +2 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-tglb: [FAIL][155] ([i915#79]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglb2/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][157] ([i915#79]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- {shard-rkl}: [SKIP][159] ([i915#1849] / [i915#4098]) -> [PASS][160] +12 similar issues
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-skl: [INCOMPLETE][161] ([i915#4939]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane@plane-panning-bottom-right@pipe-a-planes:
- {shard-rkl}: [SKIP][163] ([i915#1849] / [i915#3558]) -> [PASS][164] +1 similar issue
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- {shard-rkl}: [SKIP][165] ([i915#1849] / [i915#3546] / [i915#4098]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- {shard-rkl}: [SKIP][167] ([i915#1849] / [i915#3546] / [i915#4070] / [i915#4098]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_properties@crtc-properties-legacy:
- {shard-rkl}: [SKIP][169] ([i915#1849]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_properties@crtc-properties-legacy.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_properties@crtc-properties-legacy.html
* igt@kms_psr@primary_render:
- {shard-rkl}: [SKIP][171] ([i915#1072]) -> [PASS][172] +1 similar issue
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_psr@primary_render.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_psr@primary_render.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][173] ([fdo#109441]) -> [PASS][174] +1 similar issue
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb4/igt@kms_psr@psr2_primary_blt.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- {shard-rkl}: [SKIP][175] ([i915#5461]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-b:
- {shard-rkl}: [SKIP][177] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-rkl-2/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-rkl-6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][179] ([i915#180]) -> [PASS][180] +5 similar issues
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [FAIL][181] ([i915#1542]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl2/igt@perf@polling.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl10/igt@perf@polling.html
#### Warnings ####
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: [SKIP][183] ([fdo#109271] / [i915#1888] / [i915#3886]) -> [SKIP][184] ([fdo#109271] / [i915#3886])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl2/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color_chamelium@pipe-a-ctm-0-75:
- shard-skl: [SKIP][185] ([fdo#109271] / [fdo#111827] / [i915#1888]) -> [SKIP][186] ([fdo#109271] / [fdo#111827])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl4/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl1/igt@kms_color_chamelium@pipe-a-ctm-0-75.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
- shard-glk: [SKIP][187] ([fdo#109271] / [i915#1888]) -> [SKIP][188] ([fdo#109271])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-glk2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-glk3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
- shard-skl: [SKIP][189] ([fdo#109271] / [i915#1888]) -> [SKIP][190] ([fdo#109271]) +1 similar issue
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-skl6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_plane_lowres@tiling-4:
- shard-tglb: [SKIP][191] ([i915#5288]) -> [SKIP][192] ([fdo#112054] / [i915#5288])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-tglb5/igt@kms_plane_lowres@tiling-4.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-tglb5/igt@kms_plane_lowres@tiling-4.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][193] ([i915#2920]) -> [SKIP][194] ([i915#658])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][195] ([i915#658]) -> [SKIP][196] ([i915#2920])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb4/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][197] ([fdo#111068] / [i915#658]) -> [SKIP][198] ([i915#2920])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@runner@aborted:
- shard-apl: ([FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][203], [FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl8/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl3/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl3/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11971/shard-apl2/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl7/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl7/igt@runner@aborted.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl8/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl4/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl4/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl6/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl4/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/shard-apl8/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3524]: https://gitlab.freedesktop.org/drm/intel/issues/3524
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6473]: https://gitlab.freedesktop.org/drm/intel/issues/6473
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11971 -> Patchwork_106638v2
CI-20190529: 20190529
CI_DRM_11971: 2bdae66c9988dd0f07633629c0a85383cfc05940 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6614: fbb4a4058b8f4119a079b2fda5c94aaacd850a78 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106638v2: 2bdae66c9988dd0f07633629c0a85383cfc05940 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106638v2/index.html
[-- Attachment #2: Type: text/html, Size: 52486 bytes --]
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 10/15] mei: mkhi: add memory ready command
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 15:08 ` Greg Kroah-Hartman
-1 siblings, 0 replies; 80+ messages in thread
From: Greg Kroah-Hartman @ 2022-09-01 15:08 UTC (permalink / raw)
To: Tomas Winkler
Cc: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, intel-gfx, linux-kernel,
Alexander Usyskin, Vitaly Lubart, Daniele Ceraolo Spurio
On Sat, Aug 06, 2022 at 03:26:31PM +0300, Tomas Winkler wrote:
> Add GSC memory ready command.
> The command indicates to the firmware that extend operation
> memory was setup and the firmware may enter PXP mode.
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/mkhi.h | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
> index 27a9b476904e..056b76e73d40 100644
> --- a/drivers/misc/mei/mkhi.h
> +++ b/drivers/misc/mei/mkhi.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
> + * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
It is 2022 :(
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 10/15] mei: mkhi: add memory ready command
@ 2022-09-01 15:08 ` Greg Kroah-Hartman
0 siblings, 0 replies; 80+ messages in thread
From: Greg Kroah-Hartman @ 2022-09-01 15:08 UTC (permalink / raw)
To: Tomas Winkler
Cc: David Airlie, intel-gfx, Alexander Usyskin, linux-kernel,
Daniel Vetter, Rodrigo Vivi, Vitaly Lubart
On Sat, Aug 06, 2022 at 03:26:31PM +0300, Tomas Winkler wrote:
> Add GSC memory ready command.
> The command indicates to the firmware that extend operation
> memory was setup and the firmware may enter PXP mode.
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/mkhi.h | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
> index 27a9b476904e..056b76e73d40 100644
> --- a/drivers/misc/mei/mkhi.h
> +++ b/drivers/misc/mei/mkhi.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
> + * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
It is 2022 :(
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 00/15] GSC support for XeHP SDV and DG2
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 15:09 ` Greg Kroah-Hartman
-1 siblings, 0 replies; 80+ messages in thread
From: Greg Kroah-Hartman @ 2022-09-01 15:09 UTC (permalink / raw)
To: Tomas Winkler
Cc: David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Tvrtko Ursulin, intel-gfx, linux-kernel,
Alexander Usyskin, Vitaly Lubart
On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> Add GSC support for XeHP SDV and DG2 platforms.
>
> The series includes changes for the mei driver:
> - add ability to use polling instead of interrupts
> - add ability to use extended timeouts
> - setup extended operational memory for GSC
>
> The series includes changes for the i915 driver:
> - allocate extended operational memory for GSC
> - GSC on XeHP SDV offsets and definitions
>
> This patch set should be merged via gfx tree as
> the auxiliary device belongs there.
> Greg, your ACK is required for the drives/misc/mei code base,
> please review the patches.
With the exception that you all don't know what year it is:
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-09-01 15:09 ` Greg Kroah-Hartman
0 siblings, 0 replies; 80+ messages in thread
From: Greg Kroah-Hartman @ 2022-09-01 15:09 UTC (permalink / raw)
To: Tomas Winkler
Cc: David Airlie, intel-gfx, Alexander Usyskin, linux-kernel,
Daniel Vetter, Rodrigo Vivi, Vitaly Lubart
On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> Add GSC support for XeHP SDV and DG2 platforms.
>
> The series includes changes for the mei driver:
> - add ability to use polling instead of interrupts
> - add ability to use extended timeouts
> - setup extended operational memory for GSC
>
> The series includes changes for the i915 driver:
> - allocate extended operational memory for GSC
> - GSC on XeHP SDV offsets and definitions
>
> This patch set should be merged via gfx tree as
> the auxiliary device belongs there.
> Greg, your ACK is required for the drives/misc/mei code base,
> please review the patches.
With the exception that you all don't know what year it is:
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 02/15] mei: add kdoc for struct mei_aux_device
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 15:30 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 15:30 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> struct mei_aux_device is an interface structure
> requires proper documenation.
>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> include/linux/mei_aux.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
> index 587f25128848..a0cb587006d5 100644
> --- a/include/linux/mei_aux.h
> +++ b/include/linux/mei_aux.h
> @@ -7,6 +7,12 @@
>
> #include <linux/auxiliary_bus.h>
>
> +/**
> + * struct mei_aux_device - mei auxiliary device
> + * @aux_dev: - auxiliary device object
> + * @irq: interrupt driving the mei auxiliary device
> + * @bar: mmio resource bar reserved to mei auxiliary device
> + */
> struct mei_aux_device {
> struct auxiliary_device aux_dev;
> int irq;
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 02/15] mei: add kdoc for struct mei_aux_device
@ 2022-09-01 15:30 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 15:30 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> struct mei_aux_device is an interface structure
> requires proper documenation.
>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> include/linux/mei_aux.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
> index 587f25128848..a0cb587006d5 100644
> --- a/include/linux/mei_aux.h
> +++ b/include/linux/mei_aux.h
> @@ -7,6 +7,12 @@
>
> #include <linux/auxiliary_bus.h>
>
> +/**
> + * struct mei_aux_device - mei auxiliary device
> + * @aux_dev: - auxiliary device object
> + * @irq: interrupt driving the mei auxiliary device
> + * @bar: mmio resource bar reserved to mei auxiliary device
> + */
> struct mei_aux_device {
> struct auxiliary_device aux_dev;
> int irq;
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 05/15] drm/i915/gsc: add GSC XeHP SDV platform definition
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 15:31 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 15:31 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Alexander Usyskin <alexander.usyskin@intel.com>
>
> Define GSC on XeHP SDV (Intel(R) dGPU without display)
>
> XeHP SDV uses the same hardware settings as DG1, but uses polling
> instead of interrupts and runs the firmware in slow pace due to
> hardware limitations.
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index 73498c2574c8..e1040c8f2fd3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
> }
> };
>
> +static const struct gsc_def gsc_def_xehpsdv[] = {
> + {
> + /* HECI1 not enabled on the device. */
> + },
> + {
> + .name = "mei-gscfi",
> + .bar = DG1_GSC_HECI2_BASE,
> + .bar_size = GSC_BAR_LENGTH,
> + .use_polling = true,
> + .slow_firmware = true,
> + }
> +};
> +
> static const struct gsc_def gsc_def_dg2[] = {
> {
> .name = "mei-gsc",
> @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
>
> if (IS_DG1(i915)) {
> def = &gsc_def_dg1[intf_id];
> + } else if (IS_XEHPSDV(i915)) {
> + def = &gsc_def_xehpsdv[intf_id];
> } else if (IS_DG2(i915)) {
> def = &gsc_def_dg2[intf_id];
> } else {
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 05/15] drm/i915/gsc: add GSC XeHP SDV platform definition
@ 2022-09-01 15:31 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 15:31 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Alexander Usyskin <alexander.usyskin@intel.com>
>
> Define GSC on XeHP SDV (Intel(R) dGPU without display)
>
> XeHP SDV uses the same hardware settings as DG1, but uses polling
> instead of interrupts and runs the firmware in slow pace due to
> hardware limitations.
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index 73498c2574c8..e1040c8f2fd3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -56,6 +56,19 @@ static const struct gsc_def gsc_def_dg1[] = {
> }
> };
>
> +static const struct gsc_def gsc_def_xehpsdv[] = {
> + {
> + /* HECI1 not enabled on the device. */
> + },
> + {
> + .name = "mei-gscfi",
> + .bar = DG1_GSC_HECI2_BASE,
> + .bar_size = GSC_BAR_LENGTH,
> + .use_polling = true,
> + .slow_firmware = true,
> + }
> +};
> +
> static const struct gsc_def gsc_def_dg2[] = {
> {
> .name = "mei-gsc",
> @@ -107,6 +120,8 @@ static void gsc_init_one(struct drm_i915_private *i915,
>
> if (IS_DG1(i915)) {
> def = &gsc_def_dg1[intf_id];
> + } else if (IS_XEHPSDV(i915)) {
> + def = &gsc_def_xehpsdv[intf_id];
> } else if (IS_DG2(i915)) {
> def = &gsc_def_dg2[intf_id];
> } else {
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 06/15] mei: gsc: use polling instead of interrupts
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 16:00 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 16:00 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
> a gsc register when gsc is sending an interrupt. The work-around is
> to disable interrupts and to use polling instead.
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------
> drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++---
> drivers/misc/mei/hw-me.h | 12 ++++++++
> 3 files changed, 105 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index c8145e9b62b6..2caba3a9ac35 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -13,6 +13,7 @@
> #include <linux/ktime.h>
> #include <linux/delay.h>
> #include <linux/pm_runtime.h>
> +#include <linux/kthread.h>
>
> #include "mei_dev.h"
> #include "hw-me.h"
> @@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
>
> dev_set_drvdata(device, dev);
>
> - ret = devm_request_threaded_irq(device, hw->irq,
> - mei_me_irq_quick_handler,
> - mei_me_irq_thread_handler,
> - IRQF_ONESHOT, KBUILD_MODNAME, dev);
> - if (ret) {
> - dev_err(device, "irq register failed %d\n", ret);
> - goto err;
> + /* use polling */
> + if (mei_me_hw_use_polling(hw)) {
> + mei_disable_interrupts(dev);
> + mei_clear_interrupts(dev);
> + init_waitqueue_head(&hw->wait_active);
> + hw->is_active = true; /* start in active mode for initialization */
> + hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
> + "kmegscirqd/%s", dev_name(device));
> + if (IS_ERR(hw->polling_thread)) {
> + ret = PTR_ERR(hw->polling_thread);
> + dev_err(device, "unable to create kernel thread: %d\n", ret);
> + goto err;
> + }
> + } else {
> + ret = devm_request_threaded_irq(device, hw->irq,
> + mei_me_irq_quick_handler,
> + mei_me_irq_thread_handler,
> + IRQF_ONESHOT, KBUILD_MODNAME, dev);
> + if (ret) {
> + dev_err(device, "irq register failed %d\n", ret);
> + goto err;
> + }
> }
>
> pm_runtime_get_noresume(device);
> @@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
>
> register_err:
> mei_stop(dev);
> - devm_free_irq(device, hw->irq, dev);
> + if (!mei_me_hw_use_polling(hw))
> + devm_free_irq(device, hw->irq, dev);
>
> err:
> dev_err(device, "probe failed: %d\n", ret);
> @@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *aux_dev)
>
> mei_stop(dev);
>
> + hw = to_me_hw(dev);
> + if (mei_me_hw_use_polling(hw))
> + kthread_stop(hw->polling_thread);
> +
> mei_deregister(dev);
>
> pm_runtime_disable(&aux_dev->dev);
>
> mei_disable_interrupts(dev);
> - devm_free_irq(&aux_dev->dev, hw->irq, dev);
> + if (!mei_me_hw_use_polling(hw))
> + devm_free_irq(&aux_dev->dev, hw->irq, dev);
> }
>
> static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
> @@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
> if (mei_write_is_idle(dev)) {
> hw = to_me_hw(dev);
> hw->pg_state = MEI_PG_ON;
> +
> + if (mei_me_hw_use_polling(hw))
> + hw->is_active = false;
> ret = 0;
> } else {
> ret = -EAGAIN;
> @@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
> hw = to_me_hw(dev);
> hw->pg_state = MEI_PG_OFF;
>
> + if (mei_me_hw_use_polling(hw)) {
> + hw->is_active = true;
> + wake_up(&hw->wait_active);
> + }
> +
> mutex_unlock(&dev->device_lock);
>
> irq_ret = mei_me_irq_thread_handler(1, dev);
> diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
> index befa491e3344..46559517a902 100644
> --- a/drivers/misc/mei/hw-me.c
> +++ b/drivers/misc/mei/hw-me.c
> @@ -10,6 +10,7 @@
> #include <linux/interrupt.h>
> #include <linux/pm_runtime.h>
> #include <linux/sizes.h>
> +#include <linux/delay.h>
>
> #include "mei_dev.h"
> #include "hbm.h"
> @@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
> */
> static void mei_me_intr_enable(struct mei_device *dev)
> {
> - u32 hcsr = mei_hcsr_read(dev);
> + u32 hcsr;
> +
> + if (mei_me_hw_use_polling(to_me_hw(dev)))
> + return;
>
> - hcsr |= H_CSR_IE_MASK;
> + hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
> mei_hcsr_set(dev, hcsr);
> }
>
> @@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *dev)
> {
> struct mei_me_hw *hw = to_me_hw(dev);
>
> + if (mei_me_hw_use_polling(hw))
> + return;
> +
> synchronize_irq(hw->irq);
> }
>
> @@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *dev)
> {
> u32 hcsr = mei_hcsr_read(dev);
>
> - hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
> + if (!mei_me_hw_use_polling(to_me_hw(dev)))
> + hcsr |= H_CSR_IE_MASK;
> +
> + hcsr |= H_IG | H_RDY;
> mei_hcsr_set(dev, hcsr);
> }
>
> @@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
>
> hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
>
> - if (!intr_enable)
> + if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
> hcsr &= ~H_CSR_IE_MASK;
>
> dev->recvd_hw_ready = false;
> @@ -1331,6 +1341,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
> }
> EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
>
> +#define MEI_POLLING_TIMEOUT_ACTIVE 100
> +#define MEI_POLLING_TIMEOUT_IDLE 500
> +
> +int mei_me_polling_thread(void *_dev)
> +{
> + struct mei_device *dev = _dev;
> + irqreturn_t irq_ret;
> + long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
> +
> + dev_dbg(dev->dev, "kernel thread is running\n");
> + while (!kthread_should_stop()) {
> + struct mei_me_hw *hw = to_me_hw(dev);
> + u32 hcsr;
> +
> + wait_event_timeout(hw->wait_active,
> + hw->is_active || kthread_should_stop(),
> + msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
> +
> + if (kthread_should_stop())
> + break;
> +
> + hcsr = mei_hcsr_read(dev);
> + if (me_intr_src(hcsr)) {
> + polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
> + irq_ret = mei_me_irq_thread_handler(1, dev);
> + if (irq_ret != IRQ_HANDLED)
> + dev_err(dev->dev, "irq_ret %d\n", irq_ret);
> + } else {
> + polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
> + MEI_POLLING_TIMEOUT_ACTIVE,
> + MEI_POLLING_TIMEOUT_IDLE);
> + }
> +
> + schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
> + }
IMO this loop could have used a couple of comments to make it easier to
understand what's going on with the various waits and timeouts. Not a
blocker.
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mei_me_polling_thread);
> +
> static const struct mei_hw_ops mei_me_hw_ops = {
>
> .trc_status = mei_me_trc_status,
> diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
> index a071c645e905..ca09274ac299 100644
> --- a/drivers/misc/mei/hw-me.h
> +++ b/drivers/misc/mei/hw-me.h
> @@ -51,6 +51,8 @@ struct mei_cfg {
> * @d0i3_supported: di03 support
> * @hbuf_depth: depth of hardware host/write buffer in slots
> * @read_fws: read FW status register handler
> + * @wait_active: the polling thread activity wait queue
> + * @is_active: the device is active
> */
> struct mei_me_hw {
> const struct mei_cfg *cfg;
> @@ -60,10 +62,19 @@ struct mei_me_hw {
> bool d0i3_supported;
> u8 hbuf_depth;
> int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
> + /* polling */
> + struct task_struct *polling_thread;
> + wait_queue_head_t wait_active;
> + bool is_active;
> };
>
> #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
>
> +static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
> +{
> + return hw->irq < 0;
> +}
> +
> /**
> * enum mei_cfg_idx - indices to platform specific configurations.
> *
> @@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev);
>
> irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
> irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
> +int mei_me_polling_thread(void *_dev);
>
> #endif /* _MEI_INTERFACE_H_ */
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 06/15] mei: gsc: use polling instead of interrupts
@ 2022-09-01 16:00 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 16:00 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> A work-around for a HW issue in XEHPSDV that manifests itself when SW reads
> a gsc register when gsc is sending an interrupt. The work-around is
> to disable interrupts and to use polling instead.
>
> Cc: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/gsc-me.c | 48 ++++++++++++++++++++++++++------
> drivers/misc/mei/hw-me.c | 58 ++++++++++++++++++++++++++++++++++++---
> drivers/misc/mei/hw-me.h | 12 ++++++++
> 3 files changed, 105 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index c8145e9b62b6..2caba3a9ac35 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -13,6 +13,7 @@
> #include <linux/ktime.h>
> #include <linux/delay.h>
> #include <linux/pm_runtime.h>
> +#include <linux/kthread.h>
>
> #include "mei_dev.h"
> #include "hw-me.h"
> @@ -66,13 +67,28 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
>
> dev_set_drvdata(device, dev);
>
> - ret = devm_request_threaded_irq(device, hw->irq,
> - mei_me_irq_quick_handler,
> - mei_me_irq_thread_handler,
> - IRQF_ONESHOT, KBUILD_MODNAME, dev);
> - if (ret) {
> - dev_err(device, "irq register failed %d\n", ret);
> - goto err;
> + /* use polling */
> + if (mei_me_hw_use_polling(hw)) {
> + mei_disable_interrupts(dev);
> + mei_clear_interrupts(dev);
> + init_waitqueue_head(&hw->wait_active);
> + hw->is_active = true; /* start in active mode for initialization */
> + hw->polling_thread = kthread_run(mei_me_polling_thread, dev,
> + "kmegscirqd/%s", dev_name(device));
> + if (IS_ERR(hw->polling_thread)) {
> + ret = PTR_ERR(hw->polling_thread);
> + dev_err(device, "unable to create kernel thread: %d\n", ret);
> + goto err;
> + }
> + } else {
> + ret = devm_request_threaded_irq(device, hw->irq,
> + mei_me_irq_quick_handler,
> + mei_me_irq_thread_handler,
> + IRQF_ONESHOT, KBUILD_MODNAME, dev);
> + if (ret) {
> + dev_err(device, "irq register failed %d\n", ret);
> + goto err;
> + }
> }
>
> pm_runtime_get_noresume(device);
> @@ -98,7 +114,8 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
>
> register_err:
> mei_stop(dev);
> - devm_free_irq(device, hw->irq, dev);
> + if (!mei_me_hw_use_polling(hw))
> + devm_free_irq(device, hw->irq, dev);
>
> err:
> dev_err(device, "probe failed: %d\n", ret);
> @@ -119,12 +136,17 @@ static void mei_gsc_remove(struct auxiliary_device *aux_dev)
>
> mei_stop(dev);
>
> + hw = to_me_hw(dev);
> + if (mei_me_hw_use_polling(hw))
> + kthread_stop(hw->polling_thread);
> +
> mei_deregister(dev);
>
> pm_runtime_disable(&aux_dev->dev);
>
> mei_disable_interrupts(dev);
> - devm_free_irq(&aux_dev->dev, hw->irq, dev);
> + if (!mei_me_hw_use_polling(hw))
> + devm_free_irq(&aux_dev->dev, hw->irq, dev);
> }
>
> static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
> @@ -185,6 +207,9 @@ static int __maybe_unused mei_gsc_pm_runtime_suspend(struct device *device)
> if (mei_write_is_idle(dev)) {
> hw = to_me_hw(dev);
> hw->pg_state = MEI_PG_ON;
> +
> + if (mei_me_hw_use_polling(hw))
> + hw->is_active = false;
> ret = 0;
> } else {
> ret = -EAGAIN;
> @@ -209,6 +234,11 @@ static int __maybe_unused mei_gsc_pm_runtime_resume(struct device *device)
> hw = to_me_hw(dev);
> hw->pg_state = MEI_PG_OFF;
>
> + if (mei_me_hw_use_polling(hw)) {
> + hw->is_active = true;
> + wake_up(&hw->wait_active);
> + }
> +
> mutex_unlock(&dev->device_lock);
>
> irq_ret = mei_me_irq_thread_handler(1, dev);
> diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
> index befa491e3344..46559517a902 100644
> --- a/drivers/misc/mei/hw-me.c
> +++ b/drivers/misc/mei/hw-me.c
> @@ -10,6 +10,7 @@
> #include <linux/interrupt.h>
> #include <linux/pm_runtime.h>
> #include <linux/sizes.h>
> +#include <linux/delay.h>
>
> #include "mei_dev.h"
> #include "hbm.h"
> @@ -327,9 +328,12 @@ static void mei_me_intr_clear(struct mei_device *dev)
> */
> static void mei_me_intr_enable(struct mei_device *dev)
> {
> - u32 hcsr = mei_hcsr_read(dev);
> + u32 hcsr;
> +
> + if (mei_me_hw_use_polling(to_me_hw(dev)))
> + return;
>
> - hcsr |= H_CSR_IE_MASK;
> + hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
> mei_hcsr_set(dev, hcsr);
> }
>
> @@ -354,6 +358,9 @@ static void mei_me_synchronize_irq(struct mei_device *dev)
> {
> struct mei_me_hw *hw = to_me_hw(dev);
>
> + if (mei_me_hw_use_polling(hw))
> + return;
> +
> synchronize_irq(hw->irq);
> }
>
> @@ -380,7 +387,10 @@ static void mei_me_host_set_ready(struct mei_device *dev)
> {
> u32 hcsr = mei_hcsr_read(dev);
>
> - hcsr |= H_CSR_IE_MASK | H_IG | H_RDY;
> + if (!mei_me_hw_use_polling(to_me_hw(dev)))
> + hcsr |= H_CSR_IE_MASK;
> +
> + hcsr |= H_IG | H_RDY;
> mei_hcsr_set(dev, hcsr);
> }
>
> @@ -1176,7 +1186,7 @@ static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
>
> hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
>
> - if (!intr_enable)
> + if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
> hcsr &= ~H_CSR_IE_MASK;
>
> dev->recvd_hw_ready = false;
> @@ -1331,6 +1341,46 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
> }
> EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
>
> +#define MEI_POLLING_TIMEOUT_ACTIVE 100
> +#define MEI_POLLING_TIMEOUT_IDLE 500
> +
> +int mei_me_polling_thread(void *_dev)
> +{
> + struct mei_device *dev = _dev;
> + irqreturn_t irq_ret;
> + long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
> +
> + dev_dbg(dev->dev, "kernel thread is running\n");
> + while (!kthread_should_stop()) {
> + struct mei_me_hw *hw = to_me_hw(dev);
> + u32 hcsr;
> +
> + wait_event_timeout(hw->wait_active,
> + hw->is_active || kthread_should_stop(),
> + msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
> +
> + if (kthread_should_stop())
> + break;
> +
> + hcsr = mei_hcsr_read(dev);
> + if (me_intr_src(hcsr)) {
> + polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
> + irq_ret = mei_me_irq_thread_handler(1, dev);
> + if (irq_ret != IRQ_HANDLED)
> + dev_err(dev->dev, "irq_ret %d\n", irq_ret);
> + } else {
> + polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
> + MEI_POLLING_TIMEOUT_ACTIVE,
> + MEI_POLLING_TIMEOUT_IDLE);
> + }
> +
> + schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
> + }
IMO this loop could have used a couple of comments to make it easier to
understand what's going on with the various waits and timeouts. Not a
blocker.
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(mei_me_polling_thread);
> +
> static const struct mei_hw_ops mei_me_hw_ops = {
>
> .trc_status = mei_me_trc_status,
> diff --git a/drivers/misc/mei/hw-me.h b/drivers/misc/mei/hw-me.h
> index a071c645e905..ca09274ac299 100644
> --- a/drivers/misc/mei/hw-me.h
> +++ b/drivers/misc/mei/hw-me.h
> @@ -51,6 +51,8 @@ struct mei_cfg {
> * @d0i3_supported: di03 support
> * @hbuf_depth: depth of hardware host/write buffer in slots
> * @read_fws: read FW status register handler
> + * @wait_active: the polling thread activity wait queue
> + * @is_active: the device is active
> */
> struct mei_me_hw {
> const struct mei_cfg *cfg;
> @@ -60,10 +62,19 @@ struct mei_me_hw {
> bool d0i3_supported;
> u8 hbuf_depth;
> int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
> + /* polling */
> + struct task_struct *polling_thread;
> + wait_queue_head_t wait_active;
> + bool is_active;
> };
>
> #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
>
> +static inline bool mei_me_hw_use_polling(const struct mei_me_hw *hw)
> +{
> + return hw->irq < 0;
> +}
> +
> /**
> * enum mei_cfg_idx - indices to platform specific configurations.
> *
> @@ -127,5 +138,6 @@ int mei_me_pg_exit_sync(struct mei_device *dev);
>
> irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
> irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
> +int mei_me_polling_thread(void *_dev);
>
> #endif /* _MEI_INTERFACE_H_ */
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 07/15] mei: gsc: wait for reset thread on stop
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 16:07 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 16:07 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Alexander Usyskin <alexander.usyskin@intel.com>
>
> Wait for reset work to complete before initiating
> stop reset flow sequence.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/init.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
> index eb052005ca86..5bb6ba662cc0 100644
> --- a/drivers/misc/mei/init.c
> +++ b/drivers/misc/mei/init.c
> @@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
>
> mei_clear_interrupts(dev);
> mei_synchronize_irq(dev);
> + /* to catch HW-initiated reset */
> + mei_cancel_work(dev);
>
> mutex_lock(&dev->device_lock);
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 07/15] mei: gsc: wait for reset thread on stop
@ 2022-09-01 16:07 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 16:07 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Alexander Usyskin <alexander.usyskin@intel.com>
>
> Wait for reset work to complete before initiating
> stop reset flow sequence.
>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/init.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
> index eb052005ca86..5bb6ba662cc0 100644
> --- a/drivers/misc/mei/init.c
> +++ b/drivers/misc/mei/init.c
> @@ -320,6 +320,8 @@ void mei_stop(struct mei_device *dev)
>
> mei_clear_interrupts(dev);
> mei_synchronize_irq(dev);
> + /* to catch HW-initiated reset */
> + mei_cancel_work(dev);
>
> mutex_lock(&dev->device_lock);
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 16:31 ` Teres Alexis, Alan Previn
-1 siblings, 0 replies; 80+ messages in thread
From: Teres Alexis, Alan Previn @ 2022-09-01 16:31 UTC (permalink / raw)
To: daniel, Winkler, Tomas, gregkh, airlied
Cc: Vivi, Rodrigo, Lubart, Vitaly, Usyskin, Alexander,
joonas.lahtinen, intel-gfx, linux-kernel, tvrtko.ursulin,
Ceraolo Spurio, Daniele, jani.nikula
This patch hasnt changed since v5 and i already provided the R-b then so re-posting rb so patchworks can pick it up:
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
On Sat, 2022-08-06 at 15:26 +0300, Winkler, Tomas wrote:
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
> 2 files changed, 87 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index e1040c8f2fd3..162bea57fbb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -7,6 +7,7 @@
> #include <linux/mei_aux.h>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "gem/i915_gem_region.h"
> #include "gt/intel_gsc.h"
> #include "gt/intel_gt.h"
>
> @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
> return irq_set_chip_data(irq, NULL);
> }
>
> +static int
> +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
> +{
> + struct intel_gt *gt = gsc_to_gt(gsc);
> + struct drm_i915_gem_object *obj;
> + void *vaddr;
> + int err;
> +
> + obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
> + if (IS_ERR(obj)) {
> + drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
> + return PTR_ERR(obj);
> + }
> +
> + err = i915_gem_object_pin_pages_unlocked(obj);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
> + goto out_put;
> + }
> +
> + vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
> + if (IS_ERR(vaddr)) {
> + err = PTR_ERR(vaddr);
> + drm_err(>->i915->drm, "Failed to map gsc memory\n");
> + goto out_unpin;
> + }
> +
> + memset(vaddr, 0, obj->base.size);
> +
> + i915_gem_object_unpin_map(obj);
> +
> + intf->gem_obj = obj;
> +
> + return 0;
> +
> +out_unpin:
> + i915_gem_object_unpin_pages(obj);
> +out_put:
> + i915_gem_object_put(obj);
> + return err;
> +}
> +
> +static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
> +{
> + struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
> +
> + if (!obj)
> + return;
> +
> + if (i915_gem_object_has_pinned_pages(obj))
> + i915_gem_object_unpin_pages(obj);
> +
> + i915_gem_object_put(obj);
> +}
> +
> struct gsc_def {
> const char *name;
> unsigned long bar;
> size_t bar_size;
> bool use_polling;
> bool slow_firmware;
> + size_t lmem_size;
> };
>
> /* gsc resources and definitions (HECI1 and HECI2) */
> @@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
> .name = "mei-gsc",
> .bar = DG2_GSC_HECI1_BASE,
> .bar_size = GSC_BAR_LENGTH,
> + .lmem_size = SZ_4M,
> },
> {
> .name = "mei-gscfi",
> @@ -90,26 +148,32 @@ static void gsc_release_dev(struct device *dev)
> kfree(adev);
> }
>
> -static void gsc_destroy_one(struct intel_gsc_intf *intf)
> +static void gsc_destroy_one(struct drm_i915_private *i915,
> + struct intel_gsc *gsc, unsigned int intf_id)
> {
> + struct intel_gsc_intf *intf = &gsc->intf[intf_id];
> +
> if (intf->adev) {
> auxiliary_device_delete(&intf->adev->aux_dev);
> auxiliary_device_uninit(&intf->adev->aux_dev);
> intf->adev = NULL;
> }
> +
> if (intf->irq >= 0)
> irq_free_desc(intf->irq);
> intf->irq = -1;
> +
> + gsc_ext_om_destroy(intf);
> }
>
> -static void gsc_init_one(struct drm_i915_private *i915,
> - struct intel_gsc_intf *intf,
> +static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
> unsigned int intf_id)
> {
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct mei_aux_device *adev;
> struct auxiliary_device *aux_dev;
> const struct gsc_def *def;
> + struct intel_gsc_intf *intf = &gsc->intf[intf_id];
> int ret;
>
> intf->irq = -1;
> @@ -141,7 +205,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
> intf->irq = irq_alloc_desc(0);
> if (intf->irq < 0) {
> drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
> - return;
> + goto fail;
> }
>
> ret = gsc_irq_init(intf->irq);
> @@ -155,6 +219,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
> if (!adev)
> goto fail;
>
> + if (def->lmem_size) {
> + drm_dbg(&i915->drm, "setting up GSC lmem\n");
> +
> + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> + drm_err(&i915->drm, "setting up gsc extended operational memory failed\n");
> + kfree(adev);
> + goto fail;
> + }
> +
> + adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
> + adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
> + }
> +
> adev->irq = intf->irq;
> adev->bar.parent = &pdev->resource[0];
> adev->bar.start = def->bar + pdev->resource[0].start;
> @@ -188,7 +265,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
>
> return;
> fail:
> - gsc_destroy_one(intf);
> + gsc_destroy_one(i915, gsc, intf->id);
> }
>
> static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
> @@ -229,7 +306,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
> return;
>
> for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
> - gsc_init_one(i915, &gsc->intf[i], i);
> + gsc_init_one(i915, gsc, i);
> }
>
> void intel_gsc_fini(struct intel_gsc *gsc)
> @@ -241,5 +318,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
> return;
>
> for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
> - gsc_destroy_one(&gsc->intf[i]);
> + gsc_destroy_one(gt->i915, gsc, i);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
> index 68582f912b21..fcac1775e9c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
> @@ -20,11 +20,14 @@ struct mei_aux_device;
>
> /**
> * struct intel_gsc - graphics security controller
> + *
> + * @gem_obj: scratch memory GSC operations
> * @intf : gsc interface
> */
> struct intel_gsc {
> struct intel_gsc_intf {
> struct mei_aux_device *adev;
> + struct drm_i915_gem_object *gem_obj;
> int irq;
> unsigned int id;
> } intf[INTEL_GSC_NUM_INTERFACES];
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
@ 2022-09-01 16:31 ` Teres Alexis, Alan Previn
0 siblings, 0 replies; 80+ messages in thread
From: Teres Alexis, Alan Previn @ 2022-09-01 16:31 UTC (permalink / raw)
To: daniel, Winkler, Tomas, gregkh, airlied
Cc: intel-gfx, Usyskin, Alexander, linux-kernel, Vivi, Rodrigo,
Lubart, Vitaly
This patch hasnt changed since v5 and i already provided the R-b then so re-posting rb so patchworks can pick it up:
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
On Sat, 2022-08-06 at 15:26 +0300, Winkler, Tomas wrote:
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
> 2 files changed, 87 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index e1040c8f2fd3..162bea57fbb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -7,6 +7,7 @@
> #include <linux/mei_aux.h>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "gem/i915_gem_region.h"
> #include "gt/intel_gsc.h"
> #include "gt/intel_gt.h"
>
> @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
> return irq_set_chip_data(irq, NULL);
> }
>
> +static int
> +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
> +{
> + struct intel_gt *gt = gsc_to_gt(gsc);
> + struct drm_i915_gem_object *obj;
> + void *vaddr;
> + int err;
> +
> + obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
> + if (IS_ERR(obj)) {
> + drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
> + return PTR_ERR(obj);
> + }
> +
> + err = i915_gem_object_pin_pages_unlocked(obj);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
> + goto out_put;
> + }
> +
> + vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
> + if (IS_ERR(vaddr)) {
> + err = PTR_ERR(vaddr);
> + drm_err(>->i915->drm, "Failed to map gsc memory\n");
> + goto out_unpin;
> + }
> +
> + memset(vaddr, 0, obj->base.size);
> +
> + i915_gem_object_unpin_map(obj);
> +
> + intf->gem_obj = obj;
> +
> + return 0;
> +
> +out_unpin:
> + i915_gem_object_unpin_pages(obj);
> +out_put:
> + i915_gem_object_put(obj);
> + return err;
> +}
> +
> +static void gsc_ext_om_destroy(struct intel_gsc_intf *intf)
> +{
> + struct drm_i915_gem_object *obj = fetch_and_zero(&intf->gem_obj);
> +
> + if (!obj)
> + return;
> +
> + if (i915_gem_object_has_pinned_pages(obj))
> + i915_gem_object_unpin_pages(obj);
> +
> + i915_gem_object_put(obj);
> +}
> +
> struct gsc_def {
> const char *name;
> unsigned long bar;
> size_t bar_size;
> bool use_polling;
> bool slow_firmware;
> + size_t lmem_size;
> };
>
> /* gsc resources and definitions (HECI1 and HECI2) */
> @@ -74,6 +131,7 @@ static const struct gsc_def gsc_def_dg2[] = {
> .name = "mei-gsc",
> .bar = DG2_GSC_HECI1_BASE,
> .bar_size = GSC_BAR_LENGTH,
> + .lmem_size = SZ_4M,
> },
> {
> .name = "mei-gscfi",
> @@ -90,26 +148,32 @@ static void gsc_release_dev(struct device *dev)
> kfree(adev);
> }
>
> -static void gsc_destroy_one(struct intel_gsc_intf *intf)
> +static void gsc_destroy_one(struct drm_i915_private *i915,
> + struct intel_gsc *gsc, unsigned int intf_id)
> {
> + struct intel_gsc_intf *intf = &gsc->intf[intf_id];
> +
> if (intf->adev) {
> auxiliary_device_delete(&intf->adev->aux_dev);
> auxiliary_device_uninit(&intf->adev->aux_dev);
> intf->adev = NULL;
> }
> +
> if (intf->irq >= 0)
> irq_free_desc(intf->irq);
> intf->irq = -1;
> +
> + gsc_ext_om_destroy(intf);
> }
>
> -static void gsc_init_one(struct drm_i915_private *i915,
> - struct intel_gsc_intf *intf,
> +static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc,
> unsigned int intf_id)
> {
> struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> struct mei_aux_device *adev;
> struct auxiliary_device *aux_dev;
> const struct gsc_def *def;
> + struct intel_gsc_intf *intf = &gsc->intf[intf_id];
> int ret;
>
> intf->irq = -1;
> @@ -141,7 +205,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
> intf->irq = irq_alloc_desc(0);
> if (intf->irq < 0) {
> drm_err(&i915->drm, "gsc irq error %d\n", intf->irq);
> - return;
> + goto fail;
> }
>
> ret = gsc_irq_init(intf->irq);
> @@ -155,6 +219,19 @@ static void gsc_init_one(struct drm_i915_private *i915,
> if (!adev)
> goto fail;
>
> + if (def->lmem_size) {
> + drm_dbg(&i915->drm, "setting up GSC lmem\n");
> +
> + if (gsc_ext_om_alloc(gsc, intf, def->lmem_size)) {
> + drm_err(&i915->drm, "setting up gsc extended operational memory failed\n");
> + kfree(adev);
> + goto fail;
> + }
> +
> + adev->ext_op_mem.start = i915_gem_object_get_dma_address(intf->gem_obj, 0);
> + adev->ext_op_mem.end = adev->ext_op_mem.start + def->lmem_size;
> + }
> +
> adev->irq = intf->irq;
> adev->bar.parent = &pdev->resource[0];
> adev->bar.start = def->bar + pdev->resource[0].start;
> @@ -188,7 +265,7 @@ static void gsc_init_one(struct drm_i915_private *i915,
>
> return;
> fail:
> - gsc_destroy_one(intf);
> + gsc_destroy_one(i915, gsc, intf->id);
> }
>
> static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id)
> @@ -229,7 +306,7 @@ void intel_gsc_init(struct intel_gsc *gsc, struct drm_i915_private *i915)
> return;
>
> for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
> - gsc_init_one(i915, &gsc->intf[i], i);
> + gsc_init_one(i915, gsc, i);
> }
>
> void intel_gsc_fini(struct intel_gsc *gsc)
> @@ -241,5 +318,5 @@ void intel_gsc_fini(struct intel_gsc *gsc)
> return;
>
> for (i = 0; i < INTEL_GSC_NUM_INTERFACES; i++)
> - gsc_destroy_one(&gsc->intf[i]);
> + gsc_destroy_one(gt->i915, gsc, i);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.h b/drivers/gpu/drm/i915/gt/intel_gsc.h
> index 68582f912b21..fcac1775e9c3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.h
> @@ -20,11 +20,14 @@ struct mei_aux_device;
>
> /**
> * struct intel_gsc - graphics security controller
> + *
> + * @gem_obj: scratch memory GSC operations
> * @intf : gsc interface
> */
> struct intel_gsc {
> struct intel_gsc_intf {
> struct mei_aux_device *adev;
> + struct drm_i915_gem_object *gem_obj;
> int irq;
> unsigned int id;
> } intf[INTEL_GSC_NUM_INTERFACES];
> --
> 2.37.1
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 08/15] mei: extend timeouts on slow devices.
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 17:00 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 17:00 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
<snip>
> @@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev)
> static int mei_me_d0i3_exit_sync(struct mei_device *dev)
> {
> struct mei_me_hw *hw = to_me_hw(dev);
> - unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
> int ret;
> u32 reg;
>
> @@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *dev)
>
> mutex_unlock(&dev->device_lock);
> wait_event_timeout(dev->wait_pg,
> - dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
> + dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
> + dev->timeouts.pgi);
Shouldn't this be timeouts.d0i3, given that it replaces
mei_secs_to_jiffies(MEI_D0I3_TIMEOUT)?
Apart from this, all the other replacements look ok, so with this fixed:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> mutex_lock(&dev->device_lock);
>
> if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 08/15] mei: extend timeouts on slow devices.
@ 2022-09-01 17:00 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 17:00 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
<snip>
> @@ -990,7 +991,6 @@ static int mei_me_d0i3_enter(struct mei_device *dev)
> static int mei_me_d0i3_exit_sync(struct mei_device *dev)
> {
> struct mei_me_hw *hw = to_me_hw(dev);
> - unsigned long timeout = mei_secs_to_jiffies(MEI_D0I3_TIMEOUT);
> int ret;
> u32 reg;
>
> @@ -1013,7 +1013,8 @@ static int mei_me_d0i3_exit_sync(struct mei_device *dev)
>
> mutex_unlock(&dev->device_lock);
> wait_event_timeout(dev->wait_pg,
> - dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED, timeout);
> + dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
> + dev->timeouts.pgi);
Shouldn't this be timeouts.d0i3, given that it replaces
mei_secs_to_jiffies(MEI_D0I3_TIMEOUT)?
Apart from this, all the other replacements look ok, so with this fixed:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> mutex_lock(&dev->device_lock);
>
> if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 20:54 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 20:54 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Exported common mkhi definitions from bus-fixup.c into a separate
> header file mkhi.h for other driver usage.
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/bus-fixup.c | 31 +------------------------
> drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+), 30 deletions(-)
> create mode 100644 drivers/misc/mei/mkhi.h
>
> diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
> index 24e91a9ea558..811c94ebf250 100644
> --- a/drivers/misc/mei/bus-fixup.c
> +++ b/drivers/misc/mei/bus-fixup.c
> @@ -15,6 +15,7 @@
>
> #include "mei_dev.h"
> #include "client.h"
> +#include "mkhi.h"
>
> #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
> 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
> @@ -89,20 +90,6 @@ struct mei_os_ver {
> u8 reserved2;
> } __packed;
>
> -#define MKHI_FEATURE_PTT 0x10
> -
> -struct mkhi_rule_id {
> - __le16 rule_type;
> - u8 feature_id;
> - u8 reserved;
> -} __packed;
> -
> -struct mkhi_fwcaps {
> - struct mkhi_rule_id id;
> - u8 len;
> - u8 data[];
> -} __packed;
> -
> struct mkhi_fw_ver_block {
> u16 minor;
> u8 major;
> @@ -115,22 +102,6 @@ struct mkhi_fw_ver {
> struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
> } __packed;
>
> -#define MKHI_FWCAPS_GROUP_ID 0x3
> -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
> -#define MKHI_GEN_GROUP_ID 0xFF
> -#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
> -struct mkhi_msg_hdr {
> - u8 group_id;
> - u8 command;
> - u8 reserved;
> - u8 result;
> -} __packed;
> -
> -struct mkhi_msg {
> - struct mkhi_msg_hdr hdr;
> - u8 data[];
> -} __packed;
> -
> #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
> sizeof(struct mkhi_fwcaps) + \
> sizeof(struct mei_os_ver))
> diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
> new file mode 100644
> index 000000000000..27a9b476904e
> --- /dev/null
> +++ b/drivers/misc/mei/mkhi.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
2022 (can fix when merging)
> + * Intel Management Engine Interface (Intel MEI) Linux driver
> + */
> +
> +#ifndef _MEI_MKHI_H_
> +#define _MEI_MKHI_H_
> +
> +#include "mei_dev.h"
Any reason you need the full mei_dev.h and not just linux/types.h ?
> +
> +#define MKHI_FEATURE_PTT 0x10
> +
> +#define MKHI_FWCAPS_GROUP_ID 0x3
> +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
> +#define MKHI_GEN_GROUP_ID 0xFF
> +#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
> +
> +#define MCHI_GROUP_ID 0xA
This is new and doesn't seem to be used in follow-up patches. Any reason
for adding it in?
Daniele
> +
> +struct mkhi_rule_id {
> + __le16 rule_type;
> + u8 feature_id;
> + u8 reserved;
> +} __packed;
> +
> +struct mkhi_fwcaps {
> + struct mkhi_rule_id id;
> + u8 len;
> + u8 data[];
> +} __packed;
> +
> +struct mkhi_msg_hdr {
> + u8 group_id;
> + u8 command;
> + u8 reserved;
> + u8 result;
> +} __packed;
> +
> +struct mkhi_msg {
> + struct mkhi_msg_hdr hdr;
> + u8 data[];
> +} __packed;
> +
> +#endif /* _MEI_MKHI_H_ */
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header
@ 2022-09-01 20:54 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 20:54 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Exported common mkhi definitions from bus-fixup.c into a separate
> header file mkhi.h for other driver usage.
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/bus-fixup.c | 31 +------------------------
> drivers/misc/mei/mkhi.h | 45 ++++++++++++++++++++++++++++++++++++
> 2 files changed, 46 insertions(+), 30 deletions(-)
> create mode 100644 drivers/misc/mei/mkhi.h
>
> diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
> index 24e91a9ea558..811c94ebf250 100644
> --- a/drivers/misc/mei/bus-fixup.c
> +++ b/drivers/misc/mei/bus-fixup.c
> @@ -15,6 +15,7 @@
>
> #include "mei_dev.h"
> #include "client.h"
> +#include "mkhi.h"
>
> #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
> 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06)
> @@ -89,20 +90,6 @@ struct mei_os_ver {
> u8 reserved2;
> } __packed;
>
> -#define MKHI_FEATURE_PTT 0x10
> -
> -struct mkhi_rule_id {
> - __le16 rule_type;
> - u8 feature_id;
> - u8 reserved;
> -} __packed;
> -
> -struct mkhi_fwcaps {
> - struct mkhi_rule_id id;
> - u8 len;
> - u8 data[];
> -} __packed;
> -
> struct mkhi_fw_ver_block {
> u16 minor;
> u8 major;
> @@ -115,22 +102,6 @@ struct mkhi_fw_ver {
> struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
> } __packed;
>
> -#define MKHI_FWCAPS_GROUP_ID 0x3
> -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
> -#define MKHI_GEN_GROUP_ID 0xFF
> -#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
> -struct mkhi_msg_hdr {
> - u8 group_id;
> - u8 command;
> - u8 reserved;
> - u8 result;
> -} __packed;
> -
> -struct mkhi_msg {
> - struct mkhi_msg_hdr hdr;
> - u8 data[];
> -} __packed;
> -
> #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
> sizeof(struct mkhi_fwcaps) + \
> sizeof(struct mei_os_ver))
> diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
> new file mode 100644
> index 000000000000..27a9b476904e
> --- /dev/null
> +++ b/drivers/misc/mei/mkhi.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
2022 (can fix when merging)
> + * Intel Management Engine Interface (Intel MEI) Linux driver
> + */
> +
> +#ifndef _MEI_MKHI_H_
> +#define _MEI_MKHI_H_
> +
> +#include "mei_dev.h"
Any reason you need the full mei_dev.h and not just linux/types.h ?
> +
> +#define MKHI_FEATURE_PTT 0x10
> +
> +#define MKHI_FWCAPS_GROUP_ID 0x3
> +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6
> +#define MKHI_GEN_GROUP_ID 0xFF
> +#define MKHI_GEN_GET_FW_VERSION_CMD 0x2
> +
> +#define MCHI_GROUP_ID 0xA
This is new and doesn't seem to be used in follow-up patches. Any reason
for adding it in?
Daniele
> +
> +struct mkhi_rule_id {
> + __le16 rule_type;
> + u8 feature_id;
> + u8 reserved;
> +} __packed;
> +
> +struct mkhi_fwcaps {
> + struct mkhi_rule_id id;
> + u8 len;
> + u8 data[];
> +} __packed;
> +
> +struct mkhi_msg_hdr {
> + u8 group_id;
> + u8 command;
> + u8 reserved;
> + u8 result;
> +} __packed;
> +
> +struct mkhi_msg {
> + struct mkhi_msg_hdr hdr;
> + u8 data[];
> +} __packed;
> +
> +#endif /* _MEI_MKHI_H_ */
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 10/15] mei: mkhi: add memory ready command
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 20:56 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 20:56 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Alexander Usyskin, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> Add GSC memory ready command.
> The command indicates to the firmware that extend operation
> memory was setup and the firmware may enter PXP mode.
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Copyright date aside, this is:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/mkhi.h | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
> index 27a9b476904e..056b76e73d40 100644
> --- a/drivers/misc/mei/mkhi.h
> +++ b/drivers/misc/mei/mkhi.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
> + * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
> * Intel Management Engine Interface (Intel MEI) Linux driver
> */
>
> @@ -18,6 +18,13 @@
>
> #define MCHI_GROUP_ID 0xA
>
> +#define MKHI_GROUP_ID_GFX 0x30
> +#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0
> +#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1
> +
> +/* Allow transition to PXP mode without approval */
> +#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1
> +
> struct mkhi_rule_id {
> __le16 rule_type;
> u8 feature_id;
> @@ -42,4 +49,9 @@ struct mkhi_msg {
> u8 data[];
> } __packed;
>
> +struct mkhi_gfx_mem_ready {
> + struct mkhi_msg_hdr hdr;
> + u32 flags;
> +} __packed;
> +
> #endif /* _MEI_MKHI_H_ */
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 10/15] mei: mkhi: add memory ready command
@ 2022-09-01 20:56 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 20:56 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> Add GSC memory ready command.
> The command indicates to the firmware that extend operation
> memory was setup and the firmware may enter PXP mode.
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Copyright date aside, this is:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/mkhi.h | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h
> index 27a9b476904e..056b76e73d40 100644
> --- a/drivers/misc/mei/mkhi.h
> +++ b/drivers/misc/mei/mkhi.h
> @@ -1,6 +1,6 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
> + * Copyright (c) 2003-2021, Intel Corporation. All rights reserved.
> * Intel Management Engine Interface (Intel MEI) Linux driver
> */
>
> @@ -18,6 +18,13 @@
>
> #define MCHI_GROUP_ID 0xA
>
> +#define MKHI_GROUP_ID_GFX 0x30
> +#define MKHI_GFX_RESET_WARN_CMD_REQ 0x0
> +#define MKHI_GFX_MEMORY_READY_CMD_REQ 0x1
> +
> +/* Allow transition to PXP mode without approval */
> +#define MKHI_GFX_MEM_READY_PXP_ALLOWED 0x1
> +
> struct mkhi_rule_id {
> __le16 rule_type;
> u8 feature_id;
> @@ -42,4 +49,9 @@ struct mkhi_msg {
> u8 data[];
> } __packed;
>
> +struct mkhi_gfx_mem_ready {
> + struct mkhi_msg_hdr hdr;
> + u32 flags;
> +} __packed;
> +
> #endif /* _MEI_MKHI_H_ */
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 21:02 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 21:02 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Alexander Usyskin, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> 1. Retrieve extended operational memory physical pointers from the
> auxiliary device info.
> 2. Setup memory registers.
> 3. Notify firmware that the memory is ready by sending the memory
> ready command.
> 4. Disable PXP device if GSC is not in PXP mode.
>
> V7:
> 1. Add kdoc to mei_aux
> 2. rename pxp_isready() to pxp_is_ready()
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++-
> drivers/misc/mei/gsc-me.c | 16 ++++++++
> drivers/misc/mei/hw-me-regs.h | 7 ++++
> drivers/misc/mei/hw-me.c | 28 +++++++++++++-
> drivers/misc/mei/mei_dev.h | 10 +++++
> include/linux/mei_aux.h | 3 ++
> 6 files changed, 131 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
> index 811c94ebf250..b350cc8d500c 100644
> --- a/drivers/misc/mei/bus-fixup.c
> +++ b/drivers/misc/mei/bus-fixup.c
> @@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
> return ret;
> }
>
> +static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
> +{
> + struct mkhi_gfx_mem_ready req = {0};
> + unsigned int mode = MEI_CL_IO_TX_INTERNAL;
> +
> + req.hdr.group_id = MKHI_GROUP_ID_GFX;
> + req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
> + req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
> +
> + dev_dbg(&cldev->dev, "Sending memory ready command\n");
> + return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode);
> +}
> +
> static void mei_mkhi_fix(struct mei_cl_device *cldev)
> {
> int ret;
> @@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
> dev_err(&cldev->dev, "FW version command failed %d\n", ret);
> mei_cldev_disable(cldev);
> }
> +
> +static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
> +{
> + int ret;
> +
> + /* No need to enable the client if nothing is needed from it */
> + if (!cldev->bus->fw_f_fw_ver_supported &&
> + cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
> + return;
> +
> + ret = mei_cldev_enable(cldev);
> + if (ret)
> + return;
> +
> + if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
> + ret = mei_gfx_memory_ready(cldev);
> + if (ret < 0)
> + dev_err(&cldev->dev, "memory ready command failed %d\n", ret);
> + else
> + dev_dbg(&cldev->dev, "memory ready command sent\n");
> + /* we go to reset after that */
> + cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
> + goto out;
> + }
> +
> + ret = mei_fwver(cldev);
> + if (ret < 0)
> + dev_err(&cldev->dev, "FW version command failed %d\n",
> + ret);
> +out:
> + mei_cldev_disable(cldev);
> +}
> +
> /**
> * mei_wd - wd client on the bus, change protocol version
> * as the API has changed.
> @@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev)
> cldev->do_match = 1;
> }
>
> +/**
> + * pxp_is_ready - enable bus client if pxp is ready
> + *
> + * @cldev: me clients device
> + */
> +static void pxp_is_ready(struct mei_cl_device *cldev)
> +{
> + struct mei_device *bus = cldev->bus;
> +
> + switch (bus->pxp_mode) {
> + case MEI_DEV_PXP_READY:
> + case MEI_DEV_PXP_DEFAULT:
> + cldev->do_match = 1;
Can you explain why you set do_match = 1 with MEI_DEV_PXP_DEFAULT ?
AFAIU MEI_DEV_PXP_DEFAULT means that we haven't even started to
initialize PXP, so it seems weird to match in that scenario.
Apart from this, the patch LGTM.
Daniele
> + break;
> + default:
> + cldev->do_match = 0;
> + break;
> + }
> +}
> +
> #define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
>
> static struct mei_fixup {
> @@ -486,10 +552,10 @@ static struct mei_fixup {
> MEI_FIXUP(MEI_UUID_WD, mei_wd),
> MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
> MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
> - MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
> + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
> MEI_FIXUP(MEI_UUID_HDCP, whitelist),
> MEI_FIXUP(MEI_UUID_ANY, vt_support),
> - MEI_FIXUP(MEI_UUID_PAVP, whitelist),
> + MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready),
> };
>
> /**
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index bfa6154b93e2..6b22726aed55 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
> return 0;
> }
>
> +static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)
> +{
> + u32 low = lower_32_bits(mem->start);
> + u32 hi = upper_32_bits(mem->start);
> + u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
> +
> + iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
> + iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
> + iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
> +}
> +
> static int mei_gsc_probe(struct auxiliary_device *aux_dev,
> const struct auxiliary_device_id *aux_dev_id)
> {
> @@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
>
> dev_set_drvdata(device, dev);
>
> + if (adev->ext_op_mem.start) {
> + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
> + dev->pxp_mode = MEI_DEV_PXP_INIT;
> + }
> +
> /* use polling */
> if (mei_me_hw_use_polling(hw)) {
> mei_disable_interrupts(dev);
> diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
> index 15e8e2b322b1..8049f288f74c 100644
> --- a/drivers/misc/mei/hw-me-regs.h
> +++ b/drivers/misc/mei/hw-me-regs.h
> @@ -127,6 +127,8 @@
> # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
> #define PCI_CFG_HFS_4 0x64
> #define PCI_CFG_HFS_5 0x68
> +# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
> +# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
> #define PCI_CFG_HFS_6 0x6C
>
> /* MEI registers */
> @@ -143,6 +145,11 @@
> /* H_D0I3C - D0I3 Control */
> #define H_D0I3C 0x800
>
> +#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
> +#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
> +#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
> +#define GSC_EXT_OP_MEM_VALID BIT(31)
> +
> /* register bits of H_CSR (Host Control Status register) */
> /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
> #define H_CBD 0xFF000000
> diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
> index 6a8e8f3cea7e..c86d6018bc20 100644
> --- a/drivers/misc/mei/hw-me.c
> +++ b/drivers/misc/mei/hw-me.c
> @@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *dev)
> return (mecsr & ME_RST_HRA) == ME_RST_HRA;
> }
>
> +/**
> + * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
> + *
> + * @dev: the device structure
> + */
> +static void mei_gsc_pxp_check(struct mei_device *dev)
> +{
> + struct mei_me_hw *hw = to_me_hw(dev);
> + u32 fwsts5 = 0;
> +
> + if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
> + return;
> +
> + hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
> + trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
> + if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
> + dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
> + dev->pxp_mode = MEI_DEV_PXP_READY;
> + } else {
> + dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
> + }
> +}
> +
> /**
> * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
> * or timeout is reached
> @@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
> return -ETIME;
> }
>
> + mei_gsc_pxp_check(dev);
> +
> mei_me_hw_reset_release(dev);
> dev->recvd_hw_ready = false;
> return 0;
> @@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
>
> /* check if ME wants a reset */
> if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
> - dev_warn(dev->dev, "FW not ready: resetting.\n");
> + dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
> + dev->dev_state, dev->pxp_mode);
> if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
> dev->dev_state == MEI_DEV_POWER_DOWN)
> mei_cl_all_disconnect(dev);
> diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
> index 16f59b3a45fc..7c508bca9a00 100644
> --- a/drivers/misc/mei/mei_dev.h
> +++ b/drivers/misc/mei/mei_dev.h
> @@ -62,6 +62,14 @@ enum mei_dev_state {
> MEI_DEV_POWER_UP
> };
>
> +/* MEI PXP mode state */
> +enum mei_dev_pxp_mode {
> + MEI_DEV_PXP_DEFAULT = 0,
> + MEI_DEV_PXP_INIT = 1,
> + MEI_DEV_PXP_SETUP = 2,
> + MEI_DEV_PXP_READY = 3,
> +};
> +
> const char *mei_dev_state_str(int state);
>
> enum mei_file_transaction_states {
> @@ -454,6 +462,7 @@ struct mei_dev_timeouts {
> * @reset_count : number of consecutive resets
> * @dev_state : device state
> * @hbm_state : state of host bus message protocol
> + * @pxp_mode : PXP device mode
> * @init_clients_timer : HBM init handshake timeout
> *
> * @pg_event : power gating event
> @@ -537,6 +546,7 @@ struct mei_device {
> unsigned long reset_count;
> enum mei_dev_state dev_state;
> enum mei_hbm_state hbm_state;
> + enum mei_dev_pxp_mode pxp_mode;
> u16 init_clients_timer;
>
> /*
> diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
> index 4894d8bf4159..506912ad363b 100644
> --- a/include/linux/mei_aux.h
> +++ b/include/linux/mei_aux.h
> @@ -12,6 +12,8 @@
> * @aux_dev: - auxiliary device object
> * @irq: interrupt driving the mei auxiliary device
> * @bar: mmio resource bar reserved to mei auxiliary device
> + * @ext_op_mem: resource for extend operational memory
> + * used in graphics PXP mode.
> * @slow_firmware: The device has slow underlying firmware.
> * Such firmware will require to use larger operation timeouts.
> */
> @@ -19,6 +21,7 @@ struct mei_aux_device {
> struct auxiliary_device aux_dev;
> int irq;
> struct resource bar;
> + struct resource ext_op_mem;
> bool slow_firmware;
> };
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
@ 2022-09-01 21:02 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 21:02 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> 1. Retrieve extended operational memory physical pointers from the
> auxiliary device info.
> 2. Setup memory registers.
> 3. Notify firmware that the memory is ready by sending the memory
> ready command.
> 4. Disable PXP device if GSC is not in PXP mode.
>
> V7:
> 1. Add kdoc to mei_aux
> 2. rename pxp_isready() to pxp_is_ready()
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/misc/mei/bus-fixup.c | 70 ++++++++++++++++++++++++++++++++++-
> drivers/misc/mei/gsc-me.c | 16 ++++++++
> drivers/misc/mei/hw-me-regs.h | 7 ++++
> drivers/misc/mei/hw-me.c | 28 +++++++++++++-
> drivers/misc/mei/mei_dev.h | 10 +++++
> include/linux/mei_aux.h | 3 ++
> 6 files changed, 131 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c
> index 811c94ebf250..b350cc8d500c 100644
> --- a/drivers/misc/mei/bus-fixup.c
> +++ b/drivers/misc/mei/bus-fixup.c
> @@ -188,6 +188,19 @@ static int mei_fwver(struct mei_cl_device *cldev)
> return ret;
> }
>
> +static int mei_gfx_memory_ready(struct mei_cl_device *cldev)
> +{
> + struct mkhi_gfx_mem_ready req = {0};
> + unsigned int mode = MEI_CL_IO_TX_INTERNAL;
> +
> + req.hdr.group_id = MKHI_GROUP_ID_GFX;
> + req.hdr.command = MKHI_GFX_MEMORY_READY_CMD_REQ;
> + req.flags = MKHI_GFX_MEM_READY_PXP_ALLOWED;
> +
> + dev_dbg(&cldev->dev, "Sending memory ready command\n");
> + return __mei_cl_send(cldev->cl, (u8 *)&req, sizeof(req), 0, mode);
> +}
> +
> static void mei_mkhi_fix(struct mei_cl_device *cldev)
> {
> int ret;
> @@ -234,6 +247,39 @@ static void mei_gsc_mkhi_ver(struct mei_cl_device *cldev)
> dev_err(&cldev->dev, "FW version command failed %d\n", ret);
> mei_cldev_disable(cldev);
> }
> +
> +static void mei_gsc_mkhi_fix_ver(struct mei_cl_device *cldev)
> +{
> + int ret;
> +
> + /* No need to enable the client if nothing is needed from it */
> + if (!cldev->bus->fw_f_fw_ver_supported &&
> + cldev->bus->pxp_mode != MEI_DEV_PXP_INIT)
> + return;
> +
> + ret = mei_cldev_enable(cldev);
> + if (ret)
> + return;
> +
> + if (cldev->bus->pxp_mode == MEI_DEV_PXP_INIT) {
> + ret = mei_gfx_memory_ready(cldev);
> + if (ret < 0)
> + dev_err(&cldev->dev, "memory ready command failed %d\n", ret);
> + else
> + dev_dbg(&cldev->dev, "memory ready command sent\n");
> + /* we go to reset after that */
> + cldev->bus->pxp_mode = MEI_DEV_PXP_SETUP;
> + goto out;
> + }
> +
> + ret = mei_fwver(cldev);
> + if (ret < 0)
> + dev_err(&cldev->dev, "FW version command failed %d\n",
> + ret);
> +out:
> + mei_cldev_disable(cldev);
> +}
> +
> /**
> * mei_wd - wd client on the bus, change protocol version
> * as the API has changed.
> @@ -473,6 +519,26 @@ static void vt_support(struct mei_cl_device *cldev)
> cldev->do_match = 1;
> }
>
> +/**
> + * pxp_is_ready - enable bus client if pxp is ready
> + *
> + * @cldev: me clients device
> + */
> +static void pxp_is_ready(struct mei_cl_device *cldev)
> +{
> + struct mei_device *bus = cldev->bus;
> +
> + switch (bus->pxp_mode) {
> + case MEI_DEV_PXP_READY:
> + case MEI_DEV_PXP_DEFAULT:
> + cldev->do_match = 1;
Can you explain why you set do_match = 1 with MEI_DEV_PXP_DEFAULT ?
AFAIU MEI_DEV_PXP_DEFAULT means that we haven't even started to
initialize PXP, so it seems weird to match in that scenario.
Apart from this, the patch LGTM.
Daniele
> + break;
> + default:
> + cldev->do_match = 0;
> + break;
> + }
> +}
> +
> #define MEI_FIXUP(_uuid, _hook) { _uuid, _hook }
>
> static struct mei_fixup {
> @@ -486,10 +552,10 @@ static struct mei_fixup {
> MEI_FIXUP(MEI_UUID_WD, mei_wd),
> MEI_FIXUP(MEI_UUID_MKHIF_FIX, mei_mkhi_fix),
> MEI_FIXUP(MEI_UUID_IGSC_MKHI, mei_gsc_mkhi_ver),
> - MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_ver),
> + MEI_FIXUP(MEI_UUID_IGSC_MKHI_FIX, mei_gsc_mkhi_fix_ver),
> MEI_FIXUP(MEI_UUID_HDCP, whitelist),
> MEI_FIXUP(MEI_UUID_ANY, vt_support),
> - MEI_FIXUP(MEI_UUID_PAVP, whitelist),
> + MEI_FIXUP(MEI_UUID_PAVP, pxp_is_ready),
> };
>
> /**
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index bfa6154b93e2..6b22726aed55 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -32,6 +32,17 @@ static int mei_gsc_read_hfs(const struct mei_device *dev, int where, u32 *val)
> return 0;
> }
>
> +static void mei_gsc_set_ext_op_mem(const struct mei_me_hw *hw, struct resource *mem)
> +{
> + u32 low = lower_32_bits(mem->start);
> + u32 hi = upper_32_bits(mem->start);
> + u32 limit = (resource_size(mem) / SZ_4K) | GSC_EXT_OP_MEM_VALID;
> +
> + iowrite32(low, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG);
> + iowrite32(hi, hw->mem_addr + H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG);
> + iowrite32(limit, hw->mem_addr + H_GSC_EXT_OP_MEM_LIMIT_REG);
> +}
> +
> static int mei_gsc_probe(struct auxiliary_device *aux_dev,
> const struct auxiliary_device_id *aux_dev_id)
> {
> @@ -67,6 +78,11 @@ static int mei_gsc_probe(struct auxiliary_device *aux_dev,
>
> dev_set_drvdata(device, dev);
>
> + if (adev->ext_op_mem.start) {
> + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
> + dev->pxp_mode = MEI_DEV_PXP_INIT;
> + }
> +
> /* use polling */
> if (mei_me_hw_use_polling(hw)) {
> mei_disable_interrupts(dev);
> diff --git a/drivers/misc/mei/hw-me-regs.h b/drivers/misc/mei/hw-me-regs.h
> index 15e8e2b322b1..8049f288f74c 100644
> --- a/drivers/misc/mei/hw-me-regs.h
> +++ b/drivers/misc/mei/hw-me-regs.h
> @@ -127,6 +127,8 @@
> # define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
> #define PCI_CFG_HFS_4 0x64
> #define PCI_CFG_HFS_5 0x68
> +# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
> +# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
> #define PCI_CFG_HFS_6 0x6C
>
> /* MEI registers */
> @@ -143,6 +145,11 @@
> /* H_D0I3C - D0I3 Control */
> #define H_D0I3C 0x800
>
> +#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
> +#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
> +#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
> +#define GSC_EXT_OP_MEM_VALID BIT(31)
> +
> /* register bits of H_CSR (Host Control Status register) */
> /* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
> #define H_CBD 0xFF000000
> diff --git a/drivers/misc/mei/hw-me.c b/drivers/misc/mei/hw-me.c
> index 6a8e8f3cea7e..c86d6018bc20 100644
> --- a/drivers/misc/mei/hw-me.c
> +++ b/drivers/misc/mei/hw-me.c
> @@ -433,6 +433,29 @@ static bool mei_me_hw_is_resetting(struct mei_device *dev)
> return (mecsr & ME_RST_HRA) == ME_RST_HRA;
> }
>
> +/**
> + * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
> + *
> + * @dev: the device structure
> + */
> +static void mei_gsc_pxp_check(struct mei_device *dev)
> +{
> + struct mei_me_hw *hw = to_me_hw(dev);
> + u32 fwsts5 = 0;
> +
> + if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
> + return;
> +
> + hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
> + trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
> + if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
> + dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
> + dev->pxp_mode = MEI_DEV_PXP_READY;
> + } else {
> + dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
> + }
> +}
> +
> /**
> * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
> * or timeout is reached
> @@ -452,6 +475,8 @@ static int mei_me_hw_ready_wait(struct mei_device *dev)
> return -ETIME;
> }
>
> + mei_gsc_pxp_check(dev);
> +
> mei_me_hw_reset_release(dev);
> dev->recvd_hw_ready = false;
> return 0;
> @@ -1270,7 +1295,8 @@ irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
>
> /* check if ME wants a reset */
> if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
> - dev_warn(dev->dev, "FW not ready: resetting.\n");
> + dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
> + dev->dev_state, dev->pxp_mode);
> if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
> dev->dev_state == MEI_DEV_POWER_DOWN)
> mei_cl_all_disconnect(dev);
> diff --git a/drivers/misc/mei/mei_dev.h b/drivers/misc/mei/mei_dev.h
> index 16f59b3a45fc..7c508bca9a00 100644
> --- a/drivers/misc/mei/mei_dev.h
> +++ b/drivers/misc/mei/mei_dev.h
> @@ -62,6 +62,14 @@ enum mei_dev_state {
> MEI_DEV_POWER_UP
> };
>
> +/* MEI PXP mode state */
> +enum mei_dev_pxp_mode {
> + MEI_DEV_PXP_DEFAULT = 0,
> + MEI_DEV_PXP_INIT = 1,
> + MEI_DEV_PXP_SETUP = 2,
> + MEI_DEV_PXP_READY = 3,
> +};
> +
> const char *mei_dev_state_str(int state);
>
> enum mei_file_transaction_states {
> @@ -454,6 +462,7 @@ struct mei_dev_timeouts {
> * @reset_count : number of consecutive resets
> * @dev_state : device state
> * @hbm_state : state of host bus message protocol
> + * @pxp_mode : PXP device mode
> * @init_clients_timer : HBM init handshake timeout
> *
> * @pg_event : power gating event
> @@ -537,6 +546,7 @@ struct mei_device {
> unsigned long reset_count;
> enum mei_dev_state dev_state;
> enum mei_hbm_state hbm_state;
> + enum mei_dev_pxp_mode pxp_mode;
> u16 init_clients_timer;
>
> /*
> diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h
> index 4894d8bf4159..506912ad363b 100644
> --- a/include/linux/mei_aux.h
> +++ b/include/linux/mei_aux.h
> @@ -12,6 +12,8 @@
> * @aux_dev: - auxiliary device object
> * @irq: interrupt driving the mei auxiliary device
> * @bar: mmio resource bar reserved to mei auxiliary device
> + * @ext_op_mem: resource for extend operational memory
> + * used in graphics PXP mode.
> * @slow_firmware: The device has slow underlying firmware.
> * Such firmware will require to use larger operation timeouts.
> */
> @@ -19,6 +21,7 @@ struct mei_aux_device {
> struct auxiliary_device aux_dev;
> int irq;
> struct resource bar;
> + struct resource ext_op_mem;
> bool slow_firmware;
> };
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 12/15] mei: gsc: add transition to PXP mode in resume flow
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 21:19 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 21:19 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Alexander Usyskin, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Added transition to PXP mode in resume flow.
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/gsc-me.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index 6b22726aed55..75765e4df4ed 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
> static int __maybe_unused mei_gsc_pm_resume(struct device *device)
> {
> struct mei_device *dev = dev_get_drvdata(device);
> + struct auxiliary_device *aux_dev;
> + struct mei_aux_device *adev;
> int err;
> + struct mei_me_hw *hw;
>
> if (!dev)
> return -ENODEV;
>
> + hw = to_me_hw(dev);
> + aux_dev = to_auxiliary_dev(device);
> + adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
> + if (adev->ext_op_mem.start) {
> + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
> + dev->pxp_mode = MEI_DEV_PXP_INIT;
> + }
> +
> err = mei_restart(dev);
> if (err)
> return err;
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 12/15] mei: gsc: add transition to PXP mode in resume flow
@ 2022-09-01 21:19 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 21:19 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Added transition to PXP mode in resume flow.
>
> CC: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/gsc-me.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/misc/mei/gsc-me.c b/drivers/misc/mei/gsc-me.c
> index 6b22726aed55..75765e4df4ed 100644
> --- a/drivers/misc/mei/gsc-me.c
> +++ b/drivers/misc/mei/gsc-me.c
> @@ -182,11 +182,22 @@ static int __maybe_unused mei_gsc_pm_suspend(struct device *device)
> static int __maybe_unused mei_gsc_pm_resume(struct device *device)
> {
> struct mei_device *dev = dev_get_drvdata(device);
> + struct auxiliary_device *aux_dev;
> + struct mei_aux_device *adev;
> int err;
> + struct mei_me_hw *hw;
>
> if (!dev)
> return -ENODEV;
>
> + hw = to_me_hw(dev);
> + aux_dev = to_auxiliary_dev(device);
> + adev = auxiliary_dev_to_mei_aux_dev(aux_dev);
> + if (adev->ext_op_mem.start) {
> + mei_gsc_set_ext_op_mem(hw, &adev->ext_op_mem);
> + dev->pxp_mode = MEI_DEV_PXP_INIT;
> + }
> +
> err = mei_restart(dev);
> if (err)
> return err;
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 13/15] mei: debugfs: add pxp mode to devstate in debugfs
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-01 21:20 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 21:20 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi, Vitaly Lubart
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> Add pxp mode devstate to debugfs to monitor pxp state machine progress.
> This is useful to debug issues in scenarios in which the pxp state
> needs to be re-initialized, like during power transitions such as
> suspend/resume. With this debugfs the state could be monitored
> to ensure that pxp is in the ready state.
>
> CC: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/debugfs.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
> index 1ce61e9e24fc..4074fec866a6 100644
> --- a/drivers/misc/mei/debugfs.c
> +++ b/drivers/misc/mei/debugfs.c
> @@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)
> }
> DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
>
> +static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
> +{
> +#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
> + switch (state) {
> + MEI_PXP_MODE(DEFAULT);
> + MEI_PXP_MODE(INIT);
> + MEI_PXP_MODE(SETUP);
> + MEI_PXP_MODE(READY);
> + default:
> + return "unknown";
> + }
> +#undef MEI_PXP_MODE
> +}
> +
> static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
> {
> struct mei_device *dev = m->private;
> @@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
> seq_printf(m, "pg: %s, %s\n",
> mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
> mei_pg_state_str(mei_pg_state(dev)));
> +
> + seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
> +
> return 0;
> }
> DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 13/15] mei: debugfs: add pxp mode to devstate in debugfs
@ 2022-09-01 21:20 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-01 21:20 UTC (permalink / raw)
To: Tomas Winkler, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Vitaly Lubart, intel-gfx, Alexander Usyskin, linux-kernel, Rodrigo Vivi
On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> Add pxp mode devstate to debugfs to monitor pxp state machine progress.
> This is useful to debug issues in scenarios in which the pxp state
> needs to be re-initialized, like during power transitions such as
> suspend/resume. With this debugfs the state could be monitored
> to ensure that pxp is in the ready state.
>
> CC: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/misc/mei/debugfs.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/misc/mei/debugfs.c b/drivers/misc/mei/debugfs.c
> index 1ce61e9e24fc..4074fec866a6 100644
> --- a/drivers/misc/mei/debugfs.c
> +++ b/drivers/misc/mei/debugfs.c
> @@ -86,6 +86,20 @@ static int mei_dbgfs_active_show(struct seq_file *m, void *unused)
> }
> DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_active);
>
> +static const char *mei_dev_pxp_mode_str(enum mei_dev_pxp_mode state)
> +{
> +#define MEI_PXP_MODE(state) case MEI_DEV_PXP_##state: return #state
> + switch (state) {
> + MEI_PXP_MODE(DEFAULT);
> + MEI_PXP_MODE(INIT);
> + MEI_PXP_MODE(SETUP);
> + MEI_PXP_MODE(READY);
> + default:
> + return "unknown";
> + }
> +#undef MEI_PXP_MODE
> +}
> +
> static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
> {
> struct mei_device *dev = m->private;
> @@ -112,6 +126,9 @@ static int mei_dbgfs_devstate_show(struct seq_file *m, void *unused)
> seq_printf(m, "pg: %s, %s\n",
> mei_pg_is_enabled(dev) ? "ENABLED" : "DISABLED",
> mei_pg_state_str(mei_pg_state(dev)));
> +
> + seq_printf(m, "pxp: %s\n", mei_dev_pxp_mode_str(dev->pxp_mode));
> +
> return 0;
> }
> DEFINE_SHOW_ATTRIBUTE(mei_dbgfs_devstate);
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
@ 2022-09-02 8:25 ` Matthew Auld
-1 siblings, 0 replies; 80+ messages in thread
From: Matthew Auld @ 2022-09-02 8:25 UTC (permalink / raw)
To: Tomas Winkler
Cc: Greg Kroah-Hartman, David Airlie, Daniel Vetter, Alan Previn,
Intel Graphics Development, Alexander Usyskin, kernel list,
Rodrigo Vivi, Vitaly Lubart
On Sat, 6 Aug 2022 at 13:34, Tomas Winkler <tomas.winkler@intel.com> wrote:
>
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
> 2 files changed, 87 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index e1040c8f2fd3..162bea57fbb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -7,6 +7,7 @@
> #include <linux/mei_aux.h>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "gem/i915_gem_region.h"
> #include "gt/intel_gsc.h"
> #include "gt/intel_gt.h"
>
> @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
> return irq_set_chip_data(irq, NULL);
> }
>
> +static int
> +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
> +{
> + struct intel_gt *gt = gsc_to_gt(gsc);
> + struct drm_i915_gem_object *obj;
> + void *vaddr;
> + int err;
> +
> + obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
> + if (IS_ERR(obj)) {
> + drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
> + return PTR_ERR(obj);
> + }
> +
> + err = i915_gem_object_pin_pages_unlocked(obj);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
> + goto out_put;
> + }
> +
> + vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
> + if (IS_ERR(vaddr)) {
> + err = PTR_ERR(vaddr);
> + drm_err(>->i915->drm, "Failed to map gsc memory\n");
> + goto out_unpin;
> + }
> +
> + memset(vaddr, 0, obj->base.size);
> +
> + i915_gem_object_unpin_map(obj);
I think this was mentioned before, here we should rather use:
create_lmem(gt->i915, size,
I915_BO_ALLOC_CONTIGUOUS |
I915_BO_ALLOC_CPU_CLEAR);
That way we don't need to manually map and clear it here. Instead when
first allocating the pages (like with pin_pages), the clear will be
done for you.
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM
@ 2022-09-02 8:25 ` Matthew Auld
0 siblings, 0 replies; 80+ messages in thread
From: Matthew Auld @ 2022-09-02 8:25 UTC (permalink / raw)
To: Tomas Winkler
Cc: Alan Previn, David Airlie, Greg Kroah-Hartman,
Intel Graphics Development, Alexander Usyskin, kernel list,
Daniel Vetter, Rodrigo Vivi, Vitaly Lubart
On Sat, 6 Aug 2022 at 13:34, Tomas Winkler <tomas.winkler@intel.com> wrote:
>
> GSC requires more operational memory than available on chip.
> Reserve 4M of LMEM for GSC operation. The memory is provided to the
> GSC as struct resource to the auxiliary data of the child device.
>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gsc.c | 91 ++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gsc.h | 3 +
> 2 files changed, 87 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gsc.c b/drivers/gpu/drm/i915/gt/intel_gsc.c
> index e1040c8f2fd3..162bea57fbb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gsc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gsc.c
> @@ -7,6 +7,7 @@
> #include <linux/mei_aux.h>
> #include "i915_drv.h"
> #include "i915_reg.h"
> +#include "gem/i915_gem_region.h"
> #include "gt/intel_gsc.h"
> #include "gt/intel_gt.h"
>
> @@ -36,12 +37,68 @@ static int gsc_irq_init(int irq)
> return irq_set_chip_data(irq, NULL);
> }
>
> +static int
> +gsc_ext_om_alloc(struct intel_gsc *gsc, struct intel_gsc_intf *intf, size_t size)
> +{
> + struct intel_gt *gt = gsc_to_gt(gsc);
> + struct drm_i915_gem_object *obj;
> + void *vaddr;
> + int err;
> +
> + obj = i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
> + if (IS_ERR(obj)) {
> + drm_err(>->i915->drm, "Failed to allocate gsc memory\n");
> + return PTR_ERR(obj);
> + }
> +
> + err = i915_gem_object_pin_pages_unlocked(obj);
> + if (err) {
> + drm_err(>->i915->drm, "Failed to pin pages for gsc memory\n");
> + goto out_put;
> + }
> +
> + vaddr = i915_gem_object_pin_map_unlocked(obj, i915_coherent_map_type(gt->i915, obj, true));
> + if (IS_ERR(vaddr)) {
> + err = PTR_ERR(vaddr);
> + drm_err(>->i915->drm, "Failed to map gsc memory\n");
> + goto out_unpin;
> + }
> +
> + memset(vaddr, 0, obj->base.size);
> +
> + i915_gem_object_unpin_map(obj);
I think this was mentioned before, here we should rather use:
create_lmem(gt->i915, size,
I915_BO_ALLOC_CONTIGUOUS |
I915_BO_ALLOC_CPU_CLEAR);
That way we don't need to manually map and clear it here. Instead when
first allocating the pages (like with pin_pages), the clear will be
done for you.
^ permalink raw reply [flat|nested] 80+ messages in thread
* RE: [Intel-gfx] [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header
2022-09-01 20:54 ` Ceraolo Spurio, Daniele
@ 2022-09-03 10:05 ` Winkler, Tomas
-1 siblings, 0 replies; 80+ messages in thread
From: Winkler, Tomas @ 2022-09-03 10:05 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: intel-gfx, Usyskin, Alexander, linux-kernel, Vivi, Rodrigo,
Lubart, Vitaly
>
>
> On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> > From: Vitaly Lubart <vitaly.lubart@intel.com>
> >
> > Exported common mkhi definitions from bus-fixup.c into a separate
> > header file mkhi.h for other driver usage.
> >
> > Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > ---
> > drivers/misc/mei/bus-fixup.c | 31 +------------------------
> > drivers/misc/mei/mkhi.h | 45
> ++++++++++++++++++++++++++++++++++++
> > 2 files changed, 46 insertions(+), 30 deletions(-)
> > create mode 100644 drivers/misc/mei/mkhi.h
> >
> > diff --git a/drivers/misc/mei/bus-fixup.c
> > b/drivers/misc/mei/bus-fixup.c index 24e91a9ea558..811c94ebf250 100644
> > --- a/drivers/misc/mei/bus-fixup.c
> > +++ b/drivers/misc/mei/bus-fixup.c
> > @@ -15,6 +15,7 @@
> >
> > #include "mei_dev.h"
> > #include "client.h"
> > +#include "mkhi.h"
> >
> > #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
> > 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06) @@ -
> 89,20 +90,6
> > @@ struct mei_os_ver {
> > u8 reserved2;
> > } __packed;
> >
> > -#define MKHI_FEATURE_PTT 0x10
> > -
> > -struct mkhi_rule_id {
> > - __le16 rule_type;
> > - u8 feature_id;
> > - u8 reserved;
> > -} __packed;
> > -
> > -struct mkhi_fwcaps {
> > - struct mkhi_rule_id id;
> > - u8 len;
> > - u8 data[];
> > -} __packed;
> > -
> > struct mkhi_fw_ver_block {
> > u16 minor;
> > u8 major;
> > @@ -115,22 +102,6 @@ struct mkhi_fw_ver {
> > struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
> > } __packed;
> >
> > -#define MKHI_FWCAPS_GROUP_ID 0x3
> > -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 -#define
> > MKHI_GEN_GROUP_ID 0xFF -#define
> MKHI_GEN_GET_FW_VERSION_CMD 0x2
> > -struct mkhi_msg_hdr {
> > - u8 group_id;
> > - u8 command;
> > - u8 reserved;
> > - u8 result;
> > -} __packed;
> > -
> > -struct mkhi_msg {
> > - struct mkhi_msg_hdr hdr;
> > - u8 data[];
> > -} __packed;
> > -
> > #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
> > sizeof(struct mkhi_fwcaps) + \
> > sizeof(struct mei_os_ver))
> > diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h new
> > file mode 100644 index 000000000000..27a9b476904e
> > --- /dev/null
> > +++ b/drivers/misc/mei/mkhi.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
>
> 2022 (can fix when merging)
>
> > + * Intel Management Engine Interface (Intel MEI) Linux driver */
> > +
> > +#ifndef _MEI_MKHI_H_
> > +#define _MEI_MKHI_H_
> > +
> > +#include "mei_dev.h"
>
> Any reason you need the full mei_dev.h and not just linux/types.h ?
<linux/types.h> is enough
>
> > +
> > +#define MKHI_FEATURE_PTT 0x10
> > +
> > +#define MKHI_FWCAPS_GROUP_ID 0x3
> > +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 #define
> > +MKHI_GEN_GROUP_ID 0xFF #define
> MKHI_GEN_GET_FW_VERSION_CMD 0x2
> > +
> > +#define MCHI_GROUP_ID 0xA
>
> This is new and doesn't seem to be used in follow-up patches. Any reason for
> adding it in?
Will drop.
>
> Daniele
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header
@ 2022-09-03 10:05 ` Winkler, Tomas
0 siblings, 0 replies; 80+ messages in thread
From: Winkler, Tomas @ 2022-09-03 10:05 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Greg Kroah-Hartman, David Airlie, Daniel Vetter
Cc: Lubart, Vitaly, intel-gfx, Usyskin, Alexander, linux-kernel,
Vivi, Rodrigo
>
>
> On 8/6/2022 5:26 AM, Tomas Winkler wrote:
> > From: Vitaly Lubart <vitaly.lubart@intel.com>
> >
> > Exported common mkhi definitions from bus-fixup.c into a separate
> > header file mkhi.h for other driver usage.
> >
> > Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> > Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> > Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> > ---
> > drivers/misc/mei/bus-fixup.c | 31 +------------------------
> > drivers/misc/mei/mkhi.h | 45
> ++++++++++++++++++++++++++++++++++++
> > 2 files changed, 46 insertions(+), 30 deletions(-)
> > create mode 100644 drivers/misc/mei/mkhi.h
> >
> > diff --git a/drivers/misc/mei/bus-fixup.c
> > b/drivers/misc/mei/bus-fixup.c index 24e91a9ea558..811c94ebf250 100644
> > --- a/drivers/misc/mei/bus-fixup.c
> > +++ b/drivers/misc/mei/bus-fixup.c
> > @@ -15,6 +15,7 @@
> >
> > #include "mei_dev.h"
> > #include "client.h"
> > +#include "mkhi.h"
> >
> > #define MEI_UUID_NFC_INFO UUID_LE(0xd2de1625, 0x382d, 0x417d, \
> > 0x48, 0xa4, 0xef, 0xab, 0xba, 0x8a, 0x12, 0x06) @@ -
> 89,20 +90,6
> > @@ struct mei_os_ver {
> > u8 reserved2;
> > } __packed;
> >
> > -#define MKHI_FEATURE_PTT 0x10
> > -
> > -struct mkhi_rule_id {
> > - __le16 rule_type;
> > - u8 feature_id;
> > - u8 reserved;
> > -} __packed;
> > -
> > -struct mkhi_fwcaps {
> > - struct mkhi_rule_id id;
> > - u8 len;
> > - u8 data[];
> > -} __packed;
> > -
> > struct mkhi_fw_ver_block {
> > u16 minor;
> > u8 major;
> > @@ -115,22 +102,6 @@ struct mkhi_fw_ver {
> > struct mkhi_fw_ver_block ver[MEI_MAX_FW_VER_BLOCKS];
> > } __packed;
> >
> > -#define MKHI_FWCAPS_GROUP_ID 0x3
> > -#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 -#define
> > MKHI_GEN_GROUP_ID 0xFF -#define
> MKHI_GEN_GET_FW_VERSION_CMD 0x2
> > -struct mkhi_msg_hdr {
> > - u8 group_id;
> > - u8 command;
> > - u8 reserved;
> > - u8 result;
> > -} __packed;
> > -
> > -struct mkhi_msg {
> > - struct mkhi_msg_hdr hdr;
> > - u8 data[];
> > -} __packed;
> > -
> > #define MKHI_OSVER_BUF_LEN (sizeof(struct mkhi_msg_hdr) + \
> > sizeof(struct mkhi_fwcaps) + \
> > sizeof(struct mei_os_ver))
> > diff --git a/drivers/misc/mei/mkhi.h b/drivers/misc/mei/mkhi.h new
> > file mode 100644 index 000000000000..27a9b476904e
> > --- /dev/null
> > +++ b/drivers/misc/mei/mkhi.h
> > @@ -0,0 +1,45 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
>
> 2022 (can fix when merging)
>
> > + * Intel Management Engine Interface (Intel MEI) Linux driver */
> > +
> > +#ifndef _MEI_MKHI_H_
> > +#define _MEI_MKHI_H_
> > +
> > +#include "mei_dev.h"
>
> Any reason you need the full mei_dev.h and not just linux/types.h ?
<linux/types.h> is enough
>
> > +
> > +#define MKHI_FEATURE_PTT 0x10
> > +
> > +#define MKHI_FWCAPS_GROUP_ID 0x3
> > +#define MKHI_FWCAPS_SET_OS_VER_APP_RULE_CMD 6 #define
> > +MKHI_GEN_GROUP_ID 0xFF #define
> MKHI_GEN_GET_FW_VERSION_CMD 0x2
> > +
> > +#define MCHI_GROUP_ID 0xA
>
> This is new and doesn't seem to be used in follow-up patches. Any reason for
> adding it in?
Will drop.
>
> Daniele
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* RE: [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
2022-09-01 21:02 ` [Intel-gfx] " Ceraolo Spurio, Daniele
@ 2022-09-04 7:29 ` Usyskin, Alexander
-1 siblings, 0 replies; 80+ messages in thread
From: Usyskin, Alexander @ 2022-09-04 7:29 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Winkler, Tomas, Greg Kroah-Hartman,
David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo, Tvrtko Ursulin,
intel-gfx, linux-kernel, Lubart, Vitaly
> > +static void pxp_is_ready(struct mei_cl_device *cldev)
> > +{
> > + struct mei_device *bus = cldev->bus;
> > +
> > + switch (bus->pxp_mode) {
> > + case MEI_DEV_PXP_READY:
> > + case MEI_DEV_PXP_DEFAULT:
> > + cldev->do_match = 1;
>
> Can you explain why you set do_match = 1 with MEI_DEV_PXP_DEFAULT ?
> AFAIU MEI_DEV_PXP_DEFAULT means that we haven't even started to
> initialize PXP, so it seems weird to match in that scenario.
>
> Apart from this, the patch LGTM.
>
> Daniele
MEI_DEV_PXP_DEFAULT is a state for the legacy PXP solution that uses the same firmware client
and have no need in special initialization.
--
Thanks,
Sasha
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
@ 2022-09-04 7:29 ` Usyskin, Alexander
0 siblings, 0 replies; 80+ messages in thread
From: Usyskin, Alexander @ 2022-09-04 7:29 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Winkler, Tomas, Greg Kroah-Hartman,
David Airlie, Daniel Vetter
Cc: intel-gfx, linux-kernel, Vivi, Rodrigo, Lubart, Vitaly
> > +static void pxp_is_ready(struct mei_cl_device *cldev)
> > +{
> > + struct mei_device *bus = cldev->bus;
> > +
> > + switch (bus->pxp_mode) {
> > + case MEI_DEV_PXP_READY:
> > + case MEI_DEV_PXP_DEFAULT:
> > + cldev->do_match = 1;
>
> Can you explain why you set do_match = 1 with MEI_DEV_PXP_DEFAULT ?
> AFAIU MEI_DEV_PXP_DEFAULT means that we haven't even started to
> initialize PXP, so it seems weird to match in that scenario.
>
> Apart from this, the patch LGTM.
>
> Daniele
MEI_DEV_PXP_DEFAULT is a state for the legacy PXP solution that uses the same firmware client
and have no need in special initialization.
--
Thanks,
Sasha
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
2022-09-04 7:29 ` [Intel-gfx] " Usyskin, Alexander
@ 2022-09-04 22:26 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-04 22:26 UTC (permalink / raw)
To: Usyskin, Alexander, Winkler, Tomas, Greg Kroah-Hartman,
David Airlie, Daniel Vetter
Cc: Jani Nikula, Joonas Lahtinen, Vivi, Rodrigo, Tvrtko Ursulin,
intel-gfx, linux-kernel, Lubart, Vitaly
On 9/4/2022 12:29 AM, Usyskin, Alexander wrote:
>>> +static void pxp_is_ready(struct mei_cl_device *cldev)
>>> +{
>>> + struct mei_device *bus = cldev->bus;
>>> +
>>> + switch (bus->pxp_mode) {
>>> + case MEI_DEV_PXP_READY:
>>> + case MEI_DEV_PXP_DEFAULT:
>>> + cldev->do_match = 1;
>> Can you explain why you set do_match = 1 with MEI_DEV_PXP_DEFAULT ?
>> AFAIU MEI_DEV_PXP_DEFAULT means that we haven't even started to
>> initialize PXP, so it seems weird to match in that scenario.
>>
>> Apart from this, the patch LGTM.
>>
>> Daniele
> MEI_DEV_PXP_DEFAULT is a state for the legacy PXP solution that uses the same firmware client
> and have no need in special initialization.
makes sense. Could use a comment, but anyway:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory
@ 2022-09-04 22:26 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-04 22:26 UTC (permalink / raw)
To: Usyskin, Alexander, Winkler, Tomas, Greg Kroah-Hartman,
David Airlie, Daniel Vetter
Cc: intel-gfx, linux-kernel, Vivi, Rodrigo, Lubart, Vitaly
On 9/4/2022 12:29 AM, Usyskin, Alexander wrote:
>>> +static void pxp_is_ready(struct mei_cl_device *cldev)
>>> +{
>>> + struct mei_device *bus = cldev->bus;
>>> +
>>> + switch (bus->pxp_mode) {
>>> + case MEI_DEV_PXP_READY:
>>> + case MEI_DEV_PXP_DEFAULT:
>>> + cldev->do_match = 1;
>> Can you explain why you set do_match = 1 with MEI_DEV_PXP_DEFAULT ?
>> AFAIU MEI_DEV_PXP_DEFAULT means that we haven't even started to
>> initialize PXP, so it seems weird to match in that scenario.
>>
>> Apart from this, the patch LGTM.
>>
>> Daniele
> MEI_DEV_PXP_DEFAULT is a state for the legacy PXP solution that uses the same firmware client
> and have no need in special initialization.
makes sense. Could use a comment, but anyway:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 00/15] GSC support for XeHP SDV and DG2
2022-09-01 15:09 ` [Intel-gfx] " Greg Kroah-Hartman
@ 2022-09-09 10:24 ` Joonas Lahtinen
-1 siblings, 0 replies; 80+ messages in thread
From: Joonas Lahtinen @ 2022-09-09 10:24 UTC (permalink / raw)
To: Greg Kroah-Hartman, Tomas Winkler, Daniele Ceraolo Spurio, David Airlie
Cc: Daniel Vetter, Jani Nikula, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Alexander Usyskin, Vitaly Lubart
Dave, do you have a preference how to deal with the mishap here, shall I do a
force-push to drm-intel-gt-next to correctly record the Acked-by or revert and
re-push? Or just leave it as is?
Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
> On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> > Add GSC support for XeHP SDV and DG2 platforms.
> >
> > The series includes changes for the mei driver:
> > - add ability to use polling instead of interrupts
> > - add ability to use extended timeouts
> > - setup extended operational memory for GSC
> >
> > The series includes changes for the i915 driver:
> > - allocate extended operational memory for GSC
> > - GSC on XeHP SDV offsets and definitions
> >
> > This patch set should be merged via gfx tree as
> > the auxiliary device belongs there.
> > Greg, your ACK is required for the drives/misc/mei code base,
> > please review the patches.
>
> With the exception that you all don't know what year it is:
>
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Daniele, why were the patches applied without this A-b?
I'm just preparing the drm-intel-gt-next pull request and now it appears
like we're pushing a lot of commits outside of drm without any Acks.
Please reach out to the maintainers *before* pushing code for other
subsystems. Unless you get an explicit ack to do so, do not push such
code.
Quoting from the committer guidelines[1] the first rule is:
"Only push patches changing drivers/gpu/drm/i915."
In those cases, please ping a maintainer and don't rush things.
Regards, Joonas
[1] https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-intel.html#high-level-guidelines
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-09-09 10:24 ` Joonas Lahtinen
0 siblings, 0 replies; 80+ messages in thread
From: Joonas Lahtinen @ 2022-09-09 10:24 UTC (permalink / raw)
To: Greg Kroah-Hartman, Tomas Winkler, Daniele Ceraolo Spurio, David Airlie
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Daniel Vetter,
Rodrigo Vivi, Vitaly Lubart
Dave, do you have a preference how to deal with the mishap here, shall I do a
force-push to drm-intel-gt-next to correctly record the Acked-by or revert and
re-push? Or just leave it as is?
Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
> On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> > Add GSC support for XeHP SDV and DG2 platforms.
> >
> > The series includes changes for the mei driver:
> > - add ability to use polling instead of interrupts
> > - add ability to use extended timeouts
> > - setup extended operational memory for GSC
> >
> > The series includes changes for the i915 driver:
> > - allocate extended operational memory for GSC
> > - GSC on XeHP SDV offsets and definitions
> >
> > This patch set should be merged via gfx tree as
> > the auxiliary device belongs there.
> > Greg, your ACK is required for the drives/misc/mei code base,
> > please review the patches.
>
> With the exception that you all don't know what year it is:
>
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Daniele, why were the patches applied without this A-b?
I'm just preparing the drm-intel-gt-next pull request and now it appears
like we're pushing a lot of commits outside of drm without any Acks.
Please reach out to the maintainers *before* pushing code for other
subsystems. Unless you get an explicit ack to do so, do not push such
code.
Quoting from the committer guidelines[1] the first rule is:
"Only push patches changing drivers/gpu/drm/i915."
In those cases, please ping a maintainer and don't rush things.
Regards, Joonas
[1] https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-intel.html#high-level-guidelines
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 00/15] GSC support for XeHP SDV and DG2
2022-09-09 10:24 ` [Intel-gfx] " Joonas Lahtinen
@ 2022-09-09 15:17 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-09 15:17 UTC (permalink / raw)
To: Joonas Lahtinen, Greg Kroah-Hartman, Tomas Winkler, David Airlie
Cc: Daniel Vetter, Jani Nikula, Rodrigo Vivi, Tvrtko Ursulin,
intel-gfx, linux-kernel, Alexander Usyskin, Vitaly Lubart
On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
> Dave, do you have a preference how to deal with the mishap here, shall I do a
> force-push to drm-intel-gt-next to correctly record the Acked-by or revert and
> re-push? Or just leave it as is?
>
> Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
>> On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
>>> Add GSC support for XeHP SDV and DG2 platforms.
>>>
>>> The series includes changes for the mei driver:
>>> - add ability to use polling instead of interrupts
>>> - add ability to use extended timeouts
>>> - setup extended operational memory for GSC
>>>
>>> The series includes changes for the i915 driver:
>>> - allocate extended operational memory for GSC
>>> - GSC on XeHP SDV offsets and definitions
>>>
>>> This patch set should be merged via gfx tree as
>>> the auxiliary device belongs there.
>>> Greg, your ACK is required for the drives/misc/mei code base,
>>> please review the patches.
>> With the exception that you all don't know what year it is:
>>
>> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Daniele, why were the patches applied without this A-b?
Apologies, I usually rely on dim to pick up all the correct r-bs and
acks from the ML and to warn me if something is missing, and I didn't
realize that it hadn't automagically picked up the ack.
>
> I'm just preparing the drm-intel-gt-next pull request and now it appears
> like we're pushing a lot of commits outside of drm without any Acks.
>
> Please reach out to the maintainers *before* pushing code for other
> subsystems. Unless you get an explicit ack to do so, do not push such
> code.
I'm assuming you mean the i915 maintainers here, given that there is an
ack from Greg in this email? Rodrigo was in the loop of us needing to
merge this via drm, so I thought I was good on that side. I'll make sure
to have an explicit ack on the ML next time (which is coming relatively
soon, because there are some more mei patches in the DG2 HuC series).
>
> Quoting from the committer guidelines[1] the first rule is:
> "Only push patches changing drivers/gpu/drm/i915."
>
> In those cases, please ping a maintainer and don't rush things.
Will do. And apologies again for the mistake.
Daniele
> Regards, Joonas
>
> [1] https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-intel.html#high-level-guidelines
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-09-09 15:17 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 80+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-09-09 15:17 UTC (permalink / raw)
To: Joonas Lahtinen, Greg Kroah-Hartman, Tomas Winkler, David Airlie
Cc: intel-gfx, Alexander Usyskin, linux-kernel, Daniel Vetter,
Rodrigo Vivi, Vitaly Lubart
On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
> Dave, do you have a preference how to deal with the mishap here, shall I do a
> force-push to drm-intel-gt-next to correctly record the Acked-by or revert and
> re-push? Or just leave it as is?
>
> Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
>> On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
>>> Add GSC support for XeHP SDV and DG2 platforms.
>>>
>>> The series includes changes for the mei driver:
>>> - add ability to use polling instead of interrupts
>>> - add ability to use extended timeouts
>>> - setup extended operational memory for GSC
>>>
>>> The series includes changes for the i915 driver:
>>> - allocate extended operational memory for GSC
>>> - GSC on XeHP SDV offsets and definitions
>>>
>>> This patch set should be merged via gfx tree as
>>> the auxiliary device belongs there.
>>> Greg, your ACK is required for the drives/misc/mei code base,
>>> please review the patches.
>> With the exception that you all don't know what year it is:
>>
>> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Daniele, why were the patches applied without this A-b?
Apologies, I usually rely on dim to pick up all the correct r-bs and
acks from the ML and to warn me if something is missing, and I didn't
realize that it hadn't automagically picked up the ack.
>
> I'm just preparing the drm-intel-gt-next pull request and now it appears
> like we're pushing a lot of commits outside of drm without any Acks.
>
> Please reach out to the maintainers *before* pushing code for other
> subsystems. Unless you get an explicit ack to do so, do not push such
> code.
I'm assuming you mean the i915 maintainers here, given that there is an
ack from Greg in this email? Rodrigo was in the loop of us needing to
merge this via drm, so I thought I was good on that side. I'll make sure
to have an explicit ack on the ML next time (which is coming relatively
soon, because there are some more mei patches in the DG2 HuC series).
>
> Quoting from the committer guidelines[1] the first rule is:
> "Only push patches changing drivers/gpu/drm/i915."
>
> In those cases, please ping a maintainer and don't rush things.
Will do. And apologies again for the mistake.
Daniele
> Regards, Joonas
>
> [1] https://drm.pages.freedesktop.org/maintainer-tools/committer-drm-intel.html#high-level-guidelines
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 00/15] GSC support for XeHP SDV and DG2
2022-09-09 15:17 ` [Intel-gfx] " Ceraolo Spurio, Daniele
@ 2022-09-09 16:33 ` Vivi, Rodrigo
-1 siblings, 0 replies; 80+ messages in thread
From: Vivi, Rodrigo @ 2022-09-09 16:33 UTC (permalink / raw)
To: joonas.lahtinen, gregkh, Winkler, Tomas, Ceraolo Spurio, Daniele,
airlied
Cc: daniel, Usyskin, Alexander, tvrtko.ursulin, intel-gfx,
jani.nikula, Lubart, Vitaly, linux-kernel
On Fri, 2022-09-09 at 08:17 -0700, Ceraolo Spurio, Daniele wrote:
>
>
> On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
> > Dave, do you have a preference how to deal with the mishap here,
> > shall I do a
> > force-push to drm-intel-gt-next to correctly record the Acked-by or
> > revert and
> > re-push? Or just leave it as is?
Dave and Daniel, this question is still pertinent.
> >
> > Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
> > > On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> > > > Add GSC support for XeHP SDV and DG2 platforms.
> > > >
> > > > The series includes changes for the mei driver:
> > > > - add ability to use polling instead of interrupts
> > > > - add ability to use extended timeouts
> > > > - setup extended operational memory for GSC
> > > >
> > > > The series includes changes for the i915 driver:
> > > > - allocate extended operational memory for GSC
> > > > - GSC on XeHP SDV offsets and definitions
> > > >
> > > > This patch set should be merged via gfx tree as
> > > > the auxiliary device belongs there.
> > > > Greg, your ACK is required for the drives/misc/mei code base,
> > > > please review the patches.
> > > With the exception that you all don't know what year it is:
> > >
> > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Daniele, why were the patches applied without this A-b?
>
> Apologies, I usually rely on dim to pick up all the correct r-bs and
> acks from the ML and to warn me if something is missing, and I didn't
> realize that it hadn't automagically picked up the ack.
I understand the feeling. Recently I merged a patch from Vinay relying
on patchwork to get the reviewed-by and I forgot to double check.
dim picks up the "Link:", but I don't believe it picks any ack or rv-b
from the mailing list. Patchwork does if you use pwclient or something
like that.
Anyway, lesson to both of us to always double-check, regardless the
tool used.
>
> >
> > I'm just preparing the drm-intel-gt-next pull request and now it
> > appears
> > like we're pushing a lot of commits outside of drm without any
> > Acks.
> >
> > Please reach out to the maintainers *before* pushing code for other
> > subsystems. Unless you get an explicit ack to do so, do not push
> > such
> > code.
>
> I'm assuming you mean the i915 maintainers here, given that there is
> an
> ack from Greg in this email? Rodrigo was in the loop of us needing to
> merge this via drm, so I thought I was good on that side. I'll make
> sure
> to have an explicit ack on the ML next time (which is coming
> relatively
> soon, because there are some more mei patches in the DG2 HuC series).
That's my fault indeed. I was following the movement, but I failed
to step up right after I saw Greg's ack.
Although I also noticed some re-send and reviews in progress even
after the ack, I should had been more active there.
Sorry,
Rodrigo.
>
> >
> > Quoting from the committer guidelines[1] the first rule is:
> > "Only push patches changing drivers/gpu/drm/i915."
> >
> > In those cases, please ping a maintainer and don't rush things.
>
> Will do. And apologies again for the mistake.
>
> Daniele
>
> > Regards, Joonas
> >
> > [1] https://drm.pages.freedesktop.org/maintainer-tools/committer-
> > drm-intel.html#high-level-guidelines
> >
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-09-09 16:33 ` Vivi, Rodrigo
0 siblings, 0 replies; 80+ messages in thread
From: Vivi, Rodrigo @ 2022-09-09 16:33 UTC (permalink / raw)
To: joonas.lahtinen, gregkh, Winkler, Tomas, Ceraolo Spurio, Daniele,
airlied
Cc: intel-gfx, Usyskin, Alexander, linux-kernel, daniel, Lubart, Vitaly
On Fri, 2022-09-09 at 08:17 -0700, Ceraolo Spurio, Daniele wrote:
>
>
> On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
> > Dave, do you have a preference how to deal with the mishap here,
> > shall I do a
> > force-push to drm-intel-gt-next to correctly record the Acked-by or
> > revert and
> > re-push? Or just leave it as is?
Dave and Daniel, this question is still pertinent.
> >
> > Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
> > > On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> > > > Add GSC support for XeHP SDV and DG2 platforms.
> > > >
> > > > The series includes changes for the mei driver:
> > > > - add ability to use polling instead of interrupts
> > > > - add ability to use extended timeouts
> > > > - setup extended operational memory for GSC
> > > >
> > > > The series includes changes for the i915 driver:
> > > > - allocate extended operational memory for GSC
> > > > - GSC on XeHP SDV offsets and definitions
> > > >
> > > > This patch set should be merged via gfx tree as
> > > > the auxiliary device belongs there.
> > > > Greg, your ACK is required for the drives/misc/mei code base,
> > > > please review the patches.
> > > With the exception that you all don't know what year it is:
> > >
> > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > Daniele, why were the patches applied without this A-b?
>
> Apologies, I usually rely on dim to pick up all the correct r-bs and
> acks from the ML and to warn me if something is missing, and I didn't
> realize that it hadn't automagically picked up the ack.
I understand the feeling. Recently I merged a patch from Vinay relying
on patchwork to get the reviewed-by and I forgot to double check.
dim picks up the "Link:", but I don't believe it picks any ack or rv-b
from the mailing list. Patchwork does if you use pwclient or something
like that.
Anyway, lesson to both of us to always double-check, regardless the
tool used.
>
> >
> > I'm just preparing the drm-intel-gt-next pull request and now it
> > appears
> > like we're pushing a lot of commits outside of drm without any
> > Acks.
> >
> > Please reach out to the maintainers *before* pushing code for other
> > subsystems. Unless you get an explicit ack to do so, do not push
> > such
> > code.
>
> I'm assuming you mean the i915 maintainers here, given that there is
> an
> ack from Greg in this email? Rodrigo was in the loop of us needing to
> merge this via drm, so I thought I was good on that side. I'll make
> sure
> to have an explicit ack on the ML next time (which is coming
> relatively
> soon, because there are some more mei patches in the DG2 HuC series).
That's my fault indeed. I was following the movement, but I failed
to step up right after I saw Greg's ack.
Although I also noticed some re-send and reviews in progress even
after the ack, I should had been more active there.
Sorry,
Rodrigo.
>
> >
> > Quoting from the committer guidelines[1] the first rule is:
> > "Only push patches changing drivers/gpu/drm/i915."
> >
> > In those cases, please ping a maintainer and don't rush things.
>
> Will do. And apologies again for the mistake.
>
> Daniele
>
> > Regards, Joonas
> >
> > [1] https://drm.pages.freedesktop.org/maintainer-tools/committer-
> > drm-intel.html#high-level-guidelines
> >
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
2022-09-09 16:33 ` [Intel-gfx] " Vivi, Rodrigo
@ 2022-09-09 17:16 ` Lucas De Marchi
-1 siblings, 0 replies; 80+ messages in thread
From: Lucas De Marchi @ 2022-09-09 17:16 UTC (permalink / raw)
To: Vivi, Rodrigo
Cc: joonas.lahtinen, gregkh, Winkler, Tomas, Ceraolo Spurio, Daniele,
airlied, intel-gfx, Usyskin, Alexander, linux-kernel, daniel,
Lubart, Vitaly
On Fri, Sep 09, 2022 at 04:33:45PM +0000, Rodrigo Vivi wrote:
>On Fri, 2022-09-09 at 08:17 -0700, Ceraolo Spurio, Daniele wrote:
>>
>>
>> On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
>> > Dave, do you have a preference how to deal with the mishap here,
>> > shall I do a
>> > force-push to drm-intel-gt-next to correctly record the Acked-by or
>> > revert and
>> > re-push? Or just leave it as is?
>
>Dave and Daniel, this question is still pertinent.
>
>> >
>> > Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
>> > > On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
>> > > > Add GSC support for XeHP SDV and DG2 platforms.
>> > > >
>> > > > The series includes changes for the mei driver:
>> > > > - add ability to use polling instead of interrupts
>> > > > - add ability to use extended timeouts
>> > > > - setup extended operational memory for GSC
>> > > >
>> > > > The series includes changes for the i915 driver:
>> > > > - allocate extended operational memory for GSC
>> > > > - GSC on XeHP SDV offsets and definitions
>> > > >
>> > > > This patch set should be merged via gfx tree as
>> > > > the auxiliary device belongs there.
>> > > > Greg, your ACK is required for the drives/misc/mei code base,
>> > > > please review the patches.
>> > > With the exception that you all don't know what year it is:
>> > >
>> > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> > Daniele, why were the patches applied without this A-b?
>>
>> Apologies, I usually rely on dim to pick up all the correct r-bs and
>> acks from the ML and to warn me if something is missing, and I didn't
>> realize that it hadn't automagically picked up the ack.
>
>I understand the feeling. Recently I merged a patch from Vinay relying
>on patchwork to get the reviewed-by and I forgot to double check.
>
>dim picks up the "Link:", but I don't believe it picks any ack or rv-b
>from the mailing list. Patchwork does if you use pwclient or something
>like that.
When you download the patch from patchwork, it will include the
r-b/a-b for the patches, not the cover letter.
$ curl https://patchwork.freedesktop.org/api/1.0/series/106638/revisions/5/mbox/ | \
grep Acked-by
$
Patchwork simply ignores the cover and does nothing.
b4 has an option to propagate the a-b on cover to the patches (-t):
$ b4 am -o - -t YxDLFWjIllqqh9de@kroah.com | grep Acked
...
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
...
b4 also has options to work on your local mailbox instead of relying on
the external server to apply a-b/r-b. Maybe people should be using it
more instead of relying on patchwork.
Should the Acked-by be recorded on each patch? That is what is usually
done, but if preference would be for a merge commit to be created and
Acked-by recorded in the merge commit, dim would need to learn a
few things. b4 is already prepared:
$ b4 shazam -M -P1-15 YxDLFWjIllqqh9de@kroah.com
Lucas De Marchi
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-09-09 17:16 ` Lucas De Marchi
0 siblings, 0 replies; 80+ messages in thread
From: Lucas De Marchi @ 2022-09-09 17:16 UTC (permalink / raw)
To: Vivi, Rodrigo
Cc: airlied, gregkh, intel-gfx, Usyskin, Alexander, linux-kernel,
daniel, Winkler, Tomas, Lubart, Vitaly
On Fri, Sep 09, 2022 at 04:33:45PM +0000, Rodrigo Vivi wrote:
>On Fri, 2022-09-09 at 08:17 -0700, Ceraolo Spurio, Daniele wrote:
>>
>>
>> On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
>> > Dave, do you have a preference how to deal with the mishap here,
>> > shall I do a
>> > force-push to drm-intel-gt-next to correctly record the Acked-by or
>> > revert and
>> > re-push? Or just leave it as is?
>
>Dave and Daniel, this question is still pertinent.
>
>> >
>> > Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
>> > > On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
>> > > > Add GSC support for XeHP SDV and DG2 platforms.
>> > > >
>> > > > The series includes changes for the mei driver:
>> > > > - add ability to use polling instead of interrupts
>> > > > - add ability to use extended timeouts
>> > > > - setup extended operational memory for GSC
>> > > >
>> > > > The series includes changes for the i915 driver:
>> > > > - allocate extended operational memory for GSC
>> > > > - GSC on XeHP SDV offsets and definitions
>> > > >
>> > > > This patch set should be merged via gfx tree as
>> > > > the auxiliary device belongs there.
>> > > > Greg, your ACK is required for the drives/misc/mei code base,
>> > > > please review the patches.
>> > > With the exception that you all don't know what year it is:
>> > >
>> > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>> > Daniele, why were the patches applied without this A-b?
>>
>> Apologies, I usually rely on dim to pick up all the correct r-bs and
>> acks from the ML and to warn me if something is missing, and I didn't
>> realize that it hadn't automagically picked up the ack.
>
>I understand the feeling. Recently I merged a patch from Vinay relying
>on patchwork to get the reviewed-by and I forgot to double check.
>
>dim picks up the "Link:", but I don't believe it picks any ack or rv-b
>from the mailing list. Patchwork does if you use pwclient or something
>like that.
When you download the patch from patchwork, it will include the
r-b/a-b for the patches, not the cover letter.
$ curl https://patchwork.freedesktop.org/api/1.0/series/106638/revisions/5/mbox/ | \
grep Acked-by
$
Patchwork simply ignores the cover and does nothing.
b4 has an option to propagate the a-b on cover to the patches (-t):
$ b4 am -o - -t YxDLFWjIllqqh9de@kroah.com | grep Acked
...
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
...
b4 also has options to work on your local mailbox instead of relying on
the external server to apply a-b/r-b. Maybe people should be using it
more instead of relying on patchwork.
Should the Acked-by be recorded on each patch? That is what is usually
done, but if preference would be for a merge commit to be created and
Acked-by recorded in the merge commit, dim would need to learn a
few things. b4 is already prepared:
$ b4 shazam -M -P1-15 YxDLFWjIllqqh9de@kroah.com
Lucas De Marchi
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [PATCH v7 00/15] GSC support for XeHP SDV and DG2
2022-09-09 16:33 ` [Intel-gfx] " Vivi, Rodrigo
@ 2022-09-12 12:51 ` Joonas Lahtinen
-1 siblings, 0 replies; 80+ messages in thread
From: Joonas Lahtinen @ 2022-09-12 12:51 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Vivi, Rodrigo, Winkler, Tomas, airlied, gregkh
Cc: daniel, Usyskin, Alexander, tvrtko.ursulin, intel-gfx,
jani.nikula, Lubart, Vitaly, linux-kernel
Quoting Vivi, Rodrigo (2022-09-09 19:33:45)
> On Fri, 2022-09-09 at 08:17 -0700, Ceraolo Spurio, Daniele wrote:
> >
> >
> > On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
> > > Dave, do you have a preference how to deal with the mishap here,
> > > shall I do a
> > > force-push to drm-intel-gt-next to correctly record the Acked-by or
> > > revert and
> > > re-push? Or just leave it as is?
>
> Dave and Daniel, this question is still pertinent.
Discussed with Dave and I did a force-push to add the missing
Acked-by's.
Daniele, I think the tradition is that you have volunteered
yourself to improve dim to nag about missing Acked-by's for
patches outside of i915 when pushing to drm-intel-gt-next.
Regards, Joonas
>
> > >
> > > Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
> > > > On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> > > > > Add GSC support for XeHP SDV and DG2 platforms.
> > > > >
> > > > > The series includes changes for the mei driver:
> > > > > - add ability to use polling instead of interrupts
> > > > > - add ability to use extended timeouts
> > > > > - setup extended operational memory for GSC
> > > > >
> > > > > The series includes changes for the i915 driver:
> > > > > - allocate extended operational memory for GSC
> > > > > - GSC on XeHP SDV offsets and definitions
> > > > >
> > > > > This patch set should be merged via gfx tree as
> > > > > the auxiliary device belongs there.
> > > > > Greg, your ACK is required for the drives/misc/mei code base,
> > > > > please review the patches.
> > > > With the exception that you all don't know what year it is:
> > > >
> > > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > Daniele, why were the patches applied without this A-b?
> >
> > Apologies, I usually rely on dim to pick up all the correct r-bs and
> > acks from the ML and to warn me if something is missing, and I didn't
> > realize that it hadn't automagically picked up the ack.
>
> I understand the feeling. Recently I merged a patch from Vinay relying
> on patchwork to get the reviewed-by and I forgot to double check.
>
> dim picks up the "Link:", but I don't believe it picks any ack or rv-b
> from the mailing list. Patchwork does if you use pwclient or something
> like that.
>
> Anyway, lesson to both of us to always double-check, regardless the
> tool used.
>
> >
> > >
> > > I'm just preparing the drm-intel-gt-next pull request and now it
> > > appears
> > > like we're pushing a lot of commits outside of drm without any
> > > Acks.
> > >
> > > Please reach out to the maintainers *before* pushing code for other
> > > subsystems. Unless you get an explicit ack to do so, do not push
> > > such
> > > code.
> >
> > I'm assuming you mean the i915 maintainers here, given that there is
> > an
> > ack from Greg in this email? Rodrigo was in the loop of us needing to
> > merge this via drm, so I thought I was good on that side. I'll make
> > sure
> > to have an explicit ack on the ML next time (which is coming
> > relatively
> > soon, because there are some more mei patches in the DG2 HuC series).
>
> That's my fault indeed. I was following the movement, but I failed
> to step up right after I saw Greg's ack.
> Although I also noticed some re-send and reviews in progress even
> after the ack, I should had been more active there.
>
> Sorry,
> Rodrigo.
>
> >
> > >
> > > Quoting from the committer guidelines[1] the first rule is:
> > > "Only push patches changing drivers/gpu/drm/i915."
> > >
> > > In those cases, please ping a maintainer and don't rush things.
> >
> > Will do. And apologies again for the mistake.
> >
> > Daniele
> >
> > > Regards, Joonas
> > >
> > > [1] https://drm.pages.freedesktop.org/maintainer-tools/committer-
> > > drm-intel.html#high-level-guidelines
> > >
> >
>
^ permalink raw reply [flat|nested] 80+ messages in thread
* Re: [Intel-gfx] [PATCH v7 00/15] GSC support for XeHP SDV and DG2
@ 2022-09-12 12:51 ` Joonas Lahtinen
0 siblings, 0 replies; 80+ messages in thread
From: Joonas Lahtinen @ 2022-09-12 12:51 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele, Vivi, Rodrigo, Winkler, Tomas, airlied, gregkh
Cc: intel-gfx, Usyskin, Alexander, linux-kernel, daniel, Lubart, Vitaly
Quoting Vivi, Rodrigo (2022-09-09 19:33:45)
> On Fri, 2022-09-09 at 08:17 -0700, Ceraolo Spurio, Daniele wrote:
> >
> >
> > On 9/9/2022 3:24 AM, Joonas Lahtinen wrote:
> > > Dave, do you have a preference how to deal with the mishap here,
> > > shall I do a
> > > force-push to drm-intel-gt-next to correctly record the Acked-by or
> > > revert and
> > > re-push? Or just leave it as is?
>
> Dave and Daniel, this question is still pertinent.
Discussed with Dave and I did a force-push to add the missing
Acked-by's.
Daniele, I think the tradition is that you have volunteered
yourself to improve dim to nag about missing Acked-by's for
patches outside of i915 when pushing to drm-intel-gt-next.
Regards, Joonas
>
> > >
> > > Quoting Greg Kroah-Hartman (2022-09-01 18:09:09)
> > > > On Sat, Aug 06, 2022 at 03:26:21PM +0300, Tomas Winkler wrote:
> > > > > Add GSC support for XeHP SDV and DG2 platforms.
> > > > >
> > > > > The series includes changes for the mei driver:
> > > > > - add ability to use polling instead of interrupts
> > > > > - add ability to use extended timeouts
> > > > > - setup extended operational memory for GSC
> > > > >
> > > > > The series includes changes for the i915 driver:
> > > > > - allocate extended operational memory for GSC
> > > > > - GSC on XeHP SDV offsets and definitions
> > > > >
> > > > > This patch set should be merged via gfx tree as
> > > > > the auxiliary device belongs there.
> > > > > Greg, your ACK is required for the drives/misc/mei code base,
> > > > > please review the patches.
> > > > With the exception that you all don't know what year it is:
> > > >
> > > > Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > > Daniele, why were the patches applied without this A-b?
> >
> > Apologies, I usually rely on dim to pick up all the correct r-bs and
> > acks from the ML and to warn me if something is missing, and I didn't
> > realize that it hadn't automagically picked up the ack.
>
> I understand the feeling. Recently I merged a patch from Vinay relying
> on patchwork to get the reviewed-by and I forgot to double check.
>
> dim picks up the "Link:", but I don't believe it picks any ack or rv-b
> from the mailing list. Patchwork does if you use pwclient or something
> like that.
>
> Anyway, lesson to both of us to always double-check, regardless the
> tool used.
>
> >
> > >
> > > I'm just preparing the drm-intel-gt-next pull request and now it
> > > appears
> > > like we're pushing a lot of commits outside of drm without any
> > > Acks.
> > >
> > > Please reach out to the maintainers *before* pushing code for other
> > > subsystems. Unless you get an explicit ack to do so, do not push
> > > such
> > > code.
> >
> > I'm assuming you mean the i915 maintainers here, given that there is
> > an
> > ack from Greg in this email? Rodrigo was in the loop of us needing to
> > merge this via drm, so I thought I was good on that side. I'll make
> > sure
> > to have an explicit ack on the ML next time (which is coming
> > relatively
> > soon, because there are some more mei patches in the DG2 HuC series).
>
> That's my fault indeed. I was following the movement, but I failed
> to step up right after I saw Greg's ack.
> Although I also noticed some re-send and reviews in progress even
> after the ack, I should had been more active there.
>
> Sorry,
> Rodrigo.
>
> >
> > >
> > > Quoting from the committer guidelines[1] the first rule is:
> > > "Only push patches changing drivers/gpu/drm/i915."
> > >
> > > In those cases, please ping a maintainer and don't rush things.
> >
> > Will do. And apologies again for the mistake.
> >
> > Daniele
> >
> > > Regards, Joonas
> > >
> > > [1] https://drm.pages.freedesktop.org/maintainer-tools/committer-
> > > drm-intel.html#high-level-guidelines
> > >
> >
>
^ permalink raw reply [flat|nested] 80+ messages in thread
end of thread, other threads:[~2022-09-12 12:52 UTC | newest]
Thread overview: 80+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-08-06 12:26 [PATCH v7 00/15] GSC support for XeHP SDV and DG2 Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 01/15] drm/i915/gsc: skip irq initialization if using polling Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 02/15] mei: add kdoc for struct mei_aux_device Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 15:30 ` Ceraolo Spurio, Daniele
2022-09-01 15:30 ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 03/15] mei: add slow_firmware flag to the mei auxiliary device Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 04/15] drm/i915/gsc: add slow_firmware flag to the gsc device definition Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-08-06 12:26 ` [PATCH v7 05/15] drm/i915/gsc: add GSC XeHP SDV platform definition Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 15:31 ` Ceraolo Spurio, Daniele
2022-09-01 15:31 ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 06/15] mei: gsc: use polling instead of interrupts Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 16:00 ` Ceraolo Spurio, Daniele
2022-09-01 16:00 ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 07/15] mei: gsc: wait for reset thread on stop Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 16:07 ` Ceraolo Spurio, Daniele
2022-09-01 16:07 ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 08/15] mei: extend timeouts on slow devices Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 17:00 ` Ceraolo Spurio, Daniele
2022-09-01 17:00 ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 09/15] mei: bus: export common mkhi definitions into a separate header Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 20:54 ` Ceraolo Spurio, Daniele
2022-09-01 20:54 ` Ceraolo Spurio, Daniele
2022-09-03 10:05 ` Winkler, Tomas
2022-09-03 10:05 ` Winkler, Tomas
2022-08-06 12:26 ` [PATCH v7 10/15] mei: mkhi: add memory ready command Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 15:08 ` Greg Kroah-Hartman
2022-09-01 15:08 ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-01 20:56 ` Ceraolo Spurio, Daniele
2022-09-01 20:56 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 11/15] mei: gsc: setup gsc extended operational memory Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 21:02 ` Ceraolo Spurio, Daniele
2022-09-01 21:02 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-04 7:29 ` Usyskin, Alexander
2022-09-04 7:29 ` [Intel-gfx] " Usyskin, Alexander
2022-09-04 22:26 ` Ceraolo Spurio, Daniele
2022-09-04 22:26 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 12/15] mei: gsc: add transition to PXP mode in resume flow Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 21:19 ` Ceraolo Spurio, Daniele
2022-09-01 21:19 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 13/15] mei: debugfs: add pxp mode to devstate in debugfs Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 21:20 ` Ceraolo Spurio, Daniele
2022-09-01 21:20 ` Ceraolo Spurio, Daniele
2022-08-06 12:26 ` [PATCH v7 14/15] drm/i915/gsc: allocate extended operational memory in LMEM Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-09-01 16:31 ` Teres Alexis, Alan Previn
2022-09-01 16:31 ` [Intel-gfx] " Teres Alexis, Alan Previn
2022-09-02 8:25 ` Matthew Auld
2022-09-02 8:25 ` Matthew Auld
2022-08-06 12:26 ` [PATCH v7 15/15] HAX: drm/i915: force INTEL_MEI_GSC on for CI Tomas Winkler
2022-08-06 12:26 ` [Intel-gfx] " Tomas Winkler
2022-08-06 12:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GSC support for XeHP SDV and DG2 (rev2) Patchwork
2022-08-06 12:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-08-06 13:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-06 14:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-09-01 15:09 ` [PATCH v7 00/15] GSC support for XeHP SDV and DG2 Greg Kroah-Hartman
2022-09-01 15:09 ` [Intel-gfx] " Greg Kroah-Hartman
2022-09-09 10:24 ` Joonas Lahtinen
2022-09-09 10:24 ` [Intel-gfx] " Joonas Lahtinen
2022-09-09 15:17 ` Ceraolo Spurio, Daniele
2022-09-09 15:17 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-09-09 16:33 ` Vivi, Rodrigo
2022-09-09 16:33 ` [Intel-gfx] " Vivi, Rodrigo
2022-09-09 17:16 ` Lucas De Marchi
2022-09-09 17:16 ` Lucas De Marchi
2022-09-12 12:51 ` Joonas Lahtinen
2022-09-12 12:51 ` [Intel-gfx] " Joonas Lahtinen
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