[PATCH v3 00/16] Ux500 hash cleanup

[PATCH v3 00/16] Ux500 hash cleanup

[Linus Walleij]

This has been very sparingly maintained the last few years,
but as it happens an active user appeared and sent me a
bug report, so here is a series cleaning up the driver
so we can maintain it going forward.

Most patches are modernizations, using new frameworks and
helpers.

The expensive self tests are passing fine after this series.

I think it is a bit too big to backport to stable :/
But please put it in as non-urgent fix.

If this goes well the plan is to do the same for the crypto
driver which has all the same problems.

ChangeLog v2->v3:
- Rebase on v6.0-rc1
- Use accelerated noinc regmap MMIO

ChangeLog v1->v2:
- Iron out some minor runtime bugs.
- Fix a regmap initialization error.
- Fix up to use runtime PM and drop custom power states.

Linus Walleij (16):
  crypto: ux500/hash: Pass ctx to hash_setconfiguration()
  crypto: ux500/hash: Get rid of custom device list
  crypto: ux500/hash: Pass context to zero message digest
  crypto: ux500/hash: Drop custom state save/restore
  crypto: ux500/hash: Drop bit index
  crypto: ux500/hash: Break while/do instead of if/else
  crypto: ux500/hash: Rename and switch type of member
  crypto: ux500/hash: Stop saving/restoring compulsively
  crypto: ux500/hash: Get rid of state from request context
  crypto: ux500/hash: Implement .export and .import
  crypto: ux500/hash: Drop custom uint64 type
  crypto: ux500/hash: Drop regulator handling
  crypto: ux500/hash: Convert to regmap MMIO
  crypto: ux500/hash: Use AMBA core primecell IDs
  crypto: ux500/hash: Implement runtime PM
  crypto: ux500/hash: Use accelerated noinc MMIO

 drivers/crypto/ux500/Kconfig          |    1 +
 drivers/crypto/ux500/hash/hash_alg.h  |  262 ++----
 drivers/crypto/ux500/hash/hash_core.c | 1152 ++++++++++---------------
 3 files changed, 533 insertions(+), 882 deletions(-)

-- 
2.37.2

[PATCH v3 01/16] crypto: ux500/hash: Pass ctx to hash_setconfiguration()

[Linus Walleij]

This function was dereferencing device_data->current_ctx
to get the context. This is not a good idea, the device_data
is serialized with an awkward semaphore construction and
fragile.

Also fix a checkpatch warning about putting compared constants
to the right in an expression.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  |  2 +-
 drivers/crypto/ux500/hash/hash_core.c | 15 ++++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 7c9bcc15125f..26e8b7949d7c 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -380,7 +380,7 @@ struct hash_device_data {
 int hash_check_hw(struct hash_device_data *device_data);
 
 int hash_setconfiguration(struct hash_device_data *device_data,
-		struct hash_config *config);
+			  struct hash_ctx *ctx);
 
 void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx);
 
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index f104e8a43036..1662e176de44 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -473,7 +473,7 @@ static int init_hash_hw(struct hash_device_data *device_data,
 {
 	int ret = 0;
 
-	ret = hash_setconfiguration(device_data, &ctx->config);
+	ret = hash_setconfiguration(device_data, ctx);
 	if (ret) {
 		dev_err(device_data->dev, "%s: hash_setconfiguration() failed!\n",
 			__func__);
@@ -672,11 +672,12 @@ static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
  * hash_setconfiguration - Sets the required configuration for the hash
  *                         hardware.
  * @device_data:	Structure for the hash device.
- * @config:		Pointer to a configuration structure.
+ * @ctx:		Current context
  */
 int hash_setconfiguration(struct hash_device_data *device_data,
-			  struct hash_config *config)
+			  struct hash_ctx *ctx)
 {
+	struct hash_config *config = &ctx->config;
 	int ret = 0;
 
 	if (config->algorithm != HASH_ALGO_SHA1 &&
@@ -711,12 +712,12 @@ int hash_setconfiguration(struct hash_device_data *device_data,
 	 * MODE bit. This bit selects between HASH or HMAC mode for the
 	 * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
 	 */
-	if (HASH_OPER_MODE_HASH == config->oper_mode)
+	if (config->oper_mode == HASH_OPER_MODE_HASH) {
 		HASH_CLEAR_BITS(&device_data->base->cr,
 				HASH_CR_MODE_MASK);
-	else if (HASH_OPER_MODE_HMAC == config->oper_mode) {
+	} else if (config->oper_mode == HASH_OPER_MODE_HMAC) {
 		HASH_SET_BITS(&device_data->base->cr, HASH_CR_MODE_MASK);
-		if (device_data->current_ctx->keylen > HASH_BLOCK_SIZE) {
+		if (ctx->keylen > HASH_BLOCK_SIZE) {
 			/* Truncate key to blocksize */
 			dev_dbg(device_data->dev, "%s: LKEY set\n", __func__);
 			HASH_SET_BITS(&device_data->base->cr,
@@ -878,7 +879,7 @@ static int hash_dma_final(struct ahash_request *req)
 			goto out;
 		}
 	} else {
-		ret = hash_setconfiguration(device_data, &ctx->config);
+		ret = hash_setconfiguration(device_data, ctx);
 		if (ret) {
 			dev_err(device_data->dev,
 				"%s: hash_setconfiguration() failed!\n",
-- 
2.37.2

[PATCH v3 02/16] crypto: ux500/hash: Get rid of custom device list

[Linus Walleij]

The Ux500 hash driver builds a list with one (1) hash engine
as it is all it has, then goes to great lengths to lock the
one device using a semaphore.

Instead do what other drivers do: trust the core to do the
right thing, add the device state to the algorithm template,
fill it in when registering the algorithms and assign
the device state to the context when intializing each context.

This saves us from a lot of complex code.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_core.c | 194 +++-----------------------
 1 file changed, 17 insertions(+), 177 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 1662e176de44..5c2da6d42121 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -19,7 +19,6 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
-#include <linux/klist.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
@@ -59,19 +58,6 @@ static const u8 zero_message_hmac_sha256[SHA256_DIGEST_SIZE] = {
 	0xc6, 0xc7, 0x12, 0x14, 0x42, 0x92, 0xc5, 0xad
 };
 
-/**
- * struct hash_driver_data - data specific to the driver.
- *
- * @device_list:	A list of registered devices to choose from.
- * @device_allocation:	A semaphore initialized with number of devices.
- */
-struct hash_driver_data {
-	struct klist		device_list;
-	struct semaphore	device_allocation;
-};
-
-static struct hash_driver_data	driver_data;
-
 /* Declaration of functions */
 /**
  * hash_messagepad - Pads a message and write the nblw bits.
@@ -86,24 +72,6 @@ static struct hash_driver_data	driver_data;
 static void hash_messagepad(struct hash_device_data *device_data,
 			    const u32 *message, u8 index_bytes);
 
-/**
- * release_hash_device - Releases a previously allocated hash device.
- * @device_data:	Structure for the hash device.
- *
- */
-static void release_hash_device(struct hash_device_data *device_data)
-{
-	spin_lock(&device_data->ctx_lock);
-	device_data->current_ctx->device = NULL;
-	device_data->current_ctx = NULL;
-	spin_unlock(&device_data->ctx_lock);
-
-	/*
-	 * The down_interruptible part for this semaphore is called in
-	 * cryp_get_device_data.
-	 */
-	up(&driver_data.device_allocation);
-}
 
 static void hash_dma_setup_channel(struct hash_device_data *device_data,
 				   struct device *dev)
@@ -354,65 +322,6 @@ static int hash_enable_power(struct hash_device_data *device_data,
 	return ret;
 }
 
-/**
- * hash_get_device_data - Checks for an available hash device and return it.
- * @ctx:		Structure for the hash context.
- * @device_data:	Structure for the hash device.
- *
- * This function check for an available hash device and return it to
- * the caller.
- * Note! Caller need to release the device, calling up().
- */
-static int hash_get_device_data(struct hash_ctx *ctx,
-				struct hash_device_data **device_data)
-{
-	int			ret;
-	struct klist_iter	device_iterator;
-	struct klist_node	*device_node;
-	struct hash_device_data *local_device_data = NULL;
-
-	/* Wait until a device is available */
-	ret = down_interruptible(&driver_data.device_allocation);
-	if (ret)
-		return ret;  /* Interrupted */
-
-	/* Select a device */
-	klist_iter_init(&driver_data.device_list, &device_iterator);
-	device_node = klist_next(&device_iterator);
-	while (device_node) {
-		local_device_data = container_of(device_node,
-					   struct hash_device_data, list_node);
-		spin_lock(&local_device_data->ctx_lock);
-		/* current_ctx allocates a device, NULL = unallocated */
-		if (local_device_data->current_ctx) {
-			device_node = klist_next(&device_iterator);
-		} else {
-			local_device_data->current_ctx = ctx;
-			ctx->device = local_device_data;
-			spin_unlock(&local_device_data->ctx_lock);
-			break;
-		}
-		spin_unlock(&local_device_data->ctx_lock);
-	}
-	klist_iter_exit(&device_iterator);
-
-	if (!device_node) {
-		/**
-		 * No free device found.
-		 * Since we allocated a device with down_interruptible, this
-		 * should not be able to happen.
-		 * Number of available devices, which are contained in
-		 * device_allocation, is therefore decremented by not doing
-		 * an up(device_allocation).
-		 */
-		return -EBUSY;
-	}
-
-	*device_data = local_device_data;
-
-	return 0;
-}
-
 /**
  * hash_hw_write_key - Writes the key to the hardware registries.
  *
@@ -859,14 +768,10 @@ static int hash_dma_final(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
-	struct hash_device_data *device_data;
+	struct hash_device_data *device_data = ctx->device;
 	u8 digest[SHA256_DIGEST_SIZE];
 	int bytes_written = 0;
 
-	ret = hash_get_device_data(ctx, &device_data);
-	if (ret)
-		return ret;
-
 	dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 		(unsigned long)ctx);
 
@@ -944,8 +849,6 @@ static int hash_dma_final(struct ahash_request *req)
 	memcpy(req->result, digest, ctx->digestsize);
 
 out:
-	release_hash_device(device_data);
-
 	/**
 	 * Allocated in setkey, and only used in HMAC.
 	 */
@@ -964,13 +867,9 @@ static int hash_hw_final(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
-	struct hash_device_data *device_data;
+	struct hash_device_data *device_data = ctx->device;
 	u8 digest[SHA256_DIGEST_SIZE];
 
-	ret = hash_get_device_data(ctx, &device_data);
-	if (ret)
-		return ret;
-
 	dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 		(unsigned long)ctx);
 
@@ -1047,7 +946,6 @@ static int hash_hw_final(struct ahash_request *req)
 	memcpy(req->result, digest, ctx->digestsize);
 
 out:
-	release_hash_device(device_data);
 
 	/**
 	 * Allocated in setkey, and only used in HMAC.
@@ -1068,36 +966,29 @@ int hash_hw_update(struct ahash_request *req)
 	int ret = 0;
 	u8 index = 0;
 	u8 *buffer;
-	struct hash_device_data *device_data;
 	u8 *data_buffer;
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
+	struct hash_device_data *device_data = ctx->device;
 	struct crypto_hash_walk walk;
 	int msg_length;
 
 	index = req_ctx->state.index;
 	buffer = (u8 *)req_ctx->state.buffer;
 
-	ret = hash_get_device_data(ctx, &device_data);
-	if (ret)
-		return ret;
-
 	msg_length = crypto_hash_walk_first(req, &walk);
 
 	/* Empty message ("") is correct indata */
-	if (msg_length == 0) {
-		ret = 0;
-		goto release_dev;
-	}
+	if (msg_length == 0)
+		return 0;
 
 	/* Check if ctx->state.length + msg_length
 	   overflows */
 	if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
 	    HASH_HIGH_WORD_MAX_VAL == req_ctx->state.length.high_word) {
 		pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__);
-		ret = crypto_hash_walk_done(&walk, -EPERM);
-		goto release_dev;
+		return crypto_hash_walk_done(&walk, -EPERM);
 	}
 
 	/* Main loop */
@@ -1110,7 +1001,7 @@ int hash_hw_update(struct ahash_request *req)
 			dev_err(device_data->dev, "%s: hash_internal_hw_update() failed!\n",
 				__func__);
 			crypto_hash_walk_done(&walk, ret);
-			goto release_dev;
+			return ret;
 		}
 
 		msg_length = crypto_hash_walk_done(&walk, 0);
@@ -1120,10 +1011,7 @@ int hash_hw_update(struct ahash_request *req)
 	dev_dbg(device_data->dev, "%s: indata length=%d, bin=%d\n",
 		__func__, req_ctx->state.index, req_ctx->state.bit_index);
 
-release_dev:
-	release_hash_device(device_data);
-
-	return ret;
+	return 0;
 }
 
 /**
@@ -1495,6 +1383,7 @@ static int hmac_sha256_setkey(struct crypto_ahash *tfm,
 struct hash_algo_template {
 	struct hash_config conf;
 	struct ahash_alg hash;
+	struct hash_device_data	*device;
 };
 
 static int hash_cra_init(struct crypto_tfm *tfm)
@@ -1507,6 +1396,8 @@ static int hash_cra_init(struct crypto_tfm *tfm)
 			struct hash_algo_template,
 			hash);
 
+	ctx->device = hash_alg->device;
+
 	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 				 sizeof(struct hash_req_ctx));
 
@@ -1623,6 +1514,7 @@ static int ahash_algs_register_all(struct hash_device_data *device_data)
 	int count;
 
 	for (i = 0; i < ARRAY_SIZE(hash_algs); i++) {
+		hash_algs[i].device = device_data;
 		ret = crypto_register_ahash(&hash_algs[i].hash);
 		if (ret) {
 			count = i;
@@ -1723,11 +1615,6 @@ static int ux500_hash_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, device_data);
 
-	/* Put the new device into the device list... */
-	klist_add_tail(&device_data->list_node, &driver_data.device_list);
-	/* ... and signal that a new device is available. */
-	up(&driver_data.device_allocation);
-
 	ret = ahash_algs_register_all(device_data);
 	if (ret) {
 		dev_err(dev, "%s: ahash_algs_register_all() failed!\n",
@@ -1766,10 +1653,6 @@ static int ux500_hash_remove(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	/* Try to decrease the number of available devices. */
-	if (down_trylock(&driver_data.device_allocation))
-		return -EBUSY;
-
 	/* Check that the device is free */
 	spin_lock(&device_data->ctx_lock);
 	/* current_ctx allocates a device, NULL = unallocated */
@@ -1777,19 +1660,12 @@ static int ux500_hash_remove(struct platform_device *pdev)
 		/* The device is busy */
 		spin_unlock(&device_data->ctx_lock);
 		/* Return the device to the pool. */
-		up(&driver_data.device_allocation);
 		return -EBUSY;
 	}
 
 	spin_unlock(&device_data->ctx_lock);
 
-	/* Remove the device from the list */
-	if (klist_node_attached(&device_data->list_node))
-		klist_remove(&device_data->list_node);
-
-	/* If this was the last device, remove the services */
-	if (list_empty(&driver_data.device_list.k_list))
-		ahash_algs_unregister_all(device_data);
+	ahash_algs_unregister_all(device_data);
 
 	if (hash_disable_power(device_data, false))
 		dev_err(dev, "%s: hash_disable_power() failed\n",
@@ -1820,9 +1696,6 @@ static void ux500_hash_shutdown(struct platform_device *pdev)
 	spin_lock(&device_data->ctx_lock);
 	/* current_ctx allocates a device, NULL = unallocated */
 	if (!device_data->current_ctx) {
-		if (down_trylock(&driver_data.device_allocation))
-			dev_dbg(&pdev->dev, "%s: Cryp still in use! Shutting down anyway...\n",
-				__func__);
 		/**
 		 * (Allocate the device)
 		 * Need to set this to non-null (dummy) value,
@@ -1832,13 +1705,7 @@ static void ux500_hash_shutdown(struct platform_device *pdev)
 	}
 	spin_unlock(&device_data->ctx_lock);
 
-	/* Remove the device from the list */
-	if (klist_node_attached(&device_data->list_node))
-		klist_remove(&device_data->list_node);
-
-	/* If this was the last device, remove the services */
-	if (list_empty(&driver_data.device_list.k_list))
-		ahash_algs_unregister_all(device_data);
+	ahash_algs_unregister_all(device_data);
 
 	if (hash_disable_power(device_data, false))
 		dev_err(&pdev->dev, "%s: hash_disable_power() failed\n",
@@ -1868,9 +1735,6 @@ static int ux500_hash_suspend(struct device *dev)
 	spin_unlock(&device_data->ctx_lock);
 
 	if (device_data->current_ctx == ++temp_ctx) {
-		if (down_interruptible(&driver_data.device_allocation))
-			dev_dbg(dev, "%s: down_interruptible() failed\n",
-				__func__);
 		ret = hash_disable_power(device_data, false);
 
 	} else {
@@ -1904,9 +1768,7 @@ static int ux500_hash_resume(struct device *dev)
 		device_data->current_ctx = NULL;
 	spin_unlock(&device_data->ctx_lock);
 
-	if (!device_data->current_ctx)
-		up(&driver_data.device_allocation);
-	else
+	if (device_data->current_ctx)
 		ret = hash_enable_power(device_data, true);
 
 	if (ret)
@@ -1924,7 +1786,7 @@ static const struct of_device_id ux500_hash_match[] = {
 };
 MODULE_DEVICE_TABLE(of, ux500_hash_match);
 
-static struct platform_driver hash_driver = {
+static struct platform_driver ux500_hash_driver = {
 	.probe  = ux500_hash_probe,
 	.remove = ux500_hash_remove,
 	.shutdown = ux500_hash_shutdown,
@@ -1934,29 +1796,7 @@ static struct platform_driver hash_driver = {
 		.pm    = &ux500_hash_pm,
 	}
 };
-
-/**
- * ux500_hash_mod_init - The kernel module init function.
- */
-static int __init ux500_hash_mod_init(void)
-{
-	klist_init(&driver_data.device_list, NULL, NULL);
-	/* Initialize the semaphore to 0 devices (locked state) */
-	sema_init(&driver_data.device_allocation, 0);
-
-	return platform_driver_register(&hash_driver);
-}
-
-/**
- * ux500_hash_mod_fini - The kernel module exit function.
- */
-static void __exit ux500_hash_mod_fini(void)
-{
-	platform_driver_unregister(&hash_driver);
-}
-
-module_init(ux500_hash_mod_init);
-module_exit(ux500_hash_mod_fini);
+module_platform_driver(ux500_hash_driver);
 
 MODULE_DESCRIPTION("Driver for ST-Ericsson UX500 HASH engine.");
 MODULE_LICENSE("GPL");
-- 
2.37.2

[PATCH v3 03/16] crypto: ux500/hash: Pass context to zero message digest

[Linus Walleij]

This function obtains the current context from the device state
pointer, which is fragile. Pass the context explicitly instead.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_core.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 5c2da6d42121..aa6bbae107cd 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -183,11 +183,10 @@ static int hash_dma_write(struct hash_ctx *ctx,
  * @zero_digest:	True if zero_digest returned.
  */
 static int get_empty_message_digest(
-		struct hash_device_data *device_data,
+		struct hash_device_data *device_data, struct hash_ctx *ctx,
 		u8 *zero_hash, u32 *zero_hash_size, bool *zero_digest)
 {
 	int ret = 0;
-	struct hash_ctx *ctx = device_data->current_ctx;
 	*zero_digest = false;
 
 	/**
@@ -889,7 +888,7 @@ static int hash_hw_final(struct ahash_request *req)
 		 * Use a pre-calculated empty message digest
 		 * (workaround since hw return zeroes, hw bug!?)
 		 */
-		ret = get_empty_message_digest(device_data, &zero_hash[0],
+		ret = get_empty_message_digest(device_data, ctx, &zero_hash[0],
 				&zero_hash_size, &zero_digest);
 		if (!ret && likely(zero_hash_size == ctx->digestsize) &&
 		    zero_digest) {
-- 
2.37.2

[PATCH v3 04/16] crypto: ux500/hash: Drop custom state save/restore

[Linus Walleij]

Drop the code that is saving and restoring the device state
as part of the PM operations: this is the job of .import and
.export, do not try to work around the framework.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_core.c | 52 +++++----------------------
 1 file changed, 8 insertions(+), 44 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index aa6bbae107cd..fbd6335f142b 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -243,13 +243,11 @@ static int get_empty_message_digest(
 /**
  * hash_disable_power - Request to disable power and clock.
  * @device_data:	Structure for the hash device.
- * @save_device_state:	If true, saves the current hw state.
  *
  * This function request for disabling power (regulator) and clock,
  * and could also save current hw state.
  */
-static int hash_disable_power(struct hash_device_data *device_data,
-			      bool save_device_state)
+static int hash_disable_power(struct hash_device_data *device_data)
 {
 	int ret = 0;
 	struct device *dev = device_data->dev;
@@ -258,12 +256,6 @@ static int hash_disable_power(struct hash_device_data *device_data,
 	if (!device_data->power_state)
 		goto out;
 
-	if (save_device_state) {
-		hash_save_state(device_data,
-				&device_data->state);
-		device_data->restore_dev_state = true;
-	}
-
 	clk_disable(device_data->clk);
 	ret = regulator_disable(device_data->regulator);
 	if (ret)
@@ -280,13 +272,11 @@ static int hash_disable_power(struct hash_device_data *device_data,
 /**
  * hash_enable_power - Request to enable power and clock.
  * @device_data:		Structure for the hash device.
- * @restore_device_state:	If true, restores a previous saved hw state.
  *
  * This function request for enabling power (regulator) and clock,
  * and could also restore a previously saved hw state.
  */
-static int hash_enable_power(struct hash_device_data *device_data,
-			     bool restore_device_state)
+static int hash_enable_power(struct hash_device_data *device_data)
 {
 	int ret = 0;
 	struct device *dev = device_data->dev;
@@ -309,12 +299,6 @@ static int hash_enable_power(struct hash_device_data *device_data,
 		device_data->power_state = true;
 	}
 
-	if (device_data->restore_dev_state) {
-		if (restore_device_state) {
-			device_data->restore_dev_state = false;
-			hash_resume_state(device_data, &device_data->state);
-		}
-	}
 out:
 	spin_unlock(&device_data->power_state_lock);
 
@@ -1597,7 +1581,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	}
 
 	/* Enable device power (and clock) */
-	ret = hash_enable_power(device_data, false);
+	ret = hash_enable_power(device_data);
 	if (ret) {
 		dev_err(dev, "%s: hash_enable_power() failed!\n", __func__);
 		goto out_clk_unprepare;
@@ -1625,7 +1609,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	return 0;
 
 out_power:
-	hash_disable_power(device_data, false);
+	hash_disable_power(device_data);
 
 out_clk_unprepare:
 	clk_unprepare(device_data->clk);
@@ -1666,7 +1650,7 @@ static int ux500_hash_remove(struct platform_device *pdev)
 
 	ahash_algs_unregister_all(device_data);
 
-	if (hash_disable_power(device_data, false))
+	if (hash_disable_power(device_data))
 		dev_err(dev, "%s: hash_disable_power() failed\n",
 			__func__);
 
@@ -1706,7 +1690,7 @@ static void ux500_hash_shutdown(struct platform_device *pdev)
 
 	ahash_algs_unregister_all(device_data);
 
-	if (hash_disable_power(device_data, false))
+	if (hash_disable_power(device_data))
 		dev_err(&pdev->dev, "%s: hash_disable_power() failed\n",
 			__func__);
 }
@@ -1720,7 +1704,6 @@ static int ux500_hash_suspend(struct device *dev)
 {
 	int ret;
 	struct hash_device_data *device_data;
-	struct hash_ctx *temp_ctx = NULL;
 
 	device_data = dev_get_drvdata(dev);
 	if (!device_data) {
@@ -1728,18 +1711,7 @@ static int ux500_hash_suspend(struct device *dev)
 		return -ENOMEM;
 	}
 
-	spin_lock(&device_data->ctx_lock);
-	if (!device_data->current_ctx)
-		device_data->current_ctx++;
-	spin_unlock(&device_data->ctx_lock);
-
-	if (device_data->current_ctx == ++temp_ctx) {
-		ret = hash_disable_power(device_data, false);
-
-	} else {
-		ret = hash_disable_power(device_data, true);
-	}
-
+	ret = hash_disable_power(device_data);
 	if (ret)
 		dev_err(dev, "%s: hash_disable_power()\n", __func__);
 
@@ -1754,7 +1726,6 @@ static int ux500_hash_resume(struct device *dev)
 {
 	int ret = 0;
 	struct hash_device_data *device_data;
-	struct hash_ctx *temp_ctx = NULL;
 
 	device_data = dev_get_drvdata(dev);
 	if (!device_data) {
@@ -1762,14 +1733,7 @@ static int ux500_hash_resume(struct device *dev)
 		return -ENOMEM;
 	}
 
-	spin_lock(&device_data->ctx_lock);
-	if (device_data->current_ctx == ++temp_ctx)
-		device_data->current_ctx = NULL;
-	spin_unlock(&device_data->ctx_lock);
-
-	if (device_data->current_ctx)
-		ret = hash_enable_power(device_data, true);
-
+	ret = hash_enable_power(device_data);
 	if (ret)
 		dev_err(dev, "%s: hash_enable_power() failed!\n", __func__);
 
-- 
2.37.2

[PATCH v3 05/16] crypto: ux500/hash: Drop bit index

[Linus Walleij]

This is some leftover code because the field is only referenced
in a debug print and never assigned.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  | 4 ----
 drivers/crypto/ux500/hash/hash_core.c | 4 ++--
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 26e8b7949d7c..00730c0090ae 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -217,7 +217,6 @@ struct hash_register {
  * @buffer:	Working buffer for messages going to the hardware.
  * @length:	Length of the part of message hashed so far (floor(N/64) * 64).
  * @index:	Valid number of bytes in buffer (N % 64).
- * @bit_index:	Valid number of bits in buffer (N % 8).
  *
  * This structure is used between context switches, i.e. when ongoing jobs are
  * interupted with new jobs. When this happens we need to store intermediate
@@ -237,7 +236,6 @@ struct hash_state {
 	u32		buffer[HASH_BLOCK_SIZE / sizeof(u32)];
 	struct uint64	length;
 	u8		index;
-	u8		bit_index;
 };
 
 /**
@@ -358,7 +356,6 @@ struct hash_req_ctx {
  * @power_state_lock:	Spinlock for power_state.
  * @regulator:		Pointer to the device's power control.
  * @clk:		Pointer to the device's clock control.
- * @restore_dev_state:	TRUE = saved state, FALSE = no saved state.
  * @dma:		Structure used for dma.
  */
 struct hash_device_data {
@@ -372,7 +369,6 @@ struct hash_device_data {
 	spinlock_t		power_state_lock;
 	struct regulator	*regulator;
 	struct clk		*clk;
-	bool			restore_dev_state;
 	struct hash_state	state; /* Used for saving and resuming state */
 	struct hash_dma		dma;
 };
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index fbd6335f142b..65d328d438d2 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -991,8 +991,8 @@ int hash_hw_update(struct ahash_request *req)
 	}
 
 	req_ctx->state.index = index;
-	dev_dbg(device_data->dev, "%s: indata length=%d, bin=%d\n",
-		__func__, req_ctx->state.index, req_ctx->state.bit_index);
+	dev_dbg(device_data->dev, "%s: indata length=%d\n",
+		__func__, req_ctx->state.index);
 
 	return 0;
 }
-- 
2.37.2

[PATCH v3 06/16] crypto: ux500/hash: Break while/do instead of if/else

[Linus Walleij]

Instead of a deeply nested if/else inside the while/do loop,
just break the loop as we know the termination requirement
was just established (msg_length == 0).

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_core.c | 115 +++++++++++++-------------
 1 file changed, 58 insertions(+), 57 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 65d328d438d2..b559c53dc703 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -671,69 +671,70 @@ static int hash_process_data(struct hash_device_data *device_data,
 			}
 			*index += msg_length;
 			msg_length = 0;
-		} else {
-			if (req_ctx->updated) {
-				ret = hash_resume_state(device_data,
-						&device_data->state);
-				memmove(req_ctx->state.buffer,
-					device_data->state.buffer,
-					HASH_BLOCK_SIZE);
-				if (ret) {
-					dev_err(device_data->dev,
-						"%s: hash_resume_state() failed!\n",
-						__func__);
-					goto out;
-				}
-			} else {
-				ret = init_hash_hw(device_data, ctx);
-				if (ret) {
-					dev_err(device_data->dev,
-						"%s: init_hash_hw() failed!\n",
-						__func__);
-					goto out;
-				}
-				req_ctx->updated = 1;
-			}
-			/*
-			 * If 'data_buffer' is four byte aligned and
-			 * local buffer does not have any data, we can
-			 * write data directly from 'data_buffer' to
-			 * HW peripheral, otherwise we first copy data
-			 * to a local buffer
-			 */
-			if (IS_ALIGNED((unsigned long)data_buffer, 4) &&
-			    (0 == *index))
-				hash_processblock(device_data,
-						  (const u32 *)data_buffer,
-						  HASH_BLOCK_SIZE);
-			else {
-				for (count = 0;
-				     count < (u32)(HASH_BLOCK_SIZE - *index);
-				     count++) {
-					buffer[*index + count] =
-						*(data_buffer + count);
-				}
-				hash_processblock(device_data,
-						  (const u32 *)buffer,
-						  HASH_BLOCK_SIZE);
-			}
-			hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
-			data_buffer += (HASH_BLOCK_SIZE - *index);
-
-			msg_length -= (HASH_BLOCK_SIZE - *index);
-			*index = 0;
-
-			ret = hash_save_state(device_data,
-					&device_data->state);
+			break;
+		}
 
-			memmove(device_data->state.buffer,
-				req_ctx->state.buffer,
+		if (req_ctx->updated) {
+			ret = hash_resume_state(device_data,
+						&device_data->state);
+			memmove(req_ctx->state.buffer,
+				device_data->state.buffer,
 				HASH_BLOCK_SIZE);
 			if (ret) {
-				dev_err(device_data->dev, "%s: hash_save_state() failed!\n",
+				dev_err(device_data->dev,
+					"%s: hash_resume_state() failed!\n",
 					__func__);
 				goto out;
 			}
+		} else {
+			ret = init_hash_hw(device_data, ctx);
+			if (ret) {
+				dev_err(device_data->dev,
+					"%s: init_hash_hw() failed!\n",
+					__func__);
+				goto out;
+			}
+			req_ctx->updated = 1;
+		}
+		/*
+		 * If 'data_buffer' is four byte aligned and
+		 * local buffer does not have any data, we can
+		 * write data directly from 'data_buffer' to
+		 * HW peripheral, otherwise we first copy data
+		 * to a local buffer
+		 */
+		if (IS_ALIGNED((unsigned long)data_buffer, 4) &&
+		    (*index == 0))
+			hash_processblock(device_data,
+					  (const u32 *)data_buffer,
+					  HASH_BLOCK_SIZE);
+		else {
+			for (count = 0;
+			     count < (u32)(HASH_BLOCK_SIZE - *index);
+			     count++) {
+				buffer[*index + count] =
+					*(data_buffer + count);
+			}
+			hash_processblock(device_data,
+					  (const u32 *)buffer,
+					  HASH_BLOCK_SIZE);
+		}
+		hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
+		data_buffer += (HASH_BLOCK_SIZE - *index);
+
+		msg_length -= (HASH_BLOCK_SIZE - *index);
+		*index = 0;
+
+		ret = hash_save_state(device_data,
+				      &device_data->state);
+
+		memmove(device_data->state.buffer,
+			req_ctx->state.buffer,
+			HASH_BLOCK_SIZE);
+		if (ret) {
+			dev_err(device_data->dev, "%s: hash_save_state() failed!\n",
+				__func__);
+			goto out;
 		}
 	} while (msg_length != 0);
 out:
-- 
2.37.2

[PATCH v3 07/16] crypto: ux500/hash: Rename and switch type of member

[Linus Walleij]

The "updated" member of the context is very confusing, it
actually means "hw_intialized" so rename it to this and
switch it to a bool so it is clear how this is used.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  |  4 ++--
 drivers/crypto/ux500/hash/hash_core.c | 14 +++++++-------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 00730c0090ae..d124fd17519f 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -336,12 +336,12 @@ struct hash_ctx {
  * @state:	The state of the current calculations.
  * @dma_mode:	Used in special cases (workaround), e.g. need to change to
  *		cpu mode, if not supported/working in dma mode.
- * @updated:	Indicates if hardware is initialized for new operations.
+ * @hw_initialized: Indicates if hardware is initialized for new operations.
  */
 struct hash_req_ctx {
 	struct hash_state	state;
 	bool			dma_mode;
-	u8			updated;
+	bool			hw_initialized;
 };
 
 /**
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index b559c53dc703..c5cd9a5f7e5c 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -449,7 +449,7 @@ static int ux500_hash_init(struct ahash_request *req)
 		ctx->keylen = 0;
 
 	memset(&req_ctx->state, 0, sizeof(struct hash_state));
-	req_ctx->updated = 0;
+	req_ctx->hw_initialized = false;
 	if (hash_mode == HASH_MODE_DMA) {
 		if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
 			req_ctx->dma_mode = false; /* Don't use DMA */
@@ -674,7 +674,7 @@ static int hash_process_data(struct hash_device_data *device_data,
 			break;
 		}
 
-		if (req_ctx->updated) {
+		if (req_ctx->hw_initialized) {
 			ret = hash_resume_state(device_data,
 						&device_data->state);
 			memmove(req_ctx->state.buffer,
@@ -694,7 +694,7 @@ static int hash_process_data(struct hash_device_data *device_data,
 					__func__);
 				goto out;
 			}
-			req_ctx->updated = 1;
+			req_ctx->hw_initialized = true;
 		}
 		/*
 		 * If 'data_buffer' is four byte aligned and
@@ -759,7 +759,7 @@ static int hash_dma_final(struct ahash_request *req)
 	dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 		(unsigned long)ctx);
 
-	if (req_ctx->updated) {
+	if (req_ctx->hw_initialized) {
 		ret = hash_resume_state(device_data, &device_data->state);
 
 		if (ret) {
@@ -794,7 +794,7 @@ static int hash_dma_final(struct ahash_request *req)
 
 		/* Number of bits in last word = (nbytes * 8) % 32 */
 		HASH_SET_NBLW((req->nbytes * 8) % 32);
-		req_ctx->updated = 1;
+		req_ctx->hw_initialized = true;
 	}
 
 	/* Store the nents in the dma struct. */
@@ -857,7 +857,7 @@ static int hash_hw_final(struct ahash_request *req)
 	dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 		(unsigned long)ctx);
 
-	if (req_ctx->updated) {
+	if (req_ctx->hw_initialized) {
 		ret = hash_resume_state(device_data, &device_data->state);
 
 		if (ret) {
@@ -899,7 +899,7 @@ static int hash_hw_final(struct ahash_request *req)
 		goto out;
 	}
 
-	if (!req_ctx->updated) {
+	if (!req_ctx->hw_initialized) {
 		ret = init_hash_hw(device_data, ctx);
 		if (ret) {
 			dev_err(device_data->dev,
-- 
2.37.2

[PATCH v3 08/16] crypto: ux500/hash: Stop saving/restoring compulsively

[Linus Walleij]

The driver is saving/restoring state very intensively, because
of assumptions that suspend/resume can be called at any time.
(Android behaviours.) We removed the state save/restore from
the PM hooks and will use runtime PM for this instead so get
rid of this.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  |  1 -
 drivers/crypto/ux500/hash/hash_core.c | 44 +++------------------------
 2 files changed, 4 insertions(+), 41 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index d124fd17519f..d9d59dba6e6e 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -369,7 +369,6 @@ struct hash_device_data {
 	spinlock_t		power_state_lock;
 	struct regulator	*regulator;
 	struct clk		*clk;
-	struct hash_state	state; /* Used for saving and resuming state */
 	struct hash_dma		dma;
 };
 
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index c5cd9a5f7e5c..844ef70301d5 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -674,19 +674,7 @@ static int hash_process_data(struct hash_device_data *device_data,
 			break;
 		}
 
-		if (req_ctx->hw_initialized) {
-			ret = hash_resume_state(device_data,
-						&device_data->state);
-			memmove(req_ctx->state.buffer,
-				device_data->state.buffer,
-				HASH_BLOCK_SIZE);
-			if (ret) {
-				dev_err(device_data->dev,
-					"%s: hash_resume_state() failed!\n",
-					__func__);
-				goto out;
-			}
-		} else {
+		if (!req_ctx->hw_initialized) {
 			ret = init_hash_hw(device_data, ctx);
 			if (ret) {
 				dev_err(device_data->dev,
@@ -725,17 +713,6 @@ static int hash_process_data(struct hash_device_data *device_data,
 		msg_length -= (HASH_BLOCK_SIZE - *index);
 		*index = 0;
 
-		ret = hash_save_state(device_data,
-				      &device_data->state);
-
-		memmove(device_data->state.buffer,
-			req_ctx->state.buffer,
-			HASH_BLOCK_SIZE);
-		if (ret) {
-			dev_err(device_data->dev, "%s: hash_save_state() failed!\n",
-				__func__);
-			goto out;
-		}
 	} while (msg_length != 0);
 out:
 
@@ -759,15 +736,7 @@ static int hash_dma_final(struct ahash_request *req)
 	dev_dbg(device_data->dev, "%s: (ctx=0x%lx)!\n", __func__,
 		(unsigned long)ctx);
 
-	if (req_ctx->hw_initialized) {
-		ret = hash_resume_state(device_data, &device_data->state);
-
-		if (ret) {
-			dev_err(device_data->dev, "%s: hash_resume_state() failed!\n",
-				__func__);
-			goto out;
-		}
-	} else {
+	if (!req_ctx->hw_initialized) {
 		ret = hash_setconfiguration(device_data, ctx);
 		if (ret) {
 			dev_err(device_data->dev,
@@ -858,13 +827,8 @@ static int hash_hw_final(struct ahash_request *req)
 		(unsigned long)ctx);
 
 	if (req_ctx->hw_initialized) {
-		ret = hash_resume_state(device_data, &device_data->state);
-
-		if (ret) {
-			dev_err(device_data->dev,
-				"%s: hash_resume_state() failed!\n", __func__);
-			goto out;
-		}
+		/* That's fine, result is in HW */
+		dev_dbg(device_data->dev, "%s hw initialized\n", __func__);
 	} else if (req->nbytes == 0 && ctx->keylen == 0) {
 		u8 zero_hash[SHA256_DIGEST_SIZE];
 		u32 zero_hash_size = 0;
-- 
2.37.2

[PATCH v3 09/16] crypto: ux500/hash: Get rid of state from request context

[Linus Walleij]

The request context is exactly for that: context state related
to the request. The code was (ab)using the state used to store
the hardware state for this. Move out the three variables from
the hardware state to the request context and clean up the
mess left behind.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  | 21 +++++++--------
 drivers/crypto/ux500/hash/hash_core.c | 38 +++++++++++----------------
 2 files changed, 26 insertions(+), 33 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index d9d59dba6e6e..5aa86c4855f5 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -214,17 +214,10 @@ struct hash_register {
  * @csr[52]:	HASH Context Swap Registers 0-39.
  * @csfull:	HASH Context Swap Registers 40 ie Status flags.
  * @csdatain:	HASH Context Swap Registers 41 ie Input data.
- * @buffer:	Working buffer for messages going to the hardware.
- * @length:	Length of the part of message hashed so far (floor(N/64) * 64).
- * @index:	Valid number of bytes in buffer (N % 64).
  *
  * This structure is used between context switches, i.e. when ongoing jobs are
  * interupted with new jobs. When this happens we need to store intermediate
  * results in software.
- *
- * WARNING: "index" is the  member of the structure, to be sure  that "buffer"
- * is aligned on a 4-bytes boundary. This is highly implementation dependent
- * and MUST be checked whenever this code is ported on new platforms.
  */
 struct hash_state {
 	u32		temp_cr;
@@ -233,9 +226,6 @@ struct hash_state {
 	u32		csr[52];
 	u32		csfull;
 	u32		csdatain;
-	u32		buffer[HASH_BLOCK_SIZE / sizeof(u32)];
-	struct uint64	length;
-	u8		index;
 };
 
 /**
@@ -333,13 +323,22 @@ struct hash_ctx {
 
 /**
  * struct hash_ctx - The request context used for hash calculations.
+ * @buffer:	Working buffer for messages going to the hardware.
+ * @length:	Length of the part of message hashed so far (floor(N/64) * 64).
+ * @index:	Valid number of bytes in buffer (N % 64).
  * @state:	The state of the current calculations.
  * @dma_mode:	Used in special cases (workaround), e.g. need to change to
  *		cpu mode, if not supported/working in dma mode.
  * @hw_initialized: Indicates if hardware is initialized for new operations.
+ *
+ * WARNING: "index" is the  member of the structure, to be sure  that "buffer"
+ * is aligned on a 4-bytes boundary. This is highly implementation dependent
+ * and MUST be checked whenever this code is ported on new platforms.
  */
 struct hash_req_ctx {
-	struct hash_state	state;
+	u32			buffer[HASH_BLOCK_SIZE / sizeof(u32)];
+	struct uint64		length;
+	u8			index;
 	bool			dma_mode;
 	bool			hw_initialized;
 };
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 844ef70301d5..c55f35b366be 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -448,7 +448,9 @@ static int ux500_hash_init(struct ahash_request *req)
 	if (!ctx->key)
 		ctx->keylen = 0;
 
-	memset(&req_ctx->state, 0, sizeof(struct hash_state));
+	req_ctx->index = 0;
+	req_ctx->length.low_word = 0;
+	req_ctx->length.high_word = 0;
 	req_ctx->hw_initialized = false;
 	if (hash_mode == HASH_MODE_DMA) {
 		if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
@@ -553,11 +555,11 @@ static void hash_messagepad(struct hash_device_data *device_data,
  */
 static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
 {
-	ctx->state.length.low_word += incr;
+	ctx->length.low_word += incr;
 
 	/* Check for wrap-around */
-	if (ctx->state.length.low_word < incr)
-		ctx->state.length.high_word++;
+	if (ctx->length.low_word < incr)
+		ctx->length.high_word++;
 }
 
 /**
@@ -872,9 +874,9 @@ static int hash_hw_final(struct ahash_request *req)
 		}
 	}
 
-	if (req_ctx->state.index) {
-		hash_messagepad(device_data, req_ctx->state.buffer,
-				req_ctx->state.index);
+	if (req_ctx->index) {
+		hash_messagepad(device_data, req_ctx->buffer,
+				req_ctx->index);
 	} else {
 		HASH_SET_DCAL;
 		while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
@@ -922,8 +924,8 @@ int hash_hw_update(struct ahash_request *req)
 	struct crypto_hash_walk walk;
 	int msg_length;
 
-	index = req_ctx->state.index;
-	buffer = (u8 *)req_ctx->state.buffer;
+	index = req_ctx->index;
+	buffer = (u8 *)req_ctx->buffer;
 
 	msg_length = crypto_hash_walk_first(req, &walk);
 
@@ -931,10 +933,10 @@ int hash_hw_update(struct ahash_request *req)
 	if (msg_length == 0)
 		return 0;
 
-	/* Check if ctx->state.length + msg_length
+	/* Check if ctx->length + msg_length
 	   overflows */
-	if (msg_length > (req_ctx->state.length.low_word + msg_length) &&
-	    HASH_HIGH_WORD_MAX_VAL == req_ctx->state.length.high_word) {
+	if (msg_length > (req_ctx->length.low_word + msg_length) &&
+	    req_ctx->length.high_word == HASH_HIGH_WORD_VAL_MAX) {
 		pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__);
 		return crypto_hash_walk_done(&walk, -EPERM);
 	}
@@ -955,9 +957,9 @@ int hash_hw_update(struct ahash_request *req)
 		msg_length = crypto_hash_walk_done(&walk, 0);
 	}
 
-	req_ctx->state.index = index;
+	req_ctx->index = index;
 	dev_dbg(device_data->dev, "%s: indata length=%d\n",
-		__func__, req_ctx->state.index);
+		__func__, req_ctx->index);
 
 	return 0;
 }
@@ -980,14 +982,6 @@ int hash_resume_state(struct hash_device_data *device_data,
 		return -EPERM;
 	}
 
-	/* Check correctness of index and length members */
-	if (device_state->index > HASH_BLOCK_SIZE ||
-	    (device_state->length.low_word % HASH_BLOCK_SIZE) != 0) {
-		dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
-			__func__);
-		return -EPERM;
-	}
-
 	/*
 	 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
 	 * prepare the initialize the HASH accelerator to compute the message
-- 
2.37.2

[PATCH v3 10/16] crypto: ux500/hash: Implement .export and .import

[Linus Walleij]

The .export and .import callbacks are just implemented as stubs
which makes the tests fail:

 alg: ahash: hmac-sha256-ux500 export() failed with err -38 on
   test vector 0, cfg="import/export"
 ------------[ cut here ]------------
 WARNING: CPU: 1 PID: 92 at crypto/testmgr.c:5777
   alg_test.part.0+0x160/0x3ec
 alg: self-tests for hmac-sha256-ux500 (hmac(sha256)) failed (rc=-38)

The driver already has code for saving and restoring the hardware
state, which is now unused. Pass the tests by simply implementing the
callbacks properly, extending the state with the length, index
and buffer from the ongoing request context.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  |   5 +
 drivers/crypto/ux500/hash/hash_core.c | 227 +++++++++++++-------------
 2 files changed, 114 insertions(+), 118 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 5aa86c4855f5..05f0b0221a13 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -226,6 +226,11 @@ struct hash_state {
 	u32		csr[52];
 	u32		csfull;
 	u32		csdatain;
+	u32		buffer[HASH_BLOCK_SIZE / sizeof(u32)];
+	struct uint64	length;
+	u8		index;
+	bool		dma_mode;
+	bool		hw_initialized;
 };
 
 /**
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index c55f35b366be..c8771839ec8e 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -964,108 +964,6 @@ int hash_hw_update(struct ahash_request *req)
 	return 0;
 }
 
-/**
- * hash_resume_state - Function that resumes the state of an calculation.
- * @device_data:	Pointer to the device structure.
- * @device_state:	The state to be restored in the hash hardware
- */
-int hash_resume_state(struct hash_device_data *device_data,
-		      const struct hash_state *device_state)
-{
-	u32 temp_cr;
-	s32 count;
-	int hash_mode = HASH_OPER_MODE_HASH;
-
-	if (NULL == device_state) {
-		dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
-			__func__);
-		return -EPERM;
-	}
-
-	/*
-	 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
-	 * prepare the initialize the HASH accelerator to compute the message
-	 * digest of a new message.
-	 */
-	HASH_INITIALIZE;
-
-	temp_cr = device_state->temp_cr;
-	writel_relaxed(temp_cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
-
-	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
-		hash_mode = HASH_OPER_MODE_HMAC;
-	else
-		hash_mode = HASH_OPER_MODE_HASH;
-
-	for (count = 0; count < HASH_CSR_COUNT; count++) {
-		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
-			break;
-
-		writel_relaxed(device_state->csr[count],
-			       &device_data->base->csrx[count]);
-	}
-
-	writel_relaxed(device_state->csfull, &device_data->base->csfull);
-	writel_relaxed(device_state->csdatain, &device_data->base->csdatain);
-
-	writel_relaxed(device_state->str_reg, &device_data->base->str);
-	writel_relaxed(temp_cr, &device_data->base->cr);
-
-	return 0;
-}
-
-/**
- * hash_save_state - Function that saves the state of hardware.
- * @device_data:	Pointer to the device structure.
- * @device_state:	The strucure where the hardware state should be saved.
- */
-int hash_save_state(struct hash_device_data *device_data,
-		    struct hash_state *device_state)
-{
-	u32 temp_cr;
-	u32 count;
-	int hash_mode = HASH_OPER_MODE_HASH;
-
-	if (NULL == device_state) {
-		dev_err(device_data->dev, "%s: HASH_INVALID_PARAMETER!\n",
-			__func__);
-		return -ENOTSUPP;
-	}
-
-	/* Write dummy value to force digest intermediate calculation. This
-	 * actually makes sure that there isn't any ongoing calculation in the
-	 * hardware.
-	 */
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
-
-	temp_cr = readl_relaxed(&device_data->base->cr);
-
-	device_state->str_reg = readl_relaxed(&device_data->base->str);
-
-	device_state->din_reg = readl_relaxed(&device_data->base->din);
-
-	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
-		hash_mode = HASH_OPER_MODE_HMAC;
-	else
-		hash_mode = HASH_OPER_MODE_HASH;
-
-	for (count = 0; count < HASH_CSR_COUNT; count++) {
-		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
-			break;
-
-		device_state->csr[count] =
-			readl_relaxed(&device_data->base->csrx[count]);
-	}
-
-	device_state->csfull = readl_relaxed(&device_data->base->csfull);
-	device_state->csdatain = readl_relaxed(&device_data->base->csdatain);
-
-	device_state->temp_cr = temp_cr;
-
-	return 0;
-}
-
 /**
  * hash_check_hw - This routine checks for peripheral Ids and PCell Ids.
  * @device_data:
@@ -1244,14 +1142,107 @@ static int ahash_sha256_digest(struct ahash_request *req)
 	return ret1 ? ret1 : ret2;
 }
 
-static int ahash_noimport(struct ahash_request *req, const void *in)
+static int ahash_import(struct ahash_request *req, const void *in)
 {
-	return -ENOSYS;
+	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
+	struct hash_device_data *device_data = ctx->device;
+	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
+	const struct hash_state *hstate = in;
+	int hash_mode = HASH_OPER_MODE_HASH;
+	u32 cr;
+	s32 count;
+
+	/* Restore software state */
+	req_ctx->length = hstate->length;
+	req_ctx->index = hstate->index;
+	req_ctx->dma_mode = hstate->dma_mode;
+	req_ctx->hw_initialized = hstate->hw_initialized;
+	memcpy(req_ctx->buffer, hstate->buffer, HASH_BLOCK_SIZE);
+
+	/*
+	 * Restore hardware state
+	 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
+	 * prepare the initialize the HASH accelerator to compute the message
+	 * digest of a new message.
+	 */
+	HASH_INITIALIZE;
+
+	cr = hstate->temp_cr;
+	writel_relaxed(cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
+
+	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
+		hash_mode = HASH_OPER_MODE_HMAC;
+	else
+		hash_mode = HASH_OPER_MODE_HASH;
+
+	for (count = 0; count < HASH_CSR_COUNT; count++) {
+		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
+			break;
+		writel_relaxed(hstate->csr[count],
+			       &device_data->base->csrx[count]);
+	}
+
+	writel_relaxed(hstate->csfull, &device_data->base->csfull);
+	writel_relaxed(hstate->csdatain, &device_data->base->csdatain);
+	writel_relaxed(hstate->str_reg, &device_data->base->str);
+	writel_relaxed(cr, &device_data->base->cr);
+
+	return 0;
 }
 
-static int ahash_noexport(struct ahash_request *req, void *out)
+static int ahash_export(struct ahash_request *req, void *out)
 {
-	return -ENOSYS;
+	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
+	struct hash_device_data *device_data = ctx->device;
+	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
+	struct hash_state *hstate = out;
+	int hash_mode = HASH_OPER_MODE_HASH;
+	u32 cr;
+	u32 count;
+
+	/*
+	 * Save hardware state:
+	 * Write dummy value to force digest intermediate calculation. This
+	 * actually makes sure that there isn't any ongoing calculation in the
+	 * hardware.
+	 */
+	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
+		cpu_relax();
+
+	cr = readl_relaxed(&device_data->base->cr);
+
+	hstate->str_reg = readl_relaxed(&device_data->base->str);
+
+	hstate->din_reg = readl_relaxed(&device_data->base->din);
+
+	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
+		hash_mode = HASH_OPER_MODE_HMAC;
+	else
+		hash_mode = HASH_OPER_MODE_HASH;
+
+	for (count = 0; count < HASH_CSR_COUNT; count++) {
+		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
+			break;
+
+		hstate->csr[count] =
+			readl_relaxed(&device_data->base->csrx[count]);
+	}
+
+	hstate->csfull = readl_relaxed(&device_data->base->csfull);
+	hstate->csdatain = readl_relaxed(&device_data->base->csdatain);
+
+	hstate->temp_cr = cr;
+
+	/* Save software state */
+	hstate->length = req_ctx->length;
+	hstate->index = req_ctx->index;
+	hstate->dma_mode = req_ctx->dma_mode;
+	hstate->hw_initialized = req_ctx->hw_initialized;
+	memcpy(hstate->buffer, req_ctx->buffer, HASH_BLOCK_SIZE);
+
+	return 0;
 }
 
 static int hmac_sha1_init(struct ahash_request *req)
@@ -1361,10 +1352,10 @@ static struct hash_algo_template hash_algs[] = {
 			.update = ahash_update,
 			.final = ahash_final,
 			.digest = ahash_sha1_digest,
-			.export = ahash_noexport,
-			.import = ahash_noimport,
+			.export = ahash_export,
+			.import = ahash_import,
 			.halg.digestsize = SHA1_DIGEST_SIZE,
-			.halg.statesize = sizeof(struct hash_ctx),
+			.halg.statesize = sizeof(struct hash_state),
 			.halg.base = {
 				.cra_name = "sha1",
 				.cra_driver_name = "sha1-ux500",
@@ -1384,10 +1375,10 @@ static struct hash_algo_template hash_algs[] = {
 			.update	= ahash_update,
 			.final = ahash_final,
 			.digest = ahash_sha256_digest,
-			.export = ahash_noexport,
-			.import = ahash_noimport,
+			.export = ahash_export,
+			.import = ahash_import,
 			.halg.digestsize = SHA256_DIGEST_SIZE,
-			.halg.statesize = sizeof(struct hash_ctx),
+			.halg.statesize = sizeof(struct hash_state),
 			.halg.base = {
 				.cra_name = "sha256",
 				.cra_driver_name = "sha256-ux500",
@@ -1408,10 +1399,10 @@ static struct hash_algo_template hash_algs[] = {
 			.final = ahash_final,
 			.digest = hmac_sha1_digest,
 			.setkey = hmac_sha1_setkey,
-			.export = ahash_noexport,
-			.import = ahash_noimport,
+			.export = ahash_export,
+			.import = ahash_import,
 			.halg.digestsize = SHA1_DIGEST_SIZE,
-			.halg.statesize = sizeof(struct hash_ctx),
+			.halg.statesize = sizeof(struct hash_state),
 			.halg.base = {
 				.cra_name = "hmac(sha1)",
 				.cra_driver_name = "hmac-sha1-ux500",
@@ -1432,10 +1423,10 @@ static struct hash_algo_template hash_algs[] = {
 			.final = ahash_final,
 			.digest = hmac_sha256_digest,
 			.setkey = hmac_sha256_setkey,
-			.export = ahash_noexport,
-			.import = ahash_noimport,
+			.export = ahash_export,
+			.import = ahash_import,
 			.halg.digestsize = SHA256_DIGEST_SIZE,
-			.halg.statesize = sizeof(struct hash_ctx),
+			.halg.statesize = sizeof(struct hash_state),
 			.halg.base = {
 				.cra_name = "hmac(sha256)",
 				.cra_driver_name = "hmac-sha256-ux500",
-- 
2.37.2

Re: [PATCH v3 10/16] crypto: ux500/hash: Implement .export and .import

[Herbert Xu]

On Tue, Aug 16, 2022 at 04:00:43PM +0200, Linus Walleij wrote:
>
> -static int ahash_noimport(struct ahash_request *req, const void *in)
> +static int ahash_import(struct ahash_request *req, const void *in)
>  {
> -	return -ENOSYS;
> +	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
> +	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
> +	struct hash_device_data *device_data = ctx->device;
> +	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
> +	const struct hash_state *hstate = in;
> +	int hash_mode = HASH_OPER_MODE_HASH;
> +	u32 cr;
> +	s32 count;
> +
> +	/* Restore software state */
> +	req_ctx->length = hstate->length;
> +	req_ctx->index = hstate->index;
> +	req_ctx->dma_mode = hstate->dma_mode;
> +	req_ctx->hw_initialized = hstate->hw_initialized;
> +	memcpy(req_ctx->buffer, hstate->buffer, HASH_BLOCK_SIZE);
> +
> +	/*
> +	 * Restore hardware state
> +	 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
> +	 * prepare the initialize the HASH accelerator to compute the message
> +	 * digest of a new message.
> +	 */
> +	HASH_INITIALIZE;
> +
> +	cr = hstate->temp_cr;
> +	writel_relaxed(cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
> +
> +	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
> +		hash_mode = HASH_OPER_MODE_HMAC;
> +	else
> +		hash_mode = HASH_OPER_MODE_HASH;
> +
> +	for (count = 0; count < HASH_CSR_COUNT; count++) {
> +		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
> +			break;
> +		writel_relaxed(hstate->csr[count],
> +			       &device_data->base->csrx[count]);
> +	}
> +
> +	writel_relaxed(hstate->csfull, &device_data->base->csfull);
> +	writel_relaxed(hstate->csdatain, &device_data->base->csdatain);
> +	writel_relaxed(hstate->str_reg, &device_data->base->str);
> +	writel_relaxed(cr, &device_data->base->cr);
> +
> +	return 0;
>  }

At any time we may have multiple requests outstanding for a given
tfm/device, so I'm a bit worried with the direct writes to hardware
in the import function.

Normally import just transfers data from the caller into the
request object as a "soft" state, while the actual update/final
functions will then move them into the hardware state as needed.

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH v3 10/16] crypto: ux500/hash: Implement .export and .import

[Linus Walleij]

On Thu, Aug 25, 2022 at 11:30 AM Herbert Xu <herbert@gondor.apana.org.au> wrote:

> > +     writel_relaxed(hstate->csfull, &device_data->base->csfull);
> > +     writel_relaxed(hstate->csdatain, &device_data->base->csdatain);
> > +     writel_relaxed(hstate->str_reg, &device_data->base->str);
> > +     writel_relaxed(cr, &device_data->base->cr);
> > +
> > +     return 0;
> >  }
>
> At any time we may have multiple requests outstanding for a given
> tfm/device, so I'm a bit worried with the direct writes to hardware
> in the import function.
>
> Normally import just transfers data from the caller into the
> request object as a "soft" state, while the actual update/final
> functions will then move them into the hardware state as needed.

I see the problem.

Do you think we could merge patches 1 thru 9 for this kernel
cycle though to lower my patch stack? I can resend just those
if you like.

Yours,
Linus Walleij

Re: [PATCH v3 10/16] crypto: ux500/hash: Implement .export and .import

[Herbert Xu]

On Tue, Sep 13, 2022 at 09:14:55PM +0200, Linus Walleij wrote:
>
> I see the problem.
> 
> Do you think we could merge patches 1 thru 9 for this kernel
> cycle though to lower my patch stack? I can resend just those
> if you like.

I had a look through 1-9 but quite a few seem like they were part
of the import/export rework.  For example, I think patch 8 would
actually break multiple hash attempts in parallel.

Could you plesae go through them and repost the ones that make
sense on their own?

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

[PATCH v3 11/16] crypto: ux500/hash: Drop custom uint64 type

[Linus Walleij]

Drop the homebrewn uint64 support, the kernel has a u64 type
that works just fine so we use that instead.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- No changes
---
 drivers/crypto/ux500/hash/hash_alg.h  | 19 ++----------------
 drivers/crypto/ux500/hash/hash_core.c | 28 ++++-----------------------
 2 files changed, 6 insertions(+), 41 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 05f0b0221a13..6a610c83e63d 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -16,9 +16,6 @@
 #define HASH_DMA_PERFORMANCE_MIN_SIZE	1024
 #define HASH_BYTES_PER_WORD		4
 
-/* Maximum value of the length's high word */
-#define HASH_HIGH_WORD_MAX_VAL		0xFFFFFFFFUL
-
 /* Power on Reset values HASH registers */
 #define HASH_RESET_CR_VALUE		0x0
 #define HASH_RESET_STR_VALUE		0x0
@@ -135,18 +132,6 @@ enum hash_mode {
 	HASH_MODE_DMA
 };
 
-/**
- * struct uint64 - Structure to handle 64 bits integers.
- * @high_word:	Most significant bits.
- * @low_word:	Least significant bits.
- *
- * Used to handle 64 bits integers.
- */
-struct uint64 {
-	u32 high_word;
-	u32 low_word;
-};
-
 /**
  * struct hash_register - Contains all registers in ux500 hash hardware.
  * @cr:		HASH control register (0x000).
@@ -227,7 +212,7 @@ struct hash_state {
 	u32		csfull;
 	u32		csdatain;
 	u32		buffer[HASH_BLOCK_SIZE / sizeof(u32)];
-	struct uint64	length;
+	u64		length;
 	u8		index;
 	bool		dma_mode;
 	bool		hw_initialized;
@@ -342,7 +327,7 @@ struct hash_ctx {
  */
 struct hash_req_ctx {
 	u32			buffer[HASH_BLOCK_SIZE / sizeof(u32)];
-	struct uint64		length;
+	u64			length;
 	u8			index;
 	bool			dma_mode;
 	bool			hw_initialized;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index c8771839ec8e..5fe0720cb1f5 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -449,8 +449,7 @@ static int ux500_hash_init(struct ahash_request *req)
 		ctx->keylen = 0;
 
 	req_ctx->index = 0;
-	req_ctx->length.low_word = 0;
-	req_ctx->length.high_word = 0;
+	req_ctx->length = 0;
 	req_ctx->hw_initialized = false;
 	if (hash_mode == HASH_MODE_DMA) {
 		if (req->nbytes < HASH_DMA_ALIGN_SIZE) {
@@ -545,23 +544,6 @@ static void hash_messagepad(struct hash_device_data *device_data,
 		cpu_relax();
 }
 
-/**
- * hash_incrementlength - Increments the length of the current message.
- * @ctx: Hash context
- * @incr: Length of message processed already
- *
- * Overflow cannot occur, because conditions for overflow are checked in
- * hash_hw_update.
- */
-static void hash_incrementlength(struct hash_req_ctx *ctx, u32 incr)
-{
-	ctx->length.low_word += incr;
-
-	/* Check for wrap-around */
-	if (ctx->length.low_word < incr)
-		ctx->length.high_word++;
-}
-
 /**
  * hash_setconfiguration - Sets the required configuration for the hash
  *                         hardware.
@@ -709,7 +691,7 @@ static int hash_process_data(struct hash_device_data *device_data,
 					  (const u32 *)buffer,
 					  HASH_BLOCK_SIZE);
 		}
-		hash_incrementlength(req_ctx, HASH_BLOCK_SIZE);
+		req_ctx->length += HASH_BLOCK_SIZE;
 		data_buffer += (HASH_BLOCK_SIZE - *index);
 
 		msg_length -= (HASH_BLOCK_SIZE - *index);
@@ -933,10 +915,8 @@ int hash_hw_update(struct ahash_request *req)
 	if (msg_length == 0)
 		return 0;
 
-	/* Check if ctx->length + msg_length
-	   overflows */
-	if (msg_length > (req_ctx->length.low_word + msg_length) &&
-	    req_ctx->length.high_word == HASH_HIGH_WORD_VAL_MAX) {
+	/* Check if ctx->length + msg_length overflows */
+	if ((req_ctx->length + msg_length) < msg_length) {
 		pr_err("%s: HASH_MSG_LENGTH_OVERFLOW!\n", __func__);
 		return crypto_hash_walk_done(&walk, -EPERM);
 	}
-- 
2.37.2

[PATCH v3 12/16] crypto: ux500/hash: Drop regulator handling

[Linus Walleij]

This "APE" voltage is not handled by a regulator but by the
power domain, drop it.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- New patch after noticing the power domain is handling this
  voltage.
---
 drivers/crypto/ux500/hash/hash_core.c | 38 +++------------------------
 1 file changed, 4 insertions(+), 34 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 5fe0720cb1f5..21657c9c79a7 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -24,8 +24,6 @@
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
 #include <linux/crypto.h>
-
-#include <linux/regulator/consumer.h>
 #include <linux/dmaengine.h>
 #include <linux/bitops.h>
 
@@ -244,22 +242,17 @@ static int get_empty_message_digest(
  * hash_disable_power - Request to disable power and clock.
  * @device_data:	Structure for the hash device.
  *
- * This function request for disabling power (regulator) and clock,
- * and could also save current hw state.
+ * This function request for disabling the clock.
  */
 static int hash_disable_power(struct hash_device_data *device_data)
 {
 	int ret = 0;
-	struct device *dev = device_data->dev;
 
 	spin_lock(&device_data->power_state_lock);
 	if (!device_data->power_state)
 		goto out;
 
 	clk_disable(device_data->clk);
-	ret = regulator_disable(device_data->regulator);
-	if (ret)
-		dev_err(dev, "%s: regulator_disable() failed!\n", __func__);
 
 	device_data->power_state = false;
 
@@ -273,8 +266,7 @@ static int hash_disable_power(struct hash_device_data *device_data)
  * hash_enable_power - Request to enable power and clock.
  * @device_data:		Structure for the hash device.
  *
- * This function request for enabling power (regulator) and clock,
- * and could also restore a previously saved hw state.
+ * This function request for enabling the clock.
  */
 static int hash_enable_power(struct hash_device_data *device_data)
 {
@@ -283,17 +275,9 @@ static int hash_enable_power(struct hash_device_data *device_data)
 
 	spin_lock(&device_data->power_state_lock);
 	if (!device_data->power_state) {
-		ret = regulator_enable(device_data->regulator);
-		if (ret) {
-			dev_err(dev, "%s: regulator_enable() failed!\n",
-				__func__);
-			goto out;
-		}
 		ret = clk_enable(device_data->clk);
 		if (ret) {
 			dev_err(dev, "%s: clk_enable() failed!\n", __func__);
-			ret = regulator_disable(
-					device_data->regulator);
 			goto out;
 		}
 		device_data->power_state = true;
@@ -1487,27 +1471,17 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	spin_lock_init(&device_data->ctx_lock);
 	spin_lock_init(&device_data->power_state_lock);
 
-	/* Enable power for HASH1 hardware block */
-	device_data->regulator = regulator_get(dev, "v-ape");
-	if (IS_ERR(device_data->regulator)) {
-		dev_err(dev, "%s: regulator_get() failed!\n", __func__);
-		ret = PTR_ERR(device_data->regulator);
-		device_data->regulator = NULL;
-		goto out;
-	}
-
-	/* Enable the clock for HASH1 hardware block */
 	device_data->clk = devm_clk_get(dev, NULL);
 	if (IS_ERR(device_data->clk)) {
 		dev_err(dev, "%s: clk_get() failed!\n", __func__);
 		ret = PTR_ERR(device_data->clk);
-		goto out_regulator;
+		goto out;
 	}
 
 	ret = clk_prepare(device_data->clk);
 	if (ret) {
 		dev_err(dev, "%s: clk_prepare() failed!\n", __func__);
-		goto out_regulator;
+		goto out;
 	}
 
 	/* Enable device power (and clock) */
@@ -1544,9 +1518,6 @@ static int ux500_hash_probe(struct platform_device *pdev)
 out_clk_unprepare:
 	clk_unprepare(device_data->clk);
 
-out_regulator:
-	regulator_put(device_data->regulator);
-
 out:
 	return ret;
 }
@@ -1585,7 +1556,6 @@ static int ux500_hash_remove(struct platform_device *pdev)
 			__func__);
 
 	clk_unprepare(device_data->clk);
-	regulator_put(device_data->regulator);
 
 	return 0;
 }
-- 
2.37.2

[PATCH v3 13/16] crypto: ux500/hash: Convert to regmap MMIO

[Linus Walleij]

The driver goes to extents to map a struct over all the registers
and access the registers and macros to access certain fields
and bits in a way equivalent but inferior to the existing Linux
regmap.

The driver predates the introduction of regmap MMIO, so this is
understandable.

Convert the driver to use regmap MMIO instead.

Break out two helper functions to wait for an STR flag and to
fill the data in (DIN) FIFO to avoid repetitive code.

Disable the regcache: this drives sends a LOT of data into a
single register (DIN), which is pointless to cache and only takes
extra execution time. Any other accesses are stray and few.

Checkpatch complains about -ENOTSUPP so use -ENODEV instead.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- Mark PrimeCell ID registers volatile as they have interesting
  power-on defaults.
- Avoid using noinc calls, they don't work with regmap MMIO
  right now. (Working on a solution.)
---
 drivers/crypto/ux500/Kconfig          |   1 +
 drivers/crypto/ux500/hash/hash_alg.h  | 200 +++----------
 drivers/crypto/ux500/hash/hash_core.c | 415 ++++++++++++++++----------
 3 files changed, 302 insertions(+), 314 deletions(-)

diff --git a/drivers/crypto/ux500/Kconfig b/drivers/crypto/ux500/Kconfig
index f56d65c56ccf..5d70f5965d06 100644
--- a/drivers/crypto/ux500/Kconfig
+++ b/drivers/crypto/ux500/Kconfig
@@ -20,6 +20,7 @@ config CRYPTO_DEV_UX500_HASH
 	select CRYPTO_HASH
 	select CRYPTO_SHA1
 	select CRYPTO_SHA256
+	select REGMAP_MMIO
 	help
 	  This selects the hash driver for the UX500_HASH hardware.
 	  Depends on UX500/STM DMA if running in DMA mode.
diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 6a610c83e63d..cc44d3cb21ac 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -8,6 +8,7 @@
 #ifndef _HASH_ALG_H
 #define _HASH_ALG_H
 
+#include <linux/regmap.h>
 #include <linux/bitops.h>
 
 #define HASH_BLOCK_SIZE			64
@@ -16,70 +17,50 @@
 #define HASH_DMA_PERFORMANCE_MIN_SIZE	1024
 #define HASH_BYTES_PER_WORD		4
 
-/* Power on Reset values HASH registers */
-#define HASH_RESET_CR_VALUE		0x0
-#define HASH_RESET_STR_VALUE		0x0
-
 /* Number of context swap registers */
 #define HASH_CSR_COUNT			52
 
-#define HASH_RESET_CSRX_REG_VALUE	0x0
-#define HASH_RESET_CSFULL_REG_VALUE	0x0
-#define HASH_RESET_CSDATAIN_REG_VALUE	0x0
-
-#define HASH_RESET_INDEX_VAL		0x0
-#define HASH_RESET_BIT_INDEX_VAL	0x0
-#define HASH_RESET_BUFFER_VAL		0x0
-#define HASH_RESET_LEN_HIGH_VAL		0x0
-#define HASH_RESET_LEN_LOW_VAL		0x0
+#define UX500_HASH_CR			0x00
+#define UX500_HASH_DIN			0x04
+#define UX500_HASH_STR			0x08
+#define UX500_HASH_H(x)			(0x0C + ((x) * 0x04))
+#define UX500_HASH_ITCR			0x80
+#define UX500_HASH_ITIP			0x84
+#define UX500_HASH_ITOP			0x88
+#define UX500_HASH_CSFULL		0xF8
+#define UX500_HASH_CSDATAIN		0xFC
+#define UX500_HASH_CSR(x)		(0x100 + ((x) * 0x04))
+#define UX500_HASH_PERIPHID0		0xFE0
+#define UX500_HASH_PERIPHID1		0xFE4
+#define UX500_HASH_PERIPHID2		0xFE8
+#define UX500_HASH_PERIPHID3		0xFEC
+#define UX500_HASH_CELLID0		0xFF0
+#define UX500_HASH_CELLID1		0xFF4
+#define UX500_HASH_CELLID2		0xFF8
+#define UX500_HASH_CELLID3		0xFFC
 
 /* Control register bitfields */
 #define HASH_CR_RESUME_MASK	0x11FCF
-
-#define HASH_CR_SWITCHON_POS	31
-#define HASH_CR_SWITCHON_MASK	BIT(31)
-
-#define HASH_CR_EMPTYMSG_POS	20
-#define HASH_CR_EMPTYMSG_MASK	BIT(20)
-
-#define HASH_CR_DINF_POS	12
-#define HASH_CR_DINF_MASK	BIT(12)
-
-#define HASH_CR_NBW_POS		8
+#define HASH_CR_SWITCHON	BIT(31)
+#define HASH_CR_EMPTYMSG	BIT(20)
+#define HASH_CR_DINF		BIT(12)
 #define HASH_CR_NBW_MASK	0x00000F00UL
-
-#define HASH_CR_LKEY_POS	16
-#define HASH_CR_LKEY_MASK	BIT(16)
-
-#define HASH_CR_ALGO_POS	7
-#define HASH_CR_ALGO_MASK	BIT(7)
-
-#define HASH_CR_MODE_POS	6
-#define HASH_CR_MODE_MASK	BIT(6)
-
-#define HASH_CR_DATAFORM_POS	4
+#define HASH_CR_LKEY		BIT(16)
+#define HASH_CR_ALGO		BIT(7)
+#define HASH_CR_MODE		BIT(6)
 #define HASH_CR_DATAFORM_MASK	(BIT(4) | BIT(5))
-
-#define HASH_CR_DMAE_POS	3
-#define HASH_CR_DMAE_MASK	BIT(3)
-
-#define HASH_CR_INIT_POS	2
-#define HASH_CR_INIT_MASK	BIT(2)
-
-#define HASH_CR_PRIVN_POS	1
-#define HASH_CR_PRIVN_MASK	BIT(1)
-
-#define HASH_CR_SECN_POS	0
-#define HASH_CR_SECN_MASK	BIT(0)
+#define HASH_CR_DATAFORM_32BIT	0
+#define HASH_CR_DATAFORM_16BIT	BIT(4)
+#define HASH_CR_DATAFORM_8BIT	BIT(5)
+#define HASH_CR_DATAFORM_1BIT	(BIT(4) | BIT(5))
+#define HASH_CR_DMAE		BIT(3)
+#define HASH_CR_INIT		BIT(2)
+#define HASH_CR_PRIVN		BIT(1)
+#define HASH_CR_SECN		BIT(0)
 
 /* Start register bitfields */
-#define HASH_STR_DCAL_POS	8
-#define HASH_STR_DCAL_MASK	BIT(8)
-#define HASH_STR_DEFAULT	0x0
-
-#define HASH_STR_NBLW_POS	0
+#define HASH_STR_DCAL		BIT(8)
 #define HASH_STR_NBLW_MASK	0x0000001FUL
-
 #define HASH_NBLW_MAX_VAL	0x1F
 
 /* PrimeCell IDs */
@@ -92,105 +73,12 @@
 #define HASH_CELL_ID2		0x05
 #define HASH_CELL_ID3		0xB1
 
-#define HASH_SET_BITS(reg_name, mask)	\
-	writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
-
-#define HASH_CLEAR_BITS(reg_name, mask)	\
-	writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
-
-#define HASH_PUT_BITS(reg, val, shift, mask)	\
-	writel_relaxed(((readl(reg) & ~(mask)) |	\
-		(((u32)val << shift) & (mask))), reg)
-
-#define HASH_SET_DIN(val, len)	writesl(&device_data->base->din, (val), (len))
-
-#define HASH_INITIALIZE			\
-	HASH_PUT_BITS(			\
-		&device_data->base->cr,	\
-		0x01, HASH_CR_INIT_POS,	\
-		HASH_CR_INIT_MASK)
-
-#define HASH_SET_DATA_FORMAT(data_format)				\
-		HASH_PUT_BITS(						\
-			&device_data->base->cr,				\
-			(u32) (data_format), HASH_CR_DATAFORM_POS,	\
-			HASH_CR_DATAFORM_MASK)
-#define HASH_SET_NBLW(val)					\
-		HASH_PUT_BITS(					\
-			&device_data->base->str,		\
-			(u32) (val), HASH_STR_NBLW_POS,		\
-			HASH_STR_NBLW_MASK)
-#define HASH_SET_DCAL					\
-		HASH_PUT_BITS(				\
-			&device_data->base->str,	\
-			0x01, HASH_STR_DCAL_POS,	\
-			HASH_STR_DCAL_MASK)
-
 /* Hardware access method */
 enum hash_mode {
 	HASH_MODE_CPU,
 	HASH_MODE_DMA
 };
 
-/**
- * struct hash_register - Contains all registers in ux500 hash hardware.
- * @cr:		HASH control register (0x000).
- * @din:	HASH data input register (0x004).
- * @str:	HASH start register (0x008).
- * @hx:		HASH digest register 0..7 (0x00c-0x01C).
- * @padding0:	Reserved (0x02C).
- * @itcr:	Integration test control register (0x080).
- * @itip:	Integration test input register (0x084).
- * @itop:	Integration test output register (0x088).
- * @padding1:	Reserved (0x08C).
- * @csfull:	HASH context full register (0x0F8).
- * @csdatain:	HASH context swap data input register (0x0FC).
- * @csrx:	HASH context swap register 0..51 (0x100-0x1CC).
- * @padding2:	Reserved (0x1D0).
- * @periphid0:	HASH peripheral identification register 0 (0xFE0).
- * @periphid1:	HASH peripheral identification register 1 (0xFE4).
- * @periphid2:	HASH peripheral identification register 2 (0xFE8).
- * @periphid3:	HASH peripheral identification register 3 (0xFEC).
- * @cellid0:	HASH PCell identification register 0 (0xFF0).
- * @cellid1:	HASH PCell identification register 1 (0xFF4).
- * @cellid2:	HASH PCell identification register 2 (0xFF8).
- * @cellid3:	HASH PCell identification register 3 (0xFFC).
- *
- * The device communicates to the HASH via 32-bit-wide control registers
- * accessible via the 32-bit width AMBA rev. 2.0 AHB Bus. Below is a structure
- * with the registers used.
- */
-struct hash_register {
-	u32 cr;
-	u32 din;
-	u32 str;
-	u32 hx[8];
-
-	u32 padding0[(0x080 - 0x02C) / sizeof(u32)];
-
-	u32 itcr;
-	u32 itip;
-	u32 itop;
-
-	u32 padding1[(0x0F8 - 0x08C) / sizeof(u32)];
-
-	u32 csfull;
-	u32 csdatain;
-	u32 csrx[HASH_CSR_COUNT];
-
-	u32 padding2[(0xFE0 - 0x1D0) / sizeof(u32)];
-
-	u32 periphid0;
-	u32 periphid1;
-	u32 periphid2;
-	u32 periphid3;
-
-	u32 cellid0;
-	u32 cellid1;
-	u32 cellid2;
-	u32 cellid3;
-};
-
 /**
  * struct hash_state - Hash context state.
  * @temp_cr:	Temporary HASH Control Register.
@@ -228,20 +116,6 @@ enum hash_device_id {
 	HASH_DEVICE_ID_1 = 1
 };
 
-/**
- * enum hash_data_format - HASH data format.
- * @HASH_DATA_32_BITS:	32 bits data format
- * @HASH_DATA_16_BITS:	16 bits data format
- * @HASH_DATA_8_BITS:	8 bits data format.
- * @HASH_DATA_1_BITS:	1 bit data format.
- */
-enum hash_data_format {
-	HASH_DATA_32_BITS	= 0x0,
-	HASH_DATA_16_BITS	= 0x1,
-	HASH_DATA_8_BITS	= 0x2,
-	HASH_DATA_1_BIT		= 0x3
-};
-
 /**
  * enum hash_algo - Enumeration for selecting between SHA1 or SHA2 algorithm.
  * @HASH_ALGO_SHA1: Indicates that SHA1 is used.
@@ -269,7 +143,7 @@ enum hash_op {
  * @oper_mode:		Operating mode selection bit.
  */
 struct hash_config {
-	int data_format;
+	unsigned int data_format;
 	int algorithm;
 	int oper_mode;
 };
@@ -335,7 +209,7 @@ struct hash_req_ctx {
 
 /**
  * struct hash_device_data - structure for a hash device.
- * @base:		Pointer to virtual base address of the hash device.
+ * @map:		Regmap for the MMIO for the device
  * @phybase:		Pointer to physical memory location of the hash device.
  * @list_node:		For inclusion in klist.
  * @dev:		Pointer to the device dev structure.
@@ -348,7 +222,7 @@ struct hash_req_ctx {
  * @dma:		Structure used for dma.
  */
 struct hash_device_data {
-	struct hash_register __iomem	*base;
+	struct regmap		*map;
 	phys_addr_t             phybase;
 	struct klist_node	list_node;
 	struct device		*dev;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 21657c9c79a7..ed54e71efbb2 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
+#include <linux/regmap.h>
 #include <linux/crypto.h>
 #include <linux/dmaengine.h>
 #include <linux/bitops.h>
@@ -289,6 +290,45 @@ static int hash_enable_power(struct hash_device_data *device_data)
 	return ret;
 }
 
+static void hash_wait_for_dcal(struct hash_device_data *device_data)
+{
+	unsigned int val;
+
+	regmap_read(device_data->map, UX500_HASH_STR, &val);
+	while (val & HASH_STR_DCAL) {
+		cpu_relax();
+		regmap_read(device_data->map, UX500_HASH_STR, &val);
+	}
+}
+
+static void hash_fill_din(struct hash_device_data *device_data,
+			  const void *data, unsigned int len)
+{
+	const u8 *datap = data;
+	u32 val;
+
+	/*
+	 * We cannot use regmap_write_noinc() because regmap MMIO does
+	 * not support the noinc operations (requires .write() callback).
+	 * TODO: revisit when regmap MMIO supports regmap_write_noinc().
+	 */
+	while (len > 4) {
+		val = *((u32 *)datap);
+		regmap_write(device_data->map, UX500_HASH_DIN, val);
+		datap += 4;
+		len -= 4;
+	}
+
+	if (len) {
+		val = 0;
+		while (len) {
+			val |= (datap[len - 1] << (8 * (len - 1)));
+			len--;
+		}
+		regmap_write(device_data->map, UX500_HASH_DIN, val);
+	}
+}
+
 /**
  * hash_hw_write_key - Writes the key to the hardware registries.
  *
@@ -303,37 +343,17 @@ static int hash_enable_power(struct hash_device_data *device_data)
 static void hash_hw_write_key(struct hash_device_data *device_data,
 			      const u8 *key, unsigned int keylen)
 {
-	u32 word = 0;
-	int nwords = 1;
-
-	HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
-
-	while (keylen >= 4) {
-		u32 *key_word = (u32 *)key;
-
-		HASH_SET_DIN(key_word, nwords);
-		keylen -= 4;
-		key += 4;
-	}
-
-	/* Take care of the remaining bytes in the last word */
-	if (keylen) {
-		word = 0;
-		while (keylen) {
-			word |= (key[keylen - 1] << (8 * (keylen - 1)));
-			keylen--;
-		}
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_NBLW_MASK, 0);
 
-		HASH_SET_DIN(&word, nwords);
-	}
+	hash_fill_din(device_data, key, keylen);
 
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
+	hash_wait_for_dcal(device_data);
 
-	HASH_SET_DCAL;
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_DCAL, HASH_STR_DCAL);
 
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
+	hash_wait_for_dcal(device_data);
 }
 
 /**
@@ -468,16 +488,16 @@ static int ux500_hash_init(struct ahash_request *req)
 static void hash_processblock(struct hash_device_data *device_data,
 			      const u32 *message, int length)
 {
-	int len = length / HASH_BYTES_PER_WORD;
 	/*
 	 * NBLW bits. Reset the number of bits in last word (NBLW).
 	 */
-	HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_NBLW_MASK, 0);
 
 	/*
 	 * Write message data to the HASH_DIN register.
 	 */
-	HASH_SET_DIN(message, len);
+	hash_fill_din(device_data, message, length);
 }
 
 /**
@@ -493,39 +513,24 @@ static void hash_processblock(struct hash_device_data *device_data,
 static void hash_messagepad(struct hash_device_data *device_data,
 			    const u32 *message, u8 index_bytes)
 {
-	int nwords = 1;
-
 	/*
 	 * Clear hash str register, only clear NBLW
 	 * since DCAL will be reset by hardware.
 	 */
-	HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_NBLW_MASK, 0);
 
-	/* Main loop */
-	while (index_bytes >= 4) {
-		HASH_SET_DIN(message, nwords);
-		index_bytes -= 4;
-		message++;
-	}
-
-	if (index_bytes)
-		HASH_SET_DIN(message, nwords);
+	hash_fill_din(device_data, message, index_bytes);
 
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
+	hash_wait_for_dcal(device_data);
 
 	/* num_of_bytes == 0 => NBLW <- 0 (32 bits valid in DATAIN) */
-	HASH_SET_NBLW(index_bytes * 8);
-	dev_dbg(device_data->dev, "%s: DIN=0x%08x NBLW=%lu\n",
-		__func__, readl_relaxed(&device_data->base->din),
-		readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK);
-	HASH_SET_DCAL;
-	dev_dbg(device_data->dev, "%s: after dcal -> DIN=0x%08x NBLW=%lu\n",
-		__func__, readl_relaxed(&device_data->base->din),
-		readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK);
-
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_NBLW_MASK, index_bytes * 8);
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_DCAL, HASH_STR_DCAL);
+
+	hash_wait_for_dcal(device_data);
 }
 
 /**
@@ -548,18 +553,21 @@ int hash_setconfiguration(struct hash_device_data *device_data,
 	 * DATAFORM bits. Set the DATAFORM bits to 0b11, which means the data
 	 * to be written to HASH_DIN is considered as 32 bits.
 	 */
-	HASH_SET_DATA_FORMAT(config->data_format);
+	regmap_update_bits(device_data->map, UX500_HASH_CR,
+			   HASH_CR_DATAFORM_MASK, config->data_format);
 
 	/*
 	 * ALGO bit. Set to 0b1 for SHA-1 and 0b0 for SHA-256
 	 */
 	switch (config->algorithm) {
 	case HASH_ALGO_SHA1:
-		HASH_SET_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
+		regmap_update_bits(device_data->map, UX500_HASH_CR,
+				   HASH_CR_ALGO, HASH_CR_ALGO);
 		break;
 
 	case HASH_ALGO_SHA256:
-		HASH_CLEAR_BITS(&device_data->base->cr, HASH_CR_ALGO_MASK);
+		regmap_update_bits(device_data->map, UX500_HASH_CR,
+				   HASH_CR_ALGO, 0);
 		break;
 
 	default:
@@ -573,20 +581,21 @@ int hash_setconfiguration(struct hash_device_data *device_data,
 	 * selected algorithm. 0b0 = HASH and 0b1 = HMAC.
 	 */
 	if (config->oper_mode == HASH_OPER_MODE_HASH) {
-		HASH_CLEAR_BITS(&device_data->base->cr,
-				HASH_CR_MODE_MASK);
+		regmap_update_bits(device_data->map, UX500_HASH_CR,
+				   HASH_CR_MODE, 0);
 	} else if (config->oper_mode == HASH_OPER_MODE_HMAC) {
-		HASH_SET_BITS(&device_data->base->cr, HASH_CR_MODE_MASK);
+		regmap_update_bits(device_data->map, UX500_HASH_CR,
+				   HASH_CR_MODE, HASH_CR_MODE);
 		if (ctx->keylen > HASH_BLOCK_SIZE) {
 			/* Truncate key to blocksize */
 			dev_dbg(device_data->dev, "%s: LKEY set\n", __func__);
-			HASH_SET_BITS(&device_data->base->cr,
-				      HASH_CR_LKEY_MASK);
+			regmap_update_bits(device_data->map, UX500_HASH_CR,
+					   HASH_CR_LKEY, HASH_CR_LKEY);
 		} else {
 			dev_dbg(device_data->dev, "%s: LKEY cleared\n",
 				__func__);
-			HASH_CLEAR_BITS(&device_data->base->cr,
-					HASH_CR_LKEY_MASK);
+			regmap_update_bits(device_data->map, UX500_HASH_CR,
+					   HASH_CR_LKEY, 0);
 		}
 	} else {	/* Wrong hash mode */
 		ret = -EPERM;
@@ -607,20 +616,21 @@ void hash_begin(struct hash_device_data *device_data, struct hash_ctx *ctx)
 	/* HW and SW initializations */
 	/* Note: there is no need to initialize buffer and digest members */
 
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
+	hash_wait_for_dcal(device_data);
 
 	/*
 	 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
 	 * prepare the initialize the HASH accelerator to compute the message
 	 * digest of a new message.
 	 */
-	HASH_INITIALIZE;
+	regmap_update_bits(device_data->map, UX500_HASH_CR,
+			   HASH_CR_INIT, HASH_CR_INIT);
 
 	/*
 	 * NBLW bits. Reset the number of bits in last word (NBLW).
 	 */
-	HASH_CLEAR_BITS(&device_data->base->str, HASH_STR_NBLW_MASK);
+	regmap_update_bits(device_data->map, UX500_HASH_STR,
+			   HASH_STR_NBLW_MASK, 0);
 }
 
 static int hash_process_data(struct hash_device_data *device_data,
@@ -715,22 +725,24 @@ static int hash_dma_final(struct ahash_request *req)
 
 		/* Enable DMA input */
 		if (hash_mode != HASH_MODE_DMA || !req_ctx->dma_mode) {
-			HASH_CLEAR_BITS(&device_data->base->cr,
-					HASH_CR_DMAE_MASK);
+			regmap_update_bits(device_data->map, UX500_HASH_CR,
+					   HASH_CR_DMAE, 0);
 		} else {
-			HASH_SET_BITS(&device_data->base->cr,
-				      HASH_CR_DMAE_MASK);
-			HASH_SET_BITS(&device_data->base->cr,
-				      HASH_CR_PRIVN_MASK);
+			regmap_update_bits(device_data->map, UX500_HASH_CR,
+					   HASH_CR_DMAE | HASH_CR_PRIVN,
+					   HASH_CR_DMAE | HASH_CR_PRIVN);
 		}
 
-		HASH_INITIALIZE;
+		regmap_update_bits(device_data->map, UX500_HASH_CR,
+				   HASH_CR_INIT, HASH_CR_INIT);
 
 		if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC)
 			hash_hw_write_key(device_data, ctx->key, ctx->keylen);
 
 		/* Number of bits in last word = (nbytes * 8) % 32 */
-		HASH_SET_NBLW((req->nbytes * 8) % 32);
+		regmap_update_bits(device_data->map, UX500_HASH_STR,
+				   HASH_STR_NBLW_MASK, (req->nbytes * 8) % 32);
+
 		req_ctx->hw_initialized = true;
 	}
 
@@ -754,8 +766,7 @@ static int hash_dma_final(struct ahash_request *req)
 	wait_for_completion(&ctx->device->dma.complete);
 	hash_dma_done(ctx);
 
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
+	hash_wait_for_dcal(device_data);
 
 	if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
 		unsigned int keylen = ctx->keylen;
@@ -844,9 +855,9 @@ static int hash_hw_final(struct ahash_request *req)
 		hash_messagepad(device_data, req_ctx->buffer,
 				req_ctx->index);
 	} else {
-		HASH_SET_DCAL;
-		while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-			cpu_relax();
+		regmap_update_bits(device_data->map, UX500_HASH_STR,
+				   HASH_STR_DCAL, HASH_STR_DCAL);
+		hash_wait_for_dcal(device_data);
 	}
 
 	if (ctx->config.oper_mode == HASH_OPER_MODE_HMAC && ctx->key) {
@@ -935,20 +946,24 @@ int hash_hw_update(struct ahash_request *req)
  */
 int hash_check_hw(struct hash_device_data *device_data)
 {
-	/* Checking Peripheral Ids  */
-	if (HASH_P_ID0 == readl_relaxed(&device_data->base->periphid0) &&
-	    HASH_P_ID1 == readl_relaxed(&device_data->base->periphid1) &&
-	    HASH_P_ID2 == readl_relaxed(&device_data->base->periphid2) &&
-	    HASH_P_ID3 == readl_relaxed(&device_data->base->periphid3) &&
-	    HASH_CELL_ID0 == readl_relaxed(&device_data->base->cellid0) &&
-	    HASH_CELL_ID1 == readl_relaxed(&device_data->base->cellid1) &&
-	    HASH_CELL_ID2 == readl_relaxed(&device_data->base->cellid2) &&
-	    HASH_CELL_ID3 == readl_relaxed(&device_data->base->cellid3)) {
-		return 0;
+	unsigned int regs[] = { UX500_HASH_PERIPHID0, UX500_HASH_PERIPHID1,
+		UX500_HASH_PERIPHID2, UX500_HASH_PERIPHID3, UX500_HASH_CELLID0,
+		UX500_HASH_CELLID1, UX500_HASH_CELLID2, UX500_HASH_CELLID3 };
+	unsigned int expected[] = { HASH_P_ID0, HASH_P_ID1, HASH_P_ID2, HASH_P_ID3,
+		HASH_CELL_ID0, HASH_CELL_ID1, HASH_CELL_ID2, HASH_CELL_ID3 };
+	unsigned int val;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(regs); i++) {
+		regmap_read(device_data->map, regs[i], &val);
+		if (val != expected[i]) {
+			dev_err(device_data->dev, "ID word %d was %08x expected %08x\n",
+				i, val, expected[i]);
+			return -ENODEV;
+		}
 	}
 
-	dev_err(device_data->dev, "%s: HASH_UNSUPPORTED_HW!\n", __func__);
-	return -ENOTSUPP;
+	return 0;
 }
 
 /**
@@ -960,8 +975,9 @@ int hash_check_hw(struct hash_device_data *device_data)
 void hash_get_digest(struct hash_device_data *device_data,
 		     u8 *digest, int algorithm)
 {
-	u32 temp_hx_val, count;
 	int loop_ctr;
+	u32 val;
+	int i;
 
 	if (algorithm != HASH_ALGO_SHA1 && algorithm != HASH_ALGO_SHA256) {
 		dev_err(device_data->dev, "%s: Incorrect algorithm %d\n",
@@ -977,13 +993,13 @@ void hash_get_digest(struct hash_device_data *device_data,
 	dev_dbg(device_data->dev, "%s: digest array:(0x%lx)\n",
 		__func__, (unsigned long)digest);
 
-	/* Copy result into digest array */
-	for (count = 0; count < loop_ctr; count++) {
-		temp_hx_val = readl_relaxed(&device_data->base->hx[count]);
-		digest[count * 4] = (u8) ((temp_hx_val >> 24) & 0xFF);
-		digest[count * 4 + 1] = (u8) ((temp_hx_val >> 16) & 0xFF);
-		digest[count * 4 + 2] = (u8) ((temp_hx_val >> 8) & 0xFF);
-		digest[count * 4 + 3] = (u8) ((temp_hx_val >> 0) & 0xFF);
+	for (i = 0; i < loop_ctr; i++) {
+		regmap_read(device_data->map, UX500_HASH_H(i),
+			    &val);
+		digest[i * 4] = (u8) ((val >> 24) & 0xFF);
+		digest[i * 4 + 1] = (u8) ((val >> 16) & 0xFF);
+		digest[i * 4 + 2] = (u8) ((val >> 8) & 0xFF);
+		digest[i * 4 + 3] = (u8) ((val >> 0) & 0xFF);
 	}
 }
 
@@ -1055,7 +1071,7 @@ static int ahash_sha1_init(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 
-	ctx->config.data_format = HASH_DATA_8_BITS;
+	ctx->config.data_format = HASH_CR_DATAFORM_8BIT;
 	ctx->config.algorithm = HASH_ALGO_SHA1;
 	ctx->config.oper_mode = HASH_OPER_MODE_HASH;
 	ctx->digestsize = SHA1_DIGEST_SIZE;
@@ -1068,7 +1084,7 @@ static int ahash_sha256_init(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 
-	ctx->config.data_format = HASH_DATA_8_BITS;
+	ctx->config.data_format = HASH_CR_DATAFORM_8BIT;
 	ctx->config.algorithm = HASH_ALGO_SHA256;
 	ctx->config.oper_mode = HASH_OPER_MODE_HASH;
 	ctx->digestsize = SHA256_DIGEST_SIZE;
@@ -1113,9 +1129,8 @@ static int ahash_import(struct ahash_request *req, const void *in)
 	struct hash_device_data *device_data = ctx->device;
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 	const struct hash_state *hstate = in;
-	int hash_mode = HASH_OPER_MODE_HASH;
+	unsigned int val;
 	u32 cr;
-	s32 count;
 
 	/* Restore software state */
 	req_ctx->length = hstate->length;
@@ -1130,27 +1145,24 @@ static int ahash_import(struct ahash_request *req, const void *in)
 	 * prepare the initialize the HASH accelerator to compute the message
 	 * digest of a new message.
 	 */
-	HASH_INITIALIZE;
+	regmap_update_bits(device_data->map, UX500_HASH_CR,
+			   HASH_CR_INIT, HASH_CR_INIT);
 
 	cr = hstate->temp_cr;
-	writel_relaxed(cr & HASH_CR_RESUME_MASK, &device_data->base->cr);
+	regmap_write(device_data->map, UX500_HASH_CR, cr & HASH_CR_RESUME_MASK);
 
-	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
-		hash_mode = HASH_OPER_MODE_HMAC;
+	regmap_read(device_data->map, UX500_HASH_CR, &val);
+	if (val & HASH_CR_MODE)
+		regmap_bulk_write(device_data->map, UX500_HASH_CSR(0),
+				  hstate->csr, HASH_CSR_COUNT);
 	else
-		hash_mode = HASH_OPER_MODE_HASH;
-
-	for (count = 0; count < HASH_CSR_COUNT; count++) {
-		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
-			break;
-		writel_relaxed(hstate->csr[count],
-			       &device_data->base->csrx[count]);
-	}
+		regmap_bulk_write(device_data->map, UX500_HASH_CSR(0),
+				  hstate->csr, 36);
 
-	writel_relaxed(hstate->csfull, &device_data->base->csfull);
-	writel_relaxed(hstate->csdatain, &device_data->base->csdatain);
-	writel_relaxed(hstate->str_reg, &device_data->base->str);
-	writel_relaxed(cr, &device_data->base->cr);
+	regmap_write(device_data->map, UX500_HASH_CSFULL, hstate->csfull);
+	regmap_write(device_data->map, UX500_HASH_CSDATAIN, hstate->csdatain);
+	regmap_write(device_data->map, UX500_HASH_STR, hstate->str_reg);
+	regmap_write(device_data->map, UX500_HASH_CR, cr);
 
 	return 0;
 }
@@ -1162,9 +1174,7 @@ static int ahash_export(struct ahash_request *req, void *out)
 	struct hash_device_data *device_data = ctx->device;
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
 	struct hash_state *hstate = out;
-	int hash_mode = HASH_OPER_MODE_HASH;
 	u32 cr;
-	u32 count;
 
 	/*
 	 * Save hardware state:
@@ -1172,31 +1182,21 @@ static int ahash_export(struct ahash_request *req, void *out)
 	 * actually makes sure that there isn't any ongoing calculation in the
 	 * hardware.
 	 */
-	while (readl(&device_data->base->str) & HASH_STR_DCAL_MASK)
-		cpu_relax();
-
-	cr = readl_relaxed(&device_data->base->cr);
-
-	hstate->str_reg = readl_relaxed(&device_data->base->str);
+	hash_wait_for_dcal(device_data);
 
-	hstate->din_reg = readl_relaxed(&device_data->base->din);
+	regmap_read(device_data->map, UX500_HASH_CR, &cr);
+	regmap_read(device_data->map, UX500_HASH_STR, &hstate->str_reg);
+	regmap_read(device_data->map, UX500_HASH_DIN, &hstate->din_reg);
 
-	if (readl(&device_data->base->cr) & HASH_CR_MODE_MASK)
-		hash_mode = HASH_OPER_MODE_HMAC;
+	if (cr & HASH_CR_MODE)
+		regmap_bulk_read(device_data->map, UX500_HASH_CSR(0),
+				 hstate->csr, HASH_CSR_COUNT);
 	else
-		hash_mode = HASH_OPER_MODE_HASH;
-
-	for (count = 0; count < HASH_CSR_COUNT; count++) {
-		if ((count >= 36) && (hash_mode == HASH_OPER_MODE_HASH))
-			break;
-
-		hstate->csr[count] =
-			readl_relaxed(&device_data->base->csrx[count]);
-	}
-
-	hstate->csfull = readl_relaxed(&device_data->base->csfull);
-	hstate->csdatain = readl_relaxed(&device_data->base->csdatain);
+		regmap_bulk_read(device_data->map, UX500_HASH_CSR(0),
+				 hstate->csr, 36);
 
+	regmap_read(device_data->map, UX500_HASH_CSFULL, &hstate->csfull);
+	regmap_read(device_data->map, UX500_HASH_CSDATAIN, &hstate->csdatain);
 	hstate->temp_cr = cr;
 
 	/* Save software state */
@@ -1214,7 +1214,7 @@ static int hmac_sha1_init(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 
-	ctx->config.data_format	= HASH_DATA_8_BITS;
+	ctx->config.data_format	= HASH_CR_DATAFORM_8BIT;
 	ctx->config.algorithm	= HASH_ALGO_SHA1;
 	ctx->config.oper_mode	= HASH_OPER_MODE_HMAC;
 	ctx->digestsize		= SHA1_DIGEST_SIZE;
@@ -1227,7 +1227,7 @@ static int hmac_sha256_init(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 
-	ctx->config.data_format	= HASH_DATA_8_BITS;
+	ctx->config.data_format	= HASH_CR_DATAFORM_8BIT;
 	ctx->config.algorithm	= HASH_ALGO_SHA256;
 	ctx->config.oper_mode	= HASH_OPER_MODE_HMAC;
 	ctx->digestsize		= SHA256_DIGEST_SIZE;
@@ -1298,7 +1298,7 @@ static int hash_cra_init(struct crypto_tfm *tfm)
 	crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
 				 sizeof(struct hash_req_ctx));
 
-	ctx->config.data_format = HASH_DATA_8_BITS;
+	ctx->config.data_format = HASH_CR_DATAFORM_8BIT;
 	ctx->config.algorithm = hash_alg->conf.algorithm;
 	ctx->config.oper_mode = hash_alg->conf.oper_mode;
 
@@ -1435,6 +1435,107 @@ static void ahash_algs_unregister_all(struct hash_device_data *device_data)
 		crypto_unregister_ahash(&hash_algs[i].hash);
 }
 
+static bool ux500_hash_reg_readable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case UX500_HASH_CR:
+	case UX500_HASH_DIN:
+	case UX500_HASH_STR:
+	case UX500_HASH_H(0) ... UX500_HASH_H(7):
+	case UX500_HASH_ITCR:
+	case UX500_HASH_ITIP:
+	case UX500_HASH_ITOP:
+	case UX500_HASH_CSFULL:
+	case UX500_HASH_CSDATAIN:
+	case UX500_HASH_CSR(0) ... UX500_HASH_CSR(51):
+	case UX500_HASH_PERIPHID0:
+	case UX500_HASH_PERIPHID1:
+	case UX500_HASH_PERIPHID2:
+	case UX500_HASH_PERIPHID3:
+	case UX500_HASH_CELLID0:
+	case UX500_HASH_CELLID1:
+	case UX500_HASH_CELLID2:
+	case UX500_HASH_CELLID3:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool ux500_hash_reg_writeable(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case UX500_HASH_CR:
+	case UX500_HASH_DIN:
+	case UX500_HASH_STR:
+	case UX500_HASH_ITCR:
+	case UX500_HASH_ITIP:
+	case UX500_HASH_ITOP:
+	case UX500_HASH_CSFULL:
+	case UX500_HASH_CSDATAIN:
+	case UX500_HASH_CSR(0) ... UX500_HASH_CSR(51):
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool ux500_hash_reg_writeable_noinc(struct device *dev, unsigned int reg)
+{
+	if (reg == UX500_HASH_DIN)
+		return true;
+	return false;
+}
+
+static bool ux500_hash_reg_volatile(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case UX500_HASH_CR:
+	case UX500_HASH_STR:
+	case UX500_HASH_H(0) ... UX500_HASH_H(7):
+	case UX500_HASH_ITCR:
+	case UX500_HASH_ITIP:
+	case UX500_HASH_ITOP:
+	case UX500_HASH_CSFULL:
+	case UX500_HASH_CSDATAIN:
+	case UX500_HASH_CSR(0) ... UX500_HASH_CSR(51):
+	/*
+	 * The following IDs are read-only, but to the reg cache they are
+	 * volatile, since they have values there at startup.
+	 */
+	case UX500_HASH_PERIPHID0:
+	case UX500_HASH_PERIPHID1:
+	case UX500_HASH_PERIPHID2:
+	case UX500_HASH_PERIPHID3:
+	case UX500_HASH_CELLID0:
+	case UX500_HASH_CELLID1:
+	case UX500_HASH_CELLID2:
+	case UX500_HASH_CELLID3:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static const struct regmap_config ux500_hash_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	/*
+	 * Regcache is not helpful since we shoehorn tons of random data
+	 * into the hash engine, the few register reads outside of that
+	 * are not worth it. Disable the cache.
+	 */
+	.cache_type = REGCACHE_NONE,
+	.fast_io = true,
+	.max_register = 0xFFC,
+	.use_relaxed_mmio = true,
+	.readable_reg = ux500_hash_reg_readable,
+	.writeable_reg = ux500_hash_reg_writeable,
+	.volatile_reg = ux500_hash_reg_volatile,
+	.writeable_noinc_reg = ux500_hash_reg_writeable_noinc,
+};
+
 /**
  * ux500_hash_probe - Function that probes the hash hardware.
  * @pdev: The platform device.
@@ -1445,6 +1546,7 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	struct resource		*res = NULL;
 	struct hash_device_data *device_data;
 	struct device		*dev = &pdev->dev;
+	void __iomem *base;
 
 	device_data = devm_kzalloc(dev, sizeof(*device_data), GFP_KERNEL);
 	if (!device_data) {
@@ -1463,11 +1565,22 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	}
 
 	device_data->phybase = res->start;
-	device_data->base = devm_ioremap_resource(dev, res);
-	if (IS_ERR(device_data->base)) {
-		ret = PTR_ERR(device_data->base);
+	base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(base)) {
+		ret = PTR_ERR(base);
+		goto out;
+	}
+	device_data->map = devm_regmap_init_mmio(dev, base,
+						 &ux500_hash_regmap_config);
+	if (IS_ERR(device_data->map)) {
+		ret = PTR_ERR(device_data->map);
 		goto out;
 	}
+	/*
+	 * We use REGCACHE_NONE, so also bypass any calls not stubbed
+	 * by that.
+	 */
+	regcache_cache_bypass(device_data->map, true);
 	spin_lock_init(&device_data->ctx_lock);
 	spin_lock_init(&device_data->power_state_lock);
 
-- 
2.37.2

[PATCH v3 14/16] crypto: ux500/hash: Use AMBA core primecell IDs

[Linus Walleij]

Use the AMBA (PrimeCell) bus core define and read 32bit
CID and PID from the peripheral, then check those.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- Initialized both CID and PID to 0 appropriately.
---
 drivers/crypto/ux500/hash/hash_alg.h  | 11 ++---------
 drivers/crypto/ux500/hash/hash_core.c | 25 ++++++++++++++++++-------
 2 files changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index cc44d3cb21ac..96c614444fa2 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -63,15 +63,8 @@
 #define HASH_STR_NBLW_MASK	0x0000001FUL
 #define HASH_NBLW_MAX_VAL	0x1F
 
-/* PrimeCell IDs */
-#define HASH_P_ID0		0xE0
-#define HASH_P_ID1		0x05
-#define HASH_P_ID2		0x38
-#define HASH_P_ID3		0x00
-#define HASH_CELL_ID0		0x0D
-#define HASH_CELL_ID1		0xF0
-#define HASH_CELL_ID2		0x05
-#define HASH_CELL_ID3		0xB1
+/* PrimeCell ID */
+#define UX500_HASH_PID		0x003805E0U
 
 /* Hardware access method */
 enum hash_mode {
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index ed54e71efbb2..188e309406b2 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -13,6 +13,7 @@
 
 #define pr_fmt(fmt) "hashX hashX: " fmt
 
+#include <linux/amba/bus.h>
 #include <linux/clk.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
@@ -949,18 +950,28 @@ int hash_check_hw(struct hash_device_data *device_data)
 	unsigned int regs[] = { UX500_HASH_PERIPHID0, UX500_HASH_PERIPHID1,
 		UX500_HASH_PERIPHID2, UX500_HASH_PERIPHID3, UX500_HASH_CELLID0,
 		UX500_HASH_CELLID1, UX500_HASH_CELLID2, UX500_HASH_CELLID3 };
-	unsigned int expected[] = { HASH_P_ID0, HASH_P_ID1, HASH_P_ID2, HASH_P_ID3,
-		HASH_CELL_ID0, HASH_CELL_ID1, HASH_CELL_ID2, HASH_CELL_ID3 };
 	unsigned int val;
+	u32 pid = 0;
+	u32 cid = 0;
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(regs); i++) {
 		regmap_read(device_data->map, regs[i], &val);
-		if (val != expected[i]) {
-			dev_err(device_data->dev, "ID word %d was %08x expected %08x\n",
-				i, val, expected[i]);
-			return -ENODEV;
-		}
+		if (i < 4)
+			pid |= (val & 255) << (i * 8);
+		else
+			cid |= (val & 255) << ((i - 4) * 8);
+	}
+
+	if (cid != AMBA_CID) {
+		dev_err(device_data->dev, "AMBA CID was %08x expected %08x\n",
+			cid, AMBA_CID);
+		return -ENODEV;
+	}
+	if (pid != UX500_HASH_PID) {
+		dev_err(device_data->dev, "PID was %08x expected %08x\n",
+			pid, UX500_HASH_PID);
+		return -ENODEV;
 	}
 
 	return 0;
-- 
2.37.2

[PATCH v3 15/16] crypto: ux500/hash: Implement runtime PM

[Linus Walleij]

This implements runtime PM to gate the clock and regulator
when the hash block is unused.

Drop the own-invented "power state" and its associated lock:
we don't need that when we have runtime PM.

Delete the specific power functions and just enable/disable
the clock in the runtime PM functions. Use the full
*_prepare_enable() and *disable_unprepare() calls for
really making sure the clock is off.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v2->v3:
- Rebased on v6.0-rc1
ChangeLog v1->v2:
- New patch to clean up also the custom PM.
---
 drivers/crypto/ux500/hash/hash_alg.h  |   3 +-
 drivers/crypto/ux500/hash/hash_core.c | 164 +++++++++++---------------
 2 files changed, 71 insertions(+), 96 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h
index 96c614444fa2..344f2294a938 100644
--- a/drivers/crypto/ux500/hash/hash_alg.h
+++ b/drivers/crypto/ux500/hash/hash_alg.h
@@ -16,6 +16,7 @@
 #define HASH_DMA_ALIGN_SIZE		4
 #define HASH_DMA_PERFORMANCE_MIN_SIZE	1024
 #define HASH_BYTES_PER_WORD		4
+#define UX500_HASH_AUTOSUSPEND_DELAY_MS	50
 
 /* Number of context swap registers */
 #define HASH_CSR_COUNT			52
@@ -221,8 +222,6 @@ struct hash_device_data {
 	struct device		*dev;
 	spinlock_t		ctx_lock;
 	struct hash_ctx		*current_ctx;
-	bool			power_state;
-	spinlock_t		power_state_lock;
 	struct regulator	*regulator;
 	struct clk		*clk;
 	struct hash_dma		dma;
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index 188e309406b2..be703fe4d0ec 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -24,6 +24,7 @@
 #include <linux/module.h>
 #include <linux/mod_devicetable.h>
 #include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
 #include <linux/regmap.h>
 #include <linux/crypto.h>
 #include <linux/dmaengine.h>
@@ -240,57 +241,6 @@ static int get_empty_message_digest(
 	return ret;
 }
 
-/**
- * hash_disable_power - Request to disable power and clock.
- * @device_data:	Structure for the hash device.
- *
- * This function request for disabling the clock.
- */
-static int hash_disable_power(struct hash_device_data *device_data)
-{
-	int ret = 0;
-
-	spin_lock(&device_data->power_state_lock);
-	if (!device_data->power_state)
-		goto out;
-
-	clk_disable(device_data->clk);
-
-	device_data->power_state = false;
-
-out:
-	spin_unlock(&device_data->power_state_lock);
-
-	return ret;
-}
-
-/**
- * hash_enable_power - Request to enable power and clock.
- * @device_data:		Structure for the hash device.
- *
- * This function request for enabling the clock.
- */
-static int hash_enable_power(struct hash_device_data *device_data)
-{
-	int ret = 0;
-	struct device *dev = device_data->dev;
-
-	spin_lock(&device_data->power_state_lock);
-	if (!device_data->power_state) {
-		ret = clk_enable(device_data->clk);
-		if (ret) {
-			dev_err(dev, "%s: clk_enable() failed!\n", __func__);
-			goto out;
-		}
-		device_data->power_state = true;
-	}
-
-out:
-	spin_unlock(&device_data->power_state_lock);
-
-	return ret;
-}
-
 static void hash_wait_for_dcal(struct hash_device_data *device_data)
 {
 	unsigned int val;
@@ -449,6 +399,10 @@ static int ux500_hash_init(struct ahash_request *req)
 	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
+	struct hash_device_data *device_data = ctx->device;
+
+	/* Power up on init() power down on final() */
+	pm_runtime_get_sync(device_data->dev);
 
 	if (!ctx->key)
 		ctx->keylen = 0;
@@ -474,6 +428,7 @@ static int ux500_hash_init(struct ahash_request *req)
 			}
 		}
 	}
+
 	return 0;
 }
 
@@ -782,6 +737,8 @@ static int hash_dma_final(struct ahash_request *req)
 	memcpy(req->result, digest, ctx->digestsize);
 
 out:
+	pm_runtime_mark_last_busy(device_data->dev);
+	pm_runtime_put_autosuspend(device_data->dev);
 	/**
 	 * Allocated in setkey, and only used in HMAC.
 	 */
@@ -1040,8 +997,11 @@ static int ahash_update(struct ahash_request *req)
  */
 static int ahash_final(struct ahash_request *req)
 {
-	int ret = 0;
+	struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
+	struct hash_ctx *ctx = crypto_ahash_ctx(tfm);
+	struct hash_device_data *device_data = ctx->device;
 	struct hash_req_ctx *req_ctx = ahash_request_ctx(req);
+	int ret = 0;
 
 	pr_debug("%s: data size: %d\n", __func__, req->nbytes);
 
@@ -1050,6 +1010,9 @@ static int ahash_final(struct ahash_request *req)
 	else
 		ret = hash_hw_final(req);
 
+	pm_runtime_mark_last_busy(device_data->dev);
+	pm_runtime_put_autosuspend(device_data->dev);
+
 	if (ret) {
 		pr_err("%s: hash_hw/dma_final() failed\n", __func__);
 	}
@@ -1150,6 +1113,9 @@ static int ahash_import(struct ahash_request *req, const void *in)
 	req_ctx->hw_initialized = hstate->hw_initialized;
 	memcpy(req_ctx->buffer, hstate->buffer, HASH_BLOCK_SIZE);
 
+	/* Power up as we may have lost power being exported */
+	pm_runtime_get_sync(device_data->dev);
+
 	/*
 	 * Restore hardware state
 	 * INIT bit. Set this bit to 0b1 to reset the HASH processor core and
@@ -1217,6 +1183,10 @@ static int ahash_export(struct ahash_request *req, void *out)
 	hstate->hw_initialized = req_ctx->hw_initialized;
 	memcpy(hstate->buffer, req_ctx->buffer, HASH_BLOCK_SIZE);
 
+	/* We can power down while exported */
+	pm_runtime_mark_last_busy(device_data->dev);
+	pm_runtime_put_autosuspend(device_data->dev);
+
 	return 0;
 }
 
@@ -1593,7 +1563,6 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	 */
 	regcache_cache_bypass(device_data->map, true);
 	spin_lock_init(&device_data->ctx_lock);
-	spin_lock_init(&device_data->power_state_lock);
 
 	device_data->clk = devm_clk_get(dev, NULL);
 	if (IS_ERR(device_data->clk)) {
@@ -1602,25 +1571,24 @@ static int ux500_hash_probe(struct platform_device *pdev)
 		goto out;
 	}
 
-	ret = clk_prepare(device_data->clk);
+	ret = clk_prepare_enable(device_data->clk);
 	if (ret) {
-		dev_err(dev, "%s: clk_prepare() failed!\n", __func__);
+		dev_err(dev, "%s: clk_prepare_enable() failed!\n", __func__);
 		goto out;
 	}
 
-	/* Enable device power (and clock) */
-	ret = hash_enable_power(device_data);
-	if (ret) {
-		dev_err(dev, "%s: hash_enable_power() failed!\n", __func__);
-		goto out_clk_unprepare;
-	}
-
 	ret = hash_check_hw(device_data);
 	if (ret) {
 		dev_err(dev, "%s: hash_check_hw() failed!\n", __func__);
-		goto out_power;
+		goto out_clk;
 	}
 
+	pm_runtime_set_autosuspend_delay(dev, UX500_HASH_AUTOSUSPEND_DELAY_MS);
+	pm_runtime_use_autosuspend(dev);
+	pm_runtime_get_noresume(dev);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+
 	if (hash_mode == HASH_MODE_DMA)
 		hash_dma_setup_channel(device_data, dev);
 
@@ -1630,18 +1598,20 @@ static int ux500_hash_probe(struct platform_device *pdev)
 	if (ret) {
 		dev_err(dev, "%s: ahash_algs_register_all() failed!\n",
 			__func__);
-		goto out_power;
+		goto out_pm_disable;
 	}
 
+	pm_runtime_put_sync(dev);
 	dev_info(dev, "successfully registered\n");
-	return 0;
-
-out_power:
-	hash_disable_power(device_data);
 
-out_clk_unprepare:
-	clk_unprepare(device_data->clk);
+	return 0;
 
+out_pm_disable:
+	pm_runtime_get_sync(device_data->dev);
+	pm_runtime_put_noidle(device_data->dev);
+	pm_runtime_disable(device_data->dev);
+out_clk:
+	clk_disable_unprepare(device_data->clk);
 out:
 	return ret;
 }
@@ -1675,11 +1645,10 @@ static int ux500_hash_remove(struct platform_device *pdev)
 
 	ahash_algs_unregister_all(device_data);
 
-	if (hash_disable_power(device_data))
-		dev_err(dev, "%s: hash_disable_power() failed\n",
-			__func__);
-
-	clk_unprepare(device_data->clk);
+	pm_runtime_get_sync(device_data->dev);
+	pm_runtime_put_noidle(device_data->dev);
+	pm_runtime_disable(device_data->dev);
+	clk_disable_unprepare(device_data->clk);
 
 	return 0;
 }
@@ -1714,17 +1683,17 @@ static void ux500_hash_shutdown(struct platform_device *pdev)
 
 	ahash_algs_unregister_all(device_data);
 
-	if (hash_disable_power(device_data))
-		dev_err(&pdev->dev, "%s: hash_disable_power() failed\n",
-			__func__);
+	pm_runtime_get_sync(device_data->dev);
+	pm_runtime_put_noidle(device_data->dev);
+	pm_runtime_disable(device_data->dev);
+	clk_disable_unprepare(device_data->clk);
 }
 
-#ifdef CONFIG_PM_SLEEP
 /**
- * ux500_hash_suspend - Function that suspends the hash device.
+ * ux500_hash_runtime_suspend - Function that suspends the hash device.
  * @dev:	Device to suspend.
  */
-static int ux500_hash_suspend(struct device *dev)
+static int __maybe_unused ux500_hash_runtime_suspend(struct device *dev)
 {
 	int ret;
 	struct hash_device_data *device_data;
@@ -1735,21 +1704,20 @@ static int ux500_hash_suspend(struct device *dev)
 		return -ENOMEM;
 	}
 
-	ret = hash_disable_power(device_data);
-	if (ret)
-		dev_err(dev, "%s: hash_disable_power()\n", __func__);
+	clk_disable_unprepare(device_data->clk);
 
+	dev_info(dev, "runtime suspended\n");
 	return ret;
 }
 
 /**
- * ux500_hash_resume - Function that resume the hash device.
+ * ux500_hash_runtime_resume - Function that resume the hash device.
  * @dev:	Device to resume.
  */
-static int ux500_hash_resume(struct device *dev)
+static int __maybe_unused ux500_hash_runtime_resume(struct device *dev)
 {
-	int ret = 0;
 	struct hash_device_data *device_data;
+	int ret;
 
 	device_data = dev_get_drvdata(dev);
 	if (!device_data) {
@@ -1757,15 +1725,23 @@ static int ux500_hash_resume(struct device *dev)
 		return -ENOMEM;
 	}
 
-	ret = hash_enable_power(device_data);
-	if (ret)
-		dev_err(dev, "%s: hash_enable_power() failed!\n", __func__);
+	ret = clk_prepare_enable(device_data->clk);
+	if (ret) {
+		dev_err(dev, "%s: clk_enable() failed!\n", __func__);
+		return ret;
+	}
 
-	return ret;
+	dev_info(dev, "runtime resumed\n");
+
+	return 0;
 }
-#endif
 
-static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
+static const struct dev_pm_ops ux500_hash_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+				pm_runtime_force_resume)
+	SET_RUNTIME_PM_OPS(ux500_hash_runtime_suspend,
+			   ux500_hash_runtime_resume, NULL)
+};
 
 static const struct of_device_id ux500_hash_match[] = {
 	{ .compatible = "stericsson,ux500-hash" },
@@ -1780,7 +1756,7 @@ static struct platform_driver ux500_hash_driver = {
 	.driver = {
 		.name  = "hash1",
 		.of_match_table = ux500_hash_match,
-		.pm    = &ux500_hash_pm,
+		.pm    = &ux500_hash_pm_ops,
 	}
 };
 module_platform_driver(ux500_hash_driver);
-- 
2.37.2

[PATCH v3 16/16] crypto: ux500/hash: Use accelerated noinc MMIO

[Linus Walleij]

After fixes to regmap we can use accelerated MMIO access to
quickly fill up the hash with new data.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v3:
- New patch based on v6.0-rc1
---
 drivers/crypto/ux500/hash/hash_core.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index be703fe4d0ec..aa91bfecba15 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -256,18 +256,13 @@ static void hash_fill_din(struct hash_device_data *device_data,
 			  const void *data, unsigned int len)
 {
 	const u8 *datap = data;
+	int evenbytes = (len / 4) * 4;
 	u32 val;
 
-	/*
-	 * We cannot use regmap_write_noinc() because regmap MMIO does
-	 * not support the noinc operations (requires .write() callback).
-	 * TODO: revisit when regmap MMIO supports regmap_write_noinc().
-	 */
-	while (len > 4) {
-		val = *((u32 *)datap);
-		regmap_write(device_data->map, UX500_HASH_DIN, val);
-		datap += 4;
-		len -= 4;
+	if (evenbytes) {
+		regmap_noinc_write(device_data->map, UX500_HASH_DIN,
+				   data, evenbytes);
+		len -= evenbytes;
 	}
 
 	if (len) {
@@ -1472,6 +1467,7 @@ static bool ux500_hash_reg_volatile(struct device *dev, unsigned int reg)
 {
 	switch (reg) {
 	case UX500_HASH_CR:
+	case UX500_HASH_DIN:
 	case UX500_HASH_STR:
 	case UX500_HASH_H(0) ... UX500_HASH_H(7):
 	case UX500_HASH_ITCR:
-- 
2.37.2